JPH0691105B2 - Method of manufacturing thin film transistor - Google Patents
Method of manufacturing thin film transistorInfo
- Publication number
- JPH0691105B2 JPH0691105B2 JP60026220A JP2622085A JPH0691105B2 JP H0691105 B2 JPH0691105 B2 JP H0691105B2 JP 60026220 A JP60026220 A JP 60026220A JP 2622085 A JP2622085 A JP 2622085A JP H0691105 B2 JPH0691105 B2 JP H0691105B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- gate electrode
- thin film
- channel protective
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims description 74
- 230000001681 protective effect Effects 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 7
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000000354 decomposition reaction Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000001020 plasma etching Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は非晶質シリコンを用いた薄膜トランジスタの製
造方法に関する。The present invention relates to a method of manufacturing a thin film transistor using amorphous silicon.
アクティブマトリクスパネル用に非晶質シリコンを用い
た薄膜トランジスタの開発が活発に行なわれている。非
晶質シリコンは光導電性を有するため、これによる素子
特性劣化を防止する目的の遮光対策が重要な問題であっ
た。従来の薄膜トランジスタの代表的な構造の一例とし
て特開昭58-190058号に記されたものがある。第１図は
上記公知例に記された構造に遮光膜の配置を合せ記した
図である。本構造の薄膜トランジスタの作成手順の概略
を示すと、ゲート電極２、ゲート絶縁膜３、非晶質シリ
コンパターン5,6を形成した後で、上部電極パターン４
を形成し、次にチャネル保護膜７を形成して最後の遮光
膜８を形成するという手順になる。A thin film transistor using amorphous silicon for an active matrix panel has been actively developed. Since amorphous silicon has photoconductivity, it is an important issue to take measures against light shielding for the purpose of preventing deterioration of device characteristics due to the photoconductivity. As an example of a typical structure of a conventional thin film transistor, there is one described in JP-A-58-190058. FIG. 1 is a diagram in which the arrangement of the light-shielding film is added to the structure described in the above-mentioned known example. The outline of the procedure for manufacturing the thin film transistor having this structure is as follows. After forming the gate electrode 2, the gate insulating film 3, and the amorphous silicon patterns 5 and 6, the upper electrode pattern 4 is formed.
Is formed, then the channel protection film 7 is formed, and the final light shielding film 8 is formed.
上述のチャネル保護膜及び遮光膜は良好なトランジスタ
特性を得るために必要であるが上記手順で作成する工程
数が増えざるを得ない。そこで上記製作工程よりも少な
い工程数で確実なチャネル保護膜や遮光膜を形成する方
法が求められていた。The above-mentioned channel protective film and light-shielding film are necessary for obtaining good transistor characteristics, but the number of steps created by the above procedure must be increased. Therefore, there has been a demand for a method of forming a reliable channel protective film and a light-shielding film with a smaller number of steps than the above manufacturing steps.
本発明の目的は、非晶質シリコンを用いた薄膜トランジ
スタの製造方法において、その非晶質シリコン上へ設け
られるチャネル保護膜を少ない工程数で形成することの
できる製造方法を提供することにある。An object of the present invention is to provide a method of manufacturing a thin film transistor using amorphous silicon, which can form a channel protective film provided on the amorphous silicon with a small number of steps.
上記目的は絶縁基板上に設けられたゲート電極と、該ゲ
ート電極上に設けられたゲート絶縁膜と、該ゲート絶縁
膜上に設けられた半導体膜と、該半導体膜上に設けられ
たチャネル保護膜と、上記半導体膜と電気的に接続する
ように設けられたソース・ドレイン電極と遮光膜とを有
する薄膜トランジスタの製造方法において、上記遮光膜
は、ソース・ドレイン電極と同時に形成され、また上記
絶縁基板を透明とし、かつ、上記ゲート電極をマスクと
して露光することにより、上記チャネル保護膜を上記ゲ
ート電極に自己整合的に設けることにより達成される。The above object is to provide a gate electrode provided on an insulating substrate, a gate insulating film provided on the gate electrode, a semiconductor film provided on the gate insulating film, and a channel protection provided on the semiconductor film. In a method of manufacturing a thin film transistor having a film, a source / drain electrode and a light shielding film provided so as to be electrically connected to the semiconductor film, the light shielding film is formed at the same time as the source / drain electrode, and This is achieved by making the substrate transparent and exposing it with the gate electrode as a mask to provide the channel protective film on the gate electrode in a self-aligned manner.
遮光膜をチャネル保護膜上に設け、またゲート電極とチ
ャネル保護膜を自己整合的に設けることにより、保護し
なければならない部分を確実に覆うと共に、マスク合せ
余裕が不要となり高集積化も達成できる。By providing the light-shielding film on the channel protection film and providing the gate electrode and the channel protection film in a self-aligned manner, it is possible to surely cover the part that must be protected, and the mask alignment margin becomes unnecessary, so that high integration can be achieved. .
以下の実施例においては、絶縁基板上にまず所定パター
ンのゲート電極を通常のホトレジ工程にて形成する。次
に、その上にゲート絶縁膜、非晶質シリコン膜、チャネ
ル保護膜をこの順に真空蒸着装置の真空を破らずに連続
堆積させ、上記三層をパターニングする。更にチャネル
保護膜をパターニングした後、ホトレジストを残したま
まオーミックコンタクト用の導電膜を堆積させ、リフト
オフ法により非晶質シリコン膜上を除いた部分の上記導
電膜を除く。次に上部電極及び遮光膜用の金属膜をチャ
ネル保護膜の端面で段切れが生じるような膜厚で堆積さ
せ、これをパターニングして、所望の薄膜トランジスタ
を得る。本製造方法によれば、上部電極と遮光膜を同時
形成するために、マスク合せの回数を減らす事ができ、
またチャネル保護膜と遮光膜をセルフアラインできるた
め遮光は確実となる。またチャネル保護膜パターンをゲ
ート電極にセルフアラインして作成することもでき、こ
れによればチャネル上表面部の遮光は尚一層確実なもの
となる。In the following examples, first, a gate electrode having a predetermined pattern is formed on an insulating substrate by a normal photolithography process. Then, a gate insulating film, an amorphous silicon film, and a channel protective film are successively deposited thereon in this order without breaking the vacuum of the vacuum vapor deposition apparatus, and the three layers are patterned. Further, after patterning the channel protective film, a conductive film for ohmic contact is deposited while leaving the photoresist, and the conductive film is removed by a lift-off method except for the portion above the amorphous silicon film. Next, a metal film for the upper electrode and the light-shielding film is deposited in such a thickness as to cause step breakage on the end face of the channel protection film, and this is patterned to obtain a desired thin film transistor. According to this manufacturing method, since the upper electrode and the light-shielding film are simultaneously formed, the number of times of mask alignment can be reduced,
Further, since the channel protective film and the light shielding film can be self-aligned, the light shielding is sure. It is also possible to form the channel protective film pattern by self-aligning it with the gate electrode, which further ensures the light shielding of the upper surface of the channel.
実施例１ 以下に本発明の実施例を、より具体的に第２図（ａ）〜
（ｃ）を用いて説明する。透明は絶縁基板１上に厚さ0.
2μｍのCrを蒸着し、これを通常のホトレジ工程により
パターニングしてゲート電極２を形成する。次にSiH
4（N2ベース20％）、NH3,N2の混合気体のグロー放電分
解により第１の窒化シリコン膜を厚さ0.3μｍ堆積させ
これをゲート絶縁膜３とする。この上に真空を破ること
なく、SiH4（N2ベース10％）のグロー放電分解により能
動層となる非晶質シリコン膜５を厚さ0.4μｍ堆積す
る。更にこの上に真空を破ることなくSiH4（N2ベース20
％）、NH3,N2の混合気体のグロー放電分解により厚さ1.
5〜２μｍの第２の窒化シリコン膜を堆積させる。CF4プ
ラズマエッチングにより上記３層をパターニングする。
次にホトレジストを露光、現像し、ホトレジスト９を設
けた後、CF4プラズマエッチングにより上記第２の窒化
シリコン膜をパターニングしてチャネル保護膜７とす
る。この時用いたホトレジスト９を残したままでSiH
4（N2ベース10％）、PH3（H2ベース500ppm）を流量比1:
4から1:1で流しグロー放電分解により厚さ0.02μｍ〜0.
05μｍの低抵抗ｎ型非晶質シリコン膜６を堆積しこれを
上部電極と前記非晶質シリコン層との間のオーミックコ
ンタクト用導電膜とする（第２図（ａ））。次にホトレ
ジスト９を除去してリフトオフ法により必要部分以外の
前記ｎ型非晶質シリコン膜６を除去する（第２図
（ｂ））。最後にCr4a,A14bを真空蒸着法でこの順に0.1
μm,0.9μｍ堆積し、パターニングして、ソース・ドレ
イン電極及び遮光膜4a,4b,8a,8bとする。この時ソース
・ドレイン電極4a,4bと遮光膜8a,8bは、CF4プラズマエ
ッチングによりオーバーハング状に形成された十分な厚
みのチャネル保護膜７の端面で段切れを生ずる。最後に
素子領域外の配線部を所望のパターンに形成してTFTを
完成する（第２図（ｃ））。Example 1 Hereinafter, an example of the present invention will be described more specifically with reference to FIG.
An explanation will be given using (c). Transparent has a thickness of 0.
2 μm Cr is vapor-deposited and patterned by a normal photolithography process to form the gate electrode 2. Then SiH
A first silicon nitride film having a thickness of 0.3 μm is deposited by glow discharge decomposition of a mixed gas of 4 (N 2 base 20%), NH 3 , N 2 to form a gate insulating film 3. An amorphous silicon film 5 serving as an active layer is deposited thereon to a thickness of 0.4 μm by glow discharge decomposition of SiH 4 (N 2 base 10%) without breaking the vacuum. Furthermore, SiH 4 (N 2 base 20
%), NH 3 , N 2 mixed gas glow discharge decomposition thickness 1.
A second silicon nitride film of 5-2 μm is deposited. The above three layers are patterned by CF 4 plasma etching.
Next, the photoresist is exposed and developed to provide a photoresist 9, and then the second silicon nitride film is patterned by CF 4 plasma etching to form a channel protection film 7. SiH without removing the photoresist 9 used at this time
4 (N 2 base 10%), PH 3 (H 2 base 500ppm) flow ratio 1:
Thickness from 0.02μm to 0 due to glow discharge decomposition at 4 to 1: 1.
A low resistance n-type amorphous silicon film 6 having a thickness of 05 μm is deposited and used as a conductive film for ohmic contact between the upper electrode and the amorphous silicon layer (FIG. 2 (a)). Next, the photoresist 9 is removed, and the n-type amorphous silicon film 6 other than the necessary portion is removed by the lift-off method (FIG. 2 (b)). Finally, Cr4a and A14b were deposited in this order by vacuum evaporation to 0.1
The source / drain electrodes and the light-shielding films 4a, 4b, 8a, 8b are formed by depositing μm, 0.9 μm and patterning. At this time, the source / drain electrodes 4a, 4b and the light-shielding films 8a, 8b are discontinuous at the end face of the channel protective film 7 having a sufficient thickness formed in an overhang shape by CF 4 plasma etching. Finally, the wiring portion outside the element region is formed into a desired pattern to complete the TFT (FIG. 2 (c)).
実施例２ 上記実施例１においてグロー放電分解によりチャネル保
護膜層を形成するまでの工程は同一である。以後の手順
を以下のように変える。透明基板の上記３層膜に対して
反対側より露光してゲート電極をマスクとしてホトレジ
ストを感光させる。そのホトレジストを現像し、CF4プ
ラズマエッチングを行ないゲート電極にセルフアライン
した（すなわち自己整合的に設けられた）チャネル保護
膜パターンを形成した後で、上記ホトレジストを残した
まま、上記実施例１と同じ方法でｎ型非晶質シリコン層
（６）を形成する。次に非晶質シリコン層（５），窒化
シリコン層（３）のパターニングを終えた後でリフトオ
フ法によりチャネル保護膜（７）上のｎ型非晶質シリコ
ン膜を除去する。以後は上記実施例１と同一である。Example 2 In the above Example 1, the steps until the formation of the channel protective film layer by glow discharge decomposition were the same. The procedure after that is changed as follows. The transparent substrate is exposed from the opposite side to the above-mentioned three-layer film to expose the photoresist using the gate electrode as a mask. The photoresist was developed, and CF 4 plasma etching was performed to form a self-aligned (that is, self-aligned) channel protective film pattern on the gate electrode. An n-type amorphous silicon layer (6) is formed by the same method. Next, after the patterning of the amorphous silicon layer (5) and the silicon nitride layer (3) is completed, the n-type amorphous silicon film on the channel protective film (7) is removed by a lift-off method. The subsequent process is the same as that of the first embodiment.
なお、本発明は上記実施例で限定されない。例えば、電
極の形成法は蒸着に限らずスパッタ法でもよい。また、
ゲート絶縁膜、チャネル保護膜は窒化シリコン膜に限ら
ず酸化シリコンをその他の絶縁体でもよい。また、ゲー
ト電極、遮光膜は素子外部からの入射光を遮光する効果
を持つ不透明材料であれば他の金属でも良い。また、ソ
ース・ドレイン電極は多層構造を持つものに限らず、他
の金属でも良い。The present invention is not limited to the above embodiment. For example, the electrode formation method is not limited to vapor deposition, and may be a sputtering method. Also,
The gate insulating film and the channel protective film are not limited to the silicon nitride film, and silicon oxide may be another insulator. Further, the gate electrode and the light shielding film may be made of other metals as long as they are opaque materials having an effect of shielding incident light from the outside of the device. Further, the source / drain electrodes are not limited to those having a multi-layer structure, and other metals may be used.
本発明による薄膜トランジスタの製造方法によれば、遮
光膜をチャネル保護膜上に設け、またゲート電極とチャ
ネル保護膜を自己整合的に設けることができ、高集積化
に極めて有効である。According to the method of manufacturing a thin film transistor according to the present invention, the light shielding film can be provided on the channel protective film, and the gate electrode and the channel protective film can be provided in a self-aligned manner, which is extremely effective for high integration.
【図面の簡単な説明】 第１図は従来の薄膜トランジスタの構造に遮光膜を配置
した断面図、第２図は本発明の一実施例の薄膜トランジ
スタの製造方法を説明するための構造断面図である。 １……透明絶縁基板、２……ゲート電極、３……ゲート
絶縁膜、4,4a,4b……ソース・ドレイン電極、５……非
晶質シリコン膜、６……ｎ型非晶質シリコン膜、７……
チャネル保護膜、8a,8b……遮光膜。BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view in which a light-shielding film is arranged in the structure of a conventional thin film transistor, and FIG. 2 is a structural sectional view for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention. . 1 ... Transparent insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4,4a, 4b ... Source / drain electrodes, 5 ... Amorphous silicon film, 6 ... N-type amorphous silicon Membrane, 7 ...
Channel protective film, 8a, 8b ... Light-shielding film.
Claims (2)
記ゲート電極上に設けられたゲート絶縁膜と、前記ゲー
ト絶縁膜上に設けられた半導体膜と、前記半導体膜上に
設けられたチャネル保護膜と、前記半導体膜と電気的に
接続するように設けられたソース・ドレイン電極と遮光
膜を有する薄膜トランジスタの製造方法において、 前記遮光膜はソース・ドレイン電極と同時に形成され、
かつ前記チャネル保護膜上に直接被着されていることを
特徴とする薄膜トランジスタの製造方法。1. A gate electrode provided on an insulating substrate, a gate insulating film provided on the gate electrode, a semiconductor film provided on the gate insulating film, and provided on the semiconductor film. In a method of manufacturing a thin film transistor having a channel protective film, a source / drain electrode and a light shielding film provided so as to be electrically connected to the semiconductor film, the light shielding film is formed at the same time as the source / drain electrode,
And a method for manufacturing a thin film transistor, which is directly deposited on the channel protective film.
ート電極をマスクとして露光することにより上記チャネ
ル保護膜を上記ゲート電極に自己整合的に設けた事を特
徴とする特許請求の範囲第１項記載の薄膜トランジスタ
の製造方法。2. The insulating substrate is transparent, and the channel protective film is provided in self-alignment with the gate electrode by exposing using the gate electrode as a mask. Item 1. A method of manufacturing a thin film transistor according to Item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60026220A JPH0691105B2 (en) | 1985-02-15 | 1985-02-15 | Method of manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60026220A JPH0691105B2 (en) | 1985-02-15 | 1985-02-15 | Method of manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61187369A JPS61187369A (en) | 1986-08-21 |
| JPH0691105B2 true JPH0691105B2 (en) | 1994-11-14 |
Family
ID=12187306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60026220A Expired - Lifetime JPH0691105B2 (en) | 1985-02-15 | 1985-02-15 | Method of manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0691105B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0630360B2 (en) * | 1986-02-26 | 1994-04-20 | 松下電器産業株式会社 | Method of manufacturing thin film transistor |
| JPH08330591A (en) * | 1995-05-30 | 1996-12-13 | Nec Corp | Thin film transistor |
| US6107641A (en) * | 1997-09-10 | 2000-08-22 | Xerox Corporation | Thin film transistor with reduced parasitic capacitance and reduced feed-through voltage |
| US6803412B2 (en) | 2003-03-13 | 2004-10-12 | H.B. Fuller Licensing & Financing Inc. | Moisture curable hot melt sealants for glass constructions |
| US7576359B2 (en) * | 2005-08-12 | 2009-08-18 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device and method for manufacturing the same |
| JP6121149B2 (en) * | 2012-11-28 | 2017-04-26 | 富士フイルム株式会社 | Oxide semiconductor element, manufacturing method of oxide semiconductor element, display device, and image sensor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5927574A (en) * | 1982-08-04 | 1984-02-14 | Fujitsu Ltd | Manufacture of self-alignment thin film transistor |
| JPS59228289A (en) * | 1983-06-09 | 1984-12-21 | 富士通株式会社 | Composing of liquid crystal display panel |
| JPS6045066A (en) * | 1983-08-22 | 1985-03-11 | Fujitsu Ltd | Manufacture of thin film transistor |
-
1985
- 1985-02-15 JP JP60026220A patent/JPH0691105B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61187369A (en) | 1986-08-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |