JPS6045066A - Manufacture of thin film transistor - Google Patents
Manufacture of thin film transistorInfo
- Publication number
- JPS6045066A JPS6045066A JP15281083A JP15281083A JPS6045066A JP S6045066 A JPS6045066 A JP S6045066A JP 15281083 A JP15281083 A JP 15281083A JP 15281083 A JP15281083 A JP 15281083A JP S6045066 A JPS6045066 A JP S6045066A
- Authority
- JP
- Japan
- Prior art keywords
- film
- layer
- siox
- sinx
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000010408 film Substances 0.000 claims abstract description 44
- 238000000034 method Methods 0.000 claims abstract description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 239000011521 glass Substances 0.000 claims abstract description 11
- 230000001681 protective effect Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 14
- 229910004205 SiNX Inorganic materials 0.000 abstract description 11
- 239000002313 adhesive film Substances 0.000 abstract description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 5
- 229910001120 nichrome Inorganic materials 0.000 abstract description 4
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract 2
- 238000004090 dissolution Methods 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 229910018487 Ni—Cr Inorganic materials 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000012466 permeate Substances 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は収率と信頼度を向上したれ９膜トランジスタの
製造方法に５１する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention provides a method for manufacturing a nine-film transistor with improved yield and reliability.
（ｂ） 技術の背景
本発明に係る薄膜トランジスタは電界効果トランジスタ
（ＦＥＴ）であってガラス基板上にこの薄膜トランジス
タ素子をマトリックス状に数多く配列し液晶などの表示
素子と組み合わせ、この駆動用として用いるものである
。(b) Background of the Technology The thin film transistor according to the present invention is a field effect transistor (FET), and a large number of these thin film transistor elements are arranged in a matrix on a glass substrate and used for driving the display element, such as a liquid crystal, in combination with the display element. be.
か＼るトランジスタの％徴は単結晶基板を用いて形成す
る通常のトランジスタと異り半導体動作層や絶縁層をプ
ラズマ化学気相成長法を用いて形成するための、大きさ
に制限がなく、また比較的低温度で形成できる点にあり
、プラズマ化学気相成長法（以後略してＰＣＶＤ）を用
いて作られる。Unlike ordinary transistors formed using single crystal substrates, the size of such transistors is not limited because the semiconductor active layer and insulating layer are formed using plasma chemical vapor deposition. Furthermore, it can be formed at a relatively low temperature, and is produced using plasma chemical vapor deposition (hereinafter abbreviated as PCVD).
この方法は基板が置かれた反応室に反応ガスを導入する
と共に排気系を用いて減圧して一定圧に保ち、−刃高周
波コイルまたは平行平板型電極に高周波電力を与えてプ
ラズマを発生させ反応ガスを分解させるものである。In this method, a reaction gas is introduced into the reaction chamber in which the substrate is placed, and the pressure is reduced using an exhaust system to maintain a constant pressure, and high-frequency power is applied to a -blade high-frequency coil or parallel plate electrode to generate plasma and react. It decomposes gas.
こ＼でシラン（Ｓｉｎ４）と水素カス（Ｈ２）との混合
カスヲ用いる場合はアモルファスシリコン（以下ａ−３
ｉ）膜を生じ、シラン（ＳｉＨ４）と亜酸化窒素（Ｎ、
Ｏ）との混合ガス中で行えば酸化シリコン（ＳｉＯｘ）
膜を生じ、一方シランとアンモニア（ＮＨ３）の混合ガ
ス中で行えば窒化シリコン（ＳｉＮｘ）膜を生ずる。When using a mixture of silane (Sin4) and hydrogen gas (H2), amorphous silicon (hereinafter a-3) is used.
i) forming a film, containing silane (SiH4) and nitrous oxide (N,
silicon oxide (SiOx) if carried out in a mixed gas with
A silicon nitride (SiNx) film is produced when carried out in a mixed gas of silane and ammonia (NH3).
こ＼でａ −Ｓ ｉ膜はシリコン（Ｓｔ）原子のダング
リングボンドが水素（Ｈ）原子により飽和された半導体
であり、一方ＳｉＯｘ 、 ＳｉＮｘ膜はそれぞれ絶縁
膜である。The a-Si film is a semiconductor in which dangling bonds of silicon (St) atoms are saturated with hydrogen (H) atoms, while the SiOx and SiNx films are insulating films.
なお酸化／リコ／および窒化シリコンをＳ ｆ Ｏｘ
ｒＳｉＮｘで表わしＳｉ ０２．５ｉｓＮ４と表わさな
い理由はＰＣＶＤ法で作られた化合物は取留な化学量論
理的組成で表現するには不適当であるによる。Note that oxidation/lico/and silicon nitride are S f Ox
The reason why it is expressed as rSiNx and not as Si 02.5isN4 is that the compound produced by the PCVD method is unsuitable to be expressed in terms of a specific stoichiometric composition.
さてＩ） ＣＶ Ｄ法による場合は反応ガスの構成を変
えるだけで基板上に半導体ノＶと絶縁層とを適宜形成で
きるので薄膜ＩＣの製造には極めて都合がよい。Now, I) The CVD method is extremely convenient for manufacturing thin film ICs because it is possible to appropriately form a semiconductor layer and an insulating layer on a substrate simply by changing the composition of the reaction gas.
本発明はこの方法でガラス基板」二に形成されるＦ’
Ｅ Ｔの製法についてのものである。The present invention provides F' formed on a glass substrate by this method.
This is about the manufacturing method of ET.
（ｃ） 従来技術と問題点
第１図ｄ本発明に係るん膜ＦＥＴの構成図でａ−８ｆか
らなる半導体動作層１をゲート絶縁膜２で絶縁してゲー
ト電極（Ｇ）があり、−１反対側の半導体動作層１上に
はソース化ＴｈＺ（Ｓ）およびドレイン電極（Ｄ）が設
けられている。(c) Prior art and problems FIG. 1d is a block diagram of a film FET according to the present invention, in which a semiconductor active layer 1 consisting of a-8f is insulated by a gate insulating film 2, and a gate electrode (G) is provided. A source ThZ (S) and a drain electrode (D) are provided on the semiconductor active layer 1 on the opposite side.
かＸる構成の薄膜Ｆ Ｅ Ｔはソース電極（Ｓ）とドレ
イン電極（Ｄ）との間にドレイン電圧（ＶＤ）を印加し
である状態でゲート電極（Ｇ）に正の電圧を印加すると
ゲート絶縁膜２と半導体動作層１との界面に印加電圧値
に比例して負の電荷が銹起され、これによりソース電極
（Ｓ）とドレインｋｌｋ （Ｄ）間の電導が促進される
。In the thin film FET with the above structure, when a drain voltage (VD) is applied between the source electrode (S) and the drain electrode (D), and a positive voltage is applied to the gate electrode (G) in a certain state, the gate Negative charges are generated at the interface between the insulating film 2 and the semiconductor active layer 1 in proportion to the applied voltage value, thereby promoting conduction between the source electrode (S) and the drain klk (D).
こ＼でゲート電圧（Ｖｃ ）の有無に対応するドレイン
電流（ＩＤ）の変化が急激であるためスイッチング動作
が可能となる。Here, switching operation is possible because the drain current (ID) changes rapidly depending on the presence or absence of the gate voltage (Vc).
かＸる薄膜ＦＥＴの作り方としては第２図に示すように
ガラス基板３の上にゲート電極４をニクロム（Ｎｉ−Ｃ
ｒ）などの金属を用いてパターン形成を行って後、この
上にｌ） ＣＶ Ｄ法によりゲート絶縁膜５．半ｆ体動
作Ｊ＠６．保訛膜７と順次ｌ〆形成しこれにスピンコー
ド法によりホトレジスト層８を被覆し写真蝕刻技術（ホ
トリソクラフイ）を用いてソースおよびドレイン東極形
成のだめの選択エツチングを行っていた。To make a thin film FET, a gate electrode 4 is placed on a glass substrate 3 using nichrome (Ni-C) as shown in FIG.
After forming a pattern using a metal such as r), a gate insulating film 5.l) is formed on this using a CVD method. Half-f body motion J@6. A protective film 7 and a protective film 7 were sequentially formed, a photoresist layer 8 was coated thereon by a spin code method, and selective etching was performed using photolithography to form source and drain electrodes.
こ＼でゲート絶縁膜５は例えばＳｉＯｘかＳｉＮｘで形
成され半導体動作／ｆｉ６はａ−８ｉ膜で、保設膜７は
Ｓ ｉｏｘで才たホトレジスト層８はポジレジストを用
いて形成されている。Here, the gate insulating film 5 is formed of, for example, SiOx or SiNx, the semiconductor operation/fi 6 is formed of an a-8i film, the storage film 7 is formed of Siox, and the photoresist layer 8 is formed of a positive resist.
次にこの場合のようにガラス基板３を使用するものにつ
いては背面露光によるセルフアライメント法が適用でき
、ガラス基板３の板面より紫外線照射を行うとゲート電
極４がマスクとなりホトレジスト層８に対し高い位置合
わせ精度の露光を行うことができ、現像処理により第３
図に示すようにホトレジスト１ホ８が窓開けされる。Next, in cases where a glass substrate 3 is used as in this case, a self-alignment method using back exposure can be applied, and when ultraviolet rays are irradiated from the surface of the glass substrate 3, the gate electrode 4 acts as a mask and the height of the photoresist layer 8 is higher than that of the photoresist layer 8. Exposure with alignment accuracy can be performed, and the third
As shown in the figure, the photoresist 1 hole 8 is opened.
次に化学エツチング液例えばＦ２Ｏ３を用いてＳｉ Ｏ
ｘよりなる保豚膜７をエツチングして第４図に示すよう
に半導体動作ＪｆｔＧを露出させ、この上にｎ ’ ａ
−８ｉ層を形成すると共にＮｉ−Ｃｒなどの金属をに￥
尤しリフトオフ法によりソース電極およびドレイン電極
が形成されている。Next, use a chemical etching solution such as F2O3 to remove the SiO
The protective membrane 7 consisting of x is etched to expose the semiconductor operation JftG as shown in FIG.
- Forming an 8i layer and adding metals such as Ni-Cr
The source electrode and drain electrode are formed by a lift-off method.
然しＦ２Ｏ３などの化学エツチング液を用いて選択エツ
チングを行う場合ホトレジス［８とＳｉＯｘよりなる保
訟膜７との密Ｉｉ性が悪く、エツチング液がこの間に浸
みこみパターン形成の精度を損うと云う問題がある。However, when selective etching is performed using a chemical etching solution such as F2O3, there is a problem in that the adhesiveness between the photoresist [8] and the protective film 7 made of SiOx is poor, and the etching solution permeates between them, impairing the accuracy of pattern formation. There is.
これを解決する方法として５ｔｙｘ保護膜７の上にホト
レジストとの密着性のよいａ−８ｉ層を設けることが行
われているが、この場合はａ−８ｉ層の光吸収係数が大
きいためその厚さの分だけ半導体動作層６の厚さを減ら
す必要があり、Ｉ” Ｅ Ｔの安定性の点から良い方法
であるとは云えない。A method to solve this problem is to provide an a-8i layer with good adhesion to the photoresist on the 5tyx protective film 7, but in this case, since the light absorption coefficient of the a-8i layer is large, the thickness of the a-8i layer is Since it is necessary to reduce the thickness of the semiconductor active layer 6 by the same amount, this method cannot be said to be a good method from the viewpoint of stability of I''ET.
一方ＳｉＯｘ保股膜７と８ｉ ７ＦＸ性のよいホトレジ
ストを選択することも考えられるが、背面露光法を用い
る限りポジ型レジストの使用が必要であり、ＡＺ系のポ
ジレジストである限りＳｉＯｘ保ｈψ膜７とは良い密着
性を得ることはできない。On the other hand, it is possible to select a photoresist with good FX properties for SiOx retention films 7 and 8i, but as long as the back exposure method is used, it is necessary to use a positive resist, and as long as it is an AZ-based positive resist, the SiOx retention film 7, good adhesion cannot be obtained.
（ｄ） 発明の目的
本発明の目的はポジ系のレジストと密着性が良くまた半
導体動作層の厚さを減少でぜ力くて済む薄膜トランジス
タの製造方法を提供するにある。(d) Object of the Invention An object of the present invention is to provide a method for manufacturing a thin film transistor which has good adhesion to a positive resist and which requires less effort by reducing the thickness of the semiconductor active layer.
（ｅ） 発明のオｊｔ成
本発明の目的はＡし膜Ｆ Ｅ Ｔのチャネル部保設膜と
して使用するＳｉＯｘ膜上に更にＳ ｉＮｘ膜を設け、
この上に塗布するレジストとの密着性を向上させること
により達成することができる。(e) Ojt formation of the invention The purpose of the present invention is to further provide a SiNx film on the SiOx film used as a channel part holding film of the aluminum film FET.
This can be achieved by improving the adhesion with the resist applied thereon.
（ｆ） 発明の実施例
本発明はレジストとの密着性のよいＳｉＮｘを５ｔｙｘ
保ｈφ膜７とホトレジストＮ８との間に介在させるもの
である。(f) Embodiments of the invention The present invention uses 5tyx SiNx which has good adhesion to the resist.
It is interposed between the hφ film 7 and the photoresist N8.
こ５で介在層の条件はガラス基板３の背面露光によるセ
ルフアライメントに除して紫外線の吸収が少いＩ料であ
ることおよびＰＣＶＤ法で形成できることであるがＰＣ
ＶＤ法で得られるＳｉＮｘ膜は透明であ！２またポジ系
レジストとの密着性もよい０
以下実施例について本発明を説明する。In this step 5, the conditions for the intervening layer are that it is an I material that absorbs less ultraviolet rays compared to the self-alignment by back exposure of the glass substrate 3, and that it can be formed by the PCVD method.
The SiNx film obtained by the VD method is transparent! 2. Good adhesion to positive resists 0. The present invention will be described below with reference to Examples.
第５図はリフトオフ法により形成される薄膜ＦＥＴを示
すものでカラス基板３の上にＮｉ−Ｃｒよりなるゲート
電極４を形成後、ＰＣＶＤ法によりＳｉＯｘよりなるゲ
ート絶縁膜５＋ ａ Ｓｉよりなる半導体動作層６．
ＳｉＯｘよりなる保礁膜７． ＳｉＮｘよりなる密着膜
９とｌＩＤ１次／ｍ形成する。FIG. 5 shows a thin film FET formed by a lift-off method. After forming a gate electrode 4 made of Ni-Cr on a glass substrate 3, a gate insulating film 5+ made of SiOx is formed by a PCVD method. Layer 6.
Reef preservation film made of SiOx7. An adhesive film 9 made of SiNx and lID primary/m are formed.
次にスビノナを用いてこの上にポジレジストＭ形成した
る後背面露光を行ってゲート電極４の部分のホトレジス
ト層８を除いて感光させ現像処理により感光部分を溶解
除去させる０
次にこの上にン２ン（Ｓｉ＆）とホスフィン（ＰＨ３）
の混合ガスを用いてＰＣＶＤを行いｎ＋のａ−Ｓｉ層１
０を形成し、更にこの上にＮｉ−Ｃｒ層１１を蒸着する
０
なおソース電極とドレイン電極け′このようにして生じ
たＮ１−Ｃｒｊ梼１１とｎ＋のａ−Ｓｉ７ｍＩＯに選択
エツチングを施すことにより電極パターンが形成されま
た、ＳｉＮｘ密着膜９の上のホトレジスト層８は溶剤に
より除去されて薄膜トランジスタができ上る。Next, after forming a positive resist M on this using Subinona, back exposure is performed to expose the photoresist layer 8 except for the gate electrode 4 portion, and the exposed portion is dissolved and removed by a development process. (Si&) and phosphine (PH3)
PCVD is performed using a mixed gas of n+ a-Si layer 1.
Further, a Ni-Cr layer 11 is deposited on the source electrode and the drain electrode. An electrode pattern is formed, and the photoresist layer 8 on the SiNx adhesive film 9 is removed with a solvent to complete a thin film transistor.
（９）発明の効果
本発明は背面露光法によるセルフアライメント法とリフ
トオフ法とを用いて形成される薄膜トランジスタの製造
工程においてＳｉＯｘ保ｔム欣と、ポジレジストとの密
九性が悪いため収率および品質が低下する点を改良する
ためになされたもので、Ｓ ｊＮｘ膜を密着膜として用
いる本発明の実施によりこれらの問題点を解決すること
ができる。(9) Effects of the invention In the manufacturing process of thin film transistors formed using a self-alignment method using a back exposure method and a lift-off method, the yield is low due to poor density between the SiOx film and the positive resist. This was done to improve the problem of deterioration in quality and deterioration of quality.These problems can be solved by implementing the present invention using an SjNx film as an adhesive film.
【図面の簡単な説明】
第１図は薄膜トランジスタの構成図、第２図〜第４図は
従来の製造工程を説明する断面図、また第５図は本発明
に係る工程を説明する断面図である。
図において、
１．６Ｉ′ｉ半導体動作層、２，５はゲート絶縁膜、３
はガラス基板、４はゲート電極、７け保護膜、８はホト
レジスト層、９は密着膜。[Brief Description of the Drawings] Figure 1 is a configuration diagram of a thin film transistor, Figures 2 to 4 are cross-sectional views explaining the conventional manufacturing process, and Figure 5 is a cross-sectional view explaining the process according to the present invention. be. In the figure, 1.6I′i semiconductor operating layer, 2 and 5 are gate insulating films, and 3
4 is a glass substrate, 4 is a gate electrode, 7 is a protective film, 8 is a photoresist layer, and 9 is an adhesive film.
Claims (1)
にゲート絶縁膜、半導体動作層、チャネル部保護膜と順
次層形成し写真蝕刻技術によりゲート電極部を除いて上
記保護膜のエツチングを行い、ソースおよびドレイン電
極をパターン形成してなる薄膜トランジスタにおいて、
保護膜として使用する酸化シリコン膜上に更に窒化シリ
コン膜を設はレジストとの密着性を向上することを特徴
とするドグ膜トランジスタの製造方法。After patterning a gate electrode on a glass substrate, a gate insulating film, a semiconductor active layer, and a channel protective film are sequentially formed on the glass substrate, and the protective film is etched except for the gate electrode using photolithography, and the source layer is etched. and a thin film transistor formed by patterning the drain electrode,
A method for manufacturing a dog film transistor, characterized in that a silicon nitride film is further provided on a silicon oxide film used as a protective film to improve adhesion to a resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15281083A JPS6045066A (en) | 1983-08-22 | 1983-08-22 | Manufacture of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15281083A JPS6045066A (en) | 1983-08-22 | 1983-08-22 | Manufacture of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6045066A true JPS6045066A (en) | 1985-03-11 |
Family
ID=15548643
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15281083A Pending JPS6045066A (en) | 1983-08-22 | 1983-08-22 | Manufacture of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6045066A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139069A (en) * | 1984-12-10 | 1986-06-26 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
| JPS61187369A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Manufacture of thin film transistor |
| JPS62140467A (en) * | 1985-12-13 | 1987-06-24 | Sharp Corp | Manufacture of thin-film transistor |
| JPS62259471A (en) * | 1986-05-02 | 1987-11-11 | Fuji Xerox Co Ltd | Manufacture of thin film transistor |
| JPS63168052A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Thin film transistor and manufacture thereof |
| JPS644071A (en) * | 1987-06-26 | 1989-01-09 | Nippon Telegraph & Telephone | Thin film transistor and manufacture thereof |
| JPS6450567A (en) * | 1987-08-21 | 1989-02-27 | Nec Corp | Thin film transistor and manufacture thereof |
| JPH01173650A (en) * | 1987-12-26 | 1989-07-10 | Seikosha Co Ltd | Manufacture of amorphous silicon thin-film transistor |
| JPH06163903A (en) * | 1986-05-02 | 1994-06-10 | Fuji Xerox Co Ltd | Thin film transistor |
| US5888855A (en) * | 1994-12-14 | 1999-03-30 | Kabushiki Kaisha Toshiba | Method of manufacturing active matrix display |
-
1983
- 1983-08-22 JP JP15281083A patent/JPS6045066A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61139069A (en) * | 1984-12-10 | 1986-06-26 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
| JPS61187369A (en) * | 1985-02-15 | 1986-08-21 | Hitachi Ltd | Manufacture of thin film transistor |
| JPS62140467A (en) * | 1985-12-13 | 1987-06-24 | Sharp Corp | Manufacture of thin-film transistor |
| JPS62259471A (en) * | 1986-05-02 | 1987-11-11 | Fuji Xerox Co Ltd | Manufacture of thin film transistor |
| JPH06163903A (en) * | 1986-05-02 | 1994-06-10 | Fuji Xerox Co Ltd | Thin film transistor |
| JPS63168052A (en) * | 1986-12-29 | 1988-07-12 | Nec Corp | Thin film transistor and manufacture thereof |
| JPS644071A (en) * | 1987-06-26 | 1989-01-09 | Nippon Telegraph & Telephone | Thin film transistor and manufacture thereof |
| JPS6450567A (en) * | 1987-08-21 | 1989-02-27 | Nec Corp | Thin film transistor and manufacture thereof |
| JPH01173650A (en) * | 1987-12-26 | 1989-07-10 | Seikosha Co Ltd | Manufacture of amorphous silicon thin-film transistor |
| US5888855A (en) * | 1994-12-14 | 1999-03-30 | Kabushiki Kaisha Toshiba | Method of manufacturing active matrix display |
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