JP2002198311A - Method for forming polycrystalline semiconductor thin film and method for manufacturing semiconductor device and equipment and electro-optical system for putting these methods into practice - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for easily forming a high quality polycrystalline semiconductor thin film such as of polycrystalline silicon, at a high crystallization ratio at low cost and that for forming the film of a large area, and to provide equipment for putting such method into practice. SOLUTION: When forming the polycrystalline semiconductor thin film 7 with high crystallization ratio and the polycrystalline silicon film or the like having a large size diameter on a substrate 1 or when manufacturing a semiconductor device having the polycrystalline semiconductor thin film 7 on the substrate 1, the work is brought into contact with a catalyst 46 prepared by heating hydrogen or a hydrogen including gas and a raw material gas 40, and then a generated reaction material is deposited on the substrate 1, and a vapor deposition process (catalyst CVD) of forming a low grade crystalline semiconductor thin film of a micro crystal silicon or the like is performed. The work is brought into contact with the catalyst 46 prepared by heating the hydrogen or the hydrogen including the gas, and then the generated active material is made to operate to the low grade crystalline semiconductor thin film. Then the polycrystalline semiconductor thin film 7 is made by repeating an annealing process (catalyst AHA process) that promotes crystallization of the low grade crystalline semiconductor thin film. The method for forming such polycrystalline semiconductor thin film or the method for manufacturing a semiconductor device and the equipment for carrying out them are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for vapor-phase growing a polycrystalline semiconductor thin film such as polycrystalline silicon on a substrate, and a method for manufacturing a semiconductor device having the polycrystalline semiconductor thin film on the substrate. And its device, and an electro-optical device.

[0002]

2. Description of the Related Art Conventionally, MOSFETs (Metal-Oxide-Semi
conductor Field Effect Transistor)
When the source, drain and channel regions of an OSTFT (Thin Film Transistor) are formed of a polycrystalline silicon film, plasma CVD (Chemical Vapor Deposition) or low pressure CVD is used. The law is used.

An amorphous or polycrystalline silicon formed by such a plasma CVD method, a low pressure CVD method, etc.
JP-A-7-131030, JP-A-9-116156
As shown in JP-B-7-118443, simply high-temperature annealing or excimer laser annealing (ELA:
Excimer Laser Anneal) treatment has been used to improve the carrier mobility of the polycrystalline silicon film. However, this method has a limit of obtaining a carrier mobility of about 80 to 120 cm ² / V · sec. However, plasma C
The electron mobility of MOSTFT using polycrystalline silicon obtained by ELA of amorphous silicon by VD method is as follows.
Since it is about 100 cm ² / V · sec and can correspond to high definition, recently, LCD (Liquid Crystal Display) using polycrystalline silicon MOSTFT integrated with drive circuit
= Liquid crystal display device) (JP-A-6-242)
No. 433).

[0004]

However, the above-mentioned EL
In the method of manufacturing a polycrystalline silicon MOSTFT according to A, there are many problems such as stability of excimer laser output, increase in equipment price due to productivity and increase in size, reduction in yield / quality, and the like. In the case of a glass substrate, the above-mentioned problems are enlarged, and it becomes more difficult to improve performance / quality and reduce costs.

Also, polycrystalline silicon M by a solid phase growth method is used.
In the manufacturing method of the OSTFT, annealing for more than 10 hours at 600 ° C. or more and formation of a gate SiO ₂ for thermal oxidation at about 1000 ° C. are required, so that a semiconductor manufacturing apparatus has to be employed. For this reason, the substrate size should be wafer size 8 ~
The limit is 12 inches φ, and expensive heat-resistant and expensive quartz glass must be adopted, which makes it difficult to reduce the cost and limits its use to EVF and data / AV projectors.

Recently, a catalytic CVD method, which is an excellent thermal CVD method capable of forming a polycrystalline silicon film, a silicon nitride film and the like at a low temperature on an insulating substrate such as a glass substrate, has been developed (JP-B-63-40314). No., Tokuhei 8-250438
No.), and studies for practical use are being promoted. Catalytic CVD
In the method, 30 cm ² / V without crystallization annealing
・ Carrier mobility of about sec, but high quality M
It is still not enough to make OSTFT devices.
When a polycrystalline silicon film is formed on a glass substrate, an initial amorphous silicon transition layer (5 to 10 nm in thickness) is likely to be formed depending on the film formation conditions. Mobility is difficult to obtain. Generally, an LCD using a polycrystalline silicon MOSTFT integrated with a driving circuit is a bottom gate type MOFET.
Although STFTs are easy to manufacture in terms of yield and productivity, this problem is a bottleneck.

An object of the present invention is to provide a method capable of easily forming a polycrystalline semiconductor thin film such as polycrystalline silicon with a high crystallization rate and a high quality over a large area at a low cost, and an apparatus for implementing the method. Is to provide.

It is another object of the present invention to provide a method of manufacturing a semiconductor device such as a MOSTFT having such a polycrystalline semiconductor thin film as a constituent part, an apparatus for performing the method, and an electro-optical device.

[0009]

That is, the present invention relates to a method of forming a polycrystalline semiconductor thin film on a substrate or manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate by heating a source gas. Contacting the catalyzed body, and depositing the reactive species generated on the substrate to form a lower crystalline semiconductor thin film, and contacting hydrogen or a hydrogen-containing gas with the heated catalyzer. Obtaining the polycrystalline semiconductor thin film by repeating the annealing step of causing the active species generated thereby to act on the lower crystalline semiconductor thin film and promoting crystallization of the lower crystalline semiconductor thin film. The present invention relates to a method for forming a semiconductor thin film or a method for manufacturing a semiconductor device.

The present invention also provides an apparatus for performing the method of the present invention, wherein a raw material gas supply means, a hydrogen or hydrogen-containing gas supply means, a catalyst, a catalyst heating means, a substrate heating means, A gas phase growth step of forming a lower crystalline semiconductor thin film by depositing a reactive species generated by contacting a source gas and the hydrogen or a hydrogen-containing gas with the heated catalyst body on the substrate; Alternatively, an annealing step of promoting crystallization of the lower crystalline semiconductor thin film by causing active species generated by bringing a hydrogen-containing gas into contact with the heated catalyst to act on the lower crystalline semiconductor thin film is performed alternately. An apparatus for forming a polycrystalline semiconductor thin film or an apparatus for manufacturing a semiconductor device, comprising: a source gas supply unit and a control unit that controls the hydrogen or hydrogen-containing gas supply unit. It is intended to provide.

The present invention also provides a cathode and an anode connected to a drain or a source of a MOSTFT made of the polycrystalline semiconductor thin film, respectively, below an organic or inorganic electroluminescence layer for each color.
The present invention provides an electro-optical device in which the cathode is also covered on the active element including, or the cathode or the anode is attached to the entire surface of each of the organic or inorganic electroluminescent layers for each color and between the layers. is there.

The present invention also relates to a field emission display (FED) device, wherein an emitter is connected to a drain of a MOSTFT made of the polycrystalline semiconductor thin film via the polycrystalline semiconductor thin film and the polycrystalline semiconductor thin film is formed. An electro-optical device formed by an n-type polycrystalline semiconductor film or a polycrystalline diamond film grown on a thin film is also provided.

According to the present invention, when a polycrystalline semiconductor thin film is formed on a substrate, a raw material gas is brought into contact with a heated catalyst body as in a conventional catalytic CVD method, and a reaction species generated by the contact is supplied to the substrate. Depositing on it, vapor-growing a lower crystalline semiconductor thin film, and contacting hydrogen or a hydrogen-containing gas with a heated catalyst to cause active species generated thereby to act on the lower crystalline semiconductor thin film. Then, the annealing step for promoting the crystallization of the lower crystalline semiconductor thin film is repeated, so that the following remarkable functions and effects (1) to (4) can be obtained.

(1) Since a reactive species (deposited species or its precursor and radical ions) generated by bringing a raw material gas into contact with a heated catalyst body is deposited on a substrate, a lower crystalline semiconductor thin film can be efficiently produced. Can be formed well,
High-temperature hydrogen-based molecules, hydrogen-based atoms, active hydrogen ions, and other hydrogen generated in large quantities by the thermal decomposition reaction and the catalytic decomposition reaction under high vacuum with a heated catalyst body on this lower crystalline semiconductor thin film Since the system active species is caused to act by spraying or the like, the following remarkable effects are exhibited due to the addition of heating by the radiant heat of the high-temperature thermal catalyst.

1. Due to the radical action of the hydrogen-based active species, thermal energy moves to the film and locally raises the temperature. In the lower crystalline semiconductor thin film, the crystallization is promoted by etching the amorphous component, and the high-grain high-grain semiconductor film has a large grain size. It is possible to form a polycrystalline film having a crystallization rate, reduce crystal irregularities and internal stress existing at the crystal grain boundaries, and obtain a polycrystalline semiconductor thin film having high carrier mobility and high quality. In addition, when silicon oxide is present on or in the polycrystalline silicon or microcrystalline silicon film, it reacts with the silicon oxide to generate and evaporate SiO, so that the silicon oxide on or in the film is removed. It can be reduced / removed, and a high-carrier mobility, high-quality polycrystalline silicon film or the like can be obtained.

The recrystallization of the microcrystalline silicon-containing amorphous silicon film, the amorphous silicon-containing microcrystalline silicon film, and the like is promoted by using the microcrystalline silicon as a seed to form a polycrystalline silicon film having a large grain size. Moreover, since the amorphous silicon contained in the film is reduced (etched) by active hydrogen ions or the like, a polycrystalline film having a high crystallization ratio is formed. The treatment with hydrogen-based active species such as active hydrogen ions is described below as Catalyst AHA.
(Atomic Hydrogen Anneal) processing.

2. During this catalytic AHA treatment, the carrier impurities present in the lower crystalline semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration is obtained in each region.

3. In addition, cleaning (reduction and removal of an adsorbed gas and organic residues on a substrate or the like) by a hydrogen-based active species such as activated hydrogen ions is possible, and the catalyst is less likely to be oxidized and deteriorated (this effect is not significant). , The above catalyst CV
The same occurs in the case of D since a hydrogen-based carrier gas is used).

4. The hydrogenation of hydrogen-based active species such as activated hydrogen ions eliminates, for example, silicon dangling bonds in the semiconductor film and improves the characteristics.

(2) The step of vapor-phase growing a lower crystalline semiconductor thin film on the polycrystalline film thus treated with the catalyst AHA is repeated until the target film thickness is reached. Thus, the polycrystalline semiconductor thin film can be easily grown on the polycrystalline base film in a state of being easily polycrystallized, and a desired high crystallization rate and high quality polycrystalline semiconductor thin film can be obtained with a predetermined thickness. That is, catalytic CVD and catalytic AHA
By a multi-catalyst AHA process that repeats the process, for example, a microcrystalline silicon-containing amorphous silicon film formed by, eg, catalytic CVD, an amorphous silicon film and a microcrystalline silicon-containing polycrystalline silicon film are converted into a polycrystalline silicon film by a catalytic AHA process. Since the vapor phase growth of the polycrystalline silicon film and the catalytic AHA treatment are repeated by catalytic CVD using polycrystalline silicon as a seed, a polycrystalline silicon film having a high crystallization rate and a large grain size can be formed.

(3) Since both the catalytic CVD and the catalytic AHA treatment can be performed without generation of plasma, a plasma-damage-free, low-stress formed film can be obtained, and the method is simpler and less expensive than the plasma CVD method. Device can be realized.

(4) Even if the temperature of the substrate is lowered, the energy of the reactive species is large, so that a desired high-quality film can be obtained. Therefore, the temperature of the substrate can be lowered, and a large and inexpensive insulating substrate (glass) Substrate, heat-resistant resin substrate, etc.), and in this regard, cost can be reduced.

In the present invention, the lower crystalline semiconductor thin film refers to a structure based on microcrystals containing an amorphous component or amorphous (amorphous) containing microcrystals as defined below. The polycrystalline semiconductor thin film described above has a large grain size (such as a grain size,
(Several hundred nm or more).

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the method and the apparatus according to the present invention, it is desirable that the temperature be lower than the melting point (for example, 1600 to 1).
(800 ° C.), the raw material gas and at least a part of the hydrogen-based carrier gas are brought into contact with the catalyst body to be catalytically decomposed, and the generated reactive species such as radicals and ions are heated. After the lower crystalline semiconductor thin film is deposited on a substrate and the lower crystalline semiconductor thin film is vapor-phase grown by catalytic CVD, the supply of the raw material gas is stopped and a heated catalyst (this is preferably the same as the catalyst). ), At least a portion of the hydrogen-based carrier gas, and the resulting hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions. The annealing by catalytic AHA treatment is preferably performed by acting on the lower crystalline semiconductor thin film.

In this case, the supply amount of hydrogen or the hydrogen-containing gas during the annealing is set to be larger than the supply amount of hydrogen or the hydrogen-containing gas during the vapor phase growth. For example, the hydrogen-based carrier gas used during vapor phase growth is hydrogen or a mixed gas of hydrogen and an inert gas (argon, helium, xenon, krypton, radon, etc., which have good thermal conductivity and contribute to the improvement of reactivity). In the case of mixed gas, the hydrogen content ratio is 50 mol%
With the above, oxidation deterioration of the catalyst body can be prevented. The hydrogen or the hydrogen-containing gas used in the catalyst AHA treatment may be the same as the hydrogen-based carrier gas used in the vapor phase growth.
(Standard cc per minute) and increase the gas pressure to 10 to 50 Pa (the gas pressure during catalytic CVD is 0.1 to several P
a) It is preferable to increase the heat conduction by the gas and the amount of radical hydrogen ions generated.

The above-mentioned vapor phase growth by catalytic CVD is as follows:
Specifically, the catalyst body is heated to a temperature in the range of 800 to 2000 ° C. and lower than its melting point (for example, the catalyst body is heated by its own resistance heating), and the heated catalyst body is heated. The reaction species generated by subjecting at least a part of the raw material gas and the hydrogen or the hydrogen-containing gas to a catalytic reaction or a thermal decomposition reaction as a raw material species,
A thin film can be deposited on a substrate heated to 0 ° C. Such a catalyst body temperature and the following catalyst body material are catalyst A
The same applies to the HA processing.

Here, if the heating temperature of the catalyst is lower than 800 ° C., the catalytic reaction or the thermal decomposition reaction of the raw material gas becomes insufficient and the deposition rate tends to decrease. Constituent materials are mixed into the deposited film to inhibit the electrical properties of the film, resulting in deterioration of the film quality, and heating above the melting point of the catalytic body loses its morphological stability. The heating temperature of the catalyst body is lower than the melting point of the constituent material and is preferably 1100 ° C to 1800 ° C.

The catalyst body is formed of at least one material selected from the group consisting of tungsten, thoria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics to which metal is attached, and silicon carbide. Can be.

The catalyst and the support for supporting the catalyst have a purity of 99.99 wt% (4 N) or more, preferably 99.999 wt% (5 N) or more, thereby forming polycrystalline material. Heavy metal contamination of the semiconductor thin film can be reduced.

The substrate temperature is preferably 200 to 800 ° C., and more preferably 300 to 400 ° C., so that efficient and high quality film formation can be performed. When the substrate temperature is high, inexpensive borosilicate glass and aluminosilicate glass cannot be used, and the doping concentration distribution of impurities tends to change due to the influence of heat.

When a polycrystalline silicon film is formed by a normal thermal CVD method, the substrate temperature needs to be about 600 to 900 ° C. However, in the film formation according to the present invention, plasma or photoexcitation is required. Instead, thermal CVD at low temperature as described above
It is very advantageous that this is possible. Since the substrate temperature during the catalytic CVD according to the present invention is low as described above, the strain point of the substrate, for example, a glass substrate is 470 to 670 ° C.
Glass such as low borosilicate glass or aluminosilicate glass can be used. This is inexpensive, easy to make thin, and large (1m x 1m or more) is possible,
Also, a long rolled glass plate can be manufactured. For example, a thin film can be continuously or discontinuously formed on a long rolled glass plate by using the above method.

The source gas used for the vapor phase growth by catalytic CVD according to the present invention is a mixture of silicon hydride or a derivative thereof, silicon hydride or a derivative thereof and a gas containing hydrogen, oxygen, nitrogen, germanium, carbon or tin. A mixture of silicon hydride or a derivative thereof and a gas containing an impurity composed of an element belonging to Group III or Group V of the periodic table, containing silicon hydride or a derivative thereof and hydrogen, oxygen, nitrogen, germanium, carbon, or tin And a gas containing an impurity composed of a Group III or Group V element in the periodic table.

By using the raw material gas as described above, a microcrystalline silicon-containing amorphous silicon film, a microcrystalline silicon (amorphous silicon-containing microcrystalline silicon) film, an amorphous silicon and a microcrystalline silicon-containing polycrystalline silicon film, a microcrystalline germanium containing amorphous germanium film, a microcrystalline germanium (amorphous germanium containing microcrystalline germanium) film, an amorphous germanium and microcrystalline germanium containing polycrystalline germanium film, or Si _x Ge _1-x amorphous silicon germanium represented by (0 <x <1) The lower crystalline semiconductor thin film made of a film can be formed. The lower crystalline semiconductor thin film is based on amorphous, and when containing microcrystals, it is preferable that microcrystals having a particle size of 10 nm or less are scattered.

After the growth or growth of the lower crystalline semiconductor thin film, at least one of Group IV elements such as tin, germanium and lead is added in an appropriate amount (for example, 10 ¹⁸ to 10 ²⁰ at).
oms / cc), and in this state, when the annealing step by the catalytic AHA treatment is performed, when the lower crystalline semiconductor thin film is polycrystallized, the lower crystalline semiconductor thin film is present at a grain boundary (grain boundary) of the polycrystalline semiconductor. And the film stress thereof is reduced, so that a high mobility and high quality polycrystalline semiconductor can be easily obtained. The group IV element can be mixed as a gas component in the source gas, or can be contained in the lower crystalline semiconductor thin film by ion implantation or ion doping. The oxygen, nitrogen and carbon concentrations in the polycrystalline semiconductor film formed according to the present invention are each 1 × 10
¹⁹ atoms / cc or less, preferably 5 × 10 ¹⁸ atoms
ms / cc or less, and the hydrogen concentration is preferably 0.01 atomic% or more.

It is preferable that the catalyst is heated in a hydrogen-based gas atmosphere before supplying the raw material gas. This is because if the catalyst is heated before the supply of the raw material gas, the constituent materials of the catalyst are released and may be mixed into the formed film, but the catalyst is heated in a hydrogen-based gas atmosphere. This can eliminate such mixing. Therefore, it is preferable to heat the catalyst in a state where the film formation chamber is filled with a hydrogen-based gas, and then supply a source gas (a so-called reaction gas) using the hydrogen-based gas as a carrier gas.

In the catalytic AHA treatment, the amorphous component in the lower crystalline semiconductor thin film is removed by etching to obtain a high crystallization ratio and a large grain size (particularly, a grain size of several hundred nm).
The above is a process of obtaining a thin film based on polycrystal and activating the carrier impurities in the film. At this time, the catalyst temperature is 1600 to 1800 ° C., and the distance between the substrate and the catalyst is 20 to It may be arbitrarily changed in order to improve the processing effect such as shortening the processing time by 50 mm.

With the polycrystalline semiconductor thin film obtained by the catalytic AHA treatment, a channel, a source and a drain region, a wiring, a resistor, a capacitor, an electron emitter and the like of a MOSTFT can be formed. In this case, after the formation of the channel, source and drain regions, if these regions are subjected to the catalytic AHA treatment, the above-mentioned n-type or p-type impurities can be activated.

Further, in order to reduce the invasion of oxygen from the outside into the polycrystalline semiconductor thin film such as polycrystalline silicon, the crystal grain size is reduced from inside to outside in the polycrystalline silicon film or the like. It is preferable to cover the polycrystalline semiconductor thin film with an amorphous semiconductor film such as amorphous silicon or a fine grain size layer and an amorphous semiconductor film such as amorphous silicon. In this case, general-purpose photolithography and etching technology
A source in which the fine grain size layer or the amorphous semiconductor film is removed and the large grain size layer (the polycrystalline semiconductor thin film) is contacted;
A drain electrode can be formed.

The present invention relates to a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated device. Circuit device, liquid crystal display device, organic or inorganic electroluminescence (EL) display device, field emission display (FE)
D) It is suitable for forming thin films for devices, light-emitting polymer displays, light-emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, and solar cell devices.

In this case, at the time of manufacturing a semiconductor device having an internal circuit and a peripheral circuit, a solid-state image pickup device, an electro-optical device, etc., the channel, source and drain regions of the MOSTFT constituting at least a part of these devices are made of the polycrystalline semiconductor. It may be formed of a thin film, or may be a structure integrated with a peripheral driving circuit.

Further, under the organic or inorganic electroluminescent layer (EL layer) for each color,
An EL element structure having a cathode or an anode connected to the drain or the source of the TFT is preferable.

In this case, if the cathode also covers the active elements such as the MOSTFT and the diode, the light emitting area is increased in the structure having the anode on the upper part, and the light is emitted by the active element by the light shielding effect of the cathode. To generate a leak current. Further, if the cathode or the anode is attached to each of the organic or inorganic EL layers for the respective colors and the entire surface between the respective layers, the organic EL which is vulnerable to moisture is covered by the entire surface with the cathode or the anode. Long life, high quality, and high reliability can be prevented by preventing layer deterioration and electrode oxidation. Also, when covered with the cathode, the heat dissipation effect is enhanced, so the structural change of the thin film due to heat generation (melting or recrystallization) , And a long life, high quality, and high reliability can be achieved. Further, since a high-precision, high-quality, full-color organic EL layer can be formed with high productivity, the cost can be reduced.

The organic or inorganic EL for each of the colors
When a black mask layer of chromium, chromium dioxide, or the like is formed between layers, light leakage between colors or between pixels is prevented, and contrast is improved.

When the present invention is applied to a field emission display (FED) device, the emitter (field emission cathode) is connected to the drain of the MOSTFT via the polycrystalline semiconductor thin film and It is preferably formed by an n-type polycrystalline semiconductor film or a polycrystalline diamond film grown on a thin film.

In this case, a metal shielding film having a ground potential is formed on the active element such as the MOSTFT and the diode by using the same material and the same process as the gate lead electrode of the FED device. In this case, the gas in the hermetic container is positively ionized by the electrons emitted from the emitter and charged up on the insulating layer, and this positive charge is unnecessary for the active element below the insulating layer to invert the inversion. A runaway of an emitter current caused by forming a layer or an excess current flowing through the inversion layer can be prevented. Also, when the phosphor emits light due to the collision of electrons emitted from the emitter, this light causes TF
It is also possible to prevent generation of electrons and holes in the T gate channel to cause a leak current.

Next, preferred embodiments of the present invention will be described in more detail.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS.

In this embodiment, a top gate type polycrystalline silicon CMOS (Complementary MOS) T
This is applied to FT.

<Catalytic CVD Method and Apparatus> First, the catalytic CVD method and the catalytic AHA treatment used in the present embodiment will be described. In the catalytic CVD method, a reactive gas composed of a hydrogen-based carrier gas and a raw material gas such as silane gas is brought into contact with a heated catalyst such as tungsten, and the radical deposition species or its precursor generated thereby and activated hydrogen ions are generated. Giving high energy to hydrogen-based active species such as
A low-crystalline semiconductor thin film such as microcrystalline silicon containing amorphous silicon is vapor-phase grown on a substrate. Then, after the film formation, the supply of the source gas is stopped and only the hydrogen-based carrier gas is supplied to perform the catalytic AHA treatment of the lower crystalline semiconductor thin film (that is, high-temperature hydrogen molecules, hydrogen atoms, activated hydrogen, etc.). The amorphous silicon is reduced and etched by hydrogen-based active species such as ions), and the catalytic AHA treatment and the catalytic CVD are repeated to obtain a polycrystalline semiconductor thin film such as polycrystalline silicon having a predetermined thickness. .

The catalytic CVD and the catalytic AHA treatment are carried out using an apparatus as shown in FIGS.

According to this apparatus, a hydrogen-based carrier gas and a source gas 40 such as silicon hydride (for example, monosilane) are used.
A gas composed of a doping gas such as B ₂ H ₆ or PH ₃ (if necessary) is supplied from a supply conduit 41 through a supply port (not shown) of a shower head 42 to form a film formation chamber 44.
Is introduced to Inside the film forming chamber 44, a susceptor 45 for supporting the substrate 1 such as glass, and a shower head 42 having good heat resistance (preferably made of a material having a melting point equal to or higher than that of the catalyst body 46) are provided. For example, a coiled catalyst body 46 such as tungsten and a shutter 47 that can be opened and closed are provided. Although not shown, a magnetic seal is provided between the susceptor 45 and the film forming chamber 44, and the film forming chamber 44 follows the front chamber for performing the pre-process, and is provided via a valve by a turbo molecular pump or the like. Exhausted.

The substrate 1 is heated by a heating means such as a heater wire in the susceptor 45, and the catalyst body 46 is, for example, a resistance wire having a melting point or less (especially 800 to 2000 ° C., and about 1600 to 1800 ° C. for tungsten). Is activated by heating. Both terminals of the catalyst body 46 are connected to a DC or AC catalyst power supply 48, and are heated to a predetermined temperature by energization from the power supply.

In order to carry out the catalytic CVD method, the degree of vacuum in the film forming chamber 44 is set to 1.33 × 10 ^{−4 to} 1.3 in the state shown in FIG.
3 × 10 ⁻⁶ Pa, for example, a hydrogen-based carrier gas 100
２００200 SCCM is supplied and the catalyst is heated to a predetermined temperature to activate the catalyst, and then silicon hydride (for example, monosilane) gas 1-20 SCCM (and B ₂ H if necessary)
₆ and also includes an appropriate amount doping gas such as PH _3. ) Is introduced from the supply conduit 41 through the supply port 43 of the shower head 42 to reduce the gas pressure to 0.133 to 1
The pressure is set to 3.3 Pa, for example, 1.33 Pa. Here, the hydrogen-based carrier gas may be any gas such as hydrogen, hydrogen + argon, hydrogen + helium, hydrogen + neon, hydrogen + xenon, hydrogen + krypton, which is a gas obtained by mixing an appropriate amount of an inert gas with hydrogen. Good (hereinafter the same). Note that the hydrogen-based carrier gas is not necessarily required depending on the type of the source gas.

Then, as shown in FIG. 6, the shutter 47 is opened, and at least a part of the raw material gas 40 is brought into contact with the catalyst body 46 to be catalytically decomposed. A group of reactive species such as ions and radicals (ie, deposited species or a precursor thereof and radical hydrogen ions) is formed. The reactive species 50 such as ions and radicals generated in this manner are vapor-phase grown with high energy on the substrate 1 maintained at 200 to 800 ° C. (for example, 300 to 400 ° C.) as a predetermined film such as amorphous silicon-containing microcrystalline silicon. .

Thus, without generating plasma,
Since the catalytic action of the catalyst body 46 and the energy by the thermal energy are given to the reactive species, the reactive gas can be efficiently converted to the reactive species and uniformly deposited on the substrate 1 by thermal CVD.

Even if the substrate temperature is lowered, the energy of the deposited species is large, so that a desired high-quality film can be obtained. Therefore, the substrate temperature can be further lowered as described above.
A large and inexpensive insulating substrate (a glass substrate such as borosilicate glass or aluminosilicate glass, a heat-resistant resin substrate such as polyimide, etc.) can be used, and the cost can be reduced in this regard.

Needless to say, since no plasma is generated, there is no damage by the plasma, a low stress generated film can be obtained, and a much simpler and less expensive device can be realized as compared with the plasma CVD method. I do.

In this case, under reduced pressure (for example, 0.133
The operation can be performed at 1.33 Pa) or normal pressure, but a simpler and cheaper device is realized with the normal pressure type than with the reduced pressure type. And even the normal pressure type, the conventional normal pressure CVD
A high quality film having better density, uniformity and adhesion can be obtained. Also in this case, the normal pressure type has higher throughput, higher productivity, and cost reduction than the reduced pressure type.

In the above-described catalytic CVD, the substrate temperature rises due to the auxiliary heat generated by the catalyst body 46. However, as described above, the substrate heating heater 51 may be provided as necessary. Further, the catalyst body 46 has a coil shape (a mesh, a wire, or a perforated plate may be used in addition to the above shape). Is good. In this CVD, since the substrate 1 is disposed above the shower head 42 on the lower surface of the susceptor 45, particles generated in the film forming chamber 44 may fall and adhere to the substrate 1 or a film thereon. There is no.

<Catalyst AHA Treatment and its Apparatus> In the present embodiment, the above apparatus is used as it is, and after the vapor phase growth of a low crystalline semiconductor thin film such as amorphous silicon-containing microcrystalline silicon by catalytic CVD, monosilane is removed. Supply of only a hydrogen-based carrier gas into the film forming chamber 44 at a higher flow rate than during the catalytic CVD to perform the catalytic AHA treatment on the lower crystalline semiconductor thin film. Annealing for crystallization is performed, and the catalytic CVD and the catalytic AHA treatment are repeated a predetermined number of times to form a polycrystalline semiconductor thin film such as polycrystalline silicon having a desired film thickness.

In this catalytic AHA treatment, the amorphous component in the lower crystalline semiconductor thin film is removed by etching with the hydrogen-based active species decomposed and generated by the heated catalyst to obtain a high crystallization ratio and a large grain size (particularly, a grain size). Is several hundred n
m or more) to obtain a polycrystalline-based thin film and activate carrier impurities in the film. At this time, the catalyst temperature is 1600 to 1800 ° C., and the distance between the substrate and the catalyst is 20 to 50 mm, the substrate temperature is 200 to 800 ° C., the processing time is 10 to 20 minutes, and the hydrogen-based carrier gas is hydrogen or hydrogen and an inert gas (argon, helium, xenon, krypton, radon, etc.) as described above. And in the case of a mixed gas, the hydrogen content ratio is 50%.
When the content is at least mol%, oxidation deterioration of the catalyst body can be prevented. Further, the hydrogen or the hydrogen-containing gas used in the catalyst AHA treatment may be the same as the hydrogen-based carrier gas used in the vapor phase growth, but the gas flow rate is increased to 300 to 1000 SCCM and the gas pressure is increased to 10 to 50 Pa (for catalytic CVD). 0.1 to several Pa), it is preferable to increase the heat conduction by the gas and increase the amount of radical hydrogen ions generated.

FIG. 7 shows the introduction time and timing of the hydrogen-based carrier gas and the source gas in the above-mentioned catalytic CVD and catalytic AHA processing in the case of forming a polycrystalline silicon thin film, and FIG. 8 shows a flow meter (MFC). Shows a gas introduction system that incorporates a control valve.

First, before forming a film, the substrate 1 is loaded into a chamber (film forming chamber) 44 through a gate valve and placed on a susceptor 45, and then the exhaust system is operated to urge the inside of the chamber 44 to a predetermined level. Exhaust to the pressure and
The substrate 1 is heated to a predetermined temperature by operating a heater incorporated in the substrate 5.

Then, depending on the gas introduction system, first, a hydrogen-based carrier gas of 300 to 1000 SCCM, for example, 500
The SCCM is introduced into the chamber 1. A part of the introduced hydrogen gas becomes a hydrogen-based active species such as activated hydrogen ions by a catalytic decomposition reaction by the heating catalyst 46, reaches the substrate surface, and cleans the surface of the substrate 1. Thereafter, the hydrogen-based carrier gas is set to 150 SCCM.

As described above, while the hydrogen-based carrier gas is being supplied into the chamber 44, the gas introduction system is operated, and the raw material gas (monosilane 15 SCCM) is supplied to the chamber 4.
4 is introduced. The introduced raw material gas is used as the heating catalyst 4
The deposited species are generated by the thermal catalytic reaction and the thermal decomposition reaction of No. 6, and are vapor-phase grown on the substrate surface as an amorphous silicon-containing microcrystalline silicon thin film or the like.

Thereafter, the introduction of the source gas is stopped, the source gas is discharged from the chamber 44, and only the hydrogen-based carrier gas is supplied at 300 to 1000 SCCM, for example, 500 S
Hydrogen-based active species such as active hydrogen ions generated by the catalytic cracking reaction by the heated catalyst act on the lower crystalline silicon thin film such as the above amorphous silicon-containing microcrystalline silicon thin film. This is etched and changed into silicon (polycrystallized) from which the amorphous component has been removed.

The above-mentioned catalytic CVD is performed again on the silicon film subjected to the catalytic AHA treatment, a polycrystalline silicon thin film is grown thereon using polycrystalline silicon as a seed, and the catalytic AHA treatment and catalytic CVD are repeated. By doing so, a polycrystalline silicon thin film having a high crystallization ratio and a large grain size can be finally formed with a desired film thickness while controlling the film thickness of the polycrystalline silicon thin film.

As described above, due to the radical action of the hydrogen-based active species, thermal energy moves to the film and locally raises the temperature. As a result, the amorphous component of the lower crystalline semiconductor thin film is etched, and crystallization is promoted. A polycrystalline film having a large grain size, and reducing the crystal irregularity and internal stress existing at the crystal grain boundaries, can obtain a high mobility, high quality polycrystalline semiconductor thin film, and furthermore, polycrystalline silicon or When silicon oxide is present on or in a microcrystalline silicon film, a reduction reaction is performed with the silicon oxide to generate SiO or the like and evaporate the silicon oxide, so that the silicon oxide on or in the film is reduced / removed. Thus, a high-carrier mobility, high-quality polycrystalline silicon film or the like can be obtained.

Recrystallization of a microcrystalline silicon-containing amorphous silicon film, an amorphous silicon-containing microcrystalline silicon film, and the like is promoted by using the microcrystalline silicon as a seed, and a large grain polycrystalline silicon film is formed. Moreover, since the amorphous silicon contained in the film is reduced (etched) by active hydrogen ions or the like, a polycrystalline film having a high crystallization ratio is formed.

During the catalytic AHA treatment, the carrier impurities present in the lower crystalline semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration can be obtained in each region. Cleaning by hydrogen atoms and activated hydrogen ions (reduction and removal of adsorbed gas and organic residue on a substrate or the like) is possible, and the catalyst body is also oxidized and deteriorated. Further, hydrogenation causes, for example, silicon dang in a semiconductor film. Eliminates ring bonds and improves properties.

By repeating the annealing by the catalytic AHA treatment and the vapor-phase growth of the lower crystalline semiconductor thin film by catalytic CVD until the target film thickness is obtained, the semiconductor thin film has already been polycrystallized by the catalytic AHA treatment. It is easy to grow on the base film in a state of being easily polycrystallized, and a desired high crystallization ratio and high quality polycrystalline semiconductor thin film can be obtained with a predetermined thickness. That is, catalytic CVD and catalytic AHA
By the multi-catalyst AHA treatment which repeats the treatment, for example, a microcrystalline silicon-containing amorphous silicon film, amorphous silicon and microcrystalline silicon-containing polycrystalline silicon formed by catalytic CVD are converted into a polycrystalline silicon film by the catalytic AHA treatment. Since the vapor phase growth of a polycrystalline silicon film and the catalytic AHA treatment are repeated by catalytic CVD using polycrystalline silicon as a seed, a polycrystalline silicon film having a high crystallization rate and a large grain size can be formed. .

Since both the above-described catalytic CVD and catalytic AHA treatment can be performed without generating plasma, a plasma-damage-free, low-stress formed film can be obtained, and the method is simpler and less expensive than the plasma CVD method. Device can be realized.

FIG. 9 shows the Raman spectrum of the polycrystalline silicon thin film obtained by the above-described multi-catalyst AHA treatment (repetition of catalytic CVD and catalytic AHA treatment) according to the present embodiment according to the number of repetitions and the like. is there. According to this result, the gas flow rate during the deposition (depo) of amorphous silicon by catalytic CVD was set to SiH ₄ : H ₂ = 5: 5.
00SCCM, catalyst temperature = 1800-2000 ° C., substrate temperature = 400 ° C., various conditions for the catalyst AHA treatment and the number of repetitions were changed, the number of repetitions was increased, and the processing time was increased. When the H ₂ flow rate is increased, samples # 1 → # 2 → # 3 → # 4
It is clear that amorphous (amorphous) and microcrystals decrease and the polycrystalline layer increases (that is, the grain size increases and the crystallinity increases). Here, AHA1 is a cleaning treatment of the substrate surface before film formation, and the original catalytic AHA treatment is AHA2-4.

FIG. 10 shows the crystallization ratio of each sample in comparison with the presence or absence of microcrystals in polycrystalline silicon. According to this, it can be seen that the crystallization ratio increases in the order of samples # 1 → # 2 → # 3 → # 4, and that the underlayer containing microcrystals (Im) increases.

These results show that the treatment according to the present invention is a very excellent method for forming a polycrystalline semiconductor thin film having a high crystallization rate and a large grain size.

In the present embodiment, in the above-described catalytic CVD, the purity of the catalyst body of, for example, a 0.4 mmφ tungsten wire and the support of the, eg, 0.8 mmφ molybdenum wire (not shown) supporting the same are determined. Although there is a problem, the conventional purity: 3N (99.9 wt%) is changed to 4N.
(99.99 wt%) or more, preferably 5N (99.9 wt%).
99 wt%) or higher,
It has been demonstrated that heavy metal contamination such as iron, nickel, and chromium in a polycrystalline silicon film by catalytic CVD can be reduced. FIG. 11 (A) shows the concentration of heavy metals such as iron, nickel and chromium in the film at a purity of 3N. By increasing this to 5N, heavy metals such as iron, nickel and chromium as shown in FIG. It has been found that the concentration can be significantly reduced. Thereby, the TFT characteristics can be improved.

<Manufacture of Top Gate Type CMOS TFT>
Next, an example of manufacturing a top gate type CMOS TFT using the multi-catalyst AHA process according to the present embodiment will be described.

First, as shown in FIG. 1A, at least TF of an insulating substrate 1 made of quartz glass, crystallized glass or the like is used.
Plasma CVD, catalytic CVD, reduced pressure CV in T formation area
A protective film 100 composed of a laminated film of a protective silicon nitride film and a silicon oxide film is formed under the following conditions by a vapor phase growth method such as D (the same applies hereinafter).

In this case, a glass material is selectively used depending on the process temperature of TFT formation. In the case of a low temperature of 200 to 500 ° C .: a glass substrate (500 × 600 × 0.5) of borosilicate, aluminosilicate glass, etc.
~ 1.1 µm thick), and a heat-resistant resin substrate may be used. In the case of a high temperature of 600 to 1000 ° C .: a heat-resistant glass substrate (6 to 12 inches φ, 70
0-800 μm thick). The silicon nitride film for the protective film is formed to stop Na ions from the glass substrate, but is not required when using synthetic quartz glass.

When the catalytic CVD is used, the same apparatus as shown in FIGS. 5 and 6 can be used. However, in order to prevent the catalytic body from being oxidized and deteriorated, a hydrogen-based carrier gas is supplied to remove the catalytic body. It is necessary to heat to a predetermined temperature (about 1600 to 1800 ° C., for example, about 1700 ° C.), and after forming the film, cool the catalyst to a temperature at which there is no problem to cut off the hydrogen-based carrier gas.

The film forming conditions are as follows. A hydrogen-based carrier gas (hydrogen, argon + hydrogen, helium + hydrogen,
Neon + hydrogen, etc.) is constantly flowed, and the flow rate, pressure, and susceptor temperature are controlled to the following predetermined values. Chamber pressure: about 1 to 15 Pa, for example, 10 Pa Susceptor temperature: 300 ° C. Hydrogen-based carrier gas flow rate (in the case of mixed gas, hydrogen is 20
３０30%): 150 SCCM

The silicon nitride film has a thickness of 50
It is formed to a thickness of 200 nm. Of H ₂ as a carrier gas, formed monosilane (SiH ₄₎ as a source gas and ammonia (NH ₃₎ were mixed in an appropriate amount ratio. H ₂ flow rate: 15
0 SCCM, SiH ₄ flow rate: 15 SCCM, NH ₃ flow rate:
50 SCCM

The silicon oxide film has a thickness of 50
It is formed to a thickness of about 100 nm. H ₂ as carrier gas,
As a raw material gas, it is formed by mixing He diluted O ₂ with monosilane (SiH ₄ ) at an appropriate ratio. H ₂ flow rate: 150 SCCM,
SiH ₄ flow rate: 15 SCCM, He diluted O ₂ flow rate: 1-2
SCCM

Next, as shown in FIG. 1 (2), the multi-catalyst AHA treatment according to the present invention allows, for example, a group IV element of the periodic table, for example, tin to be 10 ¹⁸ to 10 ²⁰ atoms / c.
c-doped polycrystalline silicon film 7 (which may be doped by CVD or by ion implantation after film formation).
It is formed to a thickness of 0 nm. However, this tin doping is not always necessary (the same applies hereinafter).

In this case, for example, tin-doped lower crystalline silicon as a lower crystalline semiconductor thin film is vapor-phase grown by the above-described catalytic CVD under the following conditions using the apparatus shown in FIG. 5 and FIG. Under the following conditions, the catalyst AHA treatment is performed and annealing is performed to polycrystallize the lower crystalline silicon, and the catalyst CVD and the catalyst AHA treatment are repeated to form a polycrystalline silicon film 7 having a thickness of 50 nm. For example, a film having a thickness of 10 to 30 nm is grown by catalytic CVD, a film having a thickness of 10 to 30 nm is grown by catalytic CVD after catalytic AHA treatment, and a film having a thickness of 10 to 30 nm is further treated by catalytic CVD.
A film having a thickness of about 30 nm is grown to finally obtain a polycrystalline silicon film having a desired film thickness.

Film formation of amorphous silicon-containing microcrystalline silicon by catalytic CVD: H ₂ as carrier gas, monosilane (SiH ₄ ), tin hydride (SnH ₄ ) as source gas
Is formed by mixing at appropriate ratios. H ₂ flow rate: 150 SCC
M, SiH ₄ flow rate: 15 SCCM, SnH ₄ flow rate: 15 S
CCM. At this time, by mixing an appropriate amount of n-type phosphorus, arsenic, antimony, or the like, or a suitable amount of p-type boron, etc., into a silane-based gas (silane, disilane, trisilane, or the like) as a raw material gas, Alternatively, a tin-containing silicon film having a p-type impurity carrier concentration may be formed. For n-type: PH ₃ (phosphine), AsH ₃ (arsine), SbH ₃ (stibine) For p-type: B ₂ H ₆ (diborane)

Catalytic AHA treatment: Catalytic AHA treatment is a method in which a raw material gas is not supplied in catalytic CVD. Specifically, a hydrogen-based carrier gas is supplied at a gas flow rate of 30 under reduced pressure.
The catalyst is heated to a predetermined temperature (about 1600 to 1800 ° C., for example, about 1700 ° C.) by supplying the catalyst at a temperature of 0 to 1000 SCCM and a gas pressure of 10 to 50 Pa, and the high temperature hydrogen molecule / hydrogen atom /
Activated hydrogen ions are generated and sprayed onto a microcrystalline silicon film containing, for example, tin-containing amorphous silicon formed on a substrate. As a result, the thermal energy of the high-temperature hydrogen molecules / hydrogen atoms / activated hydrogen ions is transferred to those films to increase their film temperatures, and the tin-containing amorphous silicon-containing microcrystalline silicon film is crystallized, The microcrystalline silicon (or polycrystalline silicon film) is recrystallized to form a tin-containing polycrystalline silicon film having a large grain size, reducing irregularities and stress existing at the crystal grain boundaries, and having high carrier mobility and high carrier mobility. A high-quality polycrystalline silicon film can be formed.

The above-mentioned hydrogen-based active species, when silicon oxide is present on or in a film of microcrystalline silicon or the like, undergoes a reduction reaction to generate SiO or the like and evaporates it. Silicon oxide on or in the film can be reduced / removed, and a high mobility and high quality polycrystalline silicon film can be formed. When this catalytic AHA treatment is performed after the formation of the gate channel / source / drain described later, the thermal energy of the high-temperature hydrogen molecules / hydrogen atoms / activated hydrogen ions is transferred to the films, raising the film temperatures. At the same time as crystallization is promoted, carrier impurities (phosphorus, arsenic, boron ions, etc.) are injected into the gate channel / source / drain and activated.

When each of the above films is formed in the same chamber, a hydrogen-based carrier gas is constantly supplied, the catalyst is heated to a predetermined temperature, and a standby is performed. Good.

Ammonia is mixed with monosilane at an appropriate ratio to form a silicon nitride film having a predetermined thickness. After sufficiently exhausting the previous source gas, monosilane and He-diluted O ₂ are continuously mixed at an appropriate ratio. After a silicon oxide film having a predetermined thickness is formed and the previous source gas and the like are sufficiently discharged, monosilane and SnH ₄ are continuously mixed at an appropriate ratio to form a microcrystalline silicon containing tin-containing amorphous silicon having a predetermined thickness. After the film is formed and the previous source gas is sufficiently discharged, the source gas is continuously cut to form a polycrystalline silicon film by catalytic AHA treatment, and the previous source gas is sufficiently discharged as necessary. After that, monosilane and He diluted O ₂ are continuously mixed at an appropriate ratio to form a silicon oxide film having a predetermined thickness. After the film formation, the raw material gas is cut, and the catalyst body is cooled to a temperature at which there is no problem to cut the hydrogen-based carrier gas. At this time, the slope of the source gas at the time of forming the insulating film may be decreased or increased to form an inclined junction insulating film.

Alternatively, when the chambers are formed in independent chambers, a hydrogen-based carrier gas may be constantly supplied into each chamber, the catalyst may be heated to a predetermined temperature, and a standby may be performed. . The wafer is transferred to the chamber A, and ammonia is mixed with monosilane in an appropriate ratio to form a silicon nitride film having a predetermined thickness. Next, the chamber is moved to the B chamber, and He-diluted O ₂ is mixed with monosilane at an appropriate ratio to form a silicon oxide film. Next, the mixture is transferred to the C chamber, and monosilane and SnH ₄ are mixed at an appropriate ratio to form a tin-containing amorphous silicon-containing microcrystalline silicon film, and the catalyst AH is continuously (or in another chamber) using a hydrogen-based carrier gas.
A process forms a polycrystalline silicon film. Then, if necessary, transfer to the B chamber and add He diluted O _{2 to} monosilane.
Are mixed at an appropriate ratio to form a silicon oxide film. After the film formation, the raw material gas is cut, and the catalyst body is cooled to a temperature at which there is no problem to cut the hydrogen-based carrier gas. At this time, the hydrogen-based carrier gas and the respective source gases may be constantly supplied into the respective chambers so as to be in a standby state.

Then, a MOSTFT using the polycrystalline silicon film 7 as a source, a channel and a drain region is manufactured.

That is, as shown in (3) of FIG. 2, after the polycrystalline silicon film 7 is formed into islands by general-purpose photolithography and etching, the threshold (V _th) by controlling the impurity concentration of the channel region for the nMOS TFT is obtained. In order to optimize), the pMOSTFT part is replaced with a photoresist 9
Masked by ion implantation or ion doping.
Type impurity ions (for example, boron ions) 10
Doping is performed at a dose of × 10 ¹¹ atoms / cm ² , the acceptor concentration is set to 1 × 10 ¹⁷ atoms / cc, and the conductivity of the polycrystalline silicon film 7 is changed to a p-type polycrystalline silicon film 11. .

Next, as shown in FIG.
In order to optimize V _th by controlling the impurity concentration of the channel region for the OSTFT, the nMOSTFT portion is masked with a photoresist 12 and n-type impurity ions (for example, phosphorus ions) 13 are ion-implanted or ion-doped.
Is doped at a dose of 1 × 10 ¹² atoms / cm ² , for example, is set to a donor concentration of 2 × 10 ¹⁷ atoms / cc, and the conductivity type of the polycrystalline silicon film 7 is changed to n-type. It is assumed to be 14.

Next, as shown in FIG. 3 (5), if necessary, the above-mentioned catalytic AHA treatment is performed to promote crystallization and activate impurities in the film, and then the gate insulating film is subjected to catalytic CVD or the like. After forming a silicon oxide film (50 nm thick) 8 of phosphorus, a phosphorus-doped polycrystalline silicon film 15 as a gate electrode material is formed on PH ₃ and 20 of 2 to 20 SCCM, for example.
Catalyst C as above under SCCM monosilane feed
It is deposited to a thickness of, for example, 400 nm by the VD method.

Next, as shown in FIG. 3 (6), a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the phosphorus-doped polycrystalline silicon film 15 is patterned into a gate electrode shape. After removing the photoresist 16, as shown in FIG. 3 (7), a silicon oxide film 17 as a gate electrode protective film is formed to a thickness of 20 to 30 nm by, for example, catalytic CVD.

Next, as shown in (8) of FIG.
The OSTFT portion is masked with a photoresist 18 and, for example, phosphorus ions 19 which are n-type impurities are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms / cm ^2.
2 × 10 ²⁰ atoms / c
By setting the donor concentration to c, the n ⁺ -type source region 20 and the drain region 21 of the nMOS TFT are formed.

Next, as shown in FIG.
The OSTFT portion is masked with a photoresist 22, and a p-type impurity, for example, boron ion 23 is ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms / c.
doping with a dose of m ² , 2 × 10 ²⁰ atoms
/ Cc, the acceptor concentration is set to
^{A +} type source region 24 and a drain region 25 are formed respectively.

The gate, the source and the drain are formed in this manner, and these can be formed by a method other than the above-described process.

That is, after the step (2) in FIG. 1, the polycrystalline silicon film 7 is made into islands in pMOSTFT and nMOSTFT regions, and n-type impurities, for example, phosphorus ions are implanted into the pMOSTFT region by ion implantation or ion doping.
Doping at a dose of 10 ¹² atoms / cm ² ,
A donor concentration of 2 × 10 ¹⁷ atoms / cc was set, and n
The MOSTFT region is doped with a p-type impurity, for example, boron ion at a dose of 5 × 10 ¹¹ atoms / cm ² , set to an acceptor concentration of 1 × 10 ¹⁷ atoms / cc, and controlling the impurity concentration of each channel region. V _th is optimized.

Then, each source / drain region is formed by a general-purpose photolithography technique using a photoresist mask. In the case of an nMOS TFT, an n-type impurity such as arsenic is ion-implanted or ion-doped.
Phosphorus ions are doped at a dose of 1 × 10 ¹⁵ atoms / cm ² and a donor concentration of 2 × 10 ²⁰ atoms / cc is set. In the case of a pMOS TFT, a p-type impurity such as boron Is doped at a dose of 1 × 10 ¹⁵ atoms / cm ² to set an acceptor concentration of 2 × 10 ²⁰ atoms / cc.

After that, if necessary, a catalyst AHA treatment is performed to activate the impurities in the film, and then a silicon oxide film is formed as a gate insulating film. A silicon oxide film is formed. That is,
If necessary, continuously perform catalytic CVD after catalytic AHA treatment.
He-diluted O ₂ is mixed with hydrogen-based carrier gas and monosilane at an appropriate ratio by a suitable
A silicon nitride film is formed to a thickness of 10 to 20 nm by mixing NH ₃ with a hydrogen-based carrier gas and monosilane at an appropriate ratio, if necessary, and a silicon oxide film is formed to a thickness of 20 to 30 nm under the above conditions. It is formed thick.

Next, as shown in FIG. 4 (10), by using the same catalytic CVD method as described above, a hydrogen-based carrier gas of 150
The silicon oxide film 26 is formed, for example, by supplying O ₂ diluted with helium gas of M and monosilane of 15 to ₂₀ SCCM to 100 to 100 SCCM.
To 200nm thickness, 1~20SCCM of PH _3, 1~2S
Phosphine silicate glass (PS) under helium-diluted O ₂ of CCM and monosilane supply of 15-20 SCCM
G) The film 27 is formed to a thickness of 300 to 400 nm,
The silicon nitride film 28 is, for example, 100 to 200 n under the supply of NH ₃ at 0 SCCM and monosilane at 15 to 20 SCCM.
m, and a laminated insulating film is formed. Thereafter, for example, RTA (Rapid Therma) at about 1000 ° C. for 20 to 30 seconds.
(l Anneal) treatment to activate the ions to set the carrier impurity concentration in each region.

Then, as shown in FIG. 4 (11), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum containing 1% Si is sputtered on the entire surface including each contact hole by sputtering or the like. Is deposited to a thickness of 1 μm at 150 ° C., and is patterned to form a source or drain electrode 29 (S or D) and a gate extraction electrode or wiring 30 for each of the pMOSTFT and nMOSTFT.
(G) is formed, and each top gate type CMOSTFT is formed. After this, 400 ° C. in a forming gas,
Hydrogenate and sinter for 1 h. Incidentally, an aluminum compound gas (for example, AlCl ₃ ) is formed by the catalytic CVD method.
May be supplied to form aluminum.

Note that, instead of forming the above gate electrode,
Sputtered film of heat-resistant metal such as Mo-Ta alloy (4
(Thickness: 500 to 500 nm), and the nMOSTFT and pM
A gate electrode of the OSTFT may be formed.

For reference, the liquid phase growth method of the silicon alloy melt and the catalytic AHA treatment will be described with reference to a method of manufacturing a top gate type polycrystalline silicon CMOS TFT. After growing (precipitating) a microcrystalline silicon layer containing amorphous silicon (hereinafter referred to as an example containing tin), a low-melting-point metal film such as tin thereon is removed. A low melting metal melt such as tin containing silicon is applied and cooled. It is immersed in a low melting metal melt such as tin containing silicon, pulled up and cooled. A low melting point metal film such as tin containing silicon is melted by heating and cooled. Form a low melting metal film such as tin on the silicon film,
Heat and melt and cool. A silicon film is formed on a low melting point metal film such as tin, and is heated and melted and cooled.

Next, the amorphous silicon-containing microcrystalline silicon layer containing or not containing tin was made into islands,
_Vth is optimized by controlling the impurity concentration of the channel region by ion implantation or ion doping method by dividing into a MOSTFT portion and an nMOSTFT portion (conditions conform to those described above). Thereafter, the source and drain of the pMOSTFT portion and the nMOSTFT portion are formed by ion implantation or ion doping (the conditions are the same as those described above).

Next, crystallization promotion and ion activation are carried out by the catalytic AHA treatment (conditions are the same as those described above). A silicon oxide film as a gate insulating film is successively formed by catalytic CVD. If necessary, a silicon nitride film and a silicon oxide film are successively formed (film formation conditions are as described above). Subsequent processes are the same as those described above. The method using the liquid phase growth method is described in the bottom gate type and dual gate type CMO described below.
The same applies to STFT and the like.

An example of a method of manufacturing a top gate type polycrystalline silicon CMOS TFT to which a catalytic AHA treatment of a sputtering film is applied will be described. First, tin is 0.1 to 1 at%.
A silicon target containing or not containing is sputtered in a vacuum of 0.133 to 1.33 Pa of argon gas to form a silicon target at least on a TFT forming region of an insulating substrate.
A 0 nm thick amorphous silicon film containing, for example, tin-containing or non-containing microcrystalline silicon is formed.

Then, the formed amorphous silicon film containing tin or non-containing microcrystalline silicon is made into islands and divided into a pMOSTFT portion and an nMOSTFT portion (conditions are the same as in the case of the vapor phase growth method). Thereafter, a gate channel, a source, and a drain are formed (the conditions are the same as in the case of the vapor phase growth method).

Next, the amorphous silicon film containing microcrystalline silicon containing or not containing tin is subjected to catalytic AHA treatment.
By this catalytic AHA treatment, a polycrystalline silicon film is formed, and ion-implanted or ion-doped n-type or p-type impurities are activated to form optimal carrier impurity concentrations in the gate channel, source and drain regions (catalyst AHA
The processing conditions are as described above.

Next, a silicon oxide film is formed as a gate insulating film. If necessary, a silicon nitride film and a silicon oxide film are formed successively. That is, by a catalytic CVD method or the like, the silicon oxide film is 40 to 50 nm thick, the silicon nitride film is 10 to 20 nm thick, and the silicon oxide film is 40 to 5 nm.
A film is continuously formed to a thickness of 0 nm (film forming conditions are as described above).

The subsequent processes are the same as those described above. In addition, a method using this sputtering film is described below in a bottom gate type, dual gate type CMOS TFT.
And the like may be similarly applied.

As described above, according to the present embodiment,
The following excellent effects (a) to (h) can be obtained.

(A) Under reduced pressure (particularly 10 to 50 Pa)
Contacting hydrogen or a hydrogen-containing gas with a high-temperature catalyst (for example, tungsten, 800 to 2000 ° C.) to generate high-temperature hydrogen molecules, hydrogen atoms, and activated hydrogen ions, and to form tin-containing or non-tin formed on the substrate; In particular, the catalyst AHA is sprayed on a lower crystalline silicon film such as a tin-containing amorphous silicon-containing microcrystalline silicon film (substrate temperature 300 to 400 ° C.).
By the treatment, high energy of high-temperature hydrogen molecules, hydrogen atoms, and activated hydrogen ions is transferred to the lower crystalline silicon film, and the film temperature is increased. Further, since amorphous silicon is etched by the reducing action of activated hydrogen ions, the crystallization rate of amorphous silicon-containing microcrystalline silicon is increased, and the carrier mobility is improved. Further, the crystallization rate of amorphous silicon and polycrystalline silicon containing microcrystalline silicon is further increased, and the carrier mobility is improved by increasing the grain size. Furthermore,
By this heating, the TFT characteristics can be improved by ion implantation into the respective regions and activation of the impurities doped with the ions.

(B) When the above-mentioned high-temperature hydrogen molecules, hydrogen atoms, and activated hydrogen ions are sprayed on a film or the like formed on a substrate, when silicon oxide is present on the film, in the film, or at the grain boundary, Since SiO is generated and evaporated by a reduction reaction with this, silicon oxide on or in the polycrystalline silicon film can be reduced / removed, and mobility can be improved.

(C) A vapor phase growth method such as catalytic CVD or plasma CVD, a liquid phase growth method of a silicon alloy melt, a sputtering method or the like, in particular, by catalytic CVD, tin or other IV.
Group elements (eg, lead, germanium), eg, tin, 1 × 1
A low-crystalline silicon film containing 0 ¹⁸ to 1 × 10 ²⁰ atoms / cc is grown.
Since the treatment is repeated, the lower crystalline silicon film is made to be highly crystallized and made to have a large grain size by the catalyst AHA treatment, and polycrystallized.
Polycrystalline silicon is further grown thereon by catalytic CVD in a state where it is easily polycrystallized, so that a desired polycrystalline silicon film having a high crystallization rate and a high quality can be obtained with a predetermined thickness.

(D) When the catalyst AHA treatment is performed after the gate channel / source / drain is formed from the polycrystalline silicon film, the polycrystalline silicon film has a large grain size and the polycrystalline silicon grain boundary The internal stress is reduced by reducing the existing crystal irregularity, and at the same time, the n added to each region is reduced.
Since the p-type or p-type impurities are activated, a polycrystalline silicon film having high carrier mobility can be formed.

(E) When the catalytic AHA treatment is performed after the film formation by the catalytic CVD (or the formation of the gate channel / source / drain thereafter), the type and temperature of the catalyst body,
Depending on the substrate heating temperature, vapor deposition conditions, type of source gas, n or p-type impurity concentration to be added, tin or other group IV elements (lead, germanium) with a wide range of n or p-type impurity concentrations
A containing polycrystalline silicon film can be easily obtained. Further, in the catalytic AHA treatment after the formation of the gate channel / source / drain, the internal stress is reduced by increasing the grain size of the polycrystalline silicon film and reducing the crystal irregularity existing at the polycrystalline silicon grain boundary. Since the n-type or p-type impurity added to the region is activated, the threshold (V _th ) can be easily adjusted with high carrier mobility, and high-speed operation with low resistance can be performed.

In the case of silicon alloy melt liquid phase growth method + gate channel / source / drain formation + catalytic AHA treatment, the silicon alloy composition ratio, melt temperature,
Depending on the cooling method / rate, the added n- or p-type impurity concentration, etc., a wide range or a p-type impurity concentration of tin or other group IV element (lead, germanium) -containing amorphous silicon and microcrystalline silicon-containing polycrystalline silicon film can be obtained. Obtained and
Catalyst AH after gate channel / source / drain formation
A treatment increases the grain size of the polycrystalline silicon film, reduces crystal irregularities existing at the polycrystalline silicon grain boundaries, reduces internal stress, and simultaneously activates n or p-type impurities added to each region. As a result, _Vth adjustment becomes easy with high carrier mobility, and high-speed operation with low resistance becomes possible.

In the case of film formation by plasma CVD + gate channel / source / drain formation + catalytic AHA treatment,
20 to 3 in lower crystalline silicon film by plasma CVD
Hydrogen containing 0% is desorbed by the catalytic AHA treatment to form a polycrystalline silicon film, which reduces crystal irregularities existing at the polycrystalline silicon grain boundaries to reduce internal stress, and simultaneously adds n to each region. Or activate the p-type impurity,
A polycrystalline silicon film with high carrier mobility can be formed. Further, tin or other group IV element having a wide range of n or p-type carrier impurity concentration depending on the substrate heating temperature, vapor deposition conditions, type of source gas, catalyst AHA treatment conditions, n or p-type impurity concentration to be added, etc. Since a (lead, germanium) -containing polycrystalline silicon film is obtained, _Vth adjustment is easy, and high-speed operation with low resistance is possible.

In the case of film formation by sputtering + gate channel / source / drain formation + catalytic AHA treatment,
Depending on the specific resistance of the silicon target (added n or p-type impurity concentration, tin or other group IV element), sputtering film forming conditions, substrate heating temperature, catalytic AHA treatment conditions, etc. Forming a polycrystalline silicon film containing tin or other group IV element (lead, germanium), reducing the crystal irregularity existing at the polycrystalline silicon grain boundary, reducing the internal stress, and simultaneously adding n to each region. Alternatively, since the p-type impurity is activated, _Vth adjustment becomes easy with high carrier mobility, and high-speed operation with low resistance becomes possible.

(F) Since a polycrystalline silicon film having high carrier mobility can be obtained not only in a top gate type but also in a bottom gate type and a dual gate type MOSTFT described later, this high performance polycrystalline silicon semiconductor is used. It is possible to manufacture used high-speed, high-current-density semiconductor devices and electro-optical devices, as well as high-efficiency solar cells and the like.

(G) Since a polycrystalline silicon film can be formed at a low temperature (300 to 400 ° C.), it is possible to use a low strain point glass which is inexpensive and easy to increase in size, and the cost can be reduced.

(H) RT is used to activate n or p-type impurities added to the gate channel / source / drain regions.
A (Rapid Thermal Anneal) or an excimer laser device is not required, and a catalytic CVD device can be used. Therefore, it is possible to reduce capital investment and reduce cost by improving productivity.

Second Embodiment <Manufacturing Example 1 of LCD> In this embodiment, the present invention is applied to an LCD (Liquid Crystal Display) using a polycrystalline silicon MOSTFT by a high-temperature process. An example of the production is shown in FIG. Note that this manufacturing example is based on an organic EL described later.
The present invention can be similarly applied to a display device such as an FED or an FED.

First, as shown in FIG. 12A, in the pixel portion and the peripheral circuit portion, a heat-resistant insulating substrate 61 (strain point of about 800 to 1100) made of quartz glass, crystallized glass or the like is used.
A protective film 100 (not shown here: the same applies hereinafter) is formed on one main surface of the substrate by a catalytic CVD method or the like described above on one main surface of the polycrystalline silicon film 67. Is reduced to 50 n by the multi-catalyst AHA treatment described above.
m thickness.

Next, as shown in FIG. 12B, the polycrystalline silicon film 67 is patterned (islanded) using a photoresist mask, and active elements such as transistors and diodes, resistance, capacitance, inductance, etc. The active layer of the passive element is formed.

Next, the channel of the transistor active layer 67 is
V by controlling the impurity concentration in the tunnel region _thFor optimization
Ion injection of specified impurities such as boron or phosphorus as described above
After the insertion, as shown in (3) of FIG.
Polycrystalline silicon by the same catalytic CVD method as above
For a gate insulating film having a thickness of, for example, 50 nm on the surface of the film 67.
Is formed. The catalyst CVD method etc.
When forming a silicon oxide film 68 for a gate insulating film,
The plate temperature and catalyst body temperature are the same as described above,
Oxygen gas flow rate is 1-2 SCCM, monosilane gas flow rate is
15-20 SCCM, 150 SC hydrogen carrier gas
It may be a CM. In addition, impurity concentration control of the channel region
Before or after, for example, about 1000 ° C., 30 minutes high temperature
The silicon oxide film 68 for the gate insulating film is formed by thermal oxidation.
It may be formed.

Next, as shown in FIG. 12 (4), as a material for the gate electrode and the gate line, for example, Mo-
A Ta alloy is deposited to a thickness of, for example, 400 nm by sputtering, or a phosphorus-doped polycrystalline silicon film is deposited, for example, in a hydrogen-based carrier gas of 150 SCCM, 2 to 20 nm.
Thickness by the similar catalytic CVD method or the like in the supply of a monosilane gas PH ₃ and 20SCCM of SCCM example is deposited 400nm thick. Then, the gate electrode material layer is patterned into the shape of the gate electrode 75 and the gate line by general-purpose photolithography and etching technology. In the case of a phosphorus-doped polycrystalline silicon film, a protective silicon oxide film (10 to 20 nm thick) may be formed on the surface by catalytic CVD or the like.

Next, as shown in (5) of FIG.
The MOSTFT portion is masked with a photoresist 78, and an n-type impurity such as arsenic (or phosphorus) ion 79 is, for example, 1 × 10 ¹⁵ a by ion implantation or ion doping.
doping at a dose of toms / cm ² , 2 × 10
The donor concentration was set to ²⁰ atoms / cc and the nMOST
An FT n ⁺ type source region 80 and a drain region 81 are formed.

Next, as shown in FIG. 13 (6), n
The MOSTFT portion is masked with a photoresist 82 and, for example, boron ions 83 which are p-type impurities are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms.
/ Cm ^{2 at} a dose of 2 × 10 ^{20 at}
ms / cc acceptor concentration, pMOSTFT
The p ⁺ type source region 84 and the drain region 85 are respectively formed.

Next, as shown in FIG. 13 (7), a hydrogen-based carrier gas of 150 SCCM is used as a common source to form 1 to 2 SC by the same catalytic CVD method or the like as described above.
Under the supply of He diluted O _{2 of} CM and monosilane of 15 to ₂₀ SCCM, the silicon oxide film is formed to have a thickness of, for example, 100 to 200 nm, and further, PH ₃ of 1 to 20 SCCM, and 1 to 2 SCCM.
Phosphine silicate glass (PSG) film was supplied under a supply of He-diluted O ₂ , 15-20 SCCM of monosilane.
0-400 nm thick, 50-60 SCCM NH
₃ , a silicon nitride film is formed to a thickness of, for example, 100 to 200 nm under supply of 15 to 20 SCCM of SiH ₄ . An interlayer insulating film 86 is formed by stacking these insulating films. Note that such an interlayer insulating film may be formed by another ordinary method different from the above. After this, for example 900 ° C., annealing or 1000 ° C. in N ₂ for 5 min, 20-30 seconds N ₂
The ions are activated by the RTA process in the inside, and the carrier impurity concentration is set in each region.

Next, as shown in (8) of FIG. 14, a contact window is opened at a predetermined position of the insulating film 86.
An electrode material such as aluminum is deposited on the entire surface including each contact hole at a temperature of 150 ° C. to a thickness of 1 μm by sputtering or the like, and is patterned to form an nMOS TFT in a pixel portion.
Source electrode 87, data line, and pM of peripheral circuit section
OSTFT and nMOSTFT source electrodes 88 and 90
And drain electrodes 89 and 91 and wiring are formed. At this time, aluminum may be formed by a catalytic CVD method. Thereafter, hydrogenation and sintering are performed, for example, in a forming gas at 400 ° C. for 1 hour.

Next, after an interlayer insulating film 92 such as a silicon oxide film is formed on the surface by the CVD method, as shown in FIG. 14 (9), the interlayer insulating films 92 and 86 are formed in the nMOSTFT drain region of the pixel portion. A contact hole is opened and, for example, ITO (indium tin oxide: a transparent electrode material in which tin is doped with indium oxide) is deposited on the entire surface by a vacuum deposition method or the like, and is patterned and the transparent pixel electrode 93 connected to the drain region 81 of the nMOS TFT is formed. To form Thereafter, for example, at 250 ° C. in a forming gas,
1h, annealing to improve ohmic contact with ITO and improve transparency of ITO.

Thus, an active matrix substrate can be manufactured, and a transmission type LCD can be manufactured. As shown in FIG. 14 (10), this transmission type LCD has a pixel electrode 9
3, an alignment film 94, a liquid crystal 95, an alignment film 96, a transparent electrode 9
7. It has a structure in which opposing substrates 98 are stacked.

The above-described steps can be similarly applied to the manufacture of a reflective LCD. FIG. 19A shows an example of this reflection type LCD.
Reference numeral 1 denotes a reflection film deposited on the roughened insulating film 92, which is connected to the drain of the MOSTFT.

When the liquid crystal cell of this LCD is manufactured by surface assembly (suitable for medium / large liquid crystal panels of 2 inch size or more), first, a TFT substrate 61 and a solid IT
Counter substrate 98 provided with O (Indium Tin Oxide) electrode 97
The polyimide alignment films 94 and 96 are formed on the element formation surface. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating, etc.
Cure with h.

Next, the TFT substrate 61 and the counter substrate 98 are subjected to rubbing or optical alignment processing. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation.
Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition, the orientation other than rubbing,
A polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound includes, for example, a polymethyl methacrylate-based polymer having azobenzene).

Next, after cleaning, a common agent is applied to the TFT substrate 61 side, and a sealing agent is applied to the counter substrate 98 side.
Wash with water or IPA (isopropyl alcohol) to remove rubbing buff debris. Common agent is acrylic or epoxy acrylate containing conductive filler,
Alternatively, the sealant may be an acrylic adhesive, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet irradiation curing, ultraviolet irradiation curing and heat curing can be used, but from the viewpoint of overlay accuracy and workability, the ultraviolet irradiation curing and heat curing type is preferable.

Next, spacers for obtaining a predetermined gap are sprayed on the counter substrate 98 side, and are superposed on the TFT substrate 61 at a predetermined position. After the alignment mark on the counter substrate 98 and the alignment mark on the TFT substrate 61 are precisely aligned, the sealant is temporarily cured by irradiating with ultraviolet light, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 61 and the counter substrate 98 are overlapped is created.

Next, the liquid crystal 95 is injected into the gap between the substrates 61-98, the injection port is sealed with an ultraviolet adhesive, and then IPA cleaning is performed. Any type of liquid crystal may be used, but for example, a high-speed response TN (twisted nematic) mode using a nematic liquid crystal is generally used.

Next, the liquid crystal 95 is oriented by heating and quenching.

Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 61 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is bonded to the counter substrate 98.

Also, in the case of a single liquid crystal panel surface assembly (suitable for a small liquid crystal panel having a size of 2 inches or less), a polyimide alignment film 94 is formed on the element forming surfaces of the TFT substrate 61 and the counter substrate 98 in the same manner as described above. , 96, and both substrates are subjected to rubbing or non-contact linear polarization ultraviolet light alignment treatment.

Next, the TFT substrate 61 and the opposing substrate 98 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 61, a sealing agent containing a spacer is applied to the counter substrate 98,
Lay both substrates together. Subsequent processes follow the above.

In the LCD described above, the counter substrate 98 is a CF (color filter) substrate in which a color filter layer (not shown) is provided below the ITO electrode 97. The incident light from the counter substrate 98 side may be efficiently reflected by, for example, the reflection film 93 and may be emitted from the counter substrate 98 side.

On the other hand, when the TFT substrate 61 is a TFT substrate having an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 61, the counter substrate 98 is provided with a solid ITO electrode (or a black mask). The ITO electrode is solid).

In the case of a transmission type LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, as shown in FIG. 14 (11), the insulating film 8 of phosphine silicate glass / silicon oxide
The drain portion of No. 6 was also opened to form an aluminum buried layer for the drain electrode, and then a photoresist 99 in which each color of R, G, and B was dispersed in a pigment for each segment to a predetermined thickness (1 to 1.5 μm). After the formation, the color filter layers 99 (R), 99 (G), and 99 are patterned by a general-purpose photolithography technique to leave only predetermined positions (each pixel portion).
(B) is formed (on-chip color filter structure).
At this time, the window of the drain part is also opened. In addition, an opaque ceramic substrate, glass with low transmittance, and a heat-resistant resin substrate cannot be used.

Next, in a contact hole communicating with the drain of the display TFT, a light-shielding layer 100 'serving as a black mask layer is formed by metal patterning over the color filter layer. For example, a molybdenum film having a thickness of 200 to 250 nm is formed by sputtering,
Patterning into a predetermined shape that covers T and shields light (on-chip black structure).

Next, a flattening film 92 made of a transparent resin is formed, and further, an ITO transparent electrode 93 is formed in a through hole provided in the flattening film so as to be connected to the light shielding layer 100 '.

As described above, by forming the color filter 99 and the black mask 100 'on the display array section, the aperture ratio of the liquid crystal display panel is improved, and the power consumption of the display module including the backlight is reduced. Is realized.

FIG. 15 shows the above-described top gate type MOST.
1 schematically shows the entirety of an active matrix liquid crystal display device (LCD) configured with a drive circuit integrated by incorporating an FT. This active matrix LCD has a flat panel structure in which a main substrate 61 (which constitutes an active matrix substrate) and a counter substrate 98 are bonded via a spacer (not shown).
Liquid crystal (not shown) is sealed between 1-98. On the surface of the main substrate 61, a display unit including pixel electrodes 93 arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. .

The switching element of the display unit is n
It is composed of a MOS, pMOS or CMOS top-gate MOSTFT having an LDD structure. In the peripheral drive circuit section, the above-mentioned top gate type M
OSTFT CMOS or nMOS or pMOSTFT
Alternatively, a mixture of these is formed. Note that one of the peripheral drive circuit units is a horizontal drive circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral drive circuit unit connects the gate of the TFT of each pixel for each scan line. , And are usually provided on both sides of the display unit. These drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 16, at the intersection of the orthogonal gate bus line and data bus line, the MOSTF
T is disposed, and a liquid crystal capacitance (C
_LC ) Writes image information and holds the charge until the next information comes. In this case, it is not enough to hold the TFT channel resistance alone. To compensate for this, a storage capacitor (auxiliary capacitor) (C _S ) is added in parallel with the liquid crystal capacitor to compensate for a decrease in the liquid crystal voltage due to leak current. May be. In such a MOSTFT for LCDs, the required performance differs between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral drive circuit. Is an important issue. For this reason, by providing a TFT having an LDD structure as described later in the display portion, an effective electric field applied to the channel region is reduced as a structure in which an electric field is hardly applied between the gate and the drain, and an off current is reduced. Can be reduced. However, the process becomes complicated, the element size becomes large, and problems such as a decrease in on-current occur. Therefore, an optimum design is required for each purpose of use.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used for TN mode of active matrix driving), STN (super twisted nematic), GH (guest / host), PC
(Phase change), FLC (ferroelectric liquid crystal), A
Liquid crystals for various modes such as FLC (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) may be employed.

<Manufacturing Example 2 of LCD> Next, a manufacturing example of an LCD (liquid crystal display device) using a polycrystalline silicon MOSTFT of a low-temperature process according to the present embodiment will be described. The present invention is similarly applicable to a display device of an FED and the like.

In this manufacturing example, aluminosilicate glass, borosilicate glass or the like is used as the substrate 61 in the above-mentioned manufacturing example 1, and the steps (1) and (2) in FIG. 12 are performed in the same manner. That is, the catalyst CVD and the catalyst AH are formed on the substrate 61.
By repeating the A process, a tin-containing (or non-containing) polycrystalline silicon film 67 is formed and islanded, and the nMOSTFT portion in the display region and the nMO TFT in the peripheral drive circuit region are formed.
An STFT section and a pMOSTFT section are formed. In this case, at the same time, regions such as a diode, a capacitor, an inductance, and a resistor are formed.

Next, as shown in FIG. 17A, in order to optimize the V _th by controlling the carrier impurity concentration of each MOSTFT gate channel region, the nM of the display region is reduced.
The OSTFT part and the nMOSTFT part in the peripheral driving circuit area are covered with a photoresist 82, and the pT in the peripheral driving circuit area is covered.
1 × 10 ¹² n-type impurities 79 such as phosphorus and arsenic are implanted into the MOSTFT portion by ion implantation or ion doping.
doping at a dose of atoms / cm ² , 2 × 1
0 ¹⁷ atoms / cc was set for the donor concentration, and FIG.
As shown in (2) of FIG. 7, the pMOS in the peripheral drive circuit area
The TFT part is covered with a photoresist 82, and the nMOSTFT part in the display area and the nMOSTFT in the peripheral drive circuit area are covered.
5 × 10 ¹¹ atoms / c by ion implantation or ion doping.
doping with a dose of m ² , 1 × 10 ¹⁷ atoms
/ Cc set acceptor concentration.

Next, as shown in FIG. 17C, the n ^- type LDD (Lightly D
In order to form an oped drain) portion, the gate portion of the nMOSTFT in the display region and all the pMOSTFTs and nMOSTFTs in the peripheral driving region are covered with a photoresist 82 by a general-purpose photolithography technique, and n in the exposed display region is formed.
An n-type impurity 7 such as phosphorus is implanted into the source / drain region of the MOSTFT by ion implantation or ion doping.
9 is doped at a dose of 1 × 10 ¹³ atoms / cm ² and the donor concentration is set to 2 × 10 ¹⁸ atoms / cc to form an n ⁻ -type LDD portion.

Next, as shown in FIG. 18D, the nMOSTFT portion in the display area and the nM TFT in the peripheral drive circuit area are used.
The entire OSTFT portion is covered with a photoresist 82,
A p-type impurity 83 such as boron, for example, is ion-implanted or ion-doped into the source and drain regions exposed by covering the gate portion of the pMOSTFT portion of the peripheral drive circuit region with the photoresist 82 at 1 × 10 ¹⁵ atoms / s.
doping with a dose of cm ² , and 2 × 10 ²⁰ atoms
A source portion 84 and a drain portion 85 of p ⁺ type are formed at an acceptor concentration of s / cc.

Next, as shown in (5) of FIG. 18, the pMOSTFT portion in the peripheral drive circuit region is
2, the gate of the nMOSTFT in the display area and the LDD part and the gate part of the nMOSTFT part in the peripheral drive circuit area are covered with a photoresist 82, and the exposed source and drain areas of the nMOSTFT in the display area and the peripheral drive area are For example, an n-type impurity 79 such as phosphorus or arsenic is doped with 1 × 10 ¹⁵ atoms by ion implantation or ion doping.
ion doping at a dose of s / cm ² ,
^At a donor concentration of ²⁰ atoms / cc, an n ⁺ -type source portion 80 and a drain portion 81 are formed.

Next, as shown in FIG. 18 (6), plasma CVD, TEOS plasma CVD, catalytic CVD
As a gate insulating film 68, a silicon oxide film (40 to 50 nm thick), a silicon nitride film (10 to 20 n
m) and a silicon oxide film (40 to 50 nm thick). Then, RTA treatment with a halogen lamp or the like is performed, for example, at about 1000 ° C. for 10 to 30 seconds, and the added n or p-type impurities are activated to obtain the set respective carrier impurity concentrations.

Thereafter, a 400-500 nm thick aluminum sputtered film containing 1% Si is formed on the entire surface, and the gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching. After this, a stacked film of a silicon oxide film (100 to 200 nm thick), a phosphine silicate glass (PSG) film (200 to 300 nm thick), and a silicon nitride film (100 to 200 nm thick) is formed by plasma CVD, catalytic CVD, or the like. An insulating film 86 made of is formed.

Next, the windows of the source / drain portions of all the TFT portions of the peripheral drive circuit and the source portions of the display nMOSTFT portion are opened by general-purpose photolithography and etching techniques. The silicon nitride film is plasma-etched with CF ₄ , and the silicon oxide film and the phosphosilicate glass film are etched with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 18 (7), an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and the source of all the TFTs of the peripheral drive circuit is formed by general-purpose photolithography and etching techniques. ,
At the same time as forming the drain electrodes 88, 89, 90 and 91, the source electrode 87 and the data line of the display nMOSTFT are formed.

Next, although not shown, the plasma CV
D, a silicon oxide film (100 to
200 nm thick), phosphine silicate glass film (P
SG film: 200 to 300 nm thick), silicon nitride film (1
(Thickness: 00 to 300 nm) is formed on the entire surface, and is subjected to hydrogenation and sintering in a forming gas at about 400 ° C. for 1 hour. Thereafter, a window for contacting the drain of the display nMOSTFT is opened.

Here, when the LCD is of a transmission type, the silicon oxide film, the phosphine silicate glass film and the silicon nitride film at the pixel opening are removed.
It is not necessary to remove the silicon oxide film, the phosphine silicate glass film, and the silicon nitride film in the pixel openings and the like (this is the same in the above-described or later-described LCD).

In the case of the transmission type, an acrylic transparent resin flattening film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like as in (10) of FIG. After forming a transparent resin window opening on the drain side of the TFT for
An ITO sputtered film with a thickness of nm is formed, and nMOSTF for display is formed by general-purpose photolithography and etching technology.
An ITO transparent electrode in contact with the drain of T is formed. Further heat treatment (200 to 25 in forming gas)
0 ° C., 1 hour) to reduce contact resistance and reduce IT
O To improve transparency.

In the case of the reflection type, a photosensitive resin film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and a concavo-convex pattern is formed at least in the pixel portion by general-purpose photolithography and etching techniques, and reflow is performed. To form a concave and convex reflecting lower portion. At the same time, a photosensitive resin window opening at the drain of the display nMOS TFT is formed. Thereafter, an aluminum sputtered film containing 1% Si with a thickness of 300 to 400 nm is formed on the entire surface, the aluminum film other than the pixel portion is removed by general-purpose photolithography and etching technology, and the irregularities connected to the drain electrode of the display nMOS TFT are formed. An aluminum reflector having a shape is formed. Then,
Sintering is performed at 300 ° C. for 1 hour in a forming gas.

In the above, if the catalyst AHA treatment is performed after forming the source and drain of the nMOS TFT, the film temperature of the polycrystalline silicon film is locally increased,
Crystallization is further promoted, and irregularities and stress existing at the grain boundaries are reduced, and a high mobility and high quality polycrystalline silicon film is formed. At the same time, hot hydrogen molecules, hydrogen atoms,
Since the thermal energy of the activated hydrogen ions moves to the film and locally increases the film temperature, phosphorus, arsenic, boron ions, etc. implanted in the gate channel / source / drain regions are activated.

When an amorphous silicon-containing microcrystalline silicon film is formed by the plasma CVD method, the film contains 10 to 30% of hydrogen. A polycrystalline silicon film having high mobility and high quality is formed by reducing the irregularity and stress existing in the crystal grain boundaries. Also, when silicon oxide exists on or in a film of amorphous silicon-containing microcrystalline silicon, etc.,
A reduction reaction with this produces SiO and evaporates it,
Silicon oxide on or in these films can be reduced / removed, and a high mobility and high quality polycrystalline silicon film can be formed.

<Bottom Gate Type or Dual Gate Type M
For example, in an LCD incorporating OSTFT> MOSTFT, a transmissive type L composed of a bottom gate type and a dual gate type MOSTFT is used instead of the above-described top gate type.
An example of manufacturing a CD will be described (however, the same applies to a reflective LCD).

As shown in FIG. 19B, a bottom gate type nMOSTFT is provided in the display portion and the peripheral portion.
Alternatively, as shown in FIG. 19C, dual-gate nMOS TFTs are provided in the display portion and the peripheral portion, respectively. Of these bottom gate type and dual gate type MOS TFTs, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and selectively using one of the upper and lower gate portions. Depending on the case, it can be operated as a top gate type or a bottom gate type.

The bottom gate type MOSTF shown in FIG.
In the figure, reference numeral 102 denotes a gate electrode of Mo / Ta, etc., 103 denotes a silicon nitride film and 104 denotes a silicon oxide film to form a gate insulating film. On this gate insulating film, a top gate type MOS TFT A channel region and the like using the same polycrystalline silicon film 67 are formed. Further, the dual gate type MOST shown in FIG.
In the FT, the lower gate portion is a bottom gate type MOST
Same as FT, except that the upper gate is
04 is formed of a laminated film of a silicon oxide film and a silicon nitride film and, if necessary, a silicon oxide film, and an upper gate electrode 105 is provided thereon.

<Manufacture of Bottom Gate MOSTFT> First, a sputtered film of a molybdenum-tantalum alloy is formed to a thickness of 300 to 400 nm on the entire surface of a glass substrate 61, and this is formed by a general-purpose photolithography and etching technique at 20 to 45 degrees. Taper etching at least TF
A gate line is formed at the same time as the bottom gate electrode 102 is formed in the T formation region. The selection of the glass material is in accordance with the above-mentioned top gate type.

Next, a silicon nitride film 10 for a gate insulating film and a protective film is formed by a vapor phase growth method such as plasma CVD, TEOS plasma CVD, catalytic CVD, and low pressure CVD.
3 and a silicon oxide film 104, and a tin-containing amorphous silicon-containing microcrystalline silicon film. This film is further subjected to the catalytic AHA treatment as described above to form a polycrystalline silicon film 67. These vapor deposition conditions are based on the above-mentioned top gate type. Note that the bottom gate insulating film and the silicon nitride film for the protective film are provided in expectation of the Na ion stopper function from the glass substrate, but are unnecessary in the case of synthetic quartz glass.

The subsequent processes are the same as those described above. However, since the gate electrode has already been formed in the above-described steps, the steps of forming a polycrystalline silicon film for a gate electrode, forming a gate electrode, and oxidizing a gate polycrystalline silicon are performed here. Is unnecessary.

Then, as described above, the pMOS
The TFT and nMOS TFT regions are made islands (however,
Only one region is shown: the same applies hereinafter), and an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping to control the carrier impurity concentration in each channel region to optimize _Vth . Later, each MOSTF
In order to form T source and drain regions, an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping. Thereafter, a catalyst AHA treatment is performed to activate the impurities.

[0182] The subsequent processes are the same as those described above.

<Manufacture of Dual Gate MOSTFT>
Similarly to the above bottom gate type, the bottom gate electrode 10
2. The gate insulating films 103 and 104 and the polycrystalline silicon film 67 are formed. However, the silicon nitride film 103 for the bottom gate insulating film and the protective film is provided in expectation of the Na ion stopper function from the glass substrate, but is unnecessary in the case of synthetic quartz glass.

Then, as described above, the pMOS
In order to optimize the V _th by controlling the carrier impurity concentration of each channel region by forming the islands of the TFT and nMOS TFT regions, an appropriate amount of n-type or p-type impurities are mixed by ion implantation or ion doping, and then, Each M
In order to form the source and drain regions of the OSTFT, an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping. Thereafter, a catalyst AHA treatment is performed to activate the impurities.

Next, a stacked film of a silicon oxide film and a silicon nitride film for the top gate insulating film 106 and, if necessary, a silicon oxide film are further formed. The vapor phase growth conditions are based on the above-mentioned top gate type.

Thereafter, a 400-500 nm thick aluminum sputtered film containing 1% Si is formed on the entire surface, and the top gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching techniques. Thereafter, a silicon oxide film (100 to 200 nm thick) and a phosphine silicate glass (PSG) film (200 to 300 nm thick) are formed by plasma CVD, catalytic CVD, or the like.
An insulating film 86 made of is formed. Next, windows of the source and drain electrode portions of all the MOSTFTs of the peripheral drive circuit and the source electrode portion of the display portion nMOSTFT are opened by general-purpose photolithography and etching technology.

Next, a 400-500 nm thick 1
An aluminum sputtered film containing% Si is formed, and source and drain aluminum electrodes 87, 88 and 89, a source line and a wiring are formed by general-purpose photolithography and etching techniques. Next, although not shown, a silicon oxide film (100 to 200 nm thick) and a phosphine silicate glass film (PSG film; 200 to 300 nm) are formed by plasma CVD, catalytic CVD, or the like.
Thickness), a silicon nitride film (100-300 nm thick) is formed on the entire surface, and is formed at about 400 ° C. for one hour in a forming gas.
Hydrogenate and sinter. Then, display nMO
A drain contact window is opened for the STFT.

As described above, according to the present embodiment,
As in the first embodiment, the catalyst CVD and the catalyst A
The HA process is repeated, and becomes the gate channel, source and drain regions of the MOSTFT of the LCD display unit and the peripheral drive circuit unit. _Vth adjustment is easy with high carrier mobility, and high-speed operation with low resistance is possible. A polycrystalline silicon film can be formed. A liquid crystal display device using a top gate, a bottom gate or a dual gate type MOSTFT made of this polycrystalline silicon film has a display portion having an LDD structure with high switching characteristics and low leakage current,
High drive capability CMOS or nMOS or pMOS
A configuration that integrates the peripheral drive circuit becomes possible, and high image quality,
High-definition, narrow-frame, high-efficiency, inexpensive liquid crystal panels can be realized.

Since the glass can be formed at a low temperature (300 to 400 ° C.), it is possible to use a low strain point glass which is inexpensive and can be easily enlarged, and the cost can be reduced. In addition, by forming a color filter and a black mask on the array portion, the aperture ratio and luminance of the liquid crystal display panel are improved, a color filter substrate is not required, and cost reduction is achieved by improving productivity and the like.

Third Embodiment In the present embodiment, the present invention is applied to an organic or inorganic electroluminescence (EL) display device, for example, an organic EL display device. An example of the structure and a manufacturing example are shown below.

<Structural Example I of Organic EL Element> FIG.
As shown in (A) and (B), according to this structural example I,
The gate channel 117 and the source of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed on a substrate 111 made of glass or the like by a polycrystalline silicon film having a high crystallization rate and a large grain size formed by the method described above according to the present invention. A region 120 and a drain region 121 are formed.
Further, a gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. MOSTFT
1 and the gate of the MOSTFT2 are connected via a drain electrode 128 and
A capacitor C is formed between the source electrode 127 and the second source electrode 127 via an insulating film 136, and the drain electrode 131 of the MOSTFT 2 extends to the cathode 138 of the organic EL element.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133,
Further, a red organic light emitting layer (not shown) is formed, an anode (first layer) 134 is formed so as to cover the organic light emitting layer, and a common anode (second layer) 135 is formed on the entire surface. In addition, a peripheral driving circuit composed of a CMOS TFT,
The method of manufacturing the video signal processing circuit, the memory circuit, and the like conforms to the above-described liquid crystal display device (the same applies hereinafter).

In the organic EL display portion having this structure, the organic EL light emitting layer is connected to the drain of the current driving MOSTFT 2, and the cathode (Li-Al, Mg-Ag, etc.) 138 is attached to the surface of the substrate 111 such as glass. Then, the anodes (ITO films and the like) 134 and 135 are provided on the upper portion thereof, and therefore, the top emission 136 is obtained. The cathode is MOSTFT
If it covers the top, the light emitting area becomes large. At this time, the cathode serves as a light-shielding film, and emitted light and the like do not enter the MOSTFT, so that no leak current is generated and the TFT characteristics do not deteriorate.

Further, as shown in FIG. 20C, a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion.
Is formed, light leakage (such as crosstalk) can be prevented, and the contrast can be improved.

It should be noted that green, blue and red colors are displayed on the pixel display section.
Either a method using a color light-emitting layer, a method using a color conversion layer, or a method using a color filter for a white light-emitting layer can realize a good full-color EL display device, and a polymer that is a light-emitting material for each color. Long-life, high-precision, high-quality, high-reliability full-color organic EL even in compound spin coating or metal complex vacuum evaporation
Since the parts can be created with high productivity, the cost can be reduced (the same applies hereinafter).

Next, the manufacturing process of the organic EL device will be described. First, as shown in FIG. 21A, the source region 120, the channel region 117 and the channel region 117 made of a polycrystalline silicon film are formed through the above-described steps. Drain region 121
Is formed, a gate insulating film 118 is formed, and the gate electrodes 115 of the MOSTFTs 1 and 2 are formed thereon by sputtering film formation of Mo-Ta alloy or the like and photolithography and etching techniques, and are connected to the gate electrode of the MOSTFT1. The gate line to be formed is formed by sputtering film formation, photolithography and etching techniques (hereinafter the same). Then, after an overcoat film (silicon oxide or the like) 137 is formed by a vapor phase growth method such as catalytic CVD (hereinafter the same), the source electrode 1 of the MOSTFT 2 is formed.
27 and an earth line are formed, and an overcoat film (silicon oxide / silicon nitride laminated film) 136 is further formed.

Next, as shown in FIG. 21 (2), M
After opening the windows of the source / drain portion of the OSTFT1 and the gate portion of the MOSTFT2, as shown in FIG. 21 (3), the MOSTFT1 is formed by sputtering of Al containing 1% Si and general-purpose photolithography and etching techniques.
1% S between the drain electrode of
connected with the Al wiring 128 containing i,
Source electrode and A containing 1% Si connected to this electrode.
1 is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 122 is formed, and a MOS
Open the window of the drain part of TFT2, MOSTFT2
The cathode 138 of the light-emitting part connected to the drain part of FIG.

Next, as shown in FIG. 21D, an organic light emitting layer 132 and the like and anodes 134 and 135 are formed.

In the above description, the green (G) light emitting organic EL layer, the blue (B) light emitting organic EL layer, and the red (R) light emitting organic EL layer are each formed to a thickness of 100 to 200 nm. The layer is formed by a vacuum heating evaporation method in the case of a low molecular weight compound, and in the case of a high molecular weight compound, a method of arranging R, G, B light emitting polymers by an application method such as dipping coating or spin coating or an inkjet method is used. . In the case of a metal complex, a sublimable material is formed by a vacuum heating evaporation method.

The organic EL layer includes a single-layer type, a two-layer type, a three-layer type, and the like. Here, an example of a three-layer type of a low molecular compound is shown. Single layer type; anode / bipolar light emitting layer / cathode, double layer type; anode / hole transporting layer / electron transporting light emitting layer / cathode, or anode / hole transporting light emitting layer / electron transporting layer / cathode, three layer type; Anode / hole transporting layer / light emitting layer / electron transporting layer / cathode, or anode / hole transporting light emitting layer / carrier blocking layer / electron transporting light emitting layer / cathode

In the element of FIG. 20B, if a known light emitting polymer is used instead of the organic light emitting layer, it can be configured as a light emitting polymer display device (LEPD) driven by a passive matrix or an active matrix (hereinafter, referred to as LEPD). And similar).

<Structural Example II of Organic EL Element> FIG.
As shown in (A) and (B), according to this structural example II,
On a substrate 111 made of glass or the like, similar to the above structure example I,
The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT1 and the current driving MOSTFT2 are formed by the high crystallization rate and large grain size polycrystalline silicon film formed by the above-described method according to the present invention. Have been. Then, the gate insulating film 11
8, a gate electrode 115 is formed on the source and drain regions, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. MOSTFT drain and MOSTF
The capacitor C is connected to the gate of T2 via the drain electrode 128, and is formed between the gate of T2 and the drain electrode 131 of the MOSTFT2 via the insulating film 136.
In addition, the source electrode 127 of the MOSTFT 2 extends to the anode 144 of the organic EL element.

Each MOSTFT is covered with an insulating film 130,
On the insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133,
Further, a red organic light emitting layer (not shown) is formed, a cathode (first layer) 141 is formed so as to cover the organic light emitting layer, and a common cathode (second layer) 142 is formed on the entire surface.

In the organic EL display section having this structure, the organic EL light emitting layer is connected to the source of the current driving MOSTFT 2,
An organic EL light emitting layer is formed so as to cover the anode 144 attached to the surface of the substrate 111 such as glass, a cathode 141 is formed so as to cover the organic EL light emitting layer, and a cathode 142 is formed over the entire surface. Therefore, bottom emission 136 is obtained. Also,
The cathode covers the organic EL light emitting layer and the MOSTFT. That is, after forming, for example, a green light-emitting organic EL layer on the entire surface by a vacuum heating evaporation method or the like, a green light-emitting organic EL section is formed by photolithography and dry etching. Finally, a cathode (electron injection layer) 141 is formed on the entire surface by magnesium:
Silver alloy or aluminum: formed of a lithium alloy. Since the entire surface is sealed by a cathode (electron injection layer) further formed, the invasion of moisture from the outside to the organic EL layer is particularly prevented by the cathode 142 applied on the entire surface, and the deterioration of the organic EL layer which is weak to moisture and the electrode are prevented. 20 is prevented, and a long life, high quality, and high reliability can be achieved.
However, the same applies because the entire surface is covered with the anode.) In addition, since the heat radiation effect is enhanced by the cathodes 141 and 142, a structural change (melting or recrystallization) of the thin film due to heat generation is reduced, and a long life, high quality, and high reliability can be achieved. In addition, since a high-precision, high-quality, full-color organic EL layer can be produced with high productivity, the cost can be reduced.

As shown in FIG. 22C, a black mask portion (chrome, chromium dioxide, etc.) 140 is formed around each pixel portion.
Is formed, light leakage (such as crosstalk) can be prevented, and the contrast can be improved. Note that the black mask portion 140 is covered with a silicon oxide film 143 (this may be formed simultaneously with the gate insulating film 118 using the same material).

Next, the manufacturing process of the organic EL device will be described. First, as shown in FIG. 23A, the source region 120, the channel region 117 and the source region 120 made of a polycrystalline silicon film are subjected to the above-described steps. Drain region 121
Is formed, a gate insulating film 118 is formed by a vapor phase growth method such as catalytic CVD, and the gate electrodes 11 of the MOSTFTs 1 and 2 are formed thereon by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques.
5 is formed, and a gate line connected to the gate electrode of the MOSTFT 1 is formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques. Then, after forming an overcoat film (silicon oxide or the like) 137 by a vapor phase growth method such as catalytic CVD, a MOSTF is formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques.
A drain electrode 131 of T2 and a _Vdd line are formed, and an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by a vapor phase growth method such as catalytic CVD.

Next, as shown in FIG. 23B, the MOS is formed by general-purpose photolithography and etching techniques.
After opening the windows of the source / drain portion of the TFT 1 and the gate portion of the MOSTFT 2, as shown in FIG. 23C, the MOST is formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques.
The drain of FT1 and the gate of MOSTFT2 are 1% Si
A source line made of Al containing 1% Si and connected to the source of the MOSTFT 1 at the same time is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 122 is formed, a window of the source portion of the MOSTFT 2 is opened by general-purpose photolithography and etching technology, and sputtering such as ITO and general-purpose photolithography are performed. And MOSTFT2 by etching technology
The anode 144 of the light emitting portion connected to the source portion of the light emitting device is formed.

Next, as shown in FIG. 23D, the organic light emitting layer 132 and the cathodes 141 and 142 are formed as described above.
To form

The constituent materials and forming method of each layer of the organic EL described below are applied to the example of FIG. 22, but may be similarly applied to the example of FIG.

When a low molecular weight compound is used for the green light emitting organic EL layer, continuous vacuum heating deposition is performed on the ITO transparent electrode in contact with the drain of the current driving MOSTFT, which is the anode (hole injection layer) on the glass substrate. It is formed by a method. 1) The hole transport layer is made of an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is made of tris (8-hydroxyxylino) Al which is a green light emitting material Complex (Alq), etc. 3) The electron transport layer is made of 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, 10 to 30 nm thickness of a 10: 1 (atomic ratio) magnesium: silver alloy 10 to 30 nm thickness of an aluminum: lithium (concentration: 0.5 to 1%) alloy Here, silver has an adhesive property with an organic interface. 1 to 10 atomic% is added to magnesium for increasing, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a green pixel portion, the green pixel portion
Mask with photoresist and CCl _FourGas plasma
The aluminum of the electron injection layer which is the cathode by the etching:
Remove the lithium alloy, continuously electron transport layer, light emitting layer,
The low-molecular compound and the photoresist in the hole transport layer are acidified.
Removed by elementary plasma etching to form a green pixel part
You. At this time, the aluminum under the photoresist:
Photoresist is etched due to lithium alloy
There is no problem if it is done. At this time, the electron transport layer,
Layer and the hole transport layer
Area larger than the ITO transparent electrode of
Electron injection layer (magnesium: silver alloy) of cathode formed on
And electrical shorts.

Next, when the blue light-emitting organic EL layer is formed of a low-molecular compound, the blue light-emitting organic EL layer is continuously formed on the ITO transparent electrode in contact with the drain of the current driving TFT which is the anode (hole injection layer) on the glass substrate. And formed by vacuum heating evaporation. 1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is a distyryl derivative such as DTVBi which is a blue light emitting material 3) The electron transport layer is composed of a 1,3,4-oxadiazole derivative (TAZ), a 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, 10 to 30 nm thickness of a 10: 1 (atomic ratio) magnesium: silver alloy 10 to 30 nm thickness of an aluminum: lithium (concentration: 0.5 to 1%) alloy Here, silver has an adhesive property with an organic interface. 1 to 10 atomic% is added to magnesium for increasing, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

In order to form a blue pixel portion, the blue pixel portion
Mask with photoresist and CCl _FourGas plasma
Of the electron injection layer which is the cathode in the etching: Li
Alloy, and the electron transport layer, light emitting layer,
Oxygen-transporting the low molecular weight compound and photoresist in the
It is removed by plasma etching to form a blue pixel portion. This
At the time of the photoresist under the aluminum: Lithium
The photoresist is etched
No problem. At this time, the electron transport layer, the light emitting layer,
The low-molecular compound layer of the hole transport layer is made of ITO of the hole injection layer.
Make the area larger than the transparent electrode and form it over the entire surface in a later process
Electron injection layer (magnesium: silver alloy) and electrical
Avoid shorts.

When the red light-emitting organic EL layer is formed of a low molecular compound, the red light-emitting organic EL layer is continuously formed on the ITO transparent electrode which is in contact with the drain of the current driving TFT which is the anode (hole injection layer) on the glass substrate. Formed by vacuum heating evaporation. 1) The hole transport layer is made of an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is made of Eu (Eu (DBM)) which is a red light emitting material
₃ ) (Phen)) 3) The electron transport layer is made of a 1,3,4-oxadiazole derivative (OXD), a 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, a 10: 1 (atomic ratio) magnesium: silver alloy having a thickness of 10 to 30 nm, an aluminum: lithium (concentration of 0.5 to 1%) alloy having a thickness of 10 to 30 nm, silver is used to increase the adhesion to an organic interface. 1 to 10 atomic% is added to magnesium, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a red pixel portion, the red pixel portion
Mask with photoresist and CCl _FourGas plasma
Of the electron injection layer which is the cathode in the etching: Li
Alloy, and the electron transport layer, light emitting layer,
Oxygen-transporting the low molecular weight compound and photoresist in the
It is removed by plasma etching to form a red pixel portion. This
At the time of the photoresist under the aluminum: Lithium
The photoresist is etched
No problem. At this time, the electron transport layer, the light emitting layer,
The low-molecular compound layer of the hole transport layer is made of ITO of the hole injection layer.
Make the area larger than the transparent electrode and form it over the entire surface in a later process
Electron injection layer (magnesium: silver alloy) and electrical
Avoid shorts.

The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example,
10 to 3 of 10: 1 (atomic ratio) magnesium: silver alloy
0 nm thick, or aluminum: lithium (concentration is 0.5
１1%) The thickness of the alloy is 10 to 30 nm. Here, silver is added to magnesium in magnesium in order to increase adhesiveness with an organic interface.
10 atomic% is added, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization. Note that the film may be formed by sputtering.

Fourth Embodiment In this embodiment, the present invention is applied to a field emission type (field emission) display device (FED: Field Emission).
Display). An example of the structure and a manufacturing example are shown below.

<Structure Example I of FED> FIG.
As shown in (B) and (C), according to this structural example I,
The gate channel 117 and the source of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed on a substrate 111 made of glass or the like by a polycrystalline silicon film having a high crystallization rate and a large grain size formed by the method described above according to the present invention. A region 120 and a drain region 121 are formed.
Then, a gate electrode 115 is formed over the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed over the source and drain regions. The drain of the MOSTFT1 and the gate of the MOSTFT2 are connected to the drain electrode 128.
, A capacitor C is formed between the source electrode 127 of the MOSTFT2 and the source electrode 127 via an insulating film 136, and the drain region 1 of the MOSTFT2 is formed.
Reference numeral 21 extends as it is to the FEC (field emission cathode) of the FED element and functions as an emitter region 152.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, an FEC gate lead electrode 150 is formed.
A metal shielding film 151 for grounding is formed of the same material and in the same step, and covers each MOSTFT. In the FEC, the emitter region 15 made of a polycrystalline silicon film is used.
An n-type polycrystalline silicon film 153 serving as a field emission emitter is formed on the substrate 2, and the insulating films 118 and 137 are formed so as to have openings for partitioning into m × n emitters.
136 and 130 are patterned, and a gate extraction electrode 150 is attached on the upper surface.

A substrate 157 such as a glass substrate formed with a phosphor 156 having a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the FEC and the FEC.

In the FEC having this structure, the n-type polycrystalline silicon film 153 grown on the polycrystalline silicon film 152 formed according to the present invention is exposed below the opening of the gate extraction electrode 150. , This is each electron 1
It functions as a thin-film type emitter emitting 54. That is, the polycrystalline silicon film 152 serving as the base of the emitter
Is composed of grains having a large grain size (a grain size of several hundred nm or more). When the n-type polycrystalline silicon film 153 is grown thereon by catalytic CVD or the like as a seed, the polycrystalline silicon film 153 grows with a larger particle size, and the surface is formed so as to generate fine irregularities 158 which are advantageous for electron emission.

Therefore, since the emitter is of a surface emission type composed of a thin film, it can be easily formed, the emitter performance is stabilized, and the life can be extended.

Further, a metal shielding film 151 of a ground potential is formed on all the active elements (including the peripheral driving circuit and the MOSTFT and the diode of the pixel display section). The same material (Nb, Ti / Mo, etc.) is formed in the same step, which is convenient for the process.) Therefore, the following (1),
The advantage of (2) can be obtained.

(1) The gas in the airtight container is the emitter 1
The electrons emitted from the electrons 53 are positively ionized and charged up on the insulating layer.
An unnecessary inversion layer is formed in the OSTFT, and an extra current flows through an unnecessary current path including the inversion layer.
Runaway of the emitter current occurs. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT and dropped to the ground potential, charge-up can be prevented, and runaway of the emitter current can be prevented.

(2) The phosphor 156 emits light due to the collision of the electrons emitted from the emitter 153, and this light generates electrons and holes in the gate channel of the MOSTFT, resulting in a leak current. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT, the MOST
Light incidence on the FT is prevented, and no operation failure of the MOSTFT occurs.

Next, the manufacturing process of this FED will be described. First, as shown in FIG. 25A, after a polycrystalline silicon film 117 is formed on the entire surface through the above-described steps, general-purpose photolithography and An island is formed in the MOSTFT1 and MOSTFT2 and the emitter region by an etching technique, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.

Next, in order to optimize V _th by controlling the gate channel impurity concentration of the MOSTFTs 1 and 2,
The whole surface is doped with boron ions 83 at a dose of 5 × 10 ¹¹ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 1 × 10 ¹⁷ atoms / cc.

Next, as shown in FIG. 25 (2), using the photoresist 82 as a mask, 1 × 10 5 phosphorus ions 79 are applied to the source / drain portions and the emitter regions of the MOSTFTs 1 and 2 by ion implantation or ion doping. ^Fifteen
doping at a dose of atoms / cm ² , 2 × 1
After setting the donor concentration to 0 ²⁰ atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the silicon oxide film for protecting the emitter region is removed by general-purpose photolithography and etching techniques.

Next, as shown in FIG. 25C, monosilane and a dopant such as PH ₃ are mixed at an appropriate ratio with the polycrystalline silicon film 152 forming the emitter region formed by catalytic CVD as a seed. It has fine irregularities 158 and the dopant is, for example, 5 × 10 ²⁰ to 1 × 10 ^{21 at.}
ms / cc-containing n-type polycrystalline silicon film 153
An n-type amorphous silicon film 160 is formed in a thickness of 1 to 5 μm on the other silicon oxide film 159 and the glass substrate 111 at the same time.

Next, as shown in (4) of FIG. 25, the amorphous silicon film 160 is removed by etching using activated hydrogen ions at the time of the above-mentioned catalytic AHA treatment, and after the silicon oxide film 159 is removed by etching, catalytic CVD or the like is performed. A gate insulating film (such as a silicon oxide film) 118 is formed.

Next, as shown in (5) of FIG. 26, the gate electrodes 115 of the MOSTFTs 1 and 2 and the MOST are made of a heat-resistant metal such as a Mo—Ta alloy by a sputtering method.
A gate line connected to the gate electrode of the FT1 is formed, an overcoat film (silicon oxide film or the like) 137 is formed, and after opening the source window of the MOSTFT2, MO is formed using a heat-resistant metal such as a Mo-Ta alloy by a sputtering method.
The source electrode 127 of STFT2 and the ground line are formed. Further, an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by plasma CVD, catalytic CVD, etc.
Perform an ion activation process for ~ 20 seconds.

Next, as shown in (6) of FIG.
Source / drain part of OSTFT1 and MOSTFT2
Of the gate of the MOSTFT1 and the gate of the MOSTFT2 are connected to the Al wiring 12 containing 1% Si.
8 and at the same time, a source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.

Next, as shown in FIG. 26 (7), after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130, a GND line window is opened, and As shown in (8), the gate lead-out electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode is opened to expose the emitter 153. Clean with hydride ions.

<Structure Example II of FED> FIG.
As shown in (B) and (C), according to this structural example II,
On a substrate 111 made of glass or the like, similar to the above structure example I,
The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT1 and the current driving MOSTFT2 are formed by the high crystallization rate and large grain size polycrystalline silicon film formed by the above-described method according to the present invention. Have been. Then, the gate insulating film 11
8, a gate electrode 115 and a source electrode 127 and a drain electrode 128 are formed on the source and drain regions. The drain of the MOSTFT1 and the gate of the MOSTFT2 are connected via a drain electrode 128, and a capacitor C is formed between the drain of the MOSTFT2 and the source electrode 127 of the MOSTFT2 via an insulating film 136.
The drain region 121 of the STFT 2 extends as it is to the FEC (field emission cathode) of the FED element, and functions as the emitter region 152.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, an FEC gate lead electrode 150 is formed.
A metal shielding film 151 for grounding is formed of the same material and in the same step, and covers each MOSTFT. In the FEC, an emitter region 152 made of a polycrystalline silicon film is used.
An n-type polycrystalline diamond film 163 serving as a field emission emitter is formed thereon, and insulating films 118 and 137 are formed so as to have openings for partitioning into m × n emitters.
136 and 130 are patterned, and a gate extraction electrode 150 is attached on the upper surface.

In addition, a substrate 157 such as a glass substrate formed with a phosphor 156 having a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the FEC and the FEC.

In the FEC having this structure, an n-type polycrystalline diamond film 163 grown on a polycrystalline silicon film 152 formed according to the present invention is exposed below an opening of a gate lead electrode 150, and this is exposed. Each functions as a thin-film emitter that emits electrons 154. In other words, since the polycrystalline silicon film 152 serving as the base of the emitter is composed of grains having a large grain size (a grain size of 100 nm or more), the n-type polycrystalline diamond film 163 is used as a seed on the catalyst to form a catalyst. When grown by CVD or the like, the polycrystalline diamond film 163 also grows with a large grain size, and the surface is formed so as to generate fine irregularities 168 advantageous for electron emission.

Therefore, since the emitter is of a surface emission type consisting of a thin film, it can be easily formed, the emitter performance is stabilized, and the life can be extended.

Further, a metal shielding film 151 of a ground potential is formed on all the active elements (including the peripheral driving circuit and the MOSTFT and the diode of the pixel display section). The same material (Nb, Ti / Mo, etc.) is formed in the same step, which is convenient for the process.) As described above, the metal shielding film 151 is formed on the insulating layer on the MOSTFT as described above. To ground potential to prevent charge-up, prevent runaway of emitter current, and reduce MOST
Since the metal shielding film 151 is formed on the insulating layer on the FT, light is prevented from being incident on the MOSTFT.
Does not occur.

Next, the manufacturing process of this FED will be described. First, as shown in FIG. 28A, after a polycrystalline silicon film 117 is formed on the entire surface through the above-described steps, general-purpose photolithography and An island is formed in the MOSTFT1 and MOSTFT2 and the emitter region by an etching technique, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.

Next, in order to optimize V _th by controlling the gate channel impurity concentration of the MOSTFTs 1 and 2,
The whole surface is doped with boron ions 83 at a dose of 5 × 10 ¹¹ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 1 × 10 ¹⁷ atoms / cc.

Next, as shown in FIG. 28 (2), using the photoresist 82 as a mask, 1 × 10 5 phosphorus ions 79 are applied to the source / drain portions and the emitter regions of the MOSTFTs 1 and 2 by ion implantation or ion doping. ^Fifteen
doping at a dose of atoms / cm ² , 2 × 1
After setting the donor concentration to 0 ²⁰ atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the silicon oxide film for protecting the emitter region is removed by general-purpose photolithography and etching techniques.

Next, as shown in FIG. 28C, monosilane and methane (CH ₄ ) are used as seeds with the polycrystalline silicon film 152 forming the emitter region by catalytic CVD.
And an appropriate amount of the dopant, and the fine irregularities 16
An n-type polycrystalline diamond film 163 having 8 is formed in the emitter region, and at the same time, an n-type amorphous diamond film 170 is formed on the other silicon oxide film 159 and the glass substrate 111.

Next, as shown in (4) of FIG. 28, the amorphous diamond film 170 was removed by etching with activated hydrogen ions at the time of the above-described catalytic AHA treatment.
Catalytic CVD after etching removal of silicon oxide film 159
Thus, a gate insulating film (silicon oxide film or the like) 118 is formed.

Next, as shown in FIG. 29 (5), the gate electrodes 115 of the MOSTFTs 1 and 2 and the MOST are made of a heat-resistant metal such as a Mo—Ta alloy by a sputtering method.
A gate line connected to the gate electrode of the FT1 is formed, an overcoat film (silicon oxide film or the like) 137 is formed, and after opening the window of the source portion of the MOSTFT2, MO is formed using a heat-resistant metal such as a Mo-Ta alloy by a sputtering method.
The source electrode 127 of STFT2 and the ground line are formed. Further, an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by plasma CVD, catalytic CVD, etc.
An ion activation process for 0 seconds is performed.

Next, as shown in FIG. 29 (6), M
Source / drain part of OSTFT1 and MOSTFT2
Of the gate of the MOSTFT1 and the gate of the MOSTFT2 are connected to the Al wiring 12 containing 1% Si.
8 and at the same time, a source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.

Next, as shown in FIG. 29 (7), after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130, a window of the GND line is opened, and FIG. As shown in (8), the gate extraction electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode portion is opened to expose the emitter 163, and the activity of the above-described catalytic AHA treatment is increased. Clean with hydride ions.

In the above, when forming the polycrystalline diamond film 163, the carbon-containing compound used as a source gas is, for example, 1) a paraffinic hydrocarbon such as methane, ethane, propane, butane, and 2) acetylene. , Allylene-based acetylene-based hydrocarbons 3) olefin-based hydrocarbons such as ethylene, propylene, butylene 4) di-olefin-based hydrocarbons such as butadiene 5) cyclopropane, cyclobutane, cyclopentane,
Alicyclic hydrocarbons such as cyclohexane 6) Aromatic hydrocarbons such as cyclobutadiene, benzene, toluene, xylene and naphthalene 7) Ketones such as acetone, diethyl ketone and benzophenone 8) Alcohols such as methanol and ethanol 9) Trimethylamine And amines such as triethylamine. 10) It may be a substance consisting of only carbon atoms such as graphite, coal, coke, etc., and these may be used alone or in combination of two or more.

Further, usable inert gases are, for example, argon, helium, neon, krypton, xenon and radon. As the dopant, for example, a compound containing boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsenic, selenium, beryllium or the like or a simple substance can be used, and the doping amount may be 10 ²⁰ atoms / cc or more.

Fifth Embodiment In the present embodiment, the present invention is applied to a solar cell as a photoelectric conversion device. The production example is shown below.

First, as shown in FIG. 30 (1), tin or other particles having a high crystallization ratio and a large grain size formed on a metal substrate 111 such as stainless steel by the above-described method according to the present invention.
An n-type polycrystalline silicon film 7 containing a group IV element (Ge, Pb) alone or as a mixture is formed to a thickness of 100 to 200 nm. An n-type impurity such as phosphorus is supplied to the polycrystalline silicon film 7 together with monosilane as PH ₃ or the like, for example, for 1
× 10 ¹⁹ to 1 × 10 ²⁰ atoms / cc.

Next, as shown in FIG. 30B, a catalyst CV is formed on the polycrystalline silicon film 7 by using it as a seed.
I-type polycrystalline silicon film 180 containing tin or another group IV element (Ge, Pb) alone or as a mixture of p or p containing tin or another group IV element (Ge, Pb) alone or as a mixture
The type polycrystalline silicon film 181 and the like are grown to form a photoelectric conversion layer.

For example, tin hydride (SnH ₄ ) is mixed with monosilane at an appropriate ratio by catalytic CVD to grow an i-type tin-containing polycrystalline silicon film 180 having a large grain size to a thickness of 2 to 5 μm. Above, monosilane mixed with p-type impurity boron (such as B ₂ H ₆ ) and tin hydride (SnH ₄ ) at an appropriate ratio, for example, 1 × 10 ¹⁹ to 1 × 10 ²⁰ atoms / cc
P-type large grain size tin-containing polycrystalline silicon film 1
81 is formed to a thickness of 100 to 200 nm. At this time, tin or other group IV element (Ge, Pb) alone or in a mixture, for example, tin is contained in each film at a concentration of 1 × 10 ¹⁵ atoms / cc or more, preferably 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / c.
By containing c, crystal irregularities and stress existing at the crystal grain boundaries are reduced, so that the carrier mobility can be improved.

At this time, the multi-catalyst A
HA treatment may be performed. For example, after a p-type tin-containing polycrystalline silicon film is grown to a thickness of 20 to 30 nm by catalytic CVD, a catalytic AHA treatment is performed, and the p-type tin-containing polycrystalline silicon film is formed to a thickness of 20 to 30 nm by catalytic CVD. To grow
After the catalyst AHA treatment, a p-type tin-containing polycrystalline silicon film is further grown to a thickness of 20 to 30 nm by catalytic CVD, and then each treatment is repeated a required number of times so that the catalyst AHA treatment is performed. Good. By this method, a tin-containing polycrystalline silicon film having a larger grain size can be formed. In addition, a high-speed film formation may be performed by increasing the supply amount of the source gas during the film formation.

Next, as shown in FIG. 30C, a transparent electrode 182 is formed on the entire surface of the tin-containing polycrystalline silicon film having a large grain size of the nip junction formed by the above method. . For example, by a general-purpose sputtering technique, ITO (Indium Tin Oxide) or IZO (Indi
um Zinc Oxide) etc.
It is formed to a thickness of nm. Then, a comb-shaped electrode 183 made of silver or the like is formed in a predetermined area on the above-mentioned layer by a general-purpose sputtering technique using a metal mask in a thickness of 100 to 150 nm.

The above film may not contain tin or another group IV element, but in this case, it can be manufactured in the same manner as described above.

In the solar cell according to the present embodiment, a large-grain polycrystalline silicon film according to the present invention can form a photoelectric conversion thin film having high carrier mobility and high conversion efficiency.
Since a good surface texture structure and a good back surface texture structure are formed, a photoelectric conversion thin film having a high light confinement effect and a high conversion efficiency can be formed. This can be advantageously used not only for a solar cell but also for a thin-film photoelectric conversion device such as a photosensitive drum for electrophotography.

The embodiments of the present invention described above can be variously modified based on the technical idea of the present invention.

For example, the above-described catalyst CVD method and the catalyst AH
The number of repetitions of the process A and each condition may be variously changed, and the material of the substrate and the like to be used is not limited to the above.

Also, the present invention relates to an internal circuit such as a display unit, a peripheral driving circuit, a video signal processing circuit, and a MO such as a memory.
It is suitable for an STFT, but in addition, an active region of an element such as a diode and a passive region such as a resistor, a capacitance (capacitance), a wiring, and an inductance may be formed of a polycrystalline silicon film according to the present invention. It is possible.

[0261]

According to the present invention, as described above, hydrogen or a hydrogen-containing gas and a raw material gas are brought into contact with a heated catalyst, and the reaction species generated by the contact are deposited on a substrate. A step of vapor-phase growing the thin film, and bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst to cause the hydrogen-based active species generated thereby to act on the lower crystalline semiconductor thin film, thereby producing the lower crystalline semiconductor thin film And the annealing step of accelerating the crystallization are repeated, so that the following remarkable functions and effects can be obtained as shown in the following (1) to (4).

(1) Hydrogen or a hydrogen-containing gas and a raw material gas are brought into contact with a heated catalyst to spray reactive species (deposited species or their precursors and radical ions) generated on a substrate to form a lower crystalline semiconductor thin film. The low-crystalline semiconductor thin film is formed, and a high-temperature hydrogen-based molecule, hydrogen-based atom, activated hydrogen ion, or other hydrogen-based activity generated in large quantities by a thermal decomposition reaction and a catalytic decomposition reaction by a heated catalyst. Since the catalyst AHA treatment in which the seeds act by spraying or the like is performed, the following remarkable effects are exhibited due to the addition of the radiant heat of the high-temperature thermal catalyst body.

[0263] 1. Due to the radical action of the hydrogen-based active species, thermal energy moves to the film and locally raises the temperature. In the lower crystalline semiconductor thin film, the crystallization is promoted by etching the amorphous component, and the high-grain high-grain semiconductor film has a large grain size. A polycrystalline film having a crystallization rate is formed, and crystal irregularities and internal stress existing at the crystal grain boundaries are reduced, so that a high carrier mobility and high quality polycrystalline semiconductor thin film can be obtained. In addition, for example, when silicon oxide exists on or in polycrystalline silicon, a reduction reaction occurs with the silicon oxide to generate SiO and the like, thereby evaporating the silicon oxide. Thus, a high-carrier mobility, high-quality polycrystalline silicon film or the like can be obtained.

The microcrystalline silicon-containing amorphous silicon film, the amorphous silicon-containing microcrystalline silicon film, and the like are recrystallized by using the microcrystalline silicon as a seed to form a polycrystalline silicon film having a large grain size. In addition, since the amorphous silicon contained in the film is reduced (etched) by activated hydrogen ions or the like,
A polycrystalline silicon film or the like having a high crystallization rate is formed.

[0265] 2. During this catalytic AHA treatment, the carrier impurities present in the lower crystalline semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration is obtained in each region.

[0266] 3. In addition, cleaning by activated hydrogen ions or the like (reduction and removal of the adsorbed gas and organic residue on the substrate or the like) is possible, and the catalyst is hardly oxidized and deteriorated. This also occurs when a hydrogen-based carrier gas is used.)

[0267] 4. By hydrogenation of activated hydrogen ions or the like, for example, silicon dangling bonds in the polycrystalline silicon film are eliminated, and characteristics are improved.

(2) The step of vapor-phase growing a lower crystalline semiconductor thin film on the polycrystalline semiconductor thin film thus treated with the catalyst AHA is repeated until the target film thickness is reached. It is easy to grow on the base film polycrystallized by the process in a state easily polycrystallized, and it is possible to obtain a target high crystallinity and high quality polycrystalline semiconductor film with a predetermined film thickness. That is, for example, a microcrystalline silicon film formed by catalytic CVD by multi-catalyst AHA processing in which catalytic CVD and catalytic AHA processing are repeated,
Amorphous silicon and microcrystalline silicon-containing polycrystalline silicon are converted into a polycrystalline silicon film by catalytic AHA treatment, and furthermore, vapor phase growth of polycrystalline silicon film by catalytic CVD using the polycrystalline silicon as a seed, and further catalytic AHA treatment Is repeated, a polycrystalline silicon film having a high crystallization rate and a large grain size can be formed.

(3) Since both the catalytic CVD and the catalytic AHA treatment can be performed without generating plasma, a plasma-damage-free, low-stress formed film can be obtained, and the method is simpler and less expensive than the plasma CVD method. Device can be realized.

(4) Even when the substrate temperature is lowered, the catalyst C
Since the desired high-quality polycrystalline semiconductor film can be obtained by the VD and catalytic AHA treatment, the substrate temperature can be lowered, so that a large and inexpensive insulating substrate (glass substrate, heat-resistant resin substrate, etc.) can be used, In this respect, the cost can be reduced.

[Brief description of the drawings]

FIG. 1 shows a MOSTFT according to a first embodiment of the present invention.
3 is a cross-sectional view showing the manufacturing process in order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process in the order of steps.

FIG. 3 is a sectional view showing the manufacturing process in the order of steps.

FIG. 4 is a sectional view showing the manufacturing process in the order of steps.

FIG. 5 is a schematic cross-sectional view of one state of an apparatus for catalytic CVD and catalytic AHA treatment used in the production.

FIG. 6 is a schematic sectional view of the same device in another state.

FIG. 7 is a timing chart of a gas flow rate during processing using the same apparatus.

FIG. 8 is a schematic view of a gas supply system of the apparatus.

FIG. 9 is a graph showing a comparison of Raman spectra of semiconductor films obtained by the same treatment.

FIG. 10 is a graph showing the crystallization ratios of the semiconductor thin films in comparison.

FIG. 11 is a graph showing the comparison of the heavy metal concentration in the membrane depending on the purity of the catalyst and the support.

FIG. 12 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 14 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 15 is a perspective view showing a schematic layout of the whole LCD.

FIG. 16 is an equivalent circuit diagram of the LCD.

FIG. 17 is a cross-sectional view showing another manufacturing process of the LCD in the order of steps.

FIG. 18 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 19 is a cross-sectional view showing various types of MOSTFTs of the LCD.

FIG. 20 is an equivalent circuit diagram of a main part of an organic EL display device according to a third embodiment of the present invention (A), an enlarged cross-sectional view of the main part (B), and a cross-sectional view of a peripheral part of the pixel (C). It is.

FIG. 21 is a cross-sectional view showing a manufacturing process of the organic EL display device in the order of steps.

22A and 22B are an equivalent circuit diagram (A) of an essential part of another organic EL display device, an enlarged sectional view (B) of the essential part, and a sectional view (C) of a peripheral portion of the pixel.

FIG. 23 is a cross-sectional view showing a manufacturing process of the organic EL display device in the order of steps.

FIG. 24 is an equivalent circuit diagram (A) of an essential part of an FED according to a fourth embodiment of the present invention, an enlarged sectional view (B) of the essential part, and a schematic plan view (C) of the essential part.

FIG. 25 is a cross-sectional view showing a manufacturing process of the FED in the order of steps.

FIG. 26 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 27 is an equivalent circuit diagram (A) of a main part of another FED,
It is the expanded sectional view (B) of the principal part, and the top view (C) of the principal part.

FIG. 28 is a cross-sectional view showing a manufacturing process of the FED in the order of steps.

FIG. 29 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 30 is a sectional view illustrating the manufacturing process of the solar cell according to the fifth embodiment of the present invention in the order of steps.

[Explanation of symbols]

1, 61, 98, 111, 157 ... substrate, 7, 67 ... polycrystalline silicon film, 14, 67, 117 ... channel,
15, 75, 102, 105, 115 ... gate electrode,
8, 68, 103, 104, 106, 118 ... gate insulating film, 20, 21, 80, 81, 120, 121 ... n ⁺
Mold source or drain regions, 24, 25, 84, 85 ...
p ⁺ type source or drain region, 27, 28, 86, 9
2, 130, 136, 137 ... insulating film, 29, 30, 8
7, 88, 89, 90, 91, 93, 97, 127, 1
28, 131: electrode, 40: raw material gas, 42: shower head, 44: film forming chamber, 45: susceptor, 46: catalyst, 47: shutter, 48: catalyst power, 94, 96
... Alignment film, 95 ... Liquid crystal, 99 ... Color filter layer, 10
0: protective film, 100 ', 140: black mask layer, 1
32, 133 ... organic light emitting layer, 134, 135, 144 ...
Anode, 138, 141, 142, 171 ... cathode, 150
.., Gate extraction electrode (gate line), 151, shielding film, 152, emitter, 153, n-type polycrystalline silicon film, 155, back metal, 156, phosphor, 158,
168: fine irregularities; 163, n-type polycrystalline diamond film; 180, i-type polycrystalline silicon film; 181, p-type polycrystalline silicon film; 182, transparent electrode; 183, comb-type electrode

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/205 H01L 21/205 5F052 29/786 H05B 33/10 5F110 21/336 33/14 A 31/04 Z H05B 33 / 10 H01L 29/78 627G 33/14 31/04 XF term (reference) 2H092 GA60 HA04 JA25 JA26 JA46 KA04 KA05 KB22 MA08 MA18 MA27 NA26 NA27 NA29 PA02 PA08 PA09 QA07 3K007 AB00 AB04 AB17 AB18 BB06 CA01 CB01 DA00 DB02 DB03 EB00 FA01 FA03 5C094 AA06 AA08 AA43 AA44 BA03 BA21 BA23 BA27 BA43 CA19 EA04 EA05 EB02 GB10 5F045 AA03 AA18 AB01 AB03 AB04 AB05 AB07 AB33 AC01 AC12 AC16 AC17 AC18 AC19 AD07 AD08 AE05 AE07 BB08 CA05 CA05 FA03 FA05 CA05 FA03 5F052 AA11 AA18 DA01 DA02 DA03 DB01 DB02 FA19 HA01 JA01 5F110 AA17 AA30 BB01 BB02 BB04 BB05 CC02 CC08 DD02 DD03 DD13 DD14 DD17 EE06 EE09 EE28 EE32 EE44 EE45 FF02 FF03 FF09 GG29 H13 GG01 HGG HL03 HL05 HL06 HL23 HM15 NN 03 NN23 NN24 NN25 NN35 NN46 NN54 NN72 PP34

Claims (42)

[Claims] In forming a polycrystalline semiconductor thin film on a substrate, a raw material gas is brought into contact with a heated catalyst body, and reactive species generated thereby are deposited on the substrate to form a lower crystalline semiconductor thin film. Forming a vapor phase growth step, contacting hydrogen or a hydrogen-containing gas with the heated catalyst,
The active species thus generated is allowed to act on the lower crystalline semiconductor thin film, and the annealing step of promoting crystallization of the lower crystalline semiconductor thin film is repeated to obtain the polycrystalline semiconductor thin film. A method for forming a thin film. 2. A method for manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate, wherein a raw material gas is brought into contact with a heated catalyst, and a reaction species generated thereby is deposited on the substrate. A vapor phase growth step of forming a conductive semiconductor thin film, and contacting hydrogen or a hydrogen-containing gas with the heated catalyst.
Producing the polycrystalline semiconductor thin film by repeating an annealing step of causing the active species generated thereby to act on the lower crystalline semiconductor thin film and promoting crystallization of the lower crystalline semiconductor thin film, thereby obtaining the polycrystalline semiconductor thin film. Method. 3. The heated catalyst body is brought into contact with at least a part of the raw material gas and the hydrogen-based carrier gas to be catalytically decomposed, and the generated reactive species such as radicals and ions are heated. After depositing on the substrate and vapor-growing the lower crystalline semiconductor thin film, the supply of the source gas is stopped, and at least a part of the hydrogen-based carrier gas is brought into contact with the heating catalyst, whereby 3. The method according to claim 1, wherein the annealing is performed by causing the generated high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions to act on the lower crystalline semiconductor thin film. 4. The method according to claim 3, wherein a supply amount of hydrogen or a hydrogen-containing gas during the annealing is set to be larger than a supply amount of hydrogen or a hydrogen-containing gas during the vapor phase growth. 5. The catalyst body is made of at least one material selected from the group consisting of tungsten, tungsten containing thoria, molybdenum, platinum, palladium, vanadium, silicon, alumina, a ceramic to which a metal is attached, and silicon carbide. A method according to claim 1 or 2, wherein the method comprises: 6. The purity of the catalyst and the support supporting the catalyst is 99.99 wt% or more, preferably 99.999.
The method according to claim 1 or 2, wherein the amount is wt% or more. 7. The low-crystalline semiconductor thin film includes a microcrystalline silicon-containing amorphous silicon film, a microcrystalline silicon (amorphous silicon-containing microcrystalline silicon) film, an amorphous silicon and a microcrystalline silicon-containing polycrystalline silicon film, and a microcrystalline germanium-containing amorphous. germanium film, a microcrystalline germanium (amorphous germanium containing microcrystalline germanium) film, an amorphous germanium and microcrystalline germanium containing polycrystalline germanium film, or Si _x Ge _1-x amorphous silicon germanium film represented by (0 <x <1) 3. The method according to claim 1, wherein the hydrogen or the hydrogen-containing gas comprises hydrogen or a mixed gas of hydrogen and an inert gas. 4. 8. The method according to claim 7, wherein the lower crystalline semiconductor thin film contains at least one kind of Group IV element such as tin in an appropriate amount, and the annealing step is performed in this state. 9. The polycrystalline semiconductor thin film according to claim 1, wherein a channel, a source and a drain region, a wiring, a resistor, a capacitor, an electron emitter, and the like of a thin film insulated gate field effect transistor are formed. Way. 10. The method according to claim 9, wherein after forming the channel, source and drain regions, active regions generated by contacting hydrogen or a hydrogen-containing gas with a heated catalyst body are applied to these regions. The method described. 11. The polycrystalline semiconductor thin film, wherein the crystal grain size is reduced from the inside to the outside to increase the density, or the polycrystalline semiconductor thin film or the fine grain layer and the amorphous semiconductor film are used to form the polycrystalline semiconductor thin film. Coating a semiconductor thin film,
The method according to claim 1. 12. A large grain size layer (the polycrystalline semiconductor thin film) by removing the fine grain size layer or the amorphous semiconductor film.
The method according to claim 11, wherein a source electrode and a drain electrode are formed in contact with the substrate. 13. A silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated circuit device. , Liquid crystal display,
Manufacturing thin films for organic or inorganic electroluminescent displays, field emission displays (FED) devices, light emitting polymer displays, light emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. 3. The method according to 1 or 2. 14. A semiconductor device having an internal circuit and a peripheral circuit, a solid-state imaging device, an electro-optical device, and the like, in which a channel, a source and a drain region of a thin-film insulated gate field-effect transistor constituting at least a part thereof are formed. 14. The method according to claim 13, wherein the method is formed by the polycrystalline semiconductor thin film. 15. The method according to claim 14, further comprising a cathode or an anode connected to a drain or a source of the thin film insulated gate field effect transistor, respectively, below the organic or inorganic electroluminescent layer for each color. 16. The cathode covers the active element including the thin-film insulated gate field-effect transistor, or the cathode or the anode is provided on each layer of the organic or inorganic electroluminescent layer for each color and on the entire surface between each layer. The method according to claim 15, wherein the device is applied. 17. A black mask layer is formed between the organic or inorganic electroluminescent layers for each color.
The method according to claim 15. 18. An n-type poly-electrode grown on the polycrystalline semiconductor thin film while connecting an emitter of the field emission display device to a drain of the thin-film insulated gate field effect transistor via the polycrystalline semiconductor thin film. The method according to claim 14, wherein the method is formed using a crystalline semiconductor film or a polycrystalline diamond film. 19. The method according to claim 18, wherein a ground potential shielding film is formed on the active device including the thin film insulated gate field effect transistor. 20. The method according to claim 19, wherein the shielding film is formed of the same material and in the same step as the gate extraction electrode of the field emission display device. 21. An apparatus for forming a polycrystalline semiconductor thin film on a substrate, comprising: a raw material gas supply unit; a hydrogen or hydrogen-containing gas supply unit; a catalyst body; a catalyst body heating unit; Means, a vapor phase growth step of forming a lower crystalline semiconductor thin film by depositing a reactive species generated by bringing the source gas into contact with the heated catalyst body on the substrate, and the hydrogen or the hydrogen-containing gas. In order to alternately perform an annealing step of accelerating crystallization of the lower crystalline semiconductor thin film by causing active species generated by contacting the heated catalyst body with the heated crystalline body to act on the lower crystalline semiconductor thin film, An apparatus for forming a polycrystalline semiconductor thin film, comprising: a source gas supply unit; and a control unit that controls the hydrogen or hydrogen-containing gas supply unit. 22. An apparatus for manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate, comprising: a raw material gas supply unit; a hydrogen or hydrogen-containing gas supply unit; a catalyst; and a catalyst heating unit A substrate heating means; a vapor phase growth step of forming a lower crystalline semiconductor thin film by depositing a reactive species generated by bringing the raw material gas into contact with the heated catalyst body on the substrate; Alternatively, an annealing step of promoting crystallization of the lower crystalline semiconductor thin film by causing active species generated by bringing a hydrogen-containing gas into contact with the heated catalyst to act on the lower crystalline semiconductor thin film is performed alternately. To this end, an apparatus for manufacturing a semiconductor device, comprising: a control unit for controlling the source gas supply unit and the hydrogen or hydrogen-containing gas supply unit. 23. The apparatus according to claim 21, wherein a supply amount of hydrogen or a hydrogen-containing gas during the annealing is set to be larger than a supply amount of hydrogen or a hydrogen-containing gas during the vapor phase growth. 24. The catalyst body is made of at least one material selected from the group consisting of tungsten, tungsten containing thoria, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics having metal attached thereto, and silicon carbide. Apparatus according to claim 21 or 22, wherein the apparatus is formed. 25. The purity of the catalyst and the support supporting the catalyst is 99.99 wt% or more, preferably 99.99 wt%.
23. The device according to claim 21 or 22, wherein the content is 9 wt% or more. 26. The low-crystalline semiconductor thin film includes a microcrystalline silicon-containing amorphous silicon film, a microcrystalline silicon (amorphous silicon-containing microcrystalline silicon) film, an amorphous silicon and a microcrystalline silicon-containing polycrystalline silicon film, and a microcrystalline germanium-containing amorphous. Germanium film, microcrystalline germanium (amorphous germanium-containing microcrystalline germanium) film, amorphous germanium and polycrystalline germanium film containing microcrystalline germanium,
Or consists Si _x Ge _1-x amorphous silicon germanium film represented by (0 <x <1), and the hydrogen or hydrogen-containing gas is a mixed gas of hydrogen or hydrogen and inert gas, claim 23. The apparatus according to 21 or 22. 27. The lower crystalline semiconductor thin film is made of IV such as tin.
27. The apparatus according to claim 26, wherein the annealing is performed in an appropriate amount of at least one group element. 28. The semiconductor device according to claim 21, wherein the polycrystalline semiconductor thin film forms a channel, a source and a drain region, a wiring, a resistor, a capacitor, an electron emitter or the like of the thin film insulated gate field effect transistor. Equipment. 29. The method according to claim 28, wherein after forming the channel, source and drain regions, active regions generated by contacting hydrogen or a hydrogen-containing gas with a heated catalyst body are applied to these regions. The described device. 30. A silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated circuit device. , Liquid crystal display,
Manufacturing thin films for organic or inorganic electroluminescent displays, field emission displays (FED) devices, light emitting polymer displays, light emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. 23. The apparatus according to 21 or 22. 31. When manufacturing a semiconductor device, a solid-state imaging device, an electro-optical device, or the like having an internal circuit and a peripheral circuit, a channel, a source, and a drain region of a thin-film insulated gate field-effect transistor constituting at least a part of these devices. 31. The device according to claim 30, wherein the device is formed by the polycrystalline semiconductor thin film. 32. The device according to claim 31, wherein a device having a cathode or an anode connected to a drain or a source of the thin-film insulated gate field effect transistor, respectively, is manufactured below the organic or inorganic electroluminescent layer for each color. The described device. 33. The cathode also covers an active element including the thin-film insulated gate field effect transistor, or the cathode or the anode is attached on each layer of the electroluminescent layer for each color and on the entire surface between each layer. 33. The device of claim 32, wherein said device is manufactured. 34. The apparatus according to claim 32, wherein a black mask layer is formed between the electroluminescent layers for each color. 35. An emitter of a field emission display device connected to the drain of the thin-film insulated gate field effect transistor via the polycrystalline semiconductor thin film and an n-type poly grown on the polycrystalline semiconductor thin film. The device according to claim 31, wherein the device is formed of a crystalline semiconductor film or a polycrystalline diamond film. 36. The apparatus according to claim 35, wherein a ground potential shielding film is formed on the active element including the thin film insulated gate field effect transistor. 37. The device according to claim 36, wherein the shielding film is formed of the same material and in the same process as a gate extraction electrode of the field emission display device. 38. A drain or source of a thin-film insulated-gate field-effect transistor comprising a polycrystalline semiconductor thin film according to claim 1 or 2 below an organic or inorganic electroluminescent layer for each color. Having a cathode or an anode, the cathode also covers the active element including the thin-film insulated gate field effect transistor, or the cathode or the entire surface of each layer of the organic or inorganic electroluminescent layer for each color and between the layers. Electro-optical device with an anode attached. 39. The electro-optical device according to claim 38, wherein a black mask layer is formed between the organic or inorganic electroluminescent layers for the respective colors. 40. An emitter of a field emission display (FED) is connected to the drain of the thin-film insulated gate field effect transistor comprising the polycrystalline semiconductor thin film according to claim 1 through the polycrystalline semiconductor thin film. And an electro-optical device formed of an n-type polycrystalline semiconductor film or a polycrystalline diamond film grown on the polycrystalline semiconductor thin film. 41. The electro-optical device according to claim 40, wherein a ground potential shielding film is formed on the active element including the thin film insulated gate field effect transistor. 42. The electro-optical device according to claim 41, wherein the shielding film is formed of the same material and in the same process as a gate extraction electrode of the field emission display device.