JP4599734B2 - Method for forming polycrystalline semiconductor thin film and method for manufacturing semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method and apparatus for forming a polycrystalline semiconductor thin film such as polycrystalline silicon on a substrate, and a method and apparatus for manufacturing a semiconductor device having the polycrystalline semiconductor thin film on a substrate.
[0002]
[Prior art]
Conventionally, when a source, drain, and channel region of a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) such as a MOS TFT (Thin Film Transistor = Thin Film Insulated Gate Field Effect Transistor) is formed of a polycrystalline silicon film, plasma CVD ( CVD: Chemical Vapor Deposition = Chemical Vapor Deposition) and low pressure CVD are used.
[0003]
For example, according to JP-A-6-140325, an amorphous carbon thin film is formed on a glass substrate by plasma CVD, sputtering, or the like, and carbon clusters existing on the surface of the amorphous carbon thin film are stabilized by plasma hydrogen treatment. Further, the amorphous carbon existing in the vicinity thereof is slightly etched. After that, a hydrogen-containing amorphous silicon film (a-Si: H film) is deposited by 2 to 20 μm by plasma CVD. Finally, the temperature of the glass substrate is raised from room temperature to 800 ° C. for 8 to 20 seconds, then rapidly heated with a halogen lamp for 15 to 500 seconds, and further lowered to room temperature for one cycle. A ring process is performed a predetermined number of times, for example, 100 times to form a polycrystalline silicon thin film from the a-Si: H film. This is a so-called high-speed lamp annealing method, in which a polycrystalline silicon film is formed with carbon ultrafine particles as nuclei.
[0004]
In addition, amorphous or polycrystalline silicon formed by plasma CVD, low pressure CVD or the like is simply subjected to high-temperature annealing or as shown in JP-A-7-131030, JP-A-9-116156, and JP-B-7-118443. Although the excimer laser annealing (ELA) treatment has improved the carrier mobility of the polycrystalline silicon film, this method uses 80 to 120 cm.²It was the limit to obtain carrier mobility of about / V · sec. However, the electron mobility of MOSTFT using polycrystalline silicon obtained by amorphous silicon ELA by plasma CVD is 100 cm.²/ V · sec, which can cope with high definition, recently, LCD (Liquid Crystal Display) using a polycrystalline silicon MOSTFT integrated with a driving circuit has been attracting attention (Japanese Patent Laid-Open No. 6). -24433)).
[0005]
[Problems to be solved by the invention]
However, none of the above methods can avoid the following drawbacks.
[0006]
1) The formation of ultrafine carbon particles (clusters) in the amorphous carbon thin film becomes unstable due to insufficient energy of the thermal decomposition reaction of the source gas by the RF plasma CVD method or the RF / DC mixed plasma CVD method.
2) Hydrogen treatment of RF plasma or RF / DC mixed plasma has low energy of hydrogen molecules / atoms / ions, low etching effect of carbon having an amorphous structure, and carbon cluster formation becomes unstable.
3) The high-speed lamp annealing method is effective when a substrate having a high thermal conductivity is used, but a glass substrate having a low thermal conductivity or the like takes a long time to cool to room temperature, so that the productivity is poor.
[0007]
In addition, when using an excimer laser, there are many problems such as stability of output, productivity, increase in device price due to increase in size, and decrease in yield / quality. Especially in a large glass substrate of 1 m × 1 m. As a result, the above-mentioned problems are enlarged, and it becomes more difficult to improve performance / quality and reduce costs.
[0008]
In addition, in the method of manufacturing a polycrystalline silicon MOSTFT by solid phase growth, a gate SiO that is annealed at 600 ° C. or more for 10 hours and thermally oxidized at about 1000 ° C.₂Therefore, it is necessary to employ a semiconductor manufacturing apparatus. For this reason, the substrate size is limited to a wafer size of 8 to 12 inches φ, and high-heat-resistant and expensive quartz glass has to be adopted, which makes it difficult to reduce costs and is used for EVF and data / AV projectors. Is limited.
[0009]
Recently, a catalytic CVD method, which is excellent thermal CVD capable of producing a polycrystalline silicon film, a silicon nitride film, etc. on an insulating substrate such as a glass substrate at a low temperature has been developed (Japanese Patent Publication No. 63-40314, Japanese Patent Publication No. 63-40314). No. 8-250438), and the practical application is being promoted. In the catalytic CVD method, 30 cm without crystallization annealing.²Although carrier mobility of about / V · sec is obtained, it is still insufficient for producing a high-quality MOSTFT device. When a polycrystalline silicon film is formed on a glass substrate, an initial amorphous silicon transition layer (thickness of 5 to 10 nm) is likely to be formed depending on the film forming conditions. Mobility is difficult to obtain. In general, an LCD using a drive circuit integrated type polycrystalline silicon MOSTFT is easy to manufacture with a bottom gate type MOSTFT in terms of yield and productivity, but this problem becomes a bottleneck.
[0010]
An object of the present invention is to provide a method capable of forming a polycrystalline semiconductor thin film such as polycrystalline silicon having a high crystallization rate and high quality easily and at a low cost and in a large area, and an apparatus for carrying out this method. There is to do.
[0011]
Another object of the present invention is to provide a method of manufacturing a semiconductor device such as a MOSTFT having such a polycrystalline semiconductor thin film as a constituent part, and an apparatus for carrying out this method.
[0012]
[Means for Solving the Problems]
That is, the present invention provides a method for forming a polycrystalline semiconductor thin film on a substrate or a semiconductor device having a polycrystalline semiconductor thin film on a substrate.
Forming a carbon thin film comprising amorphous carbon or microcrystalline carbon or a mixture thereof on the substrate;
Hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body, and the activated species produced thereby are allowed to act on the carbon thin film under the action of an electric field or / and a magnetic field lower than the glow discharge starting voltage, to thereby anneal the diamond structure. Forming a carbon ultrafine particle of
Vapor phase growth of a semiconductor material thin film on the carbon ultrafine particles;
This relates to a method for forming a polycrystalline semiconductor thin film, or a method for manufacturing a semiconductor device, wherein the polycrystalline semiconductor thin film is obtained through the steps.
[0013]
The present invention also provides an apparatus for carrying out the method of the present invention.
Means for forming a carbon thin film comprising amorphous carbon or microcrystalline carbon or a mixture thereof;
Hydrogen or hydrogen-containing gas supply means;
A source gas supply means for a semiconductor material thin film to be the polycrystalline semiconductor thin film;
A catalyst body;
Catalyst body heating means;
A substrate heating means;
An electric field or / and magnetic field applying means for applying an electric field or / and a magnetic field below the glow discharge starting voltage;
An apparatus for forming a polycrystalline semiconductor thin film or an apparatus for manufacturing a semiconductor device is provided.
[0014]
According to the present invention, when forming a polycrystalline semiconductor thin film on a substrate, microcrystalline carbon-containing amorphous carbon (hereinafter referred to as amorphous carbon) or amorphous carbon-containing microcrystalline carbon (hereinafter referred to as microcrystalline carbon) is formed on the substrate. A carbon thin film made of carbon or a mixture thereof, and hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body, and the generated active species are subjected to an electric field or / and a magnetic field below the glow discharge start voltage. Since the carbon thin film is annealed by acting on the carbon thin film under the action of the above, the semiconductor material thin film is vapor-phase grown using the carbon ultra fine particles as seeds (crystal growth nuclei). The remarkable effects as shown in the following (1) to (4) can be obtained.
[0015]
(1) Glow discharge starts for hydrogen-based active species (hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions) generated by bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst body By the annealing process (hereinafter referred to as a bias catalyst AHA (Atomic Hydrogen Anneal) process) that is performed under the action of an electric field or / and magnetic field that is lower than the voltage (that is, lower than the plasma generation voltage according to Paschen's law). Since it is made to act on the thin film by spraying or the like, the following remarkable effect is exhibited with the addition of heating by the radiant heat of the high-temperature heating catalyst body.
[0016]
In this bias catalyst AHA treatment, hydrogen is brought into contact with a high-temperature catalyst body (800 to 2000 ° C. below the melting point, for example, 1500 to 2000 ° C. for tungsten) under a hydrogen or hydrogen-containing gas pressure of 10 to 50 Pa, thereby producing a large amount of high temperature. Of hydrogen-based active species (hydrogen-based molecules / hydrogen-based atoms / activated hydrogen ions, etc.) and sprayed onto the amorphous carbon film or microcrystalline carbon film formed on the substrate (however, the substrate temperature is 200-500 ° C), sufficient directivity in the acceleration electric field and / or magnetic field by the electric field in addition to the thermal energy possessed by a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.) It moves to the film etc. by sexual kinetic energy and locally raises the temperature of the film etc., and amorphous carbon film and microcrystalline carbon film etc. are amorphous The portion is removed by etching and polycrystallized, and the carbon ultrafine particles (clusters) having a diamond structure are reliably and stably spotted on the surface of an amorphous carbon film or a microcrystalline carbon film or a substrate (for example, a glass substrate). This can be effectively used as a seed for crystal growth of the next polycrystalline silicon or the like. At this time, in particular, the gate channel region and the like are scattered in islands, and the electrical resistance needs to be small enough to be ignored.
[0017]
(2) The diamond-structured carbon ultrafine particles obtained by the bias catalyst AHA treatment are used as seeds, and the semiconductor material thin film is easily grown on the polycrystalline material (as a polycrystalline semiconductor thin film). By the subsequent bias catalyst AHA treatment and vapor phase growth, crystallization of the silicon film or the like grown on the polycrystalline semiconductor thin film is promoted by using the polycrystalline semiconductor thin film as a seed. A polycrystalline semiconductor thin film having a high crystallization rate and high quality can be obtained. That is, if there is an amorphous component in the silicon film formed by catalytic CVD, for example, by the bias catalyst AHA treatment, this is removed by etching, and the silicon film that is grown in the vapor phase is removed from the underlying polycrystalline silicon. A thin film is used as a seed (crystal growth nucleus) to make a polycrystalline silicon film more easily. Furthermore, if the same bias catalyst AHA treatment and vapor phase growth are repeated, a large amount of high-temperature hydrogen-based active species has thermal energy. Moves to the film or the like by sufficient directional kinetic energy due to the acceleration electric field or / and the magnetic field, and locally raises the temperature of the film or the like, and amorphous silicon or microcrystalline silicon is polycrystallized. Can be highly crystallized to form a polycrystalline silicon thin film having a high crystallization rate and a large grain size. As a result, not only the top gate type, but also the bottom gate type and dual gate type MOS TFT can obtain a large grain polycrystalline silicon thin film with high carrier (electron / hole) mobility. High-speed, high current density semiconductor devices, electro-optical devices, and high-efficiency solar cells using semiconductors such as polycrystalline silicon can be manufactured.
[0018]
(3) Since this bias catalyst AHA treatment can be performed without generating plasma, there is no damage caused by plasma, and a simpler and cheaper apparatus can be realized as compared with plasma treatment.
[0019]
(4) Since the energy of the active species is large even when the substrate temperature is lowered, carbon ultrafine particles having a target diamond structure can be obtained stably and reliably, and the substrate temperature is particularly low at 200 to 400 ° C. Even if it is changed, the polycrystalline semiconductor thin film grows efficiently using carbon ultrafine particles as a seed, so that large and inexpensive low-strain-point insulating substrates (glass substrates, heat-resistant resin substrates, etc.) can be used. Down is possible.
[0020]
In the present invention, diamond-structured carbon ultrafine particles formed by the above-described bias catalyst AHA treatment have a particle diameter of 10 nm or less and 1 to 100 / μm.²It is desirable that the area ratio is scattered. The polycrystalline semiconductor thin film is based on a polycrystal having a large particle size (generally several hundred nm or more in grain size) from which an amorphous component has been removed or may be present in a very small amount. Consists of a containing structure. The above-mentioned semiconductor material thin film which becomes the polycrystalline semiconductor thin film is a low crystalline semiconductor thin film other than polycrystal, and has a structure based on a microcrystal containing an amorphous component, a so-called microcrystalline semiconductor thin film. Or a structure based on an amorphous (amorphous) containing microcrystals, that is, a so-called amorphous semiconductor thin film, this is polycrystallized by using the above-mentioned carbon ultrafine particles as seeds. .
[0021]
DETAILED DESCRIPTION OF THE INVENTION
In the method and apparatus of the present invention, the carbon thin film is grown by vapor phase growth method (catalytic CVD method, plasma CVD method, low pressure CVD method, atmospheric pressure CVD method, photo CVD method, high density plasma CVD method (ECR plasma CVD or the like). ), High-density catalytic CVD method (a combination of high-density plasma CVD and catalytic CVD), etc .: hereinafter the same) or physical film-forming methods (sputtering method, etc .: hereinafter the same) It is good to form by a phase growth method. In this case, at least a part of the raw material gas and hydrogen or a hydrogen-containing gas (hydrogen gas + inert gas) is preferably brought into contact with the catalyst body heated to a temperature lower than the melting point (for example, 1600 to 1800 ° C.). If necessary, reactive species such as radicals and ions generated by catalytic decomposition are deposited on the heated substrate under the action of an electric field or / and magnetic field below the glow discharge starting voltage, and the carbon thin film and It is preferable that the semiconductor material thin film is vapor-phase grown by catalytic CVD (bias catalytic CVD in the case of the electric field or / and magnetic field). Further, after the vapor phase growth, the supply of the raw material gas is stopped, and desirably, a catalyst body heated to a temperature lower than the melting point (this may be the same as the catalyst body, but it is different. And at least a part of the hydrogen or hydrogen-containing gas may be contacted, and the hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated thereby The annealing may be performed by applying a bias catalyst AHA treatment to the semiconductor material thin film.
[0022]
In this case, the supply amount of hydrogen or hydrogen-containing gas at the time of annealing is made larger than the supply amount of hydrogen or hydrogen-containing gas at the time of vapor phase growth. For example, the hydrogen-based carrier gas used in vapor phase growth is hydrogen or a mixed gas of hydrogen and an inert gas (argon, helium, xenon, krypton, radon, etc., which has good thermal conductivity and contributes to improved reactivity). In the case of a mixed gas, the hydrogen content ratio is 70 to 80 mol% or more, whereby oxidation deterioration of the catalyst body can be prevented. The hydrogen or hydrogen-containing gas used during the treatment of the bias catalyst AHA may be the same as the hydrogen-based carrier gas used during vapor phase growth. For example, the gas flow rate is 300 to 1000 SCCM (Standard cc per minute), and the gas pressure is 10 to 50 Pa. (Gas pressure during catalytic CVD is 0.1 to several Pa), and it is preferable to increase the heat conduction by gas and increase the amount of hydrogen-based active species generated.
[0023]
In addition, after vapor growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is brought into contact with a heated catalyst body, and hydrogen-based activity such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated thereby. Annealing is performed by applying seeds to the semiconductor material thin film under the action of an electric field or / and a magnetic field below the glow discharge starting voltage, and if necessary, vapor phase growth of the semiconductor material thin film similar to the semiconductor material thin film and the annealing It is desirable to repeat. For this purpose, it is preferable to have a control means for controlling the source gas supply means and the hydrogen or hydrogen-containing gas supply means.
[0024]
That is, the process of vapor-phase-growing a semiconductor material thin film on the polycrystalline semiconductor thin film obtained by the bias catalyst AHA treatment and the annealing process are repeated until the desired film thickness is obtained, so to speak, a multi-step of two steps or more. By the bias catalyst AHA treatment, the semiconductor material thin film is easily grown on the base film already polycrystallized by the bias catalyst AHA treatment, using this as a seed, and is easily crystallized, and has a desired high crystallization rate. A high-quality polycrystalline semiconductor film can be obtained with a predetermined film thickness. That is, by using a multi-bias catalyst AHA process that repeats a catalytic CVD or a bias catalyst CVD and a bias catalyst AHA process, for example, polycrystalline silicon formed on a carbon ultrafine particle layer by catalytic CVD is seeded by a bias catalyst AHA process. A polycrystalline silicon film having a high crystallization rate and a large grain size can be formed by vapor-phase-growing a semiconductor material thin film on the surface by catalytic CVD or bias catalytic CVD and further performing a bias catalyst AHA treatment.
[0025]
Specifically, in a silicon film, the thermal energy of a large amount of high-temperature hydrogen-based active species moves with sufficient directional kinetic energy in the accelerating electric field generated by the electric field, and the temperature of the film is localized. As a result, the amorphous silicon and the like are polycrystallized, and the polycrystalline silicon is highly crystallized, so that a polycrystalline silicon film having a large grain size is easily formed. Thus, the carrier mobility can be improved.
[0026]
In addition, when silicon oxide is present on the polycrystalline silicon film or in the film or at the grain boundary, the hydrogen-based active species react with this to generate SiO and evaporate, so that on the polycrystalline silicon film or Silicon oxide in the film can be reduced / removed, and carrier mobility can be improved.
[0027]
Further, in the case of this bias catalytic CVD process, the type and temperature of the catalyst body, the type and amount of electric field or / and magnetic field applied, the substrate heating temperature, the vapor deposition conditions, the type of source gas, the n-type or p-type impurities to be added A polycrystalline silicon film having a wide range of n-type or p-type impurity concentration can be easily obtained depending on the concentration and the like, and a polycrystalline silicon film having a large grain size can be formed by the bias catalyst AHA treatment. V_th(Threshold) adjustment is easy, and high-speed operation with low resistance is possible.
[0028]
When microcrystalline silicon is formed by plasma CVD and this is subjected to bias catalyst AHA treatment, hydrogen contained in the microcrystalline silicon film by plasma CVD is reduced / removed by bias catalyst AHA treatment. Therefore, a polycrystalline silicon film having a large particle size can be formed, and thus a polycrystalline silicon film having a large carrier mobility can be formed. Furthermore, a polycrystalline silicon film having a wide range of n or p-type impurity concentration can be easily obtained depending on the substrate heating temperature, vapor phase deposition conditions, source gas type, bias catalyst AHA treatment conditions, added n or p-type impurity concentration, etc. Therefore, V with high carrier mobility_thAdjustment is easy and high-speed operation with low resistance is possible.
[0029]
In addition, when the bias catalyst AHA treatment is performed after film formation by sputtering, a wide range of n depends on the specific resistance of the silicon target (concentration of added n or p-type impurities), sputtering film formation conditions, substrate heating temperature, bias catalyst AHA treatment conditions, and the like. Alternatively, since a polycrystalline silicon film having a p-type impurity concentration can be easily obtained, V can be obtained with high carrier mobility._thAdjustment is easy and high-speed operation with low resistance is possible.
[0030]
When CVD is performed by bias catalytic CVD under the action of the bias electric field and / or magnetic field (and further when the bias catalyst AHA treatment and bias catalytic CVD are repeated), in addition to the catalytic action of the catalyst body and its thermal energy, Since an accelerating electric field or / and magnetic field is applied by the voltage, kinetic energy is increased and can be efficiently guided onto the substrate, and migration in the substrate and diffusion in the film during the generation process are sufficient. Therefore, compared with the conventional catalytic CVD method, the kinetic energy of the reactive species generated in the catalyst body can be controlled independently by an electric field or / and a magnetic field, so the reactive species generated by decomposition of the raw material gas by the catalytic body. (Deposition species or precursors thereof and radical ions) are sufficiently diffused in the film during migration and generation processes on the substrate, so that the adhesion of the generated film to the substrate is improved, the density of the generated film is increased, and the generation is performed. Improves film uniformity or smoothness, improves embedding in via holes and step coverage, further lowers the substrate temperature, controls the stress of the generated film, and provides high reaction gas utilization efficiency and production speed Speed up and reduce costs.
[0031]
Specifically, in any of catalytic CVD, bias catalytic CVD, catalytic AHA treatment, and bias catalytic AHA treatment, the catalyst body is heated to a temperature in the range of 800 to 2000 ° C. and lower than its melting point (for example, Energized and heated by its own resistance heating), and the heated catalyst body generates at least a part of the source gas and / or the hydrogen or hydrogen-containing gas (carrier gas) by catalytic reaction or pyrolysis reaction The reactive species or hydrogen-based active species can be deposited as a thin film on a substrate heated to 200 to 800 ° C., or the thin film can be annealed. Such catalyst body temperature and the following catalyst body material may be the same for the catalyst CVD, the bias catalyst CVD, the catalyst AHA, and the bias catalyst AHA treatment.
[0032]
Here, when the heating temperature of the catalyst body is less than 800 ° C., the catalytic reaction or thermal decomposition reaction becomes insufficient, and the deposition rate of the reactive species and the thermal energy of the hydrogen-based active species tend to decrease, and 2000 ° C. is reduced. If exceeded, the constituent material of the catalyst body will be mixed into the deposited film, impairing the electrical characteristics of the film, resulting in deterioration of the film quality, and heating beyond the melting point of the catalyst body will be lost because its morphological stability is lost. It is good to do. The heating temperature of the catalyst body is preferably below 1100 ° C. to 1800 ° C. below the melting point of its constituent materials.
[0033]
The catalyst body can be formed of at least one material selected from the group consisting of tungsten, tria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics with metal attached, and silicon carbide.
[0034]
The purity of the polycrystalline semiconductor thin film formed by setting the purity of the catalyst body and the support body supporting the catalyst body to 99.99 wt% (4N) or more, preferably 99.999 wt% (5N) or more. Heavy metal contamination can be reduced.
[0035]
In addition, the substrate temperature is preferably 200 to 800 ° C., more preferably 300 to 400 ° C., whereby efficient and high quality film formation can be performed. When the substrate temperature is high, inexpensive borosilicate glass and aluminosilicate glass cannot be used, and the impurity doping concentration distribution is likely to change due to the influence of heat.
[0036]
As the electric field in the bias catalyst AHA treatment (or bias catalyst CVD), a direct current voltage lower than the glow discharge start voltage (that is, a plasma generation voltage or less determined by Paschen's law, for example, 1 kV or less, several tens of volts or more) is applied, It is desirable to direct hydrogen-based active species or the like toward the substrate.
[0037]
And, as the electric field, a voltage obtained by superimposing an alternating voltage (a high frequency voltage and / or a low frequency voltage) on a direct current voltage (DC) that is equal to or lower than a glow discharge start voltage (that is, a plasma generation voltage or lower determined by Paschen's law, For example, when applying 1 kV or less and several tens of volts or more), the kinetic energy due to a subtle electric field change can be given to the hydrogen-based active species (or reactive species) by the AC voltage superimposed on the DC voltage. In addition to the effect, films with various shapes can be annealed effectively enough, or the substrate surface with complex shapes (such as uneven steps and high aspect ratio via holes) has good step coverage and is uniform A film with high adhesion and density can be formed. The same effect as this is also obtained when an AC voltage (a high frequency voltage and / or a low frequency voltage) is applied as the voltage for forming the electric field (however, the absolute value is equal to or lower than the glow discharge start voltage). can get. In the above, the AC voltage means only a high frequency voltage, only a low frequency voltage, or a voltage obtained by superimposing a high frequency voltage on a low frequency voltage.
[0038]
In the above case, the AC voltage may be a high frequency voltage (RF) and / or a low frequency voltage (AC), but the frequency of the high frequency voltage is preferably 1 to 100 MHz and the frequency of the low frequency voltage is preferably less than 1 MHz.
[0039]
The electric field is applied by applying a positive DC voltage to the electrode and applying a negative DC voltage (or ground) to the susceptor (substrate), or a ground potential to the electrode, or a negative voltage or low frequency (or high frequency) to the susceptor (substrate). Any method of applying a voltage may be used. This may be determined according to the device structure, the type of power supply, the bias effect, and the like.
[0040]
And the said catalyst body can be installed between the said base | substrate or the said susceptor, and the said electrode for electric field application. In this case, a gas supply port for leading out the hydrogen or the hydrogen-containing gas and the raw material gas is preferably formed in the electrode.
[0041]
The catalyst body and the electrode for applying an electric field may be installed between the base body or the susceptor and the gas supply means. The electrode is preferably formed of a high heat-resistant material, for example, a material having the same or higher melting point as the catalyst body (hereinafter the same).
[0042]
The catalyst body or the electrode for applying an electric field may be formed in a coil shape, a wire shape, a mesh shape, or a porous plate shape, and a plurality or a plurality of electrodes may be arranged along the gas flow. As a result, the gas flow can be effectively formed, the contact area between the catalyst body and the gas can be increased, and the catalytic reaction can be sufficiently caused. In the case where a plurality or a plurality of plates are arranged along the gas flow, they may be catalyst bodies or electrodes made of the same material or different materials. Also, different electric fields such as DC and AC / DC, DC and RF / DC, AC / DC and RF / DC are applied to each of the catalyst bodies arranged in plural or plural, and controlled independently. Also good.
[0043]
The bias catalyst AHA treatment can be performed by the following methods (1) to (3).
(1) Electric field application
When catalytic AHA treatment, so-called electric field bias catalyst AHA treatment, is performed under the action of an appropriate electric field below the glow discharge starting voltage, hydrogen gas or hydrogen-based gas (hydrogen + inert gas) is subjected to catalytic reaction or catalytic decomposition reaction of the catalyst body. The generated hydrogen-based active species interacts with the electric field and is directed in a certain direction, and is given directional kinetic energy to act on the fine particle layer on the substrate.
[0044]
(2) Magnetic field application
When catalytic AHA treatment, so-called magnetic field biased catalyst AHA treatment, is performed under the action of an appropriate magnetic field, hydrogen gas or hydrogen-based gas (hydrogen + inert gas) is generated by catalytic reaction or catalytic cracking reaction of the catalyst body. The system active species interacts with the magnetic field and is directed in a certain direction, imparting directional kinetic energy, and acts on the fine particle layer on the substrate.
[0045]
(3) Electric field and magnetic field application
When an appropriate electric field equal to or lower than the glow discharge starting voltage and an appropriate magnetic field are simultaneously applied to perform catalyst AHA treatment, so-called electric field / magnetic field bias catalyst AHA treatment, hydrogen gas or hydrogen-based gas (hydrogen + inert gas) is generated. Hydrogen-based active species generated by catalytic reaction or catalytic cracking reaction of the catalyst body are directed in a certain direction by the interaction of electric and magnetic fields, and direct kinetic energy is applied to act on the fine particle layer on the substrate. To do.
[0046]
Due to the bias effect as described above, amorphous components in carbon thin films and lower crystalline semiconductor thin films can be selectively and efficiently selected by a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions). Etched, for example, amorphous silicon-containing microcrystalline silicon or microcrystalline silicon-containing amorphous silicon is polycrystallized by etching an amorphous component, and amorphous silicon and microcrystalline silicon-containing polycrystalline silicon are highly crystallized to form a polycrystalline silicon film. Is formed efficiently.
[0047]
Moreover, said bias catalyst CVD method can be performed by the following methods (1) to (3).
(1) Electric field application
When catalytic CVD, or so-called field-biased catalytic CVD, is performed under the action of an electric field lower than the glow discharge starting voltage, the deposition species generated by the catalytic reaction or catalytic decomposition reaction of the catalytic body, for example, the electron spin of silicon atoms interact with the electric field. In this state, the crystal orientations of silicon deposited on the substrate are aligned.
[0048]
(2) Magnetic field application
When catalytic CVD under the action of an appropriate magnetic field, so-called magnetic field bias catalytic CVD, deposition species generated by catalytic reaction or catalytic decomposition reaction of the catalytic body, for example, the electron spin of silicon atoms interacts with the magnetic field and becomes constant. The crystal orientation of silicon deposited on the substrate in this state is aligned.
[0049]
(3) Electric field and magnetic field application
When an appropriate electric field below the glow discharge starting voltage and an appropriate magnetic field are simultaneously applied to perform catalytic CVD, so-called electric field / magnetic field bias catalytic CVD, the deposited species generated by catalytic reaction or catalytic decomposition reaction of the catalyst body, For example, the electron spin of silicon atoms is further directed in a certain direction due to the interaction between the electric field and the magnetic field, and the crystal orientation of silicon deposited on the substrate is aligned in this state.
[0050]
Due to the bias effect as described above,
(1) Since the crystal orientations of the crystallized film are almost aligned, the electron potential barrier of the grain boundary is lowered, and the carrier mobility is increased.
(2) By aligning the crystal grains, the surface of the polycrystalline silicon thin film is eliminated and the surface of the thin film is flattened, so the interface state with the gate insulating film, etc. formed in contact with the surface is good. Thus, carrier mobility is improved, breakdown voltage is improved, and TFT characteristics are improved.
The effect is obtained.
[0051]
For example, when a polycrystalline silicon film is formed by a normal thermal CVD method, the substrate temperature needs to be about 600 to 900 ° C. When this is formed by catalytic CVD (or bias catalytic CVD), Is advantageous because it enables thermal CVD at low temperatures as described above without requiring plasma or photoexcitation. Since the substrate temperature at the time of catalytic CVD (or bias catalytic CVD) is low as described above, a glass such as borosilicate glass or aluminosilicate glass having a low strain point of 470 to 670 ° C. as a substrate, for example, a glass substrate. Can be used. This is inexpensive, can be easily reduced in thickness, can be increased in size (1 m × 1 m or more), and a long rolled glass plate can be produced. For example, a thin film can be produced continuously or discontinuously on a long rolled glass plate using the above method.
[0052]
In the case of a carbon thin film, the raw material gas used for vapor phase growth by catalytic CVD according to the present invention includes hydrocarbons such as methane, ethane, and propane or derivatives thereof. In the case of a semiconductor material thin film, silicon hydride or a derivative thereof, a mixture of silicon hydride or a derivative thereof and a gas containing hydrogen, germanium or tin, silicon hydride or a derivative thereof and a periodic table group III or group V Mixtures of gases containing impurities consisting of elements, mixtures of silicon hydride or derivatives thereof with gases containing hydrogen, germanium or tin, and gases containing impurities consisting of Group III or V elements of the periodic table, etc. Is mentioned.
[0053]
By using the raw material gas as described above, an amorphous or microcrystalline carbon thin film (particle diameter is 10 nm or less) can be formed. In addition, as the polycrystalline semiconductor thin film, a polycrystalline silicon film, a polycrystalline germanium film, or a polycrystalline silicon germanium film can be formed.
[0054]
And, at the time of or after the growth of the semiconductor material thin film, the total amount of at least one group IV element such as tin, germanium, lead, etc. is appropriate (10¹⁶atoms / cc or more, for example, 10¹⁸-10²⁰atoms / cc) (further, the annealing step by the catalyst AHA treatment is performed in this state), the irregularities existing in the grain boundaries of the polycrystalline semiconductor thin film are reduced, and the film stress is reduced. Therefore, it becomes easy to obtain a polycrystalline semiconductor with high carrier mobility and high quality. Since these group IV elements do not generate electrons or holes in the silicon film, TFT characteristics are not impaired and gettering is not necessary. This group IV element can be mixed in the source gas as a gas component, or can be contained in the semiconductor material thin film by ion implantation or ion doping. Further, the oxygen, nitrogen and carbon concentrations in the polycrystalline semiconductor film formed according to the present invention are 1 × 10 3 respectively.¹⁹atoms / cc or less, preferably 5 × 10¹⁸atoms / cc or less is preferable, and the hydrogen concentration is preferably 0.01 atomic% or more. The sodium (Na) concentration is 1 × 10 in the SIMS lowest concentration region.¹⁸atoms / cc or less is preferred.
[0055]
In addition, it is desirable to heat-treat the catalyst body in a hydrogen-based gas atmosphere before supplying the source gas. This is because, if the catalyst body is heated before the supply of the source gas, the constituent material of the catalyst body is released and may be mixed into the film formed, but the catalyst body is heated in a hydrogen-based gas atmosphere. This can eliminate such contamination. Therefore, it is preferable to heat the catalyst body in a state where the film formation chamber is filled with the hydrogen-based gas, and then supply a source gas (so-called reaction gas) using the hydrogen-based gas as a carrier gas.
[0056]
The bias catalyst AHA treatment has an action of selectively removing an amorphous component in the polycrystalline semiconductor thin film by the action of a hydrogen-based active species or the like, and has a high crystallization rate, a large particle size (particularly a grain size of several times). (100 nm or more) is a treatment for forming a polycrystalline thin film and activating carrier impurities in the film. At this time, the catalyst body temperature is 1600 to 1800 ° C., and the distance between the substrate and the catalyst body is It may be arbitrarily changed in order to improve the processing effect such as shortening the processing time by 20 to 50 mm.
[0057]
With the polycrystalline semiconductor thin film obtained by the treatment of the present invention, the channel, source and drain regions of MOSTFT, wiring, resistance, capacitance, electron emitter, or the like can be formed. In this case, after the channel, source and drain regions are formed, if these regions are subjected to the bias catalyst AHA treatment or the catalyst AHA treatment, the n-type or p-type impurities in the film can be activated. Further, this catalyst AHA treatment (or bias catalyst AHA treatment) turns into a polycrystalline silicon film having a high crystallization rate and a large grain size, and a gate insulating film (SiO2) is subsequently formed by catalytic CVD.₂, SiOxNy, SiO₂/ SiN, etc.) can be formed. A polycrystalline silicon film having a high crystallization rate and a large grain size by forming a gate channel, a source and a drain region on a lower crystalline semiconductor thin film containing a group IV element such as Sn, Ge, Pb, etc., and then performing a bias catalyst AHA treatment In succession, the gate insulating film (SiO2) is formed by catalytic CVD.₂, SiOxNy, SiO₂/ SiN etc.) can also be formed.
[0058]
In addition, in order to reduce oxygen penetration from the outside into the polycrystalline semiconductor thin film such as polycrystalline silicon, the crystal grain size is reduced from the gate insulating film side to the outside in the polycrystalline silicon film. The polycrystalline semiconductor thin film is preferably covered with an amorphous semiconductor film such as amorphous silicon or a fine grain layer and an amorphous semiconductor film such as amorphous silicon. In this case, by using general-purpose photolithography and etching techniques, the fine particle size layer or the amorphous semiconductor film can be removed, and the source and drain electrodes in contact with the large particle size layer (the polycrystalline semiconductor thin film) can be formed.
[0059]
The present invention relates to a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, a silicon carbide semiconductor integrated circuit device, Liquid crystal display device, organic or inorganic electroluminescence (EL) display device, field emission display (FED) device, light emitting polymer display device, light emitting diode display device, CCD area / linear sensor device, MOS sensor device, solar cell device It is suitable for forming a thin film.
[0060]
In this case, when manufacturing a semiconductor device having an internal circuit and a peripheral circuit, a solid-state imaging device, an electro-optical device, etc., the channel, source and drain regions of the MOSTFT constituting at least a part thereof are formed by the polycrystalline semiconductor thin film. In addition, it may be a peripheral drive circuit integrated type configuration.
[0061]
Moreover, it is good to set it as the EL element structure which has the cathode or anode connected to the drain or source of the said MOSTFT in the lower layer of the organic or inorganic electroluminescent layer for each color, respectively.
[0062]
In this case, if the cathode is also covered on the active elements such as the MOSTFT and the diode, the light emitting area is increased in the structure having the anode on the upper side, and the emitted light is incident on the active element due to the light shielding action of the cathode. Therefore, it is possible to prevent a leak current from being generated. Further, if the cathode or anode is deposited on the entire surface of each organic or inorganic EL layer for each color and between the respective layers, the entire surface is covered with the cathode or anode, so that the organic EL is weak against moisture. Prevents layer degradation and electrode oxidation, enabling long life, high quality, and high reliability. Covering with a cathode increases the heat dissipation effect, so the structure of the thin film changes due to heat generation (melting or recrystallization). As a result, a long life, high quality, and high reliability can be achieved. In addition, a high-precision, high-quality full-color organic EL layer can be formed with high productivity, so that the cost can be reduced.
[0063]
Further, when a black mask layer of chromium, chromium dioxide or the like is formed between the organic or inorganic EL layers for each color, light leakage between each color or between pixels is prevented, and the contrast is improved.
[0064]
When the present invention is applied to a field emission display device, the emitter (field emission cathode) is connected to the drain of the MOSTFT through the polycrystalline semiconductor thin film and grown on the polycrystalline semiconductor thin film. The n-type polycrystalline semiconductor film or the polycrystalline diamond film is preferably used.
[0065]
In this case, a metal-based shielding film having a ground potential on the active element such as the MOSTFT or the diode (this is advantageous in terms of simplification of the process and the like when formed in the same process with the same material as the gate extraction electrode of the FED device). In other words, the gas in the hermetic container is positively ionized by electrons emitted from the emitter and is charged up on the insulating layer, and this positive charge forms an unnecessary inversion layer on the active element under the insulating layer. It is possible to prevent the emitter current from running away due to the formation or excessive current flowing through this inversion layer. Further, when the phosphor emits light due to collision of electrons emitted from the emitter, it is possible to prevent leakage current from being generated due to the generation of electrons and holes in the gate channel of the TFT due to this light.
[0066]
Next, the present invention will be described in more detail with respect to preferred embodiments.
[0067]
First embodiment
A first embodiment of the present invention will be described with reference to FIGS.
[0068]
In this embodiment, the present invention is applied to a top gate type polycrystalline silicon CMOS (Complementary MOS) TFT.
[0069]
<Catalytic CVD method, bias catalyst AHA treatment and apparatus>
First, the bias catalyst CVD method (or catalyst CVD method) and the bias catalyst AHA treatment used in the present embodiment will be described. In the catalytic CVD method, a reaction gas composed of a hydrogen-based carrier gas and a source gas such as silane gas is brought into contact with a heated catalyst body such as tungsten, and the radical deposition species generated thereby or its precursor and activated hydrogen are contacted. High energy is applied to hydrogen-based active species such as ions (in the case of bias catalytic CVD, direct kinetic energy is applied by the action of an electric field lower than the glow discharge starting voltage), and amorphous silicon-containing microcrystalline silicon, etc. Crystalline semiconductor thin films and amorphous or microcrystalline carbon thin films are vapor-phase grown. Then, after the film formation, the supply of the source gas is stopped and only the hydrogen-based carrier gas is supplied to perform the bias catalyst AHA treatment of the thin film (the bias catalyst AHA treatment and the catalytic CVD are repeated as necessary). ). In other words, amorphous component silicon is reductively etched by hydrogen-based active species such as high-temperature hydrogen molecules, hydrogen atoms, and activated hydrogen ions, and a high crystallization ratio of a predetermined film thickness, a large grain size of polycrystalline silicon, etc. A crystalline semiconductor thin film is obtained, or diamond-structured carbon ultrafine particles are formed, or polycrystalline silicon or the like is grown to a large particle size using these carbon ultrafine particles as seeds (crystal growth nuclei). By repeating these bias catalyst AHA treatment and catalytic CVD, a polycrystalline semiconductor thin film such as polycrystalline silicon having a larger particle diameter and a predetermined film thickness is obtained.
[0070]
In the bias catalyst AHA treatment and the bias catalyst CVD, a DC voltage not higher than a glow discharge start voltage (a DC voltage determined by Paschen's law, for example, a voltage not higher than 1 kV) is applied between the substrate and the counter electrode, and the hydrogen System active species, or the radical deposition species or precursors thereof, and radical hydrogen ions are directed toward the substrate. Hereinafter, the AHA process and the CVD method according to the present embodiment are referred to as a DC bias catalyst AHA process and a DC bias catalyst CVD method, but the same applies to the case of AC bias (RF) or AC / DC superimposed bias (RF / DC). is there.
[0071]
This DC bias catalyst AHA treatment or CVD method is carried out using an apparatus as shown in FIGS.
[0072]
According to this apparatus, a hydrogen-based carrier gas and a source gas 40 such as silicon hydride (for example, monosilane) (and B B if necessary)₂H₆And PH_ThreeIncluding a doping gas such as ) Is introduced from a supply conduit 41 into a chamber 44 for film formation or annealing through a supply port (not shown) of a shower head 42. Inside the chamber 44 are a susceptor 45 for supporting the substrate 1 such as glass, a shower head 42 with good heat resistance (desirably having a melting point equal to or higher than that of the catalyst body 46), and, for example, A catalyst body 46 such as coiled tungsten and a shutter 47 that can be opened and closed are arranged. A magnetic seal 52 is provided between the susceptor 45 and the chamber 44. The chamber 44 is followed by a front chamber 53 that performs a pre-process, and is exhausted through a valve 55 by a turbo molecular pump or the like.
[0073]
The substrate 1 is heated by heating means such as the heater wire 51 in the susceptor 45, and the catalyst body 46 is heated to a melting point or lower (particularly 800 to 2000 ° C., in the case of tungsten, about 1600 to 1800 ° C.) as a resistance wire, for example. And activated. Both terminals of the catalyst body 46 are connected to a DC or AC catalyst body power supply 48 and heated to a predetermined temperature by energization from the power supply. Further, the shower head 42 is connected to the positive side of a variable DC power source (1 kV or less, for example, 500 V) 49 via the conduit 41 as an accelerating electrode, and 1 kV between the negative side susceptor 45 (accordingly, the substrate 1). The following DC bias voltage is applied.
[0074]
In order to carry out this method, the degree of vacuum in the chamber 44 is 1.33 × 10 6 in the state of FIG.^-Four~ 1.33 × 10^-6For example, hydrogen-based carrier gas 100 to 200 SCCM is supplied and the catalyst body is heated to a predetermined temperature and activated, and then hydrocarbon (for example, methane) gas 10 to 20 SCCM or silicon hydride (for example, monosilane) gas 1 ~ 20 SCCM (and B if necessary₂H₆And PH_ThreeAn appropriate amount of a doping gas such as is also included. ) Or a hydrogen-based carrier gas only (300 to 1000 SCCM, gas pressure 10 to 50 Pa) is supplied from the supply conduit 41 to the shower head 42. It is introduced through the mouth 43. Here, the hydrogen-based carrier gas is any gas in which an appropriate amount of an inert gas is mixed with hydrogen, such as hydrogen, hydrogen + argon, hydrogen + helium, hydrogen + neon, hydrogen + xenon, hydrogen + krypton, etc. Good (hereinafter the same). In addition, depending on the kind of source gas, hydrogen carrier gas is not necessarily required.
[0075]
Then, the shutter 47 is opened as shown in FIG. At least a part of the raw material gas 40 or the hydrogen-based carrier gas is catalytically decomposed in contact with the catalyst body 46, and high-energy ions such as silicon and radicals such as radicals are generated by catalytic decomposition reaction or thermal decomposition reaction. Formation of a group (ie, deposited species or precursor thereof and radical hydrogen ions), or hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, and reactions of ions, radicals, and the like thus generated A direct electric field is applied to the seed 50 by a direct current power source 49 of a glow discharge starting voltage (about 1 kV) or less, for example, 500 V, to give directional kinetic energy and direct toward the substrate 1, and the room temperature to 550 ° C. (for example, 200 to A predetermined film of amorphous carbon, lower crystalline silicon or the like is vapor-phase grown on the substrate 1 held at 300 ° C. by DC bias catalytic CVD. Alternatively, directional kinetic energy is imparted to the hydrogen-based active species, and the DC bias catalyst AHA treatment is performed by acting on the film on the substrate 1 held at room temperature to 550 ° C. (for example, 200 to 300 ° C.). The lower crystalline silicon film or the like may be vapor-phase grown by catalytic CVD without using a bias. In this case, the DC power supply 49 is turned off.
[0076]
In this way, directing kinetic energy obtained by applying acceleration energy by a direct current electric field to the catalytic action of the catalyst body 46 and its thermal energy is given to the reactive species or hydrogen-based active species without generating plasma. It can be efficiently converted into reactive species and deposited uniformly on the substrate 1 by thermal CVD. Since the deposited species 56 migrate on the substrate 1 and diffuse in the thin film, it is possible to form a flat and uniform thin film with high density and good step coverage. Alternatively, the hydrogen-based active species generated from the hydrogen-based carrier gas can be efficiently applied to the CVD film with sufficient energy.
[0077]
When DC bias catalytic CVD is applied in the present embodiment, this is independent of the control factors of conventional catalytic CVD, such as substrate temperature, catalyst body temperature, gas pressure (reaction gas flow rate), source gas type, etc. The feature is to add control of thin film formation with a direct current electric field. For this reason, the adhesion of the produced film to the substrate, the produced film density, the produced film uniformity or smoothness, the penetration into the via hole and the step coverage are improved, the substrate temperature is further lowered, and the produced film is Stress control and the like are possible, and a high quality film (for example, a silicon film or a metal film having physical properties close to a bulk) can be obtained. In addition, the reactive species generated by the catalyst body 46 can be independently controlled by a direct current electric field and can be efficiently deposited on the substrate, so that the use efficiency of the reaction gas is high, the production speed is increased, the productivity is improved, and the reaction gas is reduced. Can reduce costs.
[0078]
Also, in the DC bias catalyst AHA treatment, annealing can be controlled by an arbitrary DC electric field independent as described above, and lowering of the substrate temperature, reduction of film stress, etc. improve gas utilization efficiency, and increase the treatment speed. This is possible while improving and reducing costs.
[0079]
In addition, since the energy of the deposited species or active species is large even when the substrate temperature is lowered, the desired high-quality film can be obtained. Therefore, the substrate temperature can be further lowered as described above, and a large and inexpensive insulation can be obtained. A substrate (a glass substrate such as borosilicate glass or aluminosilicate glass, or a heat-resistant resin substrate such as polyimide) can be used. In this respect, the cost can be reduced. In addition, since the gas supply shower head 42 can also be used as an electrode for accelerating the reactive species described above, the structure is simplified.
[0080]
Needless to say, since no plasma is generated, there is no damage caused by plasma, and a low-stress production film can be obtained, and a much simpler and cheaper apparatus is realized as compared with the plasma CVD method or the like.
[0081]
In this case, the operation can be performed under reduced pressure (for example, 0.133 to 1.33 Pa) or under normal pressure, but the normal pressure type is simpler and less expensive than the reduced pressure type. And even if it is a normal pressure type, since said electric field is applied, a high quality film | membrane with good density, uniformity, and adhesiveness is obtained. Also in this case, the normal pressure type has a higher throughput than the reduced pressure type, so that the productivity is high and the cost can be reduced.
[0082]
In the case of the decompression type, the DC voltage depends on the gas pressure (gas flow rate), the gas type, and the like, but in any case, it is necessary to adjust the voltage to an arbitrary voltage equal to or lower than the glow discharge start voltage. In the case of the normal pressure type, no discharge is performed, but the exhaust gas is adjusted so that the exhaust gas flow does not contact the substrate so that the flow of the source gas and the reactive species or active species does not adversely affect the film thickness and film quality. Is desirable.
[0083]
In the above-described DC bias catalytic CVD (or catalytic CVD) or DC bias catalytic AHA treatment, the substrate temperature rises due to the secondary heat generated by the catalyst body 46. As described above, the heater for heating the substrate is used as necessary. 51 may be installed. Moreover, although the catalyst body 46 is coiled (other than this, a mesh, a wire, and a porous plate shape may also be sufficient), it further increases the contact area with gas by making it into multiple steps (for example, 2 to 3 steps) in the gas flow direction. It is good. In addition, since the substrate 1 is disposed above the shower head 42 on the lower surface of the susceptor 45, particles generated in the chamber 44 do not fall and adhere to the substrate 1 or a film thereon.
[0084]
In this embodiment, the apparatus used for catalytic CVD is used as it is, and after the vapor deposition of the carbon thin film such as amorphous carbon or the lower crystalline semiconductor thin film by catalytic CVD, the supply of the source gas such as monosilane is stopped, and the catalyst Only the hydrogen-based carrier gas is supplied into the film forming chamber 44 at a flow rate higher than that at the time of CVD, and a DC bias catalyst AHA treatment is performed on the lower crystalline semiconductor thin film, and the amorphous component is etched and more polycrystallized. In addition, the catalyst CVD and the DC bias catalyst AHA treatment are repeated a predetermined number of times to form a polycrystalline semiconductor thin film such as polycrystalline silicon having a desired film thickness.
[0085]
In this DC bias catalyst AHA treatment, the amorphous component is removed by etching with the hydrogen-based active species decomposed and generated by the heated catalyst to produce ultrafine carbon particles. In the case of a semiconductor material thin film, the underlying ultrafine carbon particles are removed. Although it is easy to polycrystallize as a seed, a thin film based on a polycrystal having a high crystallization rate and a large grain size (especially a grain size of several hundred nm or more) is obtained, and carrier impurities in the film are activated. In this case, the catalyst body temperature is 1600 to 1800 ° C., the distance between the substrate and the catalyst body is 20 to 50 mm, the substrate temperature is 200 to 800 ° C., the treatment time is 10 to 20 minutes, and the hydrogen-based carrier gas is the same as described above. Hydrogen or a mixed gas of hydrogen and an inert gas (argon, helium, xenon, krypton, radon, etc.). Ratio can prevent the oxidation of the catalyst by 70 to 80 mol% or more. The hydrogen or hydrogen-containing gas used during the catalyst AHA treatment may be the same as the hydrogen-based carrier gas during vapor phase growth, but the gas flow rate is increased to 300 to 1000 SCCM and the gas pressure is set to 10 to 50 Pa (for catalytic CVD). 0.1 to several Pa), it is preferable to increase the heat conduction by gas and increase the amount of hydrogen-based active species generated.
[0086]
According to the present invention, according to the crystallization process of a semiconductor thin film under the action of a bias, an electric field or a magnetic field or both of them is applied, and under this action, annealing with a hydrogen-based active species (bias catalyst AHA process) is performed. Alternatively, since the vapor deposition of the deposited species (bias catalytic CVD) is performed, the crystal orientation of the crystal grains can be made uniform. The following is a summary of the DC bias catalyst AHA treatment and the DC bias catalyst CVD described above.
[0087]
First, FIG. 8 shows a case where catalytic CVD, so-called bias catalytic CVD, is performed under the action of the above-described electric field. A high-frequency voltage (or DC voltage, or both) is provided around the vacuum vessel 44 containing the substrate 1. Electrodes 200 and 201 are provided to apply an electric field.
[0088]
At this time, in the case of bias catalytic CVD, the electron spin of the silicon atoms of the deposited species generated by the catalytic reaction or catalytic decomposition reaction of the catalyst body 46 interacts with the electric field and is directed in a certain direction, and solidifies by cooling from this state. In this case, the silicon crystallizes with a certain direction and the crystal orientation of silicon is aligned. Since the crystallized film has almost the same crystal orientation, the electron potential barrier of the grain boundary is lowered and the carrier mobility is increased. At this time, it is important to align the crystal orientation in a certain direction. Depending on the structure of the outer shell orbit of silicon atoms, the crystal may be aligned in the vertical direction of the obtained polycrystalline silicon thin film 7 or in the horizontal direction. Sometimes the crystal orientation is aligned. By aligning the crystal grains in a certain direction, there is no unevenness on the surface of the polycrystalline silicon thin film, and the surface of the thin film is flattened. Between the gate insulating film and the like formed in contact therewith The interface state is improved and the carrier mobility is improved.
[0089]
FIG. 9 shows a case where a magnetic field is applied instead of an electric field. Permanent magnets 202 and 203 or an electromagnet 204 are provided around the vacuum vessel 44 in which the substrate 1 is accommodated, and a magnetic field is applied thereto.
[0090]
Thus, as in the case of the electric field described above, crystal grains are aligned in a certain direction by the action of a magnetic field, carrier mobility is improved, and surface irregularities are also reduced.
[0091]
FIG. 10 shows an example in which a magnetic field is simultaneously applied together with the above-described electric field, but at the same time as the magnetic field generated by the permanent magnets 202 and 203 (which may be an electromagnet) around the vacuum vessel 44 containing the substrate 1, a high-frequency voltage ( Alternatively, an electric field generated by the electrodes 200 and 201 to which the voltage 49 is applied is applied simultaneously.
[0092]
At this time, the electron spin of silicon atoms is directed in a certain direction due to the interaction between the magnetic field and the electric field, and when solidified by cooling from this state, crystallization with a further sufficient directionality is caused by the synergistic action of the magnetic field and the electric field. Become. Accordingly, crystal grains are more easily aligned in a certain direction, carrier mobility is further improved, and surface irregularities are further reduced.
[0093]
The bias method shown in FIGS. 8 to 10 is similarly applied to the bias catalyst AHA treatment, and the hydrogen-based active species are efficiently applied to the fine particle layer 100A and the silicon thin film 7 by the action of the electric field or / and the magnetic field. Acting with sufficient energy, the AHA treatment effect is improved, and the amorphous component can be sufficiently etched to promote crystallization of silicon.
[0094]
FIG. 11 shows the introduction time and timing of the hydrogen-based carrier gas and source gas in the above-described catalytic CVD (same for DC bias catalytic CVD), DC bias and catalytic AHA treatment in the case of forming a polycrystalline silicon thin film. FIG. 12 shows a gas introduction system incorporating a flow meter (MFC), a regulating valve, and the like.
[0095]
First, before film formation, the substrate 1 is loaded into the chamber (film formation chamber) 44 through the gate valve, placed on the susceptor 45, and then the exhaust system is activated to exhaust the chamber 44 to a predetermined pressure. At the same time, the heater built in the susceptor 45 is operated to heat the substrate 1 to a predetermined temperature.
[0096]
Then, first, hydrogen-based carrier gas 300 to 1000 SCCM, for example, 500 SCCM is introduced into the chamber 1 by the gas introduction system. A part of the introduced hydrogen gas becomes hydrogen-based active species such as activated hydrogen ions by the catalytic decomposition reaction by the heating catalyst 46, reaches the substrate surface, and cleans the surface of the substrate 1. Thereafter, the hydrogen carrier gas is set to 150 SCCM.
[0097]
In this way, the gas introduction system is operated in a state where the hydrogen-based carrier gas is supplied into the chamber 44, and the source gas (methane or monosilane 15 SCCM) is introduced into the chamber 44. The introduced source gas generates a deposited species by the thermal catalytic reaction and thermal decomposition reaction of the heating catalyst 46, and if necessary, vapor-phase grows on the substrate surface as a polycrystalline silicon thin film or the like under the action of the bias electric field. .
[0098]
Thereafter, the introduction of the source gas is stopped, the source gas is discharged from the chamber 44, and only the hydrogen-based carrier gas is introduced at a flow rate of 300 to 1000 SCCM, for example, 500 SCCM. Hydrogen-based active species such as active hydrogen ions generated in the above acts on the thin film under the action of the bias electric field described above to etch the amorphous component, and obtain the carbon ultrafine particles of the base from which the amorphous component has been removed, Using this as a seed, polycrystalline silicon whose crystallization is promoted is obtained.
[0099]
The above-mentioned catalytic CVD is again performed on the silicon film subjected to the bias catalyst AHA treatment, and a polycrystalline silicon thin film is grown thereon using the polycrystalline silicon as a seed. Further, the bias catalyst AHA treatment and the catalytic CVD are repeated. By doing so, it is possible to finally form a polycrystalline silicon thin film having a high crystallization ratio and a large grain size with a target film thickness while controlling the film thickness of the polycrystalline silicon thin film.
[0100]
Thus, the radical action of the hydrogen-based active species with sufficient energy accelerated by the bias electric field described above causes thermal energy to move to the film and raise the temperature locally, and the semiconductor thin film is etched with amorphous components. Crystallization is promoted, a polycrystalline film having a large particle size is obtained, and a polycrystalline semiconductor thin film with high carrier mobility and high quality can be obtained. Moreover, a silicon oxide is formed on or in the polycrystalline silicon film. As a result, the silicon oxide is reduced and removed, and silicon oxide on or in the film can be reduced / removed, with high carrier mobility and high quality. A crystalline silicon film or the like can be obtained.
[0101]
In addition, microcrystalline silicon-containing amorphous silicon, amorphous silicon-containing microcrystalline silicon, etc. are polycrystallized using the carbon ultrafine particles of the base as seeds. Polycrystalline silicon is promoted to be highly crystallized and has a large grain size. Turn into a film. Moreover, since the amorphous silicon contained in the film is reduced (etched) by active hydrogen ions or the like, a polycrystalline film having a high crystallization rate is formed.
[0102]
During the bias catalyst AHA treatment, carrier impurities present in the semiconductor thin film are activated at high temperatures, and an optimum carrier impurity concentration can be obtained in each region. Also, high-temperature hydrogen molecules, hydrogen atoms, and activation can be obtained. Cleaning with hydrogen ions (reduction and removal of adsorbed gas and organic residue etc. on the substrate, etc.) is possible, the catalyst body also becomes difficult to oxidatively deteriorate, and further, for example, silicon dangling bonds in the semiconductor film are eliminated by hydrogenation, Improved characteristics.
[0103]
By repeating the annealing by the bias catalyst AHA treatment and the vapor phase growth by catalytic CVD of the semiconductor thin film until a desired film thickness is obtained, the semiconductor thin film is formed on the base film already polycrystallized by the bias catalyst AHA treatment. It becomes easy to grow in a state where it is easily polycrystallized, and an intended high crystallization rate and high quality polycrystalline semiconductor thin film can be obtained with a predetermined film thickness. That is, by the multi-bias catalyst AHA process in which the catalytic CVD and the bias catalyst AHA process are repeated, for example, microcrystalline silicon-containing amorphous silicon, amorphous silicon, microcrystalline silicon-containing polycrystalline silicon, etc. formed by catalytic CVD are subjected to the bias catalyst AHA process. Polycrystalline silicon is converted into highly crystalline polycrystalline silicon, and further, vapor phase growth of the polycrystalline silicon film is repeated by catalytic CVD using the polycrystalline silicon as a seed, and further, the bias catalytic AHA treatment is repeated. A polycrystalline silicon film having a high conversion rate and a large grain size can be formed.
[0104]
In addition, since both the above-described catalytic CVD and bias catalyst AHA treatment can be performed without generating plasma, a plasma is not damaged and a low-stress production film can be obtained. Compared with the plasma CVD method, the apparatus is simple and inexpensive. Can be realized.
[0105]
FIG. 13 shows the Raman spectrum of the polycrystalline silicon thin film obtained by the multi-bias catalyst AHA treatment (repetition of the catalytic CVD and the bias catalyst AHA treatment) according to the present embodiment in accordance with the number of repetitions. is there. According to this result, the gas flow rate at the time of deposition by catalytic CVD is SiH._Four: H₂= 5: 500 SCCM, catalyst temperature = 1800-2000 ° C., substrate temperature = 400 ° C., various conditions for bias catalyst AHA treatment, and the number of repetitions was changed, the number of repetitions was increased and the processing time was lengthened. , H during processing₂When the flow rate is increased, the amorphous (amorphous) and microcrystals decrease and the polycrystalline layer increases in the order of sample # 1 → # 2 → # 3 → # 4 (that is, increase in grain size, increase in grain size). It is clear that it crystallizes). Here, AHA1 is a cleaning process of the substrate surface before film formation, and the original bias catalyst AHA process is AHA2-4.
[0106]
FIG. 14 shows the crystallization rate of each sample in comparison with the presence or absence of microcrystals in polycrystalline silicon. According to this, it can be seen that the crystallization ratio increases in the order of samples # 1 → # 2 → # 3 → # 4, and the base contains fine crystals (Im).
[0107]
These results indicate that the treatment according to the present invention is a very excellent method for forming a polycrystalline semiconductor thin film having a high crystallization ratio and a large grain size.
[0108]
In the present embodiment, in the above-described catalytic CVD, the purity of, for example, a catalyst body of 0.4 mmφ tungsten wire and a support body (not shown) of, for example, 0.8 mmφ molybdenum wire supporting the same becomes a problem. However, the conventional purity: 3N (99.9 wt%) is increased to 4N (99.99 wt%) or more, preferably 5N (99.999 wt%) or more, so that a polycrystalline silicon film by catalytic CVD is used. It has been demonstrated that heavy metal contamination such as iron, nickel, and chromium can be reduced. FIG. 15A shows the concentration of heavy metals such as iron, nickel and chromium in the film with a purity of 3N. By increasing this to 5N, heavy metals such as iron, nickel and chromium are shown in FIG. 15B. It has been found that the concentration can be greatly reduced. As a result, the TFT characteristics can be improved.
[0109]
<Manufacture of top gate type CMOS TFT>
Next, a manufacturing example of a top gate type CMOS TFT using the bias catalyst AHA treatment according to the present embodiment will be shown.
[0110]
First, at least the TFT formation region of the insulating substrate 1 such as quartz glass or crystallized glass shown in FIG. 1A is formed by vapor phase growth method such as plasma CVD, catalytic CVD, high density plasma CVD, high density catalytic CVD. Then, a base protective film (not shown) made of a laminated film of a protective silicon nitride film and a silicon oxide film is formed under the following conditions (the same applies hereinafter).
[0111]
In this case, different glass materials are used depending on the process temperature of TFT formation.
In the case of a low temperature of 200 to 500 ° C .: A glass substrate (500 × 600 × 0.5 to 1.1 μm thickness) such as borosilicate or aluminosilicate glass, or a heat resistant resin substrate may be used.
In the case of a high temperature of 600 to 1000 ° C .: A heat-resistant glass substrate (6 to 12 inches φ, 700 to 800 μm thickness) such as quartz glass or crystallized glass may be used. The protective silicon nitride film is formed to stop Na ions from the glass substrate, but is unnecessary when synthetic quartz glass is used.
[0112]
In the case of using catalytic CVD, an apparatus similar to that shown in FIGS. 5 to 7 can be used. However, in order to prevent oxidative degradation of the catalyst body, a hydrogen-based carrier gas is supplied to bring the catalyst body to a predetermined temperature ( It is necessary to cut the hydrogen-based carrier gas by heating to about 1600 to 1800 ° C. (for example, about 1700 ° C.) and cooling the catalyst body to a temperature at which there is no problem after film formation.
[0113]
As film formation conditions, a hydrogen-based carrier gas (hydrogen, argon + hydrogen, helium + hydrogen, neon + hydrogen, etc.) is constantly flowed into the chamber, and the flow rate, pressure, and susceptor temperature are controlled to the following predetermined values.
Pressure inside the chamber: about 1 to 15 Pa, for example 10 Pa
Susceptor temperature: 200-300 ° C
Hydrogen carrier gas flow rate (in the case of mixed gas, hydrogen is 70 to 80 mol%): 50 to 150 SCCM
[0114]
The silicon nitride film is formed to a thickness of 50 to 200 nm under the following conditions.
Hydrogen (H₂) As carrier gas and monosilane (SiH) as source gas_Four) To ammonia (NH_Three) Are mixed at an appropriate ratio.
Hydrogen (H₂) Flow rate: 50-150 SCCM,
SiH_FourFlow rate: 10-20 SCCM, NH_ThreeFlow rate: 50-60 SCCM
[0115]
The silicon oxide film is formed to a thickness of 50 to 100 nm under the following conditions.
Hydrogen (H₂) As a carrier gas and source gas, monosilane (SiH)_Four) To He dilution O₂Formed by mixing at an appropriate ratio.
H₂Flow rate: 50-150 SCCM, SiH_FourFlow rate: 10-20 SCCM, He rare
Buddha O₂Flow rate: 1-2 SCCM
[0116]
Next, as shown in FIG. 1A, an amorphous carbon or microcrystalline carbon film 100A is formed to a thickness of 50 to 100 nm on the above protective film by the catalytic CVD method or the like according to the present invention under the following conditions. .
Hydrogen (H₂) As carrier gas and source gas_FourThe proper amount ratio is mixed to form.
H₂Flow rate: 50-100 SCCM, CH_FourFlow rate: 10-20 SCCM
[0117]
Next, as shown in FIG. 1 (2), the amorphous component is removed from the amorphous carbon or microcrystalline carbon film 100A by a continuous bias catalyst AHA process to form a carbon ultrafine particle layer 100B having a diamond structure. To do.
[0118]
This bias catalyst AHA treatment is a method in which the source gas is not supplied in the bias catalyst CVD method. Specifically, the hydrogen carrier gas is supplied to a gas pressure of 10 to 50 Pa, and the catalyst body is set to a predetermined temperature. (Approx. 1600-1800 ° C., for example, about 1700 ° C.) to generate a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions), and start glow discharge For example, amorphous carbon or microcrystalline carbon film 100A formed on the substrate is sprayed under application of directional kinetic energy by the action of an electric field or / and a magnetic field below voltage. As a result, high thermal energy possessed by a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) is transferred to these films, and the film temperatures are locally increased. This stabilizes the diamond-structured carbon ultrafine particles (clusters) present on the amorphous carbon or microcrystalline carbon film 100A, and slightly etches the amorphous-structured carbon present in the vicinity thereof, so that the diamond-structured carbon Fine particles are formed and used as the nucleus of polycrystalline silicon growth. At this time, it is necessary that carbon ultrafine particles (clusters) having a diamond structure are interspersed in the TFT formation region, and the electric resistance between them is negligible (not electrically short-circuited).
[0119]
Next, as shown in FIG. 1 (3), for example, a group IV element of the periodic table, eg, tin is added by a catalytic CVD method (or bias catalytic CVD).¹⁸-10²⁰Atoms / cc doped (this may be doped by CVD or ion implantation after film formation) The polycrystalline silicon film 7 is 50-100 nm thick, for example, 50 nm thick, with the diamond structure carbon ultrafine particle layer 100B as a seed. Vapor phase growth. However, this tin doping is not necessarily required (hereinafter the same).
[0120]
At this time, if necessary, an appropriate amount of n-type impurities (phosphorus, arsenic, antimony) or p-type impurities (boron, etc.) is added to monosilane, for example, 10¹⁷-10¹⁸N-type or p-type polycrystalline silicon may be formed by containing atoms / cc. Further, after growing amorphous silicon, microcrystalline silicon, or polycrystalline silicon to a thickness of 10 to 30 nm on the ultrafine carbon particle 100B having a diamond structure, a bias catalyst AHA treatment is performed to form amorphous silicon, microcrystalline silicon, or polycrystalline. The crystalline silicon may be grown to a thickness of 10 to 30 nm and further subjected to a bias catalyst AHA treatment, and an amorphous silicon, microcrystalline silicon, or polycrystalline silicon film may be grown to a thickness of 10 to 30 nm and further subjected to a bias catalyst AHA treatment. By this method, a polycrystalline silicon film having a larger grain size can be formed.
[0121]
In this case, the apparatus shown in FIGS. 5 to 7 is used to vapor-phase, for example, tin-doped polycrystalline silicon by the above-described catalytic CVD under the following conditions, and thereafter, the bias catalyst AHA treatment is performed under the following conditions. Then, the polycrystalline silicon may be further polycrystallized and highly crystallized, and the catalytic CVD and the bias catalyst AHA treatment may be repeated to form the polycrystalline silicon film 7 having a thickness of 50 nm. For example, a film having a thickness of 10 to 30 nm is grown by catalytic CVD, a film having a thickness of 10 to 30 nm is grown by catalytic CVD after the treatment with bias catalyst AHA, and a film having a thickness of 10 to 30 nm is formed by catalytic CVD after the treatment with bias catalyst AHA. Is finally obtained to obtain a polycrystalline silicon film having a target film thickness. At this time, instead of catalytic CVD, bias catalytic CVD may be used.
[0122]
Polycrystalline silicon deposition by catalytic CVD:
Hydrogen (H₂) As a carrier gas and source gas, monosilane (SiH)_Four), Tin hydride (SnH_Four) Are mixed at an appropriate ratio. H₂Flow rate: 150 SCCM, SiH_FourFlow rate: 15 SCCM, SnH_FourFlow rate: 15 SCCM. At this time, an appropriate amount of n-type phosphorus, arsenic, antimony, or the like is mixed into the silane-based gas (such as silane, disilane, or trisilane), or an appropriate amount of p-type boron is mixed. Alternatively, a tin-containing silicon film having a p-type impurity carrier concentration may be formed.
n-type: Phosphine (PH_Three), Arsine (AsH_Three), Stibine (SbH_Three)
For p-type: diborane (B₂H₆)
[0123]
Bias catalyst AHA treatment:
The bias catalyst AHA treatment is a method in which source gas is not supplied in bias catalyst CVD. Specifically, a hydrogen carrier gas is supplied at a gas flow rate of 300 to 1000 SCCM and a gas pressure of 10 to 50 Pa under reduced pressure. Is heated to a predetermined temperature (about 1600 to 1800 ° C., for example, about 1700 ° C.) to generate a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) and the like on the substrate. For example, sprayed onto a polycrystalline silicon film. As a result, thermal energy possessed by a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) moves to these films, raising their film temperature, When microcrystalline silicon is contained, these are polycrystallized, and the polycrystalline silicon is highly crystallized to form a tin-containing polycrystalline silicon film having a large grain size, thereby reducing irregularities and stress existing in the crystal grain boundary, A polycrystalline silicon film with high carrier mobility and high quality can be formed.
[0124]
The bias electric field during the above-described bias catalyst AHA treatment (or bias catalyst CVD) can be formed by applying one of the following voltages.
[0125]
1) DC voltage (eg 500V)
2) Low frequency voltage (eg 500V)_PP/ 26kHz)
3) High frequency voltage (eg 500V)_PP/13.56MHz)
4) A voltage (for example, 500 V) in which a high frequency voltage is overlapped with a low frequency voltage_PP/ 26kHz + 200V_PP/13.56MHz)
5) A voltage obtained by overlapping a low frequency voltage with a DC voltage (eg, 500V + 200V)_PP/ 26kHz)
6) A voltage obtained by overlapping a high-frequency voltage with a DC voltage (for example, 500V + 200V)_PP/13.56MHz)
7) A voltage obtained by overlapping a low-frequency voltage and a high-frequency voltage with a DC voltage (for example, 500V + 100V)_PP/ 26kHz + 100V_PP/13.56MHz)
[0126]
In addition, the above-mentioned hydrogen-based active species, when silicon oxide is present on the film of polycrystalline silicon or the like, when it is present, reacts with this to generate SiO and the like and evaporates, so Alternatively, silicon oxide in the film can be reduced / removed, and a polycrystalline silicon film with high carrier mobility and high quality can be formed. When this bias catalyst AHA treatment (or catalyst AHA treatment) is performed after the formation of the gate channel / source / drain described later, the thermal energy of a large amount of high-temperature hydrogen-based active species is transferred to these films, and the film temperatures are increased. As the crystallization is promoted, carrier impurities (phosphorus, arsenic, boron ions, etc.) are activated by being implanted into the gate channel / source / drain.
[0127]
In the case where the above films are formed in the same chamber, the hydrogen-based carrier gas is always supplied, the catalyst body is heated to a predetermined temperature and is put on standby, and the following processing may be performed.
[0128]
After monosilane is mixed with ammonia at an appropriate ratio to form a silicon nitride film having a predetermined thickness, the previous source gas is sufficiently discharged, and then monosilane and He diluted O are continuously added.₂Are mixed at an appropriate ratio to form a silicon oxide film having a predetermined thickness, and after sufficiently discharging the raw material gas etc., methane is continuously supplied, or monosilane and SnH_FourAre mixed at an appropriate ratio to form an amorphous or microcrystalline carbon thin film having a predetermined film thickness or a tin-containing polycrystalline silicon film having a predetermined film thickness, and after sufficiently discharging the previous raw material gas, the raw material is continuously supplied. After cutting the gas and making the carbon thin film into ultrafine particles with diamond structure by bias catalyst AHA treatment, or crystallizing the polycrystalline silicon film more, if necessary, exhausting the previous raw material gas continuously, continuously Monosilane and He dilution O₂Are mixed at an appropriate ratio to form a silicon oxide film having a predetermined thickness. After film formation, the raw material gas is cut, the catalyst body is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut. At this time, the source gas at the time of forming the insulating film may be decreased or increased in inclination to form an insulating film for inclined bonding.
[0129]
Alternatively, when each chamber is formed independently, a hydrogen-based carrier gas is constantly supplied into each chamber, the catalyst body is heated to a predetermined temperature and is put on standby, and processing may be performed as follows. Transfer to the A chamber and mix monosilane with ammonia in an appropriate ratio to form a silicon nitride film having a predetermined thickness. Then move to chamber B and dilute O with monosilane.₂Are mixed at an appropriate ratio to form a silicon oxide film. Next, move to C chamber and supply methane, or monosilane and SnH_FourAre mixed in an appropriate ratio to form an amorphous or microcrystalline carbon thin film or a tin-containing polycrystalline silicon film, and continuously (or in another chamber) by a bias catalyst AHA treatment with a hydrogen-based carrier gas, The thin film is made into ultrafine particles having a diamond structure, or the polycrystalline silicon film is further crystallized. If necessary then move to chamber B and dilute monosilane with He₂Are mixed at an appropriate ratio to form a silicon oxide film. After film formation, the raw material gas is cut, the catalyst body is cooled to a temperature at which there is no problem, and the hydrogen-based carrier gas is cut. At this time, the hydrogen-based carrier gas and the respective source gases may be constantly supplied into the respective chambers to be in a standby state.
[0130]
Next, a MOSTFT using the polycrystalline silicon film 7 as a source, channel and drain region is manufactured.
[0131]
That is, as shown in FIG. 2 (4), after the polycrystalline silicon film 7 is made into an island by general-purpose photolithography and etching, the threshold value (V) is controlled by controlling the impurity concentration in the channel region for the nMOS TFT._th) Is masked with a photoresist 9, and p-type impurity ions (for example, boron ions) 10 are, for example, 5 × 10 5 by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷An acceptor concentration of atoms / cc is set, and a polycrystalline silicon film 11 is obtained in which the conductivity type of the polycrystalline silicon film 7 is changed to p-type.
[0132]
Next, as shown in FIG. 2 (5), V by the impurity concentration control of the channel region for the pMOS TFT._thThis time, the nMOS TFT portion is masked with a photoresist 12, and n-type impurity ions (for example, phosphorus ions) 13 are, for example, 1 × 10 6 by ion implantation or ion doping.¹²atoms / cm²Doping with a dose of 2 × 10¹⁷A donor concentration of atoms / cc is set, and a polycrystalline silicon film 14 in which the conductivity type of the polycrystalline silicon film 7 is changed to n-type is obtained.
[0133]
Next, as shown in (6) of FIG. 3, after performing the above-described bias catalyst AHA treatment for crystallization promotion and activation of impurities in the film, if necessary, the gate is formed by catalyst CVD or bias catalyst CVD. After forming a silicon oxide film 50 nm thickness 8 as an insulating film, a phosphorus-doped polycrystalline silicon film 15 as a gate electrode material is formed with a PH of 2-20 SCCM, for example._ThreeAnd a thickness of 400 nm, for example, by the same catalytic CVD method as described above under the supply of 20 SCCM monosilane.
[0134]
Next, as shown in (7) of FIG. 3, a photoresist 16 is formed in a predetermined pattern, and using this as a mask, the phosphorus-doped polycrystalline silicon film 15 is patterned into a gate electrode shape, and further, if necessary, a photoresist is formed. After removing 16, as shown in FIG. 3 (8), a silicon oxide film 17 as a gate electrode protective film is formed to a thickness of 20 to 30 nm by, for example, catalytic CVD or the like.
[0135]
Next, as shown in (9) of FIG. 3, the pMOS TFT portion is masked with a photoresist 18, and, for example, phosphorus ions 19 which are n-type impurities are ion-implanted or ion-doped, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The donor concentration is set to atoms / cc, and nMOSTFT n⁺A type source region 20 and a drain region 21 are formed.
[0136]
Next, as shown in (10) of FIG. 4, the nMOS TFT portion is masked with a photoresist 22, and, for example, boron ions 23 that are p-type impurities are ion-implanted or ion-doped, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The acceptor concentration is set to atoms / cc and the pMOSTFT p⁺A type source region 24 and a drain region 25 are formed.
[0137]
Thus, a gate, a source, and a drain are formed, but these can be formed by a method other than the above-described process.
[0138]
That is, after the step (3) in FIG. 1, the polycrystalline silicon film 7 is islanded in the pMOSTFT and nMOSTFT regions, and n-type impurities such as phosphorous ions, for example, phosphorus ions are implanted into the pMOSTFT region by ion implantation or ion doping.¹²atoms / cm²Doping with a dose of 2 × 10¹⁷The donor concentration is set to atoms / cc, and a p-type impurity such as boron ion is 5 × 10 5 in the nMOS TFT region.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷The acceptor concentration of atoms / cc is set, the impurity concentration of each channel region is controlled, and V_thTo optimize.
[0139]
Then, each source / drain region is formed with a photoresist mask by a general-purpose photolithography technique. In the case of an nMOS TFT, an n-type impurity such as arsenic or phosphorus ion is introduced by 1 × 10 5 by ion implantation or ion doping.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The donor concentration is set to atoms / cc, and in the case of a pMOS TFT, a p-type impurity such as boron ion is 1 × 10 1 by ion implantation or ion doping.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The acceptor concentration is set to atoms / cc.
[0140]
Thereafter, if necessary, after performing the bias catalyst AHA treatment for activating the impurities in the film, a silicon oxide film is formed as a gate insulating film. If necessary, a silicon nitride film and a silicon oxide film are continuously formed. A film is formed. That is, if necessary, the hydrogen-based carrier gas and monosilane are diluted with He diluted O by the bias catalyst CVD method continuously after the bias catalyst AHA treatment.₂Are mixed at an appropriate ratio to form a silicon oxide film 8 having a thickness of 20 to 30 nm, and if necessary, NH is added to hydrogen carrier gas and monosilane._ThreeAre mixed at an appropriate ratio to form a silicon nitride film having a thickness of 10 to 20 nm, and further a silicon oxide film is formed to have a thickness of 20 to 30 nm under the above conditions. Thereafter, a gate electrode is formed by the same general-purpose catalytic CVD method and photolithography technique as described above.
[0141]
After forming the gate, source and drain, as shown in FIG. 4 (11), the hydrogen carrier gas 150 SCCM is commonly used on the entire surface by the same catalytic CVD or bias catalytic CVD method as described above. Helium gas dilution O₂The silicon oxide film 26 is formed to a thickness of, for example, 100 to 200 nm under a monosilane supply of 15 to 20 SCCM, and a PH of 1 to 20 SCCM._Three, 1-2 SCCM helium diluted O₂A phosphine silicate glass (PSG) film 27 is formed to a thickness of 300 to 400 nm under a monosilane supply of 15 to 20 SCCM, and NH of 50 to 60 SCCM is formed._ThreeUnder the supply of 15-20 SCCM monosilane, the silicon nitride film 28 is formed to a thickness of, for example, 100-200 nm to form a laminated insulating film. Thereafter, ion activation is performed by, for example, RTA (Rapid Thermal Anneal) treatment at about 1000 ° C. for 20 to 30 seconds to obtain carrier impurity concentrations set in each region.
[0142]
Next, as shown in FIG. 4 (12), a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum containing 1% Si is formed on the entire surface including each contact hole by a sputtering method or the like. It is deposited to a thickness and patterned to form the source or drain electrode 29 (S or D) and the gate extraction electrode or wiring 30 (G) of each of the pMOS TFT and nMOS TFT, thereby forming each top gate type CMOS TFT. . This is followed by hydrogenation and sintering in a forming gas at 400 ° C. for 1 h.
[0143]
Instead of forming the gate electrode described above, a sputtered film of heat-resistant metal such as Mo-Ta alloy is formed on the entire surface with a thickness of 400 to 500 nm, and gate electrodes of nMOS TFT and pMOS TFT are formed by general-purpose photolithography and etching techniques. You can do it.
[0144]
An example in which the above-described amorphous or microcrystalline carbon thin film is formed by sputtering and this is treated with a bias catalyst AHA to produce a top gate type polycrystalline silicon CMOS TFT will be described. First, a graphite target is treated with argon gas 0.133. Sputtering is performed in a vacuum of ˜1.33 Pa to form an amorphous carbon film having a thickness of 10 to 20 nm in at least a TFT formation region of an insulating substrate such as a glass substrate.
[0145]
Next, this amorphous carbon film is treated with a bias catalyst AHA to form ultrafine carbon particles having a diamond structure. Bias catalyst AHA treatment conditions are the same as described above.
[0146]
Next, a silicon target is sputtered on the carbon ultrafine particles having a diamond structure in a vacuum of argon gas of 0.133 to 1.33 Pa, so that at least a TFT formation region of the insulating substrate has a thickness of 30 to 100 nm, for example, 50 nm. An amorphous silicon film is formed.
[0147]
Next, this is treated with a bias catalyst AHA to form a polycrystalline silicon film. The conditions for treating the bias catalyst AHA are the same as those described above. If necessary, for example, an amorphous silicon film having a thickness of 10 to 30 nm is formed on carbon ultrafine particles having a diamond structure, an amorphous silicon film having a thickness of 10 to 30 nm is formed after the bias catalyst AHA treatment, and the bias catalyst AHA treatment is further performed. A so-called multi-bias catalyst AHA treatment may be performed as many times as necessary. This can form a polycrystalline silicon film having a larger grain size.
[0148]
Subsequent processes are the same as those described above. However, the polycrystalline silicon film may be grown by the catalytic CVD method described above.
[0149]
Note that the method using the sputtering film may be similarly applied to a bottom gate type, dual gate type CMOS TFT and the like which will be described later.
[0150]
As described above, according to the present embodiment, the following excellent effects (a) to (o) can be obtained.
[0151]
(A) The above-described bias catalyst AHA treatment is carried out by bringing hydrogen into contact with a high-temperature catalyst body (for example, tungsten, 1500 to 2000 ° C.) under a hydrogen or hydrogen-containing gas pressure of 10 to 50 Pa to produce a high-temperature hydrogen-based active species (hydrogen System molecules, hydrogen atoms, activated hydrogen ions), etc., and direct motion by the action of an electric field or / and magnetic field below the glow discharge starting voltage on an amorphous carbon film or microcrystalline carbon film formed on an insulating substrate When sprayed under the application of energy (substrate temperature 200 to 500 ° C.), the thermal energy of a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) is transferred to the film. Then, the temperature of the film is locally increased, and amorphous carbon is etched by the action of high-temperature hydrogen-based active species. The microcrystalline carbon film is crystallized, and the surface of the amorphous carbon film, the microcrystalline carbon film, or the glass substrate is interspersed with carbon ultrafine particles (clusters) having a diamond structure, which serve as the nucleus of polycrystalline silicon growth. .
[0152]
(B) Further, in the above-described bias catalyst AHA treatment, amorphous silicon, polycrystalline silicon, or fine particles in which high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) are formed on an insulating substrate. When sprayed on crystalline silicon (substrate temperature 200-500 ° C.), the thermal energy of a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) moves to the film, etc. The temperature of the film is increased locally, the amorphous silicon is etched by the action of the high-temperature active hydrogen species, the amorphous silicon and microcrystalline silicon are polycrystallized, and the polycrystalline silicon is highly crystallized. A large grain polycrystalline silicon film is formed, and carrier mobility can be improved.
[0153]
(C) At this time, high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) and the like are independently controlled not only by the catalyst temperature, but also by an electric field or / and a magnetic field. It can be processed well, sufficiently forms ultrafine carbon particles, can be formed into a polycrystalline silicon film having a large particle size, and a polycrystalline silicon thin film with high carrier mobility and high quality can be obtained. For example, 30 keV, 10¹⁵atoms / cm²(SiF_FourIf the bias catalyst AHA treatment is performed after the implantation of silicon ions, the polycrystalline silicon film having a larger particle size can be formed by promoting the growth of crystal nuclei, and the carrier mobility can be further increased.
[0154]
(D) When a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) is sprayed on amorphous silicon, polycrystalline silicon, or microcrystalline silicon formed on the substrate, Or when silicon oxide is present in the film or at the grain boundary, it reacts with it to form and evaporate SiO, reducing the silicon oxide on or in the amorphous silicon, polycrystalline silicon, or microcrystalline silicon film / Can be removed, and carrier mobility can be improved.
[0155]
(E) At the time of this bias catalyst AHA treatment, carrier impurities present in the semiconductor thin film are efficiently activated by a high temperature, and an optimum carrier impurity concentration is obtained in each region.
[0156]
(F) In addition, cleaning with hydrogen-based active species such as activated hydrogen ions (reduction and removal of adsorbed gas and organic substance residue on the substrate and the like) is possible, and the catalyst body is also less likely to be oxidized and deteriorated (such as this The same effect occurs in the same manner because the hydrogen-based carrier gas is used when the above-described silicon thin film is formed by catalytic CVD.
[0157]
(G) Due to the hydrogenation action of hydrogen-based active species such as activated hydrogen ions, for example, silicon dangling bonds in the semiconductor film are eliminated, and the characteristics are improved.
[0158]
(H) When the process of vapor-phase growth of a lower crystalline semiconductor thin film on the polycrystalline thin film treated with the bias catalyst AHA is repeated until the target film thickness is reached, the semiconductor thin film is already subjected to the bias catalyst AHA treatment. It becomes easy to grow on a polycrystallized base film in a state where it is easily polycrystallized, and a desired high crystallization rate and high-quality polycrystalline semiconductor thin film can be obtained with a predetermined film thickness. By the same cleaning action as described above, contamination by oxygen, metal, etc. can be reduced and further performance and quality can be improved. That is, a multi-bias catalyst AHA process in which catalytic CVD and a bias catalyst AHA process are repeated, for example, a microcrystalline silicon-containing amorphous silicon film, an amorphous silicon, and a microcrystalline silicon-containing polycrystalline silicon film are converted into a polycrystalline silicon film by a bias catalyst AHA process. After that, the vapor phase growth of the polycrystalline silicon film is further performed by catalytic CVD or bias catalytic CVD using the polycrystalline silicon as a seed, and further, the bias catalyst AHA treatment is repeated (two-step bias catalyst AHA treatment with one repetition). This is referred to as a multi-bias catalyst AHA treatment twice or more times), so that a polycrystalline silicon film having a high crystallization rate and a large grain size can be formed. In this case, since the processing is performed under the action of the electric field and / or magnetic field (bias), the efficiency is improved, and the number of repeated processes can be reduced and the throughput can be improved as compared with the case where no bias is applied.
[0159]
(I) When the bias catalyst AHA treatment is performed after film formation by catalytic CVD or bias catalyst CVD, the type and processing conditions of the bias (electric field or / and magnetic field), the type and temperature of the catalyst body, the substrate heating temperature, and the vapor phase film formation Depending on conditions, source gas type, added n or p type impurity concentration, type or content of tin or other group IV element, etc., tin or other group IV element having a wide range of n or p type impurity concentration (lead, Germanium-containing polycrystalline silicon film can be easily obtained, and bias catalyst AHA treatment increases the grain size of the polycrystalline silicon film, reduces crystal irregularities existing in the polycrystalline silicon grain boundary, and reduces internal stress. At the same time, the n-type or p-type impurity added to each region is activated, so that the threshold value (V_th) Adjustment is easy and high speed operation with low resistance is possible.
[0160]
(J) When the bias catalyst AHA treatment is performed after the film formation by plasma CVD, hydrogen contained in the amorphous silicon film by the plasma CVD is reduced / removed by the bias catalyst AHA treatment, and a large particle size is obtained. Since the polycrystalline silicon film is formed, it is possible to form a polycrystalline silicon film having a large carrier mobility. Furthermore, a wide range of n or p-type impurity concentrations can be obtained depending on the substrate heating temperature, vapor phase deposition conditions, source gas type, bias (electric field or / and magnetic field) type and processing conditions, and n or p-type impurity concentration to be added. Since a polycrystalline silicon film can be easily obtained, V can be obtained with high carrier mobility._thAdjustment is easy and high-speed operation with low resistance is possible.
[0161]
(K) When the bias catalyst AHA treatment is performed after film formation by sputtering, the specific resistance of the silicon target (concentration of added n or p-type impurities), sputtering film formation conditions, substrate heating temperature, bias (electric field or / and magnetic field) A polycrystalline silicon film with a wide range of n-type or p-type impurity concentration can be easily obtained depending on the type and processing conditions, etc._thAdjustment is easy and high-speed operation with low resistance is possible.
[0162]
(L) Since a large grain polycrystalline silicon thin film having high electron / hole mobility can be obtained not only in a top gate type but also in a bottom gate type and dual gate type MOS TFT, this high performance polycrystalline silicon semiconductor is obtained. High-speed, high current density semiconductor devices, electro-optical devices, and high-efficiency solar cells can be manufactured.
[0163]
(M) Since the bias catalyst AHA treatment and the catalytic CVD can be performed without generating plasma, there is no damage caused by plasma, and a simple and inexpensive apparatus can be realized as compared with the plasma treatment.
[0164]
(N) Since the energy of the active species is large even when the substrate temperature is lowered, carbon ultrafine particles having a target diamond structure can be reliably obtained stably, and a polycrystalline silicon film can be formed. Therefore, the substrate temperature can be lowered to 300 to 400 ° C. in particular, so that a large and inexpensive low strain point insulating substrate (glass substrate, heat-resistant resin substrate, etc.) can be used. .
[0165]
(O) A catalytic CVD apparatus can also be used for activation of n-type or p-type impurities added to the gate channel / source / drain region depending on conditions, so that the capital investment can be reduced and the cost can be reduced by improving the productivity. Become.
[0166]
Second embodiment
<LCD production example 1>
In the present embodiment, the present invention is applied to an LCD (liquid crystal display device) using a polycrystalline silicon MOS TFT by a high temperature process, and a manufacturing example thereof will be shown below (this manufacturing example is an organic EL described later). It can be similarly applied to display devices such as FED and FED).
[0167]
First, as shown in (1) of FIG. 16, in the pixel portion and the peripheral circuit portion, a heat-resistant insulating substrate 61 such as quartz glass or crystallized glass (strain point is about 800 to 1100 ° C., thickness is 50 microns to several mm). ) After forming a protective film (not shown) on one main surface by the above-described catalytic CVD method or the like, an amorphous or microcrystalline carbon thin film 100A is formed thereon.
[0168]
Next, as shown in (2) of FIG. 16, the carbon thin film 100A is changed to a carbon ultrafine particle layer 100B having a diamond structure by the above-described bias catalyst AHA treatment.
[0169]
Next, as shown in (3) of FIG. 16, a polycrystalline silicon film 67 is formed to a thickness of, for example, 50 nm using the carbon ultrafine particle layer 100B as a seed by the above-described catalytic CVD method or the like. This polycrystalline silicon film may be formed by the above-described multi-bias catalyst AHA treatment.
[0170]
Next, as shown in FIG. 17 (4), the polycrystalline silicon film 67 is patterned (islanded) using a photoresist mask, and active elements such as transistors and diodes, and passive elements such as resistors, capacitors, and inductances. The active layer is formed.
[0171]
Next, V is controlled by controlling the impurity concentration in the channel region of the transistor active layer 67._thAfter the ion implantation of a predetermined impurity such as boron or phosphorus as described above for the optimization of the above, as shown in FIG. 17 (5), for example, the polycrystalline structure is formed by the catalytic CVD method similar to the above. A silicon oxide film 68 for a gate insulating film having a thickness of, for example, 50 nm is formed on the surface of the silicon film 67. When the silicon oxide film 68 for the gate insulating film is formed by a catalytic CVD method or the like, the substrate temperature and the catalyst body temperature are the same as those described above, but the oxygen gas flow rate is 1 to 2 SCCM, the monosilane gas flow rate is 15 to 20 SCCM, The hydrogen-based carrier gas may be 150 SCCM. Note that the silicon oxide film 68 for the gate insulating film may be formed by, for example, high-temperature thermal oxidation at about 1000 ° C. for 30 minutes before or after controlling the impurity concentration in the channel region.
[0172]
Next, as shown in FIG. 17 (6), as a material for the gate electrode and the gate line, for example, a Mo—Ta alloy is deposited by sputtering to a thickness of, for example, 400 nm, or a phosphorus-doped polycrystalline silicon film is formed of, for example, hydrogen. System carrier gas 150 SCCM, PH of 2-20 SCCM_ThreeAnd a thickness of, for example, 400 nm by a catalytic CVD method similar to the above under the supply of 20 SCCM monosilane gas. Then, the gate electrode material layer is patterned into the shape of the gate electrode 75 and the gate line by general-purpose photolithography and etching techniques. In the case of a phosphorus-doped polycrystalline silicon film, a protective silicon oxide film having a thickness of 10 to 20 nm may be formed on the surface by catalytic CVD or the like.
[0173]
Next, as shown in FIG. 18 (7), the pMOS TFT portion is masked with a photoresist 78, and, for example, arsenic (or phosphorus) ions 79, which are n-type impurities, are ionized by ion implantation or ion doping, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The donor concentration is set to atoms / cc, and nMOSTFT n⁺A type source region 80 and a drain region 81 are formed.
[0174]
Next, as shown in FIG. 18 (8), the nMOS TFT portion is masked with a photoresist 82, and, for example, boron ions 83 which are p-type impurities are ionized by ion implantation or ion doping, for example, 1 × 10.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰The acceptor concentration is set to atoms / cc and the pMOSTFT p⁺A type source region 84 and a drain region 85 are formed.
[0175]
Next, as shown in FIG. 18 (9), a hydrogen-based carrier gas of 150 SCCM is commonly used on the entire surface by the same catalytic CVD method as described above.₂Under a monosilane supply of 15 to 20 SCCM, the silicon oxide film has a thickness of, for example, 100 to 200 nm, and further has a PH of 1 to 20 SCCM._Three1-2 SCCM He dilution O₂A phosphine silicate glass (PSG) film having a thickness of 300 to 400 nm is formed under a monosilane supply of 15 to 20 SCCM, and NH of 50 to 60 SCCM is formed._Three15-20 SCCM SiH_FourUnder the supply, a silicon nitride film is formed to a thickness of 100 to 200 nm, for example. An interlayer insulating film 86 is formed by stacking these insulating films. In addition, you may form such an interlayer insulation film by the normal method different from the above. After this, for example, N at 900 ° C. for 5 minutes₂Annealing at 1000 ° C or N for 20-30 seconds₂The ions are activated by the RTA treatment in the region, and the carrier impurity concentration set in each region is obtained.
[0176]
Next, as shown in (10) of FIG. 19, a contact window is opened at a predetermined position of the insulating film 86, and an electrode material such as aluminum is deposited on the entire surface including the contact holes to a thickness of 1 μm by sputtering or the like. Then, this is patterned to form source electrodes 87 and data lines of nMOS TFTs in the pixel portion, source electrodes 88 and 90 and drain electrodes 89 and 91 and wirings of pMOS TFTs and nMOS TFTs in the peripheral circuit portion, respectively. After this, for example, hydrogenation and sintering are performed in forming gas at 400 ° C. for 1 h.
[0177]
Next, after an interlayer insulating film 92 such as a silicon oxide film is formed on the surface by CVD, contact holes are formed in the interlayer insulating films 92 and 86 in the nMOS TFT drain region of the pixel portion as shown in FIG. Open, for example, ITO (Indium tin oxide: transparent electrode material doped with tin in indium oxide) is deposited on the entire surface by vacuum evaporation or the like, and patterned to form a transparent pixel electrode 93 connected to the drain region 81 of the nMOS TFT To do. Thereafter, annealing is performed in a forming gas at 250 ° C. for 1 hour, for example, to improve ohmic contact with ITO and to improve transparency of ITO.
[0178]
Thus, an active matrix substrate (hereinafter referred to as a TFT substrate) can be manufactured, and a transmissive LCD can be manufactured. As shown in FIG. 19 (12), this transmissive LCD has a structure in which an alignment film 94, a liquid crystal 95, an alignment film 96, a transparent electrode 97, and a counter substrate 98 are stacked on a pixel electrode 93.
[0179]
Note that the above-described steps can be similarly applied to the production of a reflective LCD. FIG. 24A shows an example of the reflective LCD. In FIG. 24A, reference numeral 101 in the figure denotes a reflective film deposited on the roughened insulating film 92. It is connected.
[0180]
When the liquid crystal cell of this LCD is manufactured by surface assembly (suitable for medium / large liquid crystal panels of 2 inches or more), first a TFT substrate 61 and a solid ITO (Indium Tin Oxide) electrode 97 are provided. Polyimide alignment films 94 and 96 are formed on the element forming surface of the counter substrate 98. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating or the like, and cured and cured at 180 ° C./2 h.
[0181]
Next, the TFT substrate 61 and the counter substrate 98 are rubbed or photo-aligned. The rubbing buff material includes cotton and rayon, but cotton is more stable in terms of buffing (dust) and retardation. Photo-alignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. For alignment, in addition to rubbing, a polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound is, for example, a polymethyl methacrylate polymer having azobenzene). Etc.).
[0182]
Next, after cleaning, a common agent is applied to the TFT substrate 61 side, and a sealing agent is applied to the counter substrate 98 side. Wash with water or IPA (isopropyl alcohol) to remove rubbing buff. The common agent may be an acrylic containing a conductive filler, or an epoxy acrylate, or an epoxy adhesive, and the sealant may be an acrylic, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet radiation curing, ultraviolet radiation curing + heat curing can be used, but the ultraviolet radiation curing + heat curing type is preferable in terms of overlay accuracy and workability.
[0183]
Next, spacers for obtaining a predetermined gap are scattered on the counter substrate 98 side and overlapped with the TFT substrate 61 at a predetermined position. After aligning the alignment mark on the counter substrate 98 side and the alignment mark on the TFT substrate 61 side with high precision, the sealant is temporarily cured by irradiating with ultraviolet rays, and then heated and cured all at once.
[0184]
Next, a scribe break is made to produce a single liquid crystal panel in which the TFT substrate 61 and the counter substrate 98 are overlapped.
[0185]
Next, liquid crystal 95 is injected into the gap between the two substrates 61-98, and the injection port is sealed with an ultraviolet adhesive and then IPA cleaned. Any type of liquid crystal may be used, but for example, a fast response TN (twisted nematic) mode using nematic liquid crystal is common.
[0186]
Next, the liquid crystal 95 is aligned by heating and quenching.
[0187]
Next, a flexible wiring is connected to the panel electrode extraction portion of the TFT substrate 61 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is further bonded to the counter substrate 98.
[0188]
In the case of a single surface assembly of a liquid crystal panel (suitable for a small liquid crystal panel of 2 inches or less), polyimide alignment films 94 and 96 are formed on the element formation surfaces of the TFT substrate 61 and the counter substrate 98 as described above. Then, both substrates are rubbed or non-contact linearly polarized ultraviolet light is aligned.
[0189]
Next, the TFT substrate 61 and the counter substrate 98 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 61, a sealant containing a spacer is applied to the counter substrate 98, and the two substrates are overlapped. The subsequent processes follow the above.
[0190]
In the LCD described above, the counter substrate 98 is a CF (color filter) substrate, and a color filter layer (not shown) is provided under the ITO electrode 97. Incident light from the counter substrate 98 side may be efficiently reflected by, for example, the reflective film 93 and emitted from the counter substrate 98 side.
[0191]
On the other hand, when the TFT substrate 61 is a TFT substrate having an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 61, the counter substrate 98 has a solid ITO electrode (or an ITO electrode with a black mask). It is solid).
[0192]
In the case of a transmissive LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.
[0193]
That is, as shown in FIG. 19 (13), the drain portion of the phosphine silicate glass / silicon oxide insulating film 86 is also opened to form an aluminum buried layer for the drain electrode. Each color filter layer 99 is patterned by forming a photoresist 99 in which each color is pigment-dispersed in each segment with a predetermined thickness (1 to 1.5 μm) and then leaving only a predetermined position (each pixel portion) by general-purpose photolithography technology. (R), 99 (G), and 99 (B) are formed (on-chip color filter structure). At this time, the window of the drain part is also opened. Note that an opaque ceramic substrate, low-transmittance glass, and a heat-resistant resin substrate cannot be used.
[0194]
Next, a light shielding layer 100 'serving as a black mask layer is formed by metal patterning over the color filter layer in a contact hole communicating with the drain of the display TFT. For example, molybdenum is formed to a thickness of 200 to 250 nm by sputtering, and is patterned into a predetermined shape that covers the display MOS TFT and shields it from light (on-chip black structure).
[0195]
Next, a planarizing film 92 of transparent resin is formed, and further, an ITO transparent electrode 93 is formed in a through hole provided in the planarizing film so as to be connected to the light shielding layer 100 ′.
[0196]
As described above, the color filter 99 and the black mask 100 ′ are formed on the display array portion, thereby improving the aperture ratio of the liquid crystal display panel and realizing low power consumption of the display module including the backlight. .
[0197]
FIG. 20 schematically shows the entire active matrix liquid crystal display device (LCD) in which the above-mentioned top gate type MOSTFT is incorporated to form a drive circuit integrated type. This active matrix LCD has a flat panel structure in which a main substrate 61 (which constitutes an active matrix substrate) and a counter substrate 98 are bonded together via a spacer (not shown). Liquid crystal (not shown here) is enclosed in the. On the surface of the main substrate 61, there are provided a display unit composed of pixel electrodes 93 arranged in a matrix, switching elements for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit. .
[0198]
The switching element of the display unit is composed of the above-mentioned nMOS, pMOS, or CMOS, and a top gate type MOSTFT having an LDD structure. Also, in the peripheral drive circuit section, the above-mentioned top gate MOSTFT CMOS, nMOS, pMOSTFT, or a mixture thereof is formed as a circuit element. One peripheral driving circuit unit is a horizontal driving circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral driving circuit unit sets the gate of the TFT of each pixel for each scanning line. The vertical driving circuit is normally provided on both sides of the display portion. These drive circuits can be configured in either a dot sequential analog system or a line sequential digital system.
[0199]
As shown in FIG. 21, the MOSTFT is arranged at the intersection of the orthogonal gate bus line and the data bus line, and the liquid crystal capacitance (C_LCThe image information is written in () and the electric charge is held until the next information comes. In this case, since it is not sufficient to hold only the channel resistance of the TFT, a storage capacitor (auxiliary capacitor) (C_S) May be added to compensate for the decrease in the liquid crystal voltage due to the leakage current. Such LCD MOSTFTs have different performance requirements depending on the characteristics of TFTs used in the pixel portion (display portion) and TFTs used in the peripheral drive circuit. In particular, TFTs in the pixel portion control off current and ensure on current. Is an important issue. For this reason, the display portion is provided with a TFT having an LDD structure as will be described later, thereby reducing the effective electric field applied to the channel region as a structure in which an electric field is unlikely to be applied between the gate and the drain, thereby reducing the off-current. The change of can be made small. However, the process is complicated, the element size is increased, and problems such as a decrease in on-current occur. Therefore, an optimum design for each purpose of use is required.
[0200]
Available liquid crystals include TN liquid crystal (nematic liquid crystal used for active matrix drive TN mode), STN (super twisted nematic), GH (guest / host), PC (phase change), FLC. Liquid crystals for various modes such as (ferroelectric liquid crystal), AFLC (antiferroelectric liquid crystal), and PDLC (polymer dispersion type liquid crystal) may be employed.
[0201]
<LCD production example 2>
Next, an example of manufacturing an LCD (Liquid Crystal Display) using a low-temperature process polycrystalline silicon MOSTFT according to the present embodiment will be shown (this example is applied to an organic EL or FED display device to be described later). Is possible).
[0202]
In this manufacturing example, aluminosilicate glass, borosilicate glass, or the like is used as the substrate 61 in the manufacturing example 1 described above, and the steps (1), (2), and (3) in FIG. That is, a tin-containing (or non-containing) polycrystalline silicon film 67 is formed on the substrate 61 by catalytic CVD and bias catalyst AHA treatment to form an island, and an nMOS TFT portion in the display region and an nMOS TFT portion in the peripheral drive circuit region are formed. And a pMOS TFT portion. In this case, regions such as a diode, a capacitor, an inductance, and a resistance are formed at the same time.
[0203]
Next, as shown in (1) of FIG. 22 (however, the ultrafine particle layer 100B having a diamond structure is not shown: the same applies hereinafter), the carrier impurity concentration in each MOSTFT gate channel region is controlled to control V_thFor example, the nMOS TFT portion in the display region and the nMOS TFT portion in the peripheral drive circuit region are covered with a photoresist 82, and the pMOS TFT portion in the peripheral drive circuit region is made of, for example, phosphorus or arsenic by ion implantation or ion doping. 1 × 10 of n-type impurity 79¹²atoms / cm²Doping with a dose of 2 × 10¹⁷The donor concentration is set to atoms / cc, and as shown in FIG. 22 (2), the pMOS TFT portion in the peripheral drive circuit region is covered with a photoresist 82, and the nMOS TFT portion in the display region and the nMOS TFT portion in the peripheral drive circuit region. Next, 5 × 10 5 of p-type impurity 83 such as boron is formed by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷An acceptor concentration of atoms / cc is set.
[0204]
Next, as shown in (3) of FIG.^-In order to form an LDD (Lightly Doped Drain) portion of the mold, the gate portion of the nMOS TFT in the display region and the pMOS TFT and nMOS TFT in the peripheral drive region are all covered with a photoresist 82 by a general-purpose photolithography technique, and the nMOS TFT in the exposed display region An n-type impurity 79 such as phosphorus, for example, is implanted into the source / drain regions of 1 × 10 10 by ion implantation or ion doping.¹³atoms / cm²Doping with a dose of 2 × 10¹⁸Set the donor concentration to atoms / cc and n^-The LDD part of the mold is formed.
[0205]
Next, as shown in FIG. 23 (4), the entire nMOS TFT portion in the display region and the nMOS TFT portion in the peripheral drive circuit region are covered with the photoresist 82, and the gate portion of the pMOS TFT portion in the peripheral drive circuit region is covered with the photoresist 82. A p-type impurity 83 such as boron, for example, by ion implantation or ion doping is applied to the exposed source and drain regions covered with¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰Set acceptor concentration at atoms / cc and set p⁺A mold source portion 84 and drain portion 85 are formed.
[0206]
Next, as shown in FIG. 23 (5), the pMOS TFT portion in the peripheral drive circuit region is covered with a photoresist 82, and the gate and LDD portion of the display region and the gate portion of the nMOS TFT portion in the peripheral drive circuit region are exposed to photo. An n-type impurity 79 such as phosphorus or arsenic, for example, by ion implantation or ion doping is applied to the source and drain regions of the nMOS TFT in the exposed display region and the peripheral drive region by covering the resist 82 with 1 × 10 × 10.¹⁵atoms / cm²Ion doping with a dose of 2 × 10²⁰set to donors concentration of atoms / cc, n⁺A mold source 80 and drain 81 are formed.
[0207]
Next, as shown in FIG. 23 (6), the gate insulating film 68 is formed as a silicon oxide film 40 to 50 nm thick, a silicon nitride film 10 to 20 nm thick, oxidized by plasma CVD, TEOS plasma CVD, catalytic CVD, or the like. A laminated film having a silicon film thickness of 40 to 50 nm is formed. Then, RTA treatment with a halogen lamp or the like is performed, for example, at about 1000 ° C. for 10 to 30 seconds, and the added n or p-type impurities are activated to obtain each set carrier impurity concentration.
[0208]
Thereafter, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching. Thereafter, an insulating film 86 made of a laminated film having a silicon oxide film thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film of 200 to 300 nm, and a silicon nitride film of 100 to 200 nm is formed by plasma CVD, catalytic CVD, or the like. Form.
[0209]
Next, the windows of the source / drain portions of all TFT portions of the peripheral drive circuit and the source portion of the display nMOS TFT portion are opened by general-purpose photolithography and etching techniques. Silicon nitride film is CF_FourThe plasma etching, the silicon oxide film, and the phosphorous silicate glass film are etched with a hydrofluoric acid-based etchant.
[0210]
Next, as shown in (7) of FIG. 23, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and source and drain electrodes of all TFTs of the peripheral drive circuit are formed by general-purpose photolithography and etching techniques. At the same time as forming 88, 89, 90, 91, the source electrode 87 and the data line of the display nMOS TFT are formed.
[0211]
Next, although not shown in the figure, an interlayer insulating film (silicon oxide film 100 to 200 nm thick, phosphine silicate glass (PSG film) 200 to 300 nm thick, silicon nitride film 100 to 300 nm thick is formed by plasma CVD, catalytic CVD, or the like. The above-mentioned 92) is formed on the entire surface, and hydrogenated and sintered in a forming gas at about 400 ° C. for 1 hour. Thereafter, a window for drain contact of the display nMOS TFT is opened.
[0212]
Here, when the LCD is a transmission type, the silicon oxide film, phosphine silicate glass film, and silicon nitride film in the pixel opening are removed, and when the LCD is a reflection type, the silicon oxide film such as the pixel opening and the phosphine are removed. It is not necessary to remove the silicate glass film and the silicon nitride film (the same applies to the LCD described above or later).
[0213]
In the case of the transmission type, an acrylic transparent resin flattening film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, as in (10) of FIG. After forming the transparent resin window on the drain side, an ITO sputtered film having a thickness of 130 to 150 nm is formed on the entire surface, and an ITO transparent electrode in contact with the drain portion of the display nMOS TFT is formed by general-purpose photolithography and etching techniques. Further, the contact resistance is reduced and the ITO transparency is improved by heat treatment (200 to 250 ° C., 1 hour in forming gas).
[0214]
In the case of the reflective type, a photosensitive resin film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating, etc., and a concavo-convex pattern is formed at least on the pixel portion by general-purpose photolithography and etching technology, and reflow is performed to reflect the concavo-convex Form the bottom. At the same time, a photosensitive resin window opening in the drain portion of the display nMOS TFT is formed. Thereafter, an aluminum sputtered film containing 1% Si having a thickness of 300 to 400 nm is formed on the entire surface, the aluminum film other than the pixel portion is removed by general-purpose photolithography and etching techniques, and the unevenness connected to the drain electrode of the display nMOS TFT. A shaped aluminum reflecting portion is formed. Thereafter, sintering is performed in a forming gas at 300 ° C. for 1 hour.
[0215]
In the above, if the bias catalyst AHA treatment is performed after forming the source and drain of the nMOS TFT, the film temperature of the polycrystalline silicon film is locally increased, and crystallization is further promoted, and high mobility and high quality are achieved. A polycrystalline silicon film is formed. At the same time, the thermal energy of a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) moves to the film and locally increases the film temperature, so that the gate channel / source / Phosphorus, arsenic, boron ions, etc. implanted in the drain region are activated.
[0216]
When the amorphous silicon-containing microcrystalline silicon film is formed by the plasma CVD method, 10 to 20% hydrogen is contained in the film, but it can be reduced / removed by the bias catalyst AHA treatment, so that polycrystalline silicon A polycrystalline silicon film with high mobility and high quality is formed. In addition, when silicon oxide is present on or in the film of amorphous silicon-containing microcrystalline silicon or the like, a reduction reaction with this generates SiO and evaporates, so that silicon oxide on or in the film is oxidized. Objects can be reduced / removed, and a high mobility and high quality polycrystalline silicon film can be formed.
[0217]
<Bottom gate type or dual gate type MOSTFT>
An example of manufacturing a transmissive LCD including a bottom gate type and a dual gate type MOS TFT instead of the above-described top gate type in an LCD incorporating a MOS TFT will be described (however, the same applies to a reflective LCD).
[0218]
As shown in FIG. 24B, bottom-gate nMOS TFTs are provided in the display portion and the peripheral portion, or as shown in FIG. 24C, dual-gate nMOS TFTs are provided in the display portion and the peripheral portion. Each is provided. Among these bottom gate type and dual gate type MOSTFTs, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and either of the upper and lower gate portions is selectively used. Depending on the case, it can be operated as a top gate type or a bottom gate type.
[0219]
In the bottom gate type MOSTFT of FIG. 24B, reference numeral 102 in the figure denotes a gate electrode such as a Mo—Ta alloy, 103 denotes a silicon nitride film, and 104 denotes a silicon oxide film, which forms a gate insulating film. On the gate insulating film, a channel region or the like using a polycrystalline silicon film 67 similar to the top gate type MOS TFT is formed. In the dual gate MOSTFT of FIG. 24C, the lower gate portion is the same as the bottom gate type MOSTFT, but the upper gate portion includes a gate insulating film 106 made of a silicon oxide film and a silicon nitride film, and if necessary. Further, it is formed of a laminated film of a silicon oxide film, and an upper gate electrode 75 is provided thereon.
[0220]
<Manufacture of bottom gate type MOSTFT>
First, a sputtered film of Mo-Ta alloy is formed on the entire surface of the glass substrate 61 to a thickness of 300 to 400 nm, and this is taper-etched by 20 to 45 degrees by general-purpose photolithography and etching techniques, at least in the TFT formation region. At the same time as the bottom gate electrode 102 is formed, a gate line is formed. Glass materials are used according to the top gate type described above.
[0221]
Next, a silicon nitride film 103 and a silicon oxide film 104 for a gate insulating film and a protective film, and a tin-containing amorphous silicon-containing microcrystal are formed by vapor phase growth methods such as plasma CVD, TEOS plasma CVD, catalytic CVD, and low-pressure CVD. A silicon film is formed. As described above, this film is further subjected to the bias catalyst AHA treatment to form a polycrystalline silicon film 67. These vapor deposition conditions conform to the top gate type described above. The bottom gate insulating film and the silicon nitride film for the protective film are provided in anticipation of a Na ion stopper action from the glass substrate, but are not necessary in the case of synthetic quartz glass.
[0222]
The subsequent processes are the same as those described above, but since the gate electrode has already been formed in the above steps, the steps of forming the polysilicon film for the gate electrode, forming the gate electrode, and oxidizing the gate polysilicon are unnecessary. is there.
[0223]
Then, as described above, the pMOSTFT and nMOSTFT regions are islanded (however, only one region is shown: the same applies hereinafter), and the carrier impurity concentration in each channel region is controlled to V_thIn order to optimize the n-type or p-type impurity by ion implantation or ion doping, an n-type or p-type impurity is formed by ion implantation or ion doping to form the source and drain regions of each MOS TFT. Alternatively, an appropriate amount of p-type impurity is mixed. Thereafter, RTA treatment (about 1000 ° C., 10 to 30 seconds) is performed for impurity activation.
[0224]
The subsequent processes are the same as those described above.
[0225]
<Manufacture of dual gate type MOS TFT>
Similarly to the bottom gate type, a bottom gate electrode 102, gate insulating films 103 and 104, and a polycrystalline silicon film 67 are formed. However, the silicon nitride film 103 for the bottom gate insulating film and the protective film is provided in anticipation of the Na ion stopper action from the glass substrate, but is unnecessary in the case of synthetic quartz glass.
[0226]
Then, as described above, the pMOSTFT and nMOSTFT regions are islanded, and the carrier impurity concentration in each channel region is controlled to V_thIn order to optimize the n-type or p-type impurity by ion implantation or ion doping, an n-type or p-type impurity is formed by ion implantation or ion doping to form the source and drain regions of each MOS TFT. Alternatively, an appropriate amount of p-type impurity is mixed.
[0227]
Next, a stacked film of a silicon oxide film and a silicon nitride film for the top gate insulating film 106 and, if necessary, a silicon oxide film are formed. Vapor phase growth conditions conform to the top gate type described above. Thereafter, RTA treatment (about 1000 ° C., 10 to 30 seconds) is performed for impurity activation.
[0228]
Thereafter, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and top gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching techniques. Thereafter, an insulating film 86 having a silicon oxide film thickness of 100 to 200 nm and a phosphine silicate glass (PSG) film thickness of 200 to 300 nm is formed by plasma CVD, catalytic CVD, or the like. Next, the windows of the source and drain electrode portions of all the MOSTFTs in the peripheral drive circuit and the source electrode portion of the display nMOSTFT are opened by general-purpose photolithography and etching techniques.
[0229]
Next, an aluminum sputtered film containing 1% Si having a thickness of 400 to 500 nm is formed on the entire surface, and source and drain aluminum electrodes 87, 88 and 89, source lines, wirings, and the like are formed by general-purpose photolithography and etching techniques. Next, a silicon oxide film 100 to 200 nm thick, a phosphine silicate glass (PSG film) 200 to 300 nm thick, and a silicon nitride film 100 to 300 nm thick are formed as an interlayer insulating film 92 on the entire surface by plasma CVD, catalytic CVD, or the like. Hydrogenate and sinter in forming gas at about 400 ° C. for 1 hour. Thereafter, a drain contact window for the display nMOS TFT is opened to form a pixel electrode 93.
[0230]
As described above, according to the present embodiment, as in the first embodiment described above, by the catalytic CVD or the bias catalytic CVD and the bias catalytic AHA treatment, the MOS TFTs of the LCD display section and the peripheral driving circuit section are processed. V with high carrier mobility, which becomes the gate channel, source and drain regions_thA polycrystalline silicon film that can be easily adjusted and can operate at high speed with low resistance can be formed. A liquid crystal display device using a top gate, bottom gate or dual gate type MOS TFT with this polycrystalline silicon film has a display portion having an LDD structure with high switching characteristics and low leakage current, and a CMOS or nMOS with high driving capability. Alternatively, a configuration in which pMOS peripheral drive circuits are integrated is possible, and a liquid crystal panel with high image quality, high definition, narrow frame, high efficiency, and low cost can be realized.
[0231]
And since it can form at low temperature (300-400 degreeC), it can employ | adopt the low strain point glass which is cheap and easy to enlarge, and a cost reduction is attained. In addition, by forming a color filter or a black mask on the array portion, the aperture ratio, luminance, etc. of the liquid crystal display panel are improved, a color filter substrate is not required, and cost reduction is realized by improving productivity.
[0232]
Third embodiment
In the present embodiment, the present invention is applied to an organic or inorganic electroluminescence (EL) display device, for example, an organic EL display device. The structural examples and production examples are shown below.
[0233]
<Structural example I of organic EL element>
As shown in FIGS. 25 (A) and 25 (B), according to this structural example I, a high crystallization rate and a large particle size formed on the substrate 111 such as glass by the method described above based on the present invention. The polycrystalline silicon film forms the gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. The drain of MOSTFT 1 and the gate of MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of MOSTFT 2 via an insulating film 136, and the drain electrode 131 of MOSTFT 2 is It extends to the cathode 138 of the organic EL element.
[0234]
Each MOSTFT is covered with an insulating film 130, and on this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133 or a red organic light emitting layer not shown) of an organic EL element is formed so as to cover the cathode. An anode (first layer) 134 is formed so as to cover the organic light emitting layer, and a common anode (second layer) 135 is further formed on the entire surface. In addition, the manufacturing method of the peripheral drive circuit, the video signal processing circuit, the memory circuit, and the like made of CMOS TFT is in accordance with the above-described liquid crystal display device (the same applies hereinafter).
[0235]
In the organic EL display unit having this structure, the organic EL light emitting layer is connected to the drain of the current driving MOS TFT 2, the cathode (Li—Al, Mg—Ag, etc.) 138 is deposited on the surface of the substrate 111 such as glass, and the anode (ITO film etc.) 134, 135 are provided on the upper part thereof, and therefore, the top emission 136 ′ is obtained. Further, when the cathode covers the MOSTFT, the light emission area becomes large. At this time, the cathode serves as a light shielding film, and light emission or the like does not enter the MOSTFT so that no leak current is generated and the TFT characteristics are not deteriorated.
[0236]
Further, if a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion as shown in FIG. 25C, light leakage (crosstalk, etc.) can be prevented and contrast can be improved.
[0237]
In addition, a good full-color EL display device can be obtained by any of a method using a three-color light emitting layer of green, blue, and red for a pixel display portion, a method using a color conversion layer, and a method using a color filter for a white light emitting layer. In addition, it is possible to produce a long-life, high-accuracy, high-quality, high-reliability full-color organic EL unit in the spin coating method of polymer compounds, which are light emitting materials for each color, or the vacuum heating deposition method of metal complexes. Since it can be created well, the cost can be reduced (hereinafter the same).
[0238]
This type of conventional organic EL uses amorphous silicon TFTs, so V_thEven if fluctuates, the current value is likely to change, and the image quality is likely to fluctuate. Moreover, since the mobility is small, there is a limit to the current that can be driven with a high-speed response, it is difficult to form a p-channel, and even a small-scale CMOS circuit configuration is difficult. Therefore, it is desirable to use a polycrystalline silicon TFT that is relatively easy to increase in area, has high reliability, has high mobility, and can be configured as a CMOS circuit. Conventional polycrystalline silicon films are: 1) amorphous silicon A film is formed by plasma CVD at 300 to 400 ° C., and excimer laser annealing is performed to form a polycrystalline silicon film. 2) An amorphous silicon film is formed by LPCVD at 430 to 500 ° C., and is solid phase grown in nitrogen gas at 600 ° C./5 to 20 hr and 850 ° C./0.5 to 3 hr to form a polycrystalline silicon film.
[0239]
However, 1) increases the cost due to the use of an expensive excimer laser device, uneven TFT characteristics due to the instability of the excimer laser, quality problems, and productivity reduction. In 2), since a general-purpose glass substrate cannot be used for a long-time heat treatment at 600 ° C. or more and 15 to 20 hours, quartz glass is used, which increases costs. Also, in the full-color organic EL layer, in the microfabrication process, the electrode is oxidized and the organic EL material is easily deteriorated by exposure to oxygen and moisture, or structural change (dissolution or recrystallization) by heating. It is difficult to form the region with high accuracy.
[0240]
Next, the manufacturing process of the organic EL element according to the present embodiment will be described. First, as shown in FIG. 26 (1), the source region 120 and the channel region 117 made of a polycrystalline silicon film through the above-described steps. After forming the gate region 115 and the drain region 121, the gate insulating film 118 is formed. On the gate insulating film 118, the gate electrode 115 of the MOS TFTs 1 and 2 is formed by sputtering film formation of Mo-Ta alloy or the like and photolithography and etching techniques. A gate line connected to the gate electrode is formed by sputtering film formation, photolithography, and etching techniques (hereinafter the same). Then, after an overcoat film (silicon oxide or the like) 137 is formed by a vapor phase growth method such as catalytic CVD (hereinafter the same), a source electrode 127 and a ground line of the MOSTFT 2 are formed, and further an overcoat film (silicon oxide / nitridation) (Silicon laminated film etc.) 136 is formed.
[0241]
Next, as shown in (2) of FIG. 26, after opening the source / drain portion of MOSTFT1 and the gate portion of MOSTFT2, sputtering of Al containing 1% Si as shown in (3) of FIG. The drain electrode of MOSTFT1 and the gate electrode of MOSTFT2 are connected by Al wiring 128 containing 1% Si by general photolithography and etching techniques, and at the same time, the source electrode of MOSTFT1 and the source made of Al containing 1% Si connected to this electrode Form a line. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, the window of the drain part of the MOSTFT 2 is opened, and the cathode 138 of the light emitting part connected to the drain part of the MOSTFT 2 is formed. .
[0242]
Next, as shown in FIG. 26 (4), the organic light emitting layer 132 and the like and the anodes 134 and 135 are formed.
[0243]
In the above, the green (G) light-emitting organic EL layer, the blue (B) light-emitting organic EL layer, and the red (R) light-emitting organic EL layer are each formed to a thickness of 100 to 200 nm. In the case of a low molecular compound, it is formed by a vacuum heating vapor deposition method. In the case of a high molecular compound, a method of arranging R, G, B light emitting polymers by a coating method such as dipping coating or spin coating or an ink jet method is used. In the case of a metal complex, a sublimable material is formed by a vacuum heating vapor deposition method.
[0244]
Examples of the organic EL layer include a single-layer type, a two-layer type, and a three-layer type. Here, an example of a three-layer type of a low-molecular compound is shown.
Single layer type; anode / bipolar light emitting layer / cathode,
Two-layer type; anode / hole transport layer / electron transport light-emitting layer / cathode, or anode / hole transport light-emitting layer / electron transport layer / cathode,
Three layer type; anode / hole transport layer / light emitting layer / electron transport layer / cathode, or anode / hole transport light emitting layer / carrier block layer / electron transport light emitting layer / cathode
[0245]
Note that in the element of FIG. 25B, when a known light emitting polymer is used instead of the organic light emitting layer, a light emitting polymer display device (LEPD) driven by a passive matrix or an active matrix can be configured (hereinafter the same). .
[0246]
<Structural example II of organic EL element>
As shown in FIGS. 27 (A) and 27 (B), according to this Structural Example II, it is formed on the substrate 111 made of glass or the like by the method described above based on the present invention as in the above Structural Example I. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed of a polycrystalline silicon film having a high crystallization rate and a large grain size. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. The drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the drain electrode 131 of the MOSTFT 2 via an insulating film 136, and the source electrode 127 of the MOSTFT 2 is It extends to the anode 144 of the organic EL element.
[0247]
Each MOSTFT is covered with an insulating film 130, and on this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133 or a red organic light emitting layer (not shown)) of an organic EL element is formed so as to cover the anode. A cathode (first layer) 141 is formed so as to cover the organic light emitting layer, and a common cathode (second layer) 142 is further formed on the entire surface.
[0248]
In the organic EL display unit having this structure, the organic EL light emitting layer is connected to the source of the current driving MOS TFT 2 and the organic EL light emitting layer is formed so as to cover the anode 144 deposited on the surface of the substrate 111 such as glass. The cathode 141 is formed so as to cover the organic EL light emitting layer, and the cathode 142 is formed on the entire surface. Therefore, the bottom emission 136 ′ is obtained. A cathode covers the organic EL light emitting layer and the MOS TFT. That is, after a green light emitting organic EL layer is formed on the entire surface by, for example, vacuum heating vapor deposition or the like, a green light emitting organic EL part is formed by photolithography and dry etching. Finally, a cathode (electron injection layer) 141 is formed on the entire surface with magnesium: silver alloy or aluminum: lithium alloy. Since the cathode (electron injection layer) formed on the entire surface is sealed, moisture can be prevented from entering the organic EL layer from the outside, particularly by the cathode 142 deposited on the entire surface. Thus, a long life, high quality, and high reliability are possible (this is the same in the structural example I in FIG. 25 because the entire surface is covered with the anode). Moreover, since the heat radiation effect is enhanced by the cathodes 141 and 142, the structural change (melting or recrystallization) of the thin film due to heat generation is reduced, and a long life, high quality, and high reliability are possible. In addition, this makes it possible to produce a high-precision, high-quality full-color organic EL layer with high productivity, thereby reducing costs.
[0249]
Further, if a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion as shown in FIG. 27C, light leakage (crosstalk, etc.) can be prevented and contrast can be improved. The black mask portion 140 is covered with a silicon oxide film 143 (which may be formed of the same material as the gate insulating film 118).
[0250]
Next, the manufacturing process of this organic EL element will be described. First, as shown in FIG. 28 (1), the source region 120, the channel region 117, and the drain region 121 made of a polycrystalline silicon film through the above-described steps. Then, a gate insulating film 118 is formed by a vapor deposition method such as catalytic CVD, and the gate electrodes 115 of the MOS TFTs 1 and 2 are formed thereon by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques. Further, a gate line connected to the gate electrode of the MOS TFT 1 is formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques. Then, after an overcoat film (silicon oxide or the like) 137 is formed by a vapor phase growth method such as catalytic CVD, the drain electrode 131 and V of the MOSTFT 2 are formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching techniques._ddA line is formed, and an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is formed by a vapor phase growth method such as catalytic CVD.
[0251]
Next, as shown in (2) of FIG. 28, after opening windows of the source / drain portion of MOSTFT1 and the gate portion of MOSTFT2 by general-purpose photolithography and etching techniques, as shown in (3) of FIG. With 1% Si-containing Al sputtering film formation and general-purpose photolithography and etching techniques, the drain of MOSTFT 1 and the gate of MOSTFT 2 are connected by Al wiring 128 containing 1% Si, and at the same time, Al containing 1% Si is connected to the source of MOSTFT 1. A source line is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, a window of the source portion of the MOSTFT 2 is opened by general-purpose photolithography and etching techniques, sputtering of ITO and general-purpose photolithography Then, the anode 144 of the light emitting part connected to the source part of the MOSTFT 2 is formed by an etching technique.
[0252]
Next, as shown in FIG. 28 (4), the organic light emitting layer 132 and the cathodes 141 and 142 are formed as described above.
[0253]
In addition, although the constituent material and formation method of each layer of organic EL described below are applied to the example of FIG. 27, they may be similarly applied to the example of FIG.
[0254]
When a low molecular weight compound is used for the green light-emitting organic EL layer, it is formed by continuous vacuum heating vapor deposition on the ITO transparent electrode that is in contact with the source part of the MOST TFT for current drive, which is the anode (hole injection layer) on the glass substrate. To do.
1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.), etc.
2) The light emitting layer is a green light emitting material such as tris (8-hydroxyxylino) Al complex (Alq)
3) The electron transport layer includes 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazole derivative (TAZ), etc.
4) The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less.
For example, 10-30 nm thickness of 10: 1 (atomic ratio) magnesium: silver alloy
Aluminum: 10-30 nm thickness of lithium (concentration 0.5-1%) alloy
Here, silver is added in an amount of 1 to 10 atomic% in magnesium in order to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization.
[0255]
In order to form the green pixel portion, the green pixel portion is masked with a photoresist, and CCl is formed._FourThe cathode: electron injection layer, aluminum: lithium alloy, is removed by plasma etching of the gas, and the low molecular weight compounds and photoresist in the electron transport layer, light-emitting layer, hole transport layer, and photoresist are successively removed by oxygen plasma etching. A pixel portion is formed. At this time, since there is an aluminum: lithium alloy under the photoresist, there is no problem even if the photoresist is etched. At this time, the electron transport layer, the light emitting layer, and the low molecular weight compound layer of the hole transport layer have a larger area than the ITO transparent electrode of the hole injection layer, and the cathode electron injection layer (magnesium) formed on the entire surface in the subsequent process. : Silver alloy).
[0256]
Next, when the blue light-emitting organic EL layer is formed of a low molecular compound, a vacuum is continuously formed on the ITO transparent electrode in contact with the source part of the current driving TFT which is an anode (hole injection layer) on the glass substrate. It is formed by heat evaporation.
1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.), etc.
2) The light emitting layer is a distyryl derivative such as DTVBi which is a blue light emitting material.
3) The electron transport layer is composed of 1,3,4-oxadiazole derivative (TAZ), 1,2,4-triazole derivative (TAZ), etc.
4) The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less.
For example, 10-30 nm thickness of 10: 1 (atomic ratio) magnesium: silver alloy
Aluminum: 10-30 nm thickness of lithium (concentration 0.5-1%) alloy
Here, silver is added in an amount of 1 to 10 atomic% in magnesium in order to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization.
[0257]
To form the blue pixel portion, the blue pixel portion is masked with a photoresist, and CCl_FourGas plasma etching removes the aluminum: lithium alloy in the electron injection layer, which is the cathode, and continuously removes low molecular weight compounds and photoresists in the electron transport layer, light-emitting layer, and hole transport layer by oxygen plasma etching. A pixel portion is formed. At this time, since there is an aluminum: lithium alloy under the photoresist, there is no problem even if the photoresist is etched. At this time, the electron transport layer, the light emitting layer, and the low molecular weight compound layer of the hole transport layer have a larger area than the ITO transparent electrode of the hole injection layer, and the cathode electron injection layer (magnesium) formed on the entire surface in the subsequent process. : Silver alloy).
[0258]
When the red light-emitting organic EL layer is formed of a low-molecular compound, vacuum heating is continuously performed on the ITO transparent electrode that is in contact with the source part of the current driving TFT which is the anode (hole injection layer) on the glass substrate. It is formed by vapor deposition.
1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.), etc.
2) The light emitting layer is made of Eu (Eu (DBM)) which is a red light emitting material._Three(Phen)) etc.
3) The electron transport layer includes 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazole derivative (TAZ), etc.
4) The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less.
For example, 10-30 nm thickness of 10: 1 (atomic ratio) magnesium: silver alloy
Aluminum: 10-30 nm thickness of lithium (concentration 0.5-1%) alloy
Silver is added in an amount of 1 to 10 atomic% in magnesium to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization.
[0259]
To form the red pixel portion, the red pixel portion is masked with a photoresist, and CCl_FourGas plasma etching removes the aluminum: lithium alloy in the electron injection layer, which is the cathode, and continuously removes low molecular weight compounds and photoresist in the electron transport layer, light emitting layer, and hole transport layer by oxygen plasma etching, and red A pixel portion is formed. At this time, since there is an aluminum: lithium alloy under the photoresist, there is no problem even if the photoresist is etched. At this time, the electron transport layer, the light emitting layer, and the low molecular weight compound layer of the hole transport layer have a larger area than the ITO transparent electrode of the hole injection layer, and the cathode electron injection layer (magnesium) formed on the entire surface in the subsequent process. : Silver alloy).
[0260]
The electron injection layer as the cathode is preferably made of a material having a work function of 4 eV or less. For example, the thickness is 10 to 30 nm of a 10: 1 (atomic ratio) magnesium: silver alloy, or 10 to 30 nm of an aluminum: lithium (concentration is 0.5 to 1%) alloy. Here, silver is added in an amount of 1 to 10 atomic% in magnesium in order to increase adhesion to the organic interface, and lithium is added in an amount of 0.5 to 1% in aluminum for stabilization. Note that the film may be formed by sputtering.
[0261]
Fourth embodiment
In the present embodiment, the present invention is applied to a field emission display (FED). The structural examples and production examples are shown below.
[0262]
<Structure example I of FED>
As shown in FIGS. 29A, 29B, and 29C, according to this structural example I, the high crystallization rate formed on the substrate 111 such as glass by the method described above based on the present invention. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed by the polycrystalline silicon film having a large grain size. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed on the source and drain regions. The drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of the MOSTFT 2 via an insulating film 136, and the drain region 121 of the MOSTFT 2 is It extends as it is to the FEC (field emission cathode) of the FED element, and functions as the emitter region 152.
[0263]
Each MOSTFT is covered with an insulating film 130. On this insulating film, a metal shielding film 151 for grounding is formed in the same process with the same material as that of the FEC gate lead electrode 150 to cover each MOSTFT. In FEC, an n-type polycrystalline silicon film 153 to be a field emission emitter is formed on an emitter region 152 made of a polycrystalline silicon film, and has openings for partitioning into m × n emitters. Further, the insulating films 118, 137, 136 and 130 are patterned, and a gate extraction electrode 150 is deposited on the upper surface.
[0264]
Further, a substrate 157 such as a glass substrate formed with a phosphor 156 with a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the FEC and the FEC.
[0265]
In the FEC having this structure, the n-type polycrystalline silicon film 153 grown on the polycrystalline silicon film 152 formed in accordance with the present invention is exposed under the opening of the gate lead electrode 150, which is respectively It functions as a thin film type emitter that emits electrons 154. That is, since the polycrystalline silicon film 152 serving as the base of the emitter is composed of grains having a large grain size (grain size of several hundred nm or more), the n-type polycrystalline silicon film 153 is used as a catalyst on the polycrystalline silicon film 153 as a catalyst. When grown by CVD or the like, the polycrystalline silicon film 153 grows with a larger grain size and is formed so that the surface has fine irregularities 158 that are advantageous for electron emission.
[0266]
Therefore, since the emitter is a surface emission type made of a thin film, its formation is easy, the emitter performance is stable, and the life can be extended.
[0267]
Further, a metal-based shielding film 151 having a ground potential is formed on the upper part of all active elements (this includes the MOSTFT and the diode of the peripheral drive circuit and the pixel display portion). Since the same material (Nb, Ti / Mo, metal silicide, etc.) is formed in the same process, it is convenient in terms of the process. Therefore, the following advantages (1) and (2) can be obtained.
[0268]
(1) The gas in the hermetic container is positively ionized by electrons emitted from the emitter 153 and is charged on the insulating layer, and this positive charge forms an unnecessary inversion layer in the MOSTFT under the insulating layer. Since an excess current flows through an unnecessary current path made of an inversion layer, the emitter current runs away. However, since the metal-based shielding film 151 is formed on the insulating layer on the MOSTFT and dropped to the ground potential, it is possible to prevent charge-up and to prevent runaway of the emitter current.
[0269]
(2) The phosphor 156 emits light due to the collision of electrons emitted from the emitter 153. This light generates electrons and holes in the gate channel of the MOSTFT, resulting in a leakage current. However, since the metal-based shielding film 151 is formed on the insulating layer on the MOSTFT, light incidence to the MOSTFT is prevented and the MOSTFT does not malfunction.
[0270]
In addition, since the electron emitter (emitter) of the n-type polycrystalline silicon film is formed continuously at least in the drain region of the polycrystalline silicon MOS TFT by catalytic CVD or the like, its bonding property is good and high Efficient emitter characteristics are possible.
[0271]
In addition, if the electron emitter (emitter) region of one pixel display part is divided into a plurality of parts and the MOSTFT of the switching element is connected to each of them, even if one MOSTFT fails, the other MOSTFT operates. One pixel display unit is always configured to emit electrons, so that the quality is high, the yield is high, and the cost can be reduced. Further, in these MOSTFTs, there is no problem with MOSTFTs with poor electrical openness, but since MOSTFTs that are electrically short-circuited can be separated by laser repair, high quality, high yield, and cost reduction can be achieved.
[0272]
In contrast, in the conventional FED, since a silicon single crystal substrate is used, the substrate cost is high, and it is difficult to increase the area larger than the wafer size. And, it has been proposed to form an electron emitter by forming a conductive polycrystalline silicon film on the cathode electrode surface by low pressure CVD or the like and forming a crystalline diamond film on the surface by plasma CVD or the like. The film formation temperature during the low pressure CVD is as high as 630 ° C., and a glass substrate cannot be adopted, so that it is difficult to reduce the cost. The polycrystalline silicon film formed by the low pressure CVD has a small particle size, and the crystalline diamond film thereon also has a small particle size, and the characteristics of the electron emitter are not good. Furthermore, since the reaction energy is insufficient due to plasma CVD, it is difficult to obtain a good crystalline diamond film. Further, since the bonding property between the transparent electrode or the cathode electrode made of metal such as Al, Ti, and Cr and the conductive polycrystalline silicon film is poor, good electron emission characteristics cannot be obtained.
[0273]
Next, the manufacturing process of the FED according to the present embodiment will be described. First, as shown in FIG. 30 (1), after the polycrystalline silicon film 117 is formed on the entire surface through the above-described steps, general-purpose photolithography is performed. Then, MOSTFT1, MOSTFT2, and the emitter region are formed into islands by an etching technique, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.
[0274]
Next, V V is controlled by controlling the gate channel impurity concentration of the MOS TFTs 1 and 2._thIn order to optimize this, boron ions 83 are 5 × 10 5 on the entire surface by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷The acceptor concentration is set to atoms / cc.
[0275]
Next, as shown in (2) of FIG. 30, phosphorus ions 79 are introduced into the source / drain and emitter regions of the MOS TFTs 1 and 2 by 1 × 10 6 by ion implantation or ion doping using the photoresist 82 as a mask.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰After setting the donor concentration to atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the protective silicon oxide film in the emitter region is removed by general-purpose photolithography and etching techniques.
[0276]
Next, as shown in (3) of FIG. 30, monosilane and PH are formed using the polycrystalline silicon film 152 that forms the emitter region by catalytic CVD as a seed._ThreeEtc. are mixed at an appropriate ratio, and the surface has fine irregularities 158, and the dopant is, for example, 5 × 10²⁰~ 1x10^{twenty one}An n-type polycrystalline silicon film 153 containing atoms / cc is formed in the emitter region to a thickness of 1 to 5 μm. At the same time, an n-type amorphous silicon film 160 is formed on the other silicon oxide film 159 and the glass substrate 111 to a thickness of 1 to 5 μm. To form.
[0277]
Next, as shown in FIG. 30 (4), the amorphous silicon film 160 is etched away by the activated hydrogen ions during the catalyst AHA treatment described above, and after the silicon oxide film 159 is removed by etching, the gate insulating film is formed by catalytic CVD or the like. (Silicon oxide film or the like) 118 is formed.
[0278]
Next, as shown in FIG. 31 (5), gate lines connected to the gate electrodes 115 of the MOSTFT 1 and 2 and the gate electrode of the MOSTFT 1 are formed from a heat-resistant metal such as a Mo—Ta alloy by sputtering, and the overcoat is formed. After the film (silicon oxide film or the like) 137 is formed, the source electrode 127 of the MOSTFT 2 and the ground line are formed of a heat-resistant metal such as a Mo—Ta alloy by sputtering after opening the source window of the MOSTFT 2. Further, an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is formed by plasma CVD, catalytic CVD, or the like, and ion activation treatment is performed at 1000 ° C. for 10 to 20 seconds such as RTA treatment.
[0279]
Next, as shown in FIG. 31 (6), the source / drain portion of the MOSTFT1 and the gate portion of the MOSTFT2 are opened, and the drain of the MOSTFT1 and the gate of the MOSTFT2 are connected by an Al wiring 128 containing 1% Si. A source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.
[0280]
Next, as shown in (7) of FIG. 31, after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130, a window of the GND line is opened, and (8) of FIG. As shown in FIG. 5, the gate lead electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode portion is opened to expose the emitter 153, and the hydrogen-based activity of the bias catalyst AHA treatment described above. Clean with seeds.
[0281]
<FED Structure Example II>
As shown in FIGS. 32 (A), (B), and (C), according to the structure example II, on the substrate 111 such as glass, as described in the structure example I, the above-described structure is based on the present invention. The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed by a polycrystalline silicon film having a high crystallization rate and a large grain size formed by the method. A gate electrode 115 is formed on the gate insulating film 118, and a source electrode 127 and a drain electrode 128 are formed on the source and drain regions. The drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected via a drain electrode 128, a capacitor C is formed between the source electrode 127 of the MOSTFT 2 via an insulating film 136, and the drain region 121 of the MOSTFT 2 is It extends as it is to the FEC (field emission cathode) of the FED element, and functions as the emitter region 152.
[0282]
Each MOSTFT is covered with an insulating film 130. On this insulating film, a metal shielding film 151 for grounding is formed in the same process with the same material as that of the FEC gate lead electrode 150 to cover each MOSTFT. In FEC, an n-type polycrystalline diamond film 163 to be a field emission emitter is formed on an emitter region 152 made of a polycrystalline silicon film, and further has openings for partitioning into m × n emitters. Insulating films 118, 137, 136 and 130 are patterned, and a gate lead electrode 150 is deposited on the upper surface.
[0283]
Further, a substrate 157 such as a glass substrate formed with a phosphor 156 with a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the FEC and the FEC.
[0284]
In the FEC having this structure, an n-type polycrystalline diamond film 163 grown on the polycrystalline silicon film 152 formed in accordance with the present invention is exposed under the opening of the gate extraction electrode 150, and each of them is an electron 154. It functions as a thin film type emitter that emits. That is, since the polycrystalline silicon film 152 serving as the base of the emitter is composed of grains having a large grain size (grain size of several hundred nm or more), the n-type polycrystalline diamond film 163 is used as a catalyst on this as a seed. When grown by CVD or the like, the polycrystalline diamond film 163 also grows with a large grain size, and is formed so that the surface has fine irregularities 168 that are advantageous for electron emission.
[0285]
Therefore, since the emitter is a surface emission type made of a thin film, its formation is easy, the emitter performance is stable, and the life can be extended.
[0286]
Further, a metal-based shielding film 151 having a ground potential is formed on the upper part of all active elements (this includes the MOSTFT and the diode of the peripheral drive circuit and the pixel display portion). Since the same material (Nb, Ti / Mo, metal silicide, etc.) is formed in the same process, it is convenient in terms of process.) As described above, the metal-based shielding film 151 is formed on the insulating layer on the MOSTFT as described above. Can be reduced to the ground potential to prevent charge-up, emitter current runaway can be prevented, and since the metal-based shielding film 151 is formed on the insulating layer on the MOSTFT, light incident on the MOSTFT can be prevented. This prevents the malfunction of the MOSTFT.
[0287]
Next, the manufacturing process of the FED will be described. First, as shown in FIG. 33 (1), after the polycrystalline silicon film 117 is formed on the entire surface through the above-described steps, the general photolithography and etching techniques are used. An island is formed in the MOSTFT1, MOSTFT2, and the emitter region, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD, or the like.
[0288]
Next, V V is controlled by controlling the gate channel impurity concentration of the MOS TFTs 1 and 2._thIn order to optimize this, boron ions 83 are 5 × 10 5 on the entire surface by ion implantation or ion doping.¹¹atoms / cm²Doping with a dose of 1 × 10¹⁷The acceptor concentration is set to atoms / cc.
[0289]
Next, as shown in (2) of FIG. 33, phosphorus ions 79 are introduced into the source / drain portions and the emitter regions of the MOS TFTs 1 and 2 by 1 × 10 × 10 by ion implantation or ion doping using the photoresist 82 as a mask.¹⁵atoms / cm²Doping with a dose of 2 × 10²⁰After setting the donor concentration to atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the protective silicon oxide film in the emitter region is removed by general-purpose photolithography and etching techniques.
[0290]
Next, as shown in (3) of FIG. 33, monosilane and methane (CH) are seeded using the polycrystalline silicon film 152 that forms the emitter region by catalytic CVD._Four) And a dopant in an appropriate ratio, and an n-type polycrystalline diamond film 163 having fine irregularities 168 on the surface is formed in the emitter region. At the same time, an n-type amorphous diamond film is formed on the other silicon oxide film 159 and the glass substrate 111. 170 is formed.
[0291]
Next, as shown in FIG. 33 (4), the amorphous diamond film 170 is etched away by the activated hydrogen ions at the time of the catalyst AHA treatment described above, and after the silicon oxide film 159 is removed by etching, the gate insulating film is formed by catalytic CVD or the like. (Silicon oxide film or the like) 118 is formed.
[0292]
Next, as shown in FIG. 34 (5), gate lines connected to the gate electrodes 115 of the MOSTFT 1 and 2 and the gate electrode of the MOSTFT 1 are formed by a heat-resistant metal such as a Mo—Ta alloy by sputtering, and an overcoat is formed. After the film (silicon oxide film or the like) 137 is formed, the source electrode 127 of the MOSTFT 2 and the ground line are formed of a heat-resistant metal such as a Mo—Ta alloy by sputtering after opening the source window of the MOSTFT 2. Further, an overcoat film (silicon oxide / silicon nitride laminated film or the like) 136 is formed by plasma CVD, catalytic CVD, or the like, and ion activation treatment is performed at 1000 ° C. for 10 to 20 seconds such as RTA.
[0293]
Next, as shown in FIG. 34 (6), the source / drain portion of the MOSTFT 1 and the gate portion of the MOSTFT 2 are opened, and the drain of the MOSTFT 1 and the gate of the MOSTFT 2 are connected by an Al wiring 128 containing 1% Si. A source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.
[0294]
Next, as shown in (7) of FIG. 34, after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130, a GND line window is opened, and (8) of FIG. As shown in FIG. 5, the gate lead electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and further, the field emission cathode portion is opened to expose the emitter 163, and the hydrogen-based activity of the bias catalyst AHA treatment described above. Clean with seeds.
[0295]
In the above, when forming the polycrystalline diamond film 163, the carbon-containing compound as the source gas used is, for example,
1) Paraffinic hydrocarbons such as methane, ethane, propane and butane
2) Acetylene and arylene acetylene hydrocarbons
3) Olefin hydrocarbons such as ethylene, propylene, butylene
4) Diolefin hydrocarbons such as butadiene
5) Cyclopropane, cyclobutane, cyclopentane, cyclohexane and other alicyclic hydrocarbons
6) Aromatic hydrocarbons such as cyclobutadiene, benzene, toluene, xylene, naphthalene
7) Ketones such as acetone, diethyl ketone, and benzophenone
8) Alcohols such as methanol and ethanol
9) Amines such as trimethylamine and triethylamine
10) Substances consisting only of carbon atoms, such as graphite, coal, coke, etc.
These may be used alone or in combination of two or more.
[0296]
Further, usable inert gases are, for example, argon, helium, neon, krypton, xenon, and radon. As the dopant, for example, a compound containing boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsenic, selenium, beryllium, or the like can be used, and the doping amount is 10²⁰atoms / cc or more.
[0297]
Fifth embodiment
In this embodiment, the present invention is applied to a solar cell as a photoelectric conversion device. The production example is shown below.
[0298]
First, as shown in (1) of FIG. 35, after a protective film (not shown) is formed on a metal substrate 111 such as stainless steel by the above-described catalytic CVD method or the like, an amorphous or microcrystalline carbon thin film is formed thereon. 100A is formed.
[0299]
Next, as shown in FIG. 35 (2), the carbon thin film 100A is changed to a diamond ultrafine carbon particle layer 100B by the above-described bias catalyst AHA treatment.
[0300]
Next, as shown in (3) of FIG. 35, the n-type polycrystalline silicon film 7 is formed using the carbon ultrafine particle layer 100B as a seed by the above-described catalytic CVD or bias catalytic CVD method. This polycrystalline silicon film 7 may be formed by the above-described multi-catalyst AHA treatment, and has a high crystallization rate, a large grain size of tin or other group IV element (Ge, Pb) alone or in a mixture containing n-type. A polycrystalline silicon film is formed to a thickness of 100 to 200 nm. The polycrystalline silicon film 7 is doped with n-type impurities such as phosphorus._ThreeFor example, 1 × 10¹⁷~ 1x10¹⁸atoms / cc.
[0301]
Next, as shown in FIG. 36 (4), on the polycrystalline silicon film 7, i or a mixture containing tin or other group IV elements (Ge, Pb) alone or in mixture by catalytic CVD or the like is used as a seed. A type polycrystalline silicon film 180, a p-type polycrystalline silicon film 181 containing tin or another group IV element (Ge, Pb) alone or in a mixture, and the like are grown to form a photoelectric conversion layer.
[0302]
For example, by catalytic CVD, tin hydride (SnH_Four) Are mixed at an appropriate ratio to grow an i-type large grain tin-containing polycrystalline silicon film 180 to a thickness of 2 to 5 μm. On top of this, p-type impurity boron (B₂H₆Etc.) and tin hydride (SnH)_Four) In an appropriate ratio, for example, 1 × 10¹⁷~ 1x10¹⁸A p-type large-grain-size tin-containing polycrystalline silicon film 181 containing atoms / cc is formed to a thickness of 100 to 200 nm. At this time, tin or another group IV element (Ge, Pb) alone or a mixture such as tin, for example, 1 × 10 6 is contained in each film.¹⁶atoms / cc or more, preferably 1 × 10¹⁸~ 1x10²⁰By containing atoms / cc, crystal irregularities and stress existing in the crystal grain boundaries are reduced, so that carrier mobility can be improved (this is because the n-type or p-type polycrystalline silicon films 7 and 181 are formed). The same applies when forming).
[0303]
Further, the above-described multi-bias catalyst AHA treatment may be performed. For example, after an n-type or p-type tin-containing polycrystalline silicon film is grown to a thickness of 20 to 50 nm by catalytic CVD or bias catalytic CVD, a bias catalyst AHA treatment is performed, and n-type or A p-type tin-containing polycrystalline silicon film is grown to a thickness of 20 to 50 nm, and after the bias catalyst AHA treatment, an n-type or p-type tin-containing polycrystalline silicon film is further 20 to 50 nm by catalytic CVD or bias catalyst CVD. Then, each process may be repeated by the necessary number of times so that the bias catalyst AHA process is performed (this is also the case with the i-type polycrystalline silicon film 180). By this method, a tin-containing polycrystalline silicon film having a larger particle size can be formed. Alternatively, the amount of source gas supply may be increased during film formation to achieve high-speed film formation. After this, RTA treatment (about 1000 ° C., 10 to 30 seconds) activates ions in each layer.
[0304]
Next, as shown in FIG. 36 (5), a transparent electrode 182 is formed on the entire surface of the tin-containing polycrystalline silicon film having a large particle size of the nip junction formed by the above method. For example, a transparent electrode 182 such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) for antireflection coating is formed to a thickness of 100 to 150 nm by a general-purpose sputtering technique. Then, a comb-shaped electrode 183 made of silver or the like is formed to a thickness of 100 to 150 nm in a predetermined region by a general sputtering technique using a metal mask.
[0305]
The above film may not contain tin or other group IV elements, but in this case, it can be produced in the same manner as described above. In addition to the above-described nip junction structure, a pi-n junction, an pn junction, and a pn junction structure can be similarly manufactured.
[0306]
The solar cell according to the present embodiment can form a photoelectric conversion thin film with high carrier mobility and high conversion efficiency with a large grain polycrystalline silicon film based on the present invention, and has a good surface texture structure and back surface texture structure. Since it is formed, a photoelectric conversion thin film having a high light containment effect and a high conversion efficiency can be formed. This is not limited to the solar battery, and can be advantageously used for a thin film photoelectric conversion device such as a photosensitive drum for electrophotography.
[0307]
In contrast, in this type of conventional photoelectric conversion device, an amorphous carbon thin film is formed by RF plasma CVD, VHF plasma CVD, etc., and ultrafine carbon particles are formed by plasma hydrogen treatment, which is used to grow polycrystalline silicon crystals. A large grain polycrystalline silicon film is formed as a nucleus, and an n-type polycrystalline silicon layer, an i-type polycrystalline silicon active layer, and a p-type polycrystalline silicon layer are continuously formed, and an ITO film is laminated on the entire surface. Finally, a comb electrode is formed to obtain a thin-film polycrystalline silicon solar cell having a thickness of about 2 μm.
[0308]
However, this conventional method cannot avoid the following drawbacks.
1) A crystalline silicon thin film formed at a low temperature by RF plasma CVD, VHF plasma CVD or the like has low energy, so that chemical decomposition reaction of raw material gas or plasma hydrogen treatment tends to be insufficient, and the crystal grain size is small. Because it is small, mobility is low, and excessive current due to local electrical shorts or leaks is likely to occur due to the large number of grain boundaries and pinholes, and it is deposited in the film thickness of several μm required as a photoelectric conversion layer. In such a case, the internal stress or strain of the film increases, and in the worst case, the film peels off. As a result, the production yield and reliability of the photoelectric conversion layer are remarkably lowered, which is a major obstacle to aiming at practical use of a photoelectric conversion device including the photoelectric conversion layer.
2) Since RF plasma CVD and VHF plasma CVD have low energy, the utilization efficiency of the source gas is as low as 5 to 10%. For this reason, productivity is low and it is difficult to reduce costs.
[0309]
The embodiment of the present invention described above can be variously modified based on the technical idea of the present invention.
[0310]
For example, the number of repetitions of the above-described catalytic CVD method and bias catalyst AHA treatment and various conditions may be variously changed, and the material of the substrate used is not limited to the above.
[0311]
Further, the present invention is suitable for an internal circuit such as a display unit, a peripheral driving circuit, a video signal processing circuit, a memory circuit, and other MOSTFTs, but besides that, an active region of a device such as a diode, a resistor, It is also possible to form passive regions such as capacitance (capacitance), wiring, and inductance with the polycrystalline silicon film according to the present invention.
[0312]
[Effects of the invention]
In the present invention, as described above, when forming a polycrystalline semiconductor thin film on a substrate, a carbon thin film made of amorphous carbon, microcrystalline carbon, or a mixture thereof is formed on the substrate, and hydrogen or a hydrogen-containing gas is heated. The hydrogen-based active species produced by contacting with the formed catalyst body is allowed to act on the carbon thin film under the action of an electric field or / and magnetic field below the glow discharge starting voltage, and the amorphous-structured carbon is produced by the action of the hydrogen-based active species. Are etched to form diamond ultrafine carbon particles, and the semiconductor material thin film is vapor-grown using the ultrafine carbon particles as seeds (crystal growth nuclei). The following (1) to (4) The remarkable effect as shown is obtained.
[0313]
(1) Activated species generated by bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst body (hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions) can be subjected to any electric field or / In addition, since the carbon thin film is caused to act by spraying or the like by the bias catalyst AHA treatment by the magnetic field, the following remarkable effect is shown by adding the heating by the radiant heat of the high temperature heating catalyst body.
[0314]
In this bias catalyst AHA treatment, hydrogen is brought into contact with a high temperature catalyst body (800 to 2000 ° C. below melting point, for example, 1500 to 2000 ° C. for tungsten) under a hydrogen or hydrogen-containing gas pressure of 10 to 50 Pa, and a large amount of high temperature Of hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions) and the like are sprayed onto an amorphous carbon film or microcrystalline carbon film formed on the substrate (however, the substrate temperature is 200-500 ° C), in addition to the thermal energy possessed by a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions), etc. It moves to the film etc. with sufficient directional kinetic energy of the film and locally raises the temperature of the film etc., and the amorphous carbon film and the microcrystalline carbon film The ultrafine carbon particles having a diamond structure on the surface or substrate (for example, a glass substrate) such as an amorphous carbon film or a microcrystalline carbon film are crystallized as the amorphous component is etched away by the action of the hydrogen-based active species. Cluster) can be reliably and stably scattered, and this can be effectively used as a crystal growth nucleus (seed) for the subsequent growth of polycrystalline silicon or the like. At this time, in particular, the gate channel region and the like are scattered in islands, and the electrical resistance needs to be small enough to be ignored.
[0315]
(2) The diamond-structured carbon ultrafine particles obtained by the bias catalyst AHA treatment are used as seeds, and the semiconductor material thin film is easily grown on the polycrystalline material (as a polycrystalline semiconductor thin film). By the subsequent bias catalyst AHA treatment and vapor phase growth, crystallization of the silicon film or the like grown on the polycrystalline semiconductor thin film is promoted by using the polycrystalline semiconductor thin film as a seed. A polycrystalline semiconductor thin film having a high crystallization rate and high quality can be obtained. That is, if a silicon film formed by catalytic CVD, for example, contains an amorphous component by bias catalyst AHA treatment, this is etched away by the action of hydrogen-based active species, and a silicon film that is vapor-phase grown thereon. Is easy to form a polycrystalline silicon film by using the diamond ultrafine particles with the diamond structure as the seed (nucleus). Furthermore, if the same bias catalyst AHA treatment and vapor phase growth are repeated, a large amount of high-temperature hydrogen-based activity can be obtained. The thermal energy of the seeds moves to the film etc. by sufficient directional kinetic energy due to the acceleration electric field and / or magnetic field, and the temperature of the film etc. increases locally. Amorphous silicon and microcrystalline silicon are polycrystalline Thus, the polycrystalline silicon can be highly crystallized to form a polycrystalline silicon film having a high crystallization rate and a large grain size. As a result, not only the top gate type, but also the bottom gate type and dual gate type MOS TFT can obtain a large grain polycrystalline silicon thin film with high carrier (electron / hole) mobility. High-speed, high current density semiconductor devices, electro-optical devices, and high-efficiency solar cells using semiconductors such as polycrystalline silicon can be manufactured.
[0316]
(3) Since this bias catalyst AHA treatment can be performed without generating plasma, there is no damage caused by plasma, and a simpler and cheaper apparatus can be realized as compared with plasma treatment.
[0317]
(4) Since the energy of the active species is large even if the substrate temperature is lowered, the target diamond structure carbon ultrafine particles can be obtained stably and reliably, and the substrate temperature is as low as 300 to 400 ° C. in particular. Even if it is changed, the polycrystalline semiconductor thin film grows efficiently using carbon ultrafine particles as a seed, so that large and inexpensive low-strain-point insulating substrates (glass substrates, heat-resistant resin substrates, etc.) can be used. Down is possible.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a manufacturing process of a MOS TFT according to a first embodiment of the present invention in the order of steps.
FIG. 2 is a sectional view showing the manufacturing process in the order of steps.
FIG. 3 is a cross-sectional view showing the manufacturing process in the order of steps.
FIG. 4 is a cross-sectional view showing the manufacturing process in the order of steps.
FIG. 5 is a schematic cross-sectional view in one state of the apparatus for catalytic CVD and bias catalyst AHA treatment used in the production.
FIG. 6 is a schematic sectional view of the device in another state.
FIG. 7 is a schematic sectional view showing the apparatus in more detail.
FIG. 8 is a schematic cross-sectional view of an apparatus using a bias method.
FIG. 9 is a schematic cross-sectional view of another apparatus using a bias method.
FIG. 10 is a schematic cross-sectional view of another apparatus using a bias method.
FIG. 11 is a timing chart of the gas flow rate during processing using this apparatus.
FIG. 12 is a schematic view of a gas supply system of the apparatus.
FIG. 13 is a graph showing a comparison of Raman spectra of semiconductor films obtained by the processing.
FIG. 14 is a graph showing comparison of crystallization rates of semiconductor thin films.
FIG. 15 is a graph showing a comparison of the concentration of heavy metals in the membrane according to the purity of the catalyst body and the support body.
FIG. 16 is a cross-sectional view showing the manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.
FIG. 17 is a sectional view showing the manufacturing process in the order of steps.
FIG. 18 is a sectional view showing the manufacturing process in the order of steps.
FIG. 19 is a sectional view showing the manufacturing process in the order of steps.
FIG. 20 is a perspective view showing a schematic layout of the entire LCD.
FIG. 21 is an equivalent circuit diagram of the LCD.
FIG. 22 is a cross-sectional view showing another manufacturing process of the LCD in the order of steps.
FIG. 23 is a sectional view showing the manufacturing process in the order of steps.
FIG. 24 is a cross-sectional view showing various types of MOS TFTs of the LCD.
FIG. 25 is an equivalent circuit diagram (A) of a main part of an organic EL display device according to a third embodiment of the present invention, an enlarged cross-sectional view (B) of the main part, and a cross-sectional view of the peripheral part of the pixel (C). It is.
FIG. 26 is a cross-sectional view showing the manufacturing process of the organic EL display device in the order of steps.
FIG. 27 is an equivalent circuit diagram (A) of a main part of another organic EL display device, an enlarged cross-sectional view (B) of the main part, and a cross-sectional view (C) of the periphery of the pixel.
FIG. 28 is a cross-sectional view showing the manufacturing process of the organic EL display device in the order of steps.
FIG. 29 is an equivalent circuit diagram (A) of an essential part of an FED according to a fourth embodiment of the present invention, an enlarged sectional view (B) of the essential part, and a schematic plan view (C) of the essential part.
FIG. 30 is a cross-sectional view showing the FED manufacturing process in the order of steps.
FIG. 31 is a sectional view showing the manufacturing process in the order of steps.
FIG. 32 is an equivalent circuit diagram (A) of an essential part of another FED, an enlarged cross-sectional view (B) of the essential part, and a plan view (C) of the essential part.
FIG. 33 is a cross-sectional view showing the FED manufacturing process in the order of steps.
FIG. 34 is a sectional view showing the manufacturing process in the order of steps.
FIG. 35 is a cross-sectional view showing the manufacturing process of the solar cell according to the fifth embodiment of the present invention in the order of steps.
FIG. 36 is a sectional view showing the manufacturing process in the order of steps.
[Explanation of symbols]
1, 61, 98, 111, 157 ... substrate, 7, 67 ... polycrystalline silicon film,
14, 67, 117 ... channels,
15, 75, 102, 105, 115 ... gate electrodes,
8, 68, 103, 104, 106, 118 ... gate insulating film,
20, 21, 80, 81, 120, 121 ... n⁺Type source or drain region,
24, 25, 84, 85 ... p⁺Type source or drain region,
27, 28, 86, 92, 130, 136, 137 ... insulating film,
29, 30, 87, 88, 89, 90, 91, 93, 97, 127, 128, 131 ... electrodes, 40 ... source gas, 42 ... shower head, 44 ... film formation chamber,
45 ... susceptor, 46 ... catalyst, 47 ... shutter, 48 ... catalyst power supply,
49 ... Bias power supply, 94, 96 ... Alignment film, 95 ... Liquid crystal,
99: Color filter layer, 100A: Amorphous or microcrystalline carbon thin film,
100B ... Diamond ultrafine carbon particle layer,
100 ', 140 ... black mask layer, 132, 133 ... organic light emitting layer,
134, 135, 144 ... anode, 138, 141, 142, 171 ... cathode,
150 ... Gate lead electrode (gate line), 151 ... Shielding film,
152 ... emitter, 153 ... n-type polycrystalline silicon film, 155 ... back metal, 156 ... phosphor, 158, 168 ... fine unevenness,
163 ... n-type polycrystalline diamond film, 180 ... i-type polycrystalline silicon film,
181 ... p-type polycrystalline silicon film, 182 ... transparent electrode, 183 ... comb electrode,
200, 201 ... Electrode, 202, 203 ... Magnetic pole (permanent magnet), 204 ... Electromagnet

Claims (29)

When forming a polycrystalline semiconductor thin film on a substrate,
Forming a carbon thin film comprising amorphous carbon or microcrystalline carbon or a mixture thereof on the substrate;
Hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body, and the hydrogen-based active species generated thereby are annealed by acting on the carbon thin film under the action of an electric field or / and a magnetic field below the glow discharge starting voltage, Forming a diamond-structured carbon ultrafine particle;
A method for forming a polycrystalline semiconductor thin film, wherein the polycrystalline semiconductor thin film is obtained through vapor phase growth of a semiconductor material thin film on the carbon ultrafine particles. When manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate,
Forming a carbon thin film comprising amorphous carbon or microcrystalline carbon or a mixture thereof on the substrate;
Hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body, and the hydrogen-based active species generated thereby are annealed by acting on the carbon thin film under the action of an electric field or / and a magnetic field below the glow discharge starting voltage, Forming a diamond-structured carbon ultrafine particle;
A method of manufacturing a semiconductor device, wherein the polycrystalline semiconductor thin film is obtained through a vapor phase growth process of a semiconductor material thin film on the carbon ultrafine particles.   The method according to claim 1, wherein the carbon thin film is formed by a vapor deposition method or a physical film formation method, and the semiconductor material thin film is formed by a vapor deposition method. The carbon thin film is prepared by contacting at least a part of the source gas and hydrogen or a hydrogen-containing gas with a heated catalyst body for catalytic decomposition, and depositing reactive species composed of radicals and ions generated thereby on the substrate. 3. The method according to claim 1 or 2, wherein the thin film of semiconductor material is vapor-phase grown. The method according to claim 4, wherein the reactive species is deposited on the substrate under the action of an electric field or / and a magnetic field below a glow discharge starting voltage. After vapor phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is brought into contact with a heated catalyst body, and a hydrogen-based active species composed of high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions generated thereby. glow discharge starting voltage below the field and / or by acting on the semiconductor material thin film under the action of a magnetic field cormorants line annealing method according to claim 4. The method according to claim 6, wherein vapor phase growth of the semiconductor material thin film similar to the semiconductor material thin film and the annealing are repeated. The heated the catalyst is contacted with at least a portion of said hydrogen or hydrogen-containing gas, thereby resulting hot hydrogen-based molecules, hydrogen-based atom, hydrogen-based active species glow discharge starting voltage consisting of activated hydrogen ions The method according to claim 1, wherein annealing is performed by acting on the carbon thin film or the semiconductor material thin film under the action of the following electric field and / or magnetic field. The heated said catalyst body, the raw material gas and contacting at least a portion of the hydrogen-based carrier gas catalytically to decompose, radicals generated thereby, is deposited on the substrate the reactive species is heated made of an ion After the vapor deposition of the carbon thin film or the semiconductor material thin film, the supply of the source gas is stopped, and at least a part of the hydrogen-based carrier gas is brought into contact with the heated catalyst body, thereby generating a high temperature Annealing is performed by applying a hydrogen-based active species composed of hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions to the carbon thin film or the semiconductor material thin film under the action of an electric field or / and a magnetic field below the glow discharge starting voltage. The method according to claim 1, 2 , 6 or 7 . The method of claim 9, wherein the reactive species is deposited on the heated substrate under the action of an electric field or / and a magnetic field below a glow discharge onset voltage. The method according to claim 9 , wherein a supply amount of hydrogen or a hydrogen-containing gas at the time of annealing is made larger than a supply amount of hydrogen or a hydrogen-containing gas at the time of vapor phase growth.   The catalyst body is formed of at least one material selected from the group consisting of tungsten, tria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, metal-attached ceramics, and silicon carbide. The method described in 1 or 2.   The method according to claim 1 or 2, wherein the purity of the catalyst body and the support body supporting the catalyst body is 99.99 wt% or more.   The polycrystalline semiconductor thin film is a polycrystalline silicon film, a polycrystalline germanium film or a polycrystalline silicon germanium film, and the hydrogen or hydrogen-containing gas is hydrogen or a mixed gas of hydrogen and an inert gas. The method according to claim 1 or 2. The method according to claim 14 , wherein the semiconductor thin film contains at least one group IV element.   The method according to claim 1 or 2, wherein a voltage equal to or lower than the glow discharge start voltage is applied as a DC voltage, an AC voltage, or a voltage obtained by superimposing an AC voltage on a DC voltage. The method according to claim 16 , wherein the frequency of the high-frequency voltage as the AC voltage is 1 to 100 MHz, and the frequency of the low-frequency voltage as the AC voltage is less than 1 MHz.   The method according to claim 1, wherein the polycrystalline semiconductor thin film forms a channel, a source and a drain region, or a wiring, a resistor, a capacitor, or an electron emitter of a thin film insulated gate field effect transistor. After the channel, source and drain regions are formed, the hydrogen-based active species generated by bringing hydrogen or a hydrogen-containing gas into contact with the heated catalyst body with respect to these regions is subjected to an electric field lower than the glow discharge start voltage or / and The method according to claim 18 , wherein the method is performed under the action of a magnetic field.   In the polycrystalline semiconductor thin film, the crystal grain size is reduced from the gate insulating film side to the outside to increase the density, or the amorphous semiconductor thin film or the fine grain size layer and the amorphous semiconductor thin film are used to form the polycrystalline semiconductor thin film. The method according to claim 1 or 2, wherein the coating is applied. 21. The method according to claim 20 , wherein the fine particle layer and the amorphous semiconductor thin film or the amorphous semiconductor thin film are removed to form source and drain electrodes in contact with the polycrystalline semiconductor thin film as a large particle layer.   Silicon semiconductor device, silicon semiconductor integrated circuit device, silicon-germanium semiconductor device, silicon-germanium semiconductor integrated circuit device, compound semiconductor device, compound semiconductor integrated circuit device, silicon carbide semiconductor device, silicon carbide semiconductor integrated circuit device, liquid crystal display device, Manufacturing thin films for organic or inorganic electroluminescence display devices, field emission display (FED) devices, light emitting polymer display devices, light emitting diode display devices, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. The method described in 1 or 2. When manufacturing a semiconductor device, a solid-state imaging device, and an electro-optical device having an internal circuit and a peripheral circuit, the polycrystalline semiconductor thin film has a channel, a source, and a drain region of a thin film insulated gate field effect transistor constituting at least a part thereof. The method according to claim 22 , formed by: The method according to claim 23 , wherein a cathode or an anode connected to a drain or a source of the thin-film insulated gate field effect transistor is provided below the organic or inorganic electroluminescent layer for each color. The cathode is also covered on the active element including the thin-film insulated gate field effect transistor, or the cathode or anode is deposited on each layer of the organic or inorganic electroluminescent layer for each color and on the entire surface of each layer. The method of claim 24 , wherein the device is manufactured. 25. The method of claim 24 , wherein a black mask layer is formed between the organic or inorganic electroluminescent layers for each color. An emitter of a field emission display device is connected to the drain of the thin-film insulated gate field effect transistor through the polycrystalline semiconductor thin film, and an n-type polycrystalline semiconductor film grown on the polycrystalline semiconductor thin film or 24. The method of claim 23 , wherein the method is formed by a polycrystalline diamond film. 28. The method according to claim 27 , wherein a metal-based shielding film having a ground potential is formed on an active element including the thin-film insulated gate field effect transistor. 29. The method according to claim 28 , wherein the metal-based shielding film is formed of the same material and in the same process as the gate extraction electrode of the field emission display device.

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