JP2002294451A - Method for forming polycrystalline semiconductor thin- film, method for manufacturing semiconductor device, and apparatus for carrying out these methods - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and an apparatus which can easily form a thin film of a semiconductor such as polycrystalline silicon having high crystallization rate and high quality, on a large area and at a low cost. SOLUTION: The method for obtaining the polycrystalline semiconductor thin-film 7 comprises forming an amorphous or a microcrystalline silicon thin- film 100A containing granular products of SiOx or/and SiNy, on a substrate 1, by a catalytic CVD method or the like; etching the amorphous constituents by reacting the silicon thin film 100A with the hydrogen active species which are generated by means of contacting hydrogen gas or hydrogen-including gas with a heated catalyzer body 46 (by bias catalytic AHA(Atomic Hydrogen Anneal) treatment); further forming a layer 100B of silicon ultra-fine particles through precipitating the ultra-fine particles of silicon out of SiOx or/and SiNy; and growing a polycrystalline semiconductor thin-film on the above seeds by the catalytic CVD method or the like (by further repeating the catalytic AHA treatment and the catalytic CVD or the like).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for vapor-phase growing a polycrystalline semiconductor thin film such as polycrystalline silicon on a substrate, and to manufacture a semiconductor device having the polycrystalline semiconductor thin film on the substrate. A method and an apparatus therefor.

[0002]

2. Description of the Related Art Conventionally, MOSFETs (Metal-Oxide-Semi
conductor Field Effect Transistor)
When the source, drain and channel regions of an OSTFT (Thin Film Transistor) are formed of a polycrystalline silicon film, plasma CVD (Chemical Vapor Deposition) or low pressure CVD is used. The law is used.

According to, for example, JP-A-6-140327 and JP-A-5-275335, SiO _x (0 <
x ≦ 2) or SiN _y (1) by a plasma CVD method using a mixed gas of a silane-based gas and a nitrogen-based gas.
0 <y <70 atomic%) of the particulate product in the amorphous silicon matrix
Amorphous silicon is etched by R hydrogen plasma treatment to form microcrystalline silicon nuclei. This particulate product has a size of 10 nm or less, and preferably 100 or less are dispersed in a 0.1 μm square region. After this, (1) disilane and silane are diluted with high hydrogen and plasma CV
A polycrystalline silicon thin film is obtained by the method D. (2) An amorphous silicon film is formed by plasma CVD of disilane and silane, and is crystallized by annealing at 500 to 600 ° C. for a long time. (3) A polycrystalline silicon film is formed by repeating the formation of an extremely thin amorphous silicon film and the hydrogen plasma treatment.

In addition, plasma CVD, low pressure CVD, etc.
The amorphous or polycrystalline silicon formed by
Kaihei 7-131030, JP-A-9-116156,
As seen in Japanese Patent Publication No. Hei 7-118443, simply high temperature
Annealing or excimer laser annealing (ELA: Exci
mer Laser Anneal) treatment to produce polycrystalline silicon
The carrier mobility of the thin film has been improved.
Then 80-120cm ^Two/ V · sec carrier transfer
Mobility was the limit. However, plasma CVD
Obtained from amorphous silicon by ELA
The electron mobility of MOSTFT using crystalline silicon is 10
0cm^Two/ V · sec, compatible with high definition
Recently, polycrystalline silicon MO integrated with drive circuit
LCD using STFT (Liquid Crystal Display = liquid)
(Japanese Patent Application Laid-Open No. 6-24243)
No. 3).

[0005]

However, none of the above methods can avoid the following disadvantages.

1) When forming a polycrystalline silicon film by using a particulate product of SiO _x or SiN _y as a seed by the plasma CVD method, it is difficult to control the size and number of the particulate product by the plasma CVD method. And RF
In the / ECR hydrogen plasma treatment, the generation of activated hydrogen ions is small and the plasma energy is small, so that the etching rate of amorphous silicon is small, the variation in the grain size of the formed polycrystalline silicon is large, and the efficiency of polycrystalline silicon formation is high. Is low. For this reason, the carrier mobility is low and the efficiency of polycrystalline silicon formation is low, so that the productivity is low. And, since SiO ₂ has a strong Si—O bond, it is difficult to atomize silicon even by plasma hydrogen treatment with low energy.

[0007] Further, when an excimer laser is used, there are many problems such as stability of output, productivity, increase in apparatus price due to increase in size, and decrease in yield / quality.
In the case of a large glass substrate of mx 1 m, the above-mentioned problems are magnified, and it becomes more difficult to improve performance / quality and reduce costs.

Further, polycrystalline silicon M by a solid phase growth method is used.
In the manufacturing method of the OSTFT, annealing for more than 10 hours at 600 ° C. or more and formation of a gate SiO ₂ for thermal oxidation at about 1000 ° C. are required, so that a semiconductor manufacturing apparatus has to be employed. For this reason, the substrate size should be wafer size 8 ~
The limit is 12 inches φ, and expensive heat-resistant and expensive quartz glass must be adopted, which makes it difficult to reduce the cost and limits its use to EVF and data / AV projectors.

Recently, a catalytic CVD method, which is an excellent thermal CVD method capable of forming a polycrystalline silicon film, a silicon nitride film and the like at a low temperature on an insulating substrate such as a glass substrate, has been developed (Japanese Patent Publication No. 63-40314). No., Tokuhei 8-250438
No.), and studies for practical use are being promoted. Catalytic CVD
In the method, 30 cm ² / V without crystallization annealing
・ Carrier mobility of about sec, but high quality M
It is still not enough to make OSTFT devices.
When a polycrystalline silicon film is formed on a glass substrate, an initial amorphous silicon transition layer (5 to 10 nm in thickness) is likely to be formed depending on the film formation conditions. Mobility is difficult to obtain. Generally, an LCD using a polycrystalline silicon MOSTFT integrated with a driving circuit is a bottom gate type MOFET.
Although STFTs are easy to manufacture in terms of yield and productivity, this problem is a bottleneck.

An object of the present invention is to provide a method capable of forming a polycrystalline semiconductor thin film such as polycrystalline silicon having a high crystallization rate and a large grain size with high quality easily and at low cost and in a large area. It is to provide an apparatus for performing the method.

It is another object of the present invention to provide a method of manufacturing a semiconductor device such as a MOSTFT having such a polycrystalline semiconductor thin film as a constituent part, and an apparatus for implementing the method.

[0012]

That is, the present invention relates to a method for forming a polycrystalline semiconductor thin film on a substrate or manufacturing a semiconductor device having the polycrystalline semiconductor thin film on the substrate. Forming a lower crystalline semiconductor thin film containing a particulate product consisting of SiO _x (0 <x ≦ 2) and / or SiN _y (0.1 <y <1.4);
Contacting hydrogen or a hydrogen-containing gas with the heated catalyst body;
The step of forming the silicon ultra-fine particles by applying the hydrogen-based active species generated thereby to the lower crystalline semiconductor thin film to anneal, and growing the semiconductor material thin film in vapor phase using the silicon ultra-fine particles as a nucleus of crystal growth. A method for forming a polycrystalline semiconductor thin film, or a method for manufacturing a semiconductor device, wherein the polycrystalline semiconductor thin film is obtained through steps.

Further, the present invention provides an apparatus for carrying out the method of the present invention, wherein SiO _x (0 <x ≦ 2) and / or SiN _y.
Means for forming a lower crystalline semiconductor thin film containing a particulate product comprising (0.1 <y <1.4), hydrogen or a hydrogen-containing gas supply means, and a semiconductor material thin film serving as the polycrystalline semiconductor thin film The present invention provides an apparatus for forming a polycrystalline semiconductor thin film or an apparatus for manufacturing a semiconductor device, comprising: a raw material gas supply unit, a catalyst body, a catalyst body heating unit, and a substrate heating unit.

According to the present invention, when a polycrystalline semiconductor thin film is formed on a substrate, SiO _x (0 <x
≦ 2) and / or a lower crystalline semiconductor thin film containing a particulate product of SiN _y (0.1 <y <1.4) is formed, and hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst. The hydrogen-based active species and the like thus generated are allowed to act on the lower crystalline semiconductor thin film to perform annealing, thereby forming silicon ultra-fine particles. The semiconductor ultra-fine particles are used as seeds for crystal growth, and the semiconductor material thin film is vapor-phased. Since it is grown, remarkable effects and effects as shown in the following (1) to (3) are obtained.

(1) Active species generated by bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst (hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions)
(Hereinafter referred to as catalyst AHA (Atomic Hydro
gen Anneal) process. ), High-temperature hydrogen-based molecules, hydrogen-based atoms, active hydrogen ions, and other hydrogen-based active species are allowed to act on the lower crystalline semiconductor thin film by spraying or the like, so that the high-temperature heating catalyst can be heated by radiant heat. In addition, it has the following significant effects:

1. In the catalyst AHA treatment, hydrogen is brought into contact with a high-temperature catalyst body (800 to 2000 ° C. having a melting point lower than the melting point, for example, 1500 to 2000 ° C. for tungsten) under reduced pressure (for example, a hydrogen-based carrier gas pressure of 10 to 50 Pa). When a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules / hydrogen-based atoms / activated hydrogen ions, etc.) are generated and sprayed onto an amorphous or microcrystalline silicon film formed on a substrate (the substrate temperature is In particular, 300-400 ° C.), compared with the conventional RF / VHF plasma hydrogen treatment or ECR plasma hydrogen treatment, a large amount of thermal energy of high-energy, high-temperature hydrogen-based active species is efficiently transferred to the film or the like. , The temperature of the film or the like is increased efficiently and uniformly. As a result, the amorphous silicon film, the microcrystalline silicon film, and the like are selectively etched away at a high etching rate by the reduction action of hydrogen-based active species at a high etching rate, and the SiO _x contained in the film is further removed.
Is changed to Si and SiO or H ₂ O, and SiN _y contained in the film is decomposed into Si and NH ₃ to form a large number of high-quality silicon ultrafine particles efficiently, which is converted into the next polycrystalline silicon. Can effectively function as a nucleus (seed) for growing silicon or the like. At this time, the silicon ultrafine particles have a particle size of 1 nm.
As described above, it is preferable that the particles are scattered at 1 to 10 nm, the number is 1 / μm ² or more, preferably 1 to 100 / μm ² . The silicon etching effect of the hydrogen-based active species in the catalytic AHA treatment occurs not only in amorphous structure silicon but also in microcrystalline, polycrystalline, and single crystal structure silicon. This is a method that makes use of sex.

2. This catalytic AHA treatment is a conventional RF /
Compared to VHF plasma hydrogen treatment or ECR plasma hydrogen treatment, amorphous silicon is etched at a higher etching rate to form a large-diameter polycrystalline silicon film, and the carrier mobility thereof can be improved. That is, the catalyst A
Using the silicon ultrafine particles obtained by the HA treatment as a seed, a semiconductor material thin film is easily grown thereon (as a polycrystalline semiconductor thin film) in a state where it is easily polycrystallized. In particular, the following catalyst AHA treatment and vapor phase growth Thus, crystallization of a silicon film or the like grown by vapor phase on the polycrystalline semiconductor thin film is promoted using the polycrystalline semiconductor thin film as a seed,
It is possible to obtain an intended high crystallization ratio and high quality polycrystalline semiconductor thin film. That is, if the amorphous silicon is present in the microcrystalline silicon film formed by, for example, biased or non-biased catalytic CVD by the catalytic AHA treatment, this is etched away by hydrogen-based active species to form silicon ultrafine particles. The silicon film to be vapor-grown thereon is more easily formed into a polycrystalline silicon film by using the underlying silicon ultrafine particles as seeds (nuclei). Further, when the same catalytic AHA treatment and vapor-phase growth are repeated, Thermal energy of a large amount of high-temperature hydrogen-based active species is transferred to the film, etc., and the temperature of the film is increased, and amorphous silicon or microcrystalline silicon thin film is polycrystallized by the reducing action of the hydrogen-based active species. In addition, the polycrystalline silicon thin film is highly crystallized, so that a polycrystalline silicon thin film having a high crystallization rate and a large grain size can be formed. As a result, not only the top gate type but also the bottom gate type and the dual gate type MOS TFT can obtain a large grain size polycrystalline silicon thin film having high carrier (electron / hole) mobility. It is possible to manufacture high-speed, high-current-density semiconductor devices, electro-optical devices, and high-efficiency solar cells using semiconductor thin films such as polycrystalline silicon.

3. The catalytic AHA treatment is more efficient than conventional plasma hydrogen treatment when silicon oxide is present on the polycrystalline silicon film formed on the substrate, in the film, or at the grain boundaries and reacts with the silicon oxide to form SiO or the like. Since the silicon oxide is well removed by evaporation, silicon oxide in the film or the like can be efficiently reduced / removed, and carrier mobility can be improved.

4. In the catalyst AHA treatment, cleaning with hydrogen-based active species such as activated hydrogen ions (reduction and removal of adsorbed gas and organic residue on a substrate or the like) is possible, and the catalyst body is also less likely to be oxidized and deteriorated (as described above). The effect is
The same applies to the above-described bias or non-bias catalytic CVD because a hydrogen-based carrier gas is used.)

[5] In the catalytic AHA treatment, for example, silicon dangling bonds in the semiconductor film are eliminated by the hydrogenation of hydrogen-based active species such as activated hydrogen ions, and the characteristics are improved.

6. During the catalytic AHA treatment, the carrier impurities present in the lower crystalline or polycrystalline semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration is obtained in each region.

(2) Since the catalyst AHA treatment can be performed without generating plasma, there is no damage by plasma, and a simpler and less expensive apparatus can be realized as compared with plasma treatment.

(3) Since the energy of the hydrogen-based active species is large even when the substrate temperature is lowered, the desired silicon ultrafine particles can be obtained stably. Even when the temperature is lowered, the polycrystalline semiconductor thin film grows efficiently using the ultrafine silicon particles as seeds, so that a large, inexpensive insulating substrate (glass substrate, heat-resistant resin substrate, etc.) with a low strain point can be used. However, cost reduction becomes possible.

In the present invention, the above-mentioned catalyst AHA
Silicon formed by processing ultrafine particles, the particle diameter 1nm or more, preferably one / [mu] m ² or more at 1 to 10 nm, preferably it is desirable that interspersed with 1-100 / [mu] m ² of area ratio. In the present invention, the above-mentioned lower crystalline semiconductor thin film is a structure having substantially only an amorphous component as defined below, for example, a structure based on an amorphous silicon thin film and a microcrystal containing an amorphous component, for example, a microcrystal. It is composed of a silicon thin film or an amorphous (amorphous) based structure containing microcrystals, for example, a microcrystalline silicon-containing amorphous silicon thin film. (In grain size, usually several tens
(0 nm or more).

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the method and the apparatus according to the present invention, the lower crystalline semiconductor thin film is grown by a vapor phase growth method (biased or non-biased catalytic CVD method, high-density plasma CVD method).
, A high-density catalytic CVD method, etc .: the same applies hereinafter). In this case, it is desirable that the temperature be lower than the melting point (for example, 16
At least a part of the raw material gas and a hydrogen-based carrier gas (hydrogen or a hydrogen-containing gas or the like) is brought into contact with the catalyst body heated to the temperature of about 00 to 1800 ° C. to cause catalytic decomposition.
It is preferable that reactive species such as radicals and ions generated thereby are deposited on the heated substrate, and the lower crystalline semiconductor thin film and / or the semiconductor material thin film are vapor-phase grown by catalytic CVD. Further, after the vapor phase growth, the supply of the raw material gas is stopped continuously, and preferably, a catalyst body heated to a temperature lower than the melting point (this is preferably the same as the catalyst body, With at least a part of the hydrogen-based carrier gas (hydrogen or hydrogen-containing gas), and a large amount of high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions It is preferable that the annealing by catalytic AHA treatment is performed by causing a hydrogen-based active species such as the above to act on the lower crystalline semiconductor thin film and / or the semiconductor material thin film.

In this case, the supply amount of hydrogen or the hydrogen-containing gas during the annealing is set to be larger than the supply amount of hydrogen or the hydrogen-containing gas during the vapor phase growth. For example, the hydrogen-based carrier gas used during vapor phase growth is hydrogen or a mixed gas of hydrogen and an inert gas (argon, helium, xenon, krypton, radon, etc., which have good thermal conductivity and contribute to the improvement of reactivity). In the case of mixed gas, the hydrogen content ratio is 50 mol%
With the above, oxidation deterioration of the catalyst body can be prevented. The hydrogen or the hydrogen-containing gas used in the catalyst AHA treatment may be the same as the hydrogen-based carrier gas used in the vapor phase growth.
(Standard cc per minute), the gas pressure is increased to 10 to 50 Pa (gas pressure in the case of bias or non-bias catalytic CVD is 0.1 to several Pa), and the increase in heat conduction by the gas and the generation amount of radical hydrogen ions etc. It is better to increase.
However, when the gas pressure increases, the mean free path of radical hydrogen ions and the like decreases, and the activation energy decreases. Therefore, it is necessary to optimize the gas pressure.

Further, after the vapor phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is continuously brought into contact with the heated catalyst to generate high-temperature hydrogen-based molecules,
Hydrogen-based atoms, activated hydrogen ions or other hydrogen-based active species such as activated hydrogen ions are applied to the semiconductor material thin film to perform annealing, and if necessary, vapor-phase growth of the same semiconductor material thin film as the semiconductor material thin film and the annealing are performed. It is desirable to repeat. To this end, it is preferable to have control means for controlling the raw material gas supply means and the hydrogen or hydrogen-containing gas supply means.

That is, the step of further vapor-phase growing a semiconductor material thin film on the polycrystalline semiconductor thin film obtained by the catalytic AHA treatment and the annealing step are repeated until the target film thickness is reached, so to speak, two steps or more. Multi-catalyst A
By the HA treatment, the semiconductor material thin film has already been converted to the catalyst AHA.
On the base film polycrystallized by the treatment, it is easy to grow in a state easily polycrystallized by using this as a seed, and a target high crystallization rate, high quality polycrystalline semiconductor film with a predetermined thickness is obtained. Obtainable. That is, a polycrystalline silicon thin film formed on a silicon ultrafine particle layer by, for example, biased or non-biased catalytic CVD is seeded by a catalytic AHA treatment by a multi-catalyst AHA treatment in which a catalytic CVD and a catalytic AHA treatment are repeated, and A polycrystalline silicon thin film is vapor-phase grown by biased or non-biased catalytic CVD, and a catalyst AHA
By performing the treatment, a polycrystalline silicon film or the like having a high crystallization rate and a large grain size can be formed.

More specifically, the thermal energy of a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.) is transferred during the catalytic AHA treatment, and the temperature of the silicon thin film is locally reduced. The silicon of amorphous structure is etched by the reducing action of the hydrogen-based active species to polycrystallize the microcrystalline silicon thin film and the like, and the polycrystalline silicon thin film is highly crystallized and has a high crystallization rate and a large grain size. A polycrystalline silicon thin film is easily formed, and a silicon thin film to be further vapor-grown thereon is further crystallized and has a larger grain size, so that carrier mobility can be further improved.

In addition, when silicon oxide is present on or in the polycrystalline silicon film, or in the film or at the grain boundaries, the hydrogen-based active species reacts with the silicon oxide to form SiO and the like, thereby evaporating and removing it. Silicon oxide on or in the silicon film can be reduced / removed, and carrier mobility can be improved.

In the case of this catalytic CVD, a wide range of n-type or p-type is selected depending on the type and temperature of the catalyst body, the substrate heating temperature, the vapor deposition conditions, the type of source gas, and the concentration of n-type or p-type impurities to be added. Since a polycrystalline silicon thin film having an impurity concentration can be easily obtained, and a polycrystalline silicon thin film having a high crystallinity and a large grain size can be formed by the catalytic AHA treatment, V _th (threshold value) can be obtained with high carrier mobility. ) Easy to adjust,
High speed operation with low resistance becomes possible.

Further, hydrogen contained in the amorphous silicon film by plasma CVD at 10 to 20% is reduced / removed by the catalytic AHA treatment to form a polycrystalline silicon film having a large particle size. A polycrystalline silicon film can be formed. Further, a polycrystalline silicon thin film having a wide range of n or p-type impurity concentration can be easily formed depending on the substrate heating temperature, the vapor deposition conditions, the type of the raw material gas, the catalyst AHA treatment conditions, and the added n or p-type impurity concentration. As a result, _Vth adjustment is easy at high mobility, and high-speed operation with low resistance is possible.

The above-mentioned vapor phase growth by the catalytic CVD is as follows.
Specifically, the catalyst body is heated to a temperature in the range of 800 to 2000 ° C. and lower than its melting point (for example, the catalyst body is heated by its own resistance heating), and the heated catalyst body is heated. The reaction species generated by subjecting at least a part of the raw material gas and the hydrogen-based carrier gas (hydrogen or a hydrogen-containing gas or the like) to a catalytic reaction or a thermal decomposition reaction as a raw material species at a temperature below the strain point of the substrate, for example, 200-8
A thin film can be deposited on a substrate heated to 00 ° C. Such a catalyst body temperature and the following catalyst body material are catalyst A
The same applies to the HA processing.

Here, if the heating temperature of the catalyst is less than 800 ° C., the catalytic reaction or thermal decomposition reaction of the raw material gas becomes insufficient and the deposition rate tends to decrease. Constituent materials are mixed into the deposited film to inhibit the electrical properties of the film, resulting in deterioration of the film quality, and heating above the melting point of the catalytic body loses its morphological stability. The heating temperature of the catalyst body is lower than the melting point of the constituent material and is preferably 1100 ° C to 1800 ° C.

The catalyst body is formed of at least one material selected from the group consisting of tungsten, thoria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics having metal attached thereto, and silicon carbide. Can be.

Then, the purity of the catalyst and the support supporting the catalyst is 99.99 wt% (4 N) or more, preferably 99.999 wt% (5 N) or more, whereby the polycrystal formed is formed. Heavy metal contamination of the conductive semiconductor thin film can be reduced.

The substrate temperature is preferably lower than the strain point of the substrate, for example, 200 to 800 ° C., and more preferably 300 to 400 ° C., so that efficient and high quality film formation can be performed. When the substrate temperature is high, inexpensive borosilicate glass and aluminosilicate glass cannot be used, and the doping concentration distribution of impurities tends to change due to the influence of heat.

When a polycrystalline silicon film is formed by a normal thermal CVD method, the substrate temperature needs to be about 600 to 900 ° C. However, in the film formation according to the present invention, plasma or optical excitation is required. Instead, thermal CVD at low temperature as described above
It is very advantageous that this is possible. Since the substrate temperature during the catalytic CVD according to the present invention is low as described above, the strain point of the substrate, for example, a glass substrate is 470 to 670 ° C.
Glass such as borosilicate glass or aluminosilicate glass, or a heat-resistant resin substrate can be used. This is inexpensive, easy to make thin, and large (1m × 1m
Above) is possible, and a long rolled glass plate can be produced. For example, a thin film can be continuously or discontinuously formed on a long rolled glass plate by using the above method.

In the present invention, the source gas used for forming the lower crystalline semiconductor thin film by vapor phase growth by bias or non-bias catalytic CVD is silicon hydride or a derivative thereof,
A mixture of silicon hydride or a derivative thereof and hydrogen, a gas containing germanium, carbon or tin, a mixture of silicon hydride or a derivative thereof and a gas containing an impurity consisting of an element of Group III or Group V of the periodic table, Examples include a mixture of silicon hydride or a derivative thereof, a gas containing hydrogen, germanium, carbon, or tin, and a gas containing an impurity consisting of a Group III or Group V element in the periodic table.

By using the raw material gas as described above, amorphous silicon, microcrystalline silicon-containing amorphous silicon film, microcrystalline silicon (amorphous silicon-containing microcrystalline silicon) film, amorphous silicon and microcrystalline silicon-containing polycrystalline silicon film, microcrystalline germanium-containing amorphous germanium film, an amorphous germanium, microcrystalline germanium (amorphous germanium containing microcrystalline germanium) film, an amorphous germanium and microcrystalline germanium containing polycrystalline germanium film, or _{Si x Ge 1-x (0} <x <1) The lower crystalline semiconductor thin film made of the amorphous silicon germanium film represented by the formula (1) can be formed. This lower crystalline semiconductor is based on an amorphous material, and when it contains fine crystals, fine crystals having a particle size of 10 nm or less are preferably scattered. Further, as the polycrystalline semiconductor thin film, a polycrystalline silicon film, a polycrystalline germanium film, a polycrystalline silicon-germanium film, or a polycrystalline silicon carbide film can be formed.

At the time of or after the growth of the lower crystalline semiconductor thin film, a proper amount (10 ¹⁵ atoms / cc) of at least one of Group IV elements such as tin, germanium and lead is added.
As described above, for example, when 10 ¹⁸ to 10 ²⁰ atoms / cc is contained (further, in this state, the annealing step by the catalytic AHA treatment is performed), irregularities existing at the crystal grain boundaries of the polycrystalline semiconductor thin film are reduced, and the film is removed. Stress can be reduced to easily obtain a high carrier mobility and high quality polycrystalline semiconductor. The group IV element can be mixed as a gas component in the source gas, or can be contained in the semiconductor material thin film by ion implantation or ion doping. The oxygen, nitrogen, and carbon concentrations in the polycrystalline silicon thin film formed according to the present invention were 1 × 10 ¹⁹ atoms / s.
cc or less, preferably 5 × 10 ¹⁸ atoms / cc or less, and the hydrogen concentration is preferably 0.01 atomic% or more.
The sodium (Na) concentration is preferably 1 × 10 ¹⁸ atoms / cc or less in the SIMS minimum concentration region.

Prior to the catalytic CVD (or the bias catalytic CVD), it is desirable that the catalyst be heated (burned) in a hydrogen-based gas atmosphere. This is because, when the heat treatment of the catalyst body is insufficient, the constituent material of the catalyst body is released and may be mixed into the formed film,
Such incorporation can be eliminated by baking and heating the catalyst body before film formation in a hydrogen-based gas atmosphere.
Therefore, in a state where the film-forming chamber is filled with a hydrogen-based gas, the temperature of the catalyst body is higher than that at the time of film-forming (for example, 22% for tungsten).
(200 to 2500 ° C.) after baking for a predetermined time,
Temperature during normal film formation (for example, 1700 for tungsten)
° C), and then a source gas (a so-called reaction gas) is preferably supplied using a hydrogen-based gas as a carrier gas. Note that, depending on the purity and the material of the catalyst, this baking treatment is performed only at the beginning, and does not necessarily need to be performed for each film formation.

The catalytic AHA treatment has the effect of selectively etching particularly the amorphous component in the lower crystalline semiconductor thin film by the high-temperature hydrogen-based active species, and has a high crystallization rate and a large grain size (particularly, a grain size is small). Several hundred nm or more)
Is a process for forming a thin film based on polycrystals and activating carrier impurities in the film. At this time, the catalyst temperature is 1600 to 2000 ° C., and the distance between the substrate and the catalyst is 20 to 50 mm, biased or non-biased catalyst C
Any change may be made to improve the processing effect, such as shortening the processing time by increasing the flow rate of the hydrogen-based carrier gas (increasing the gas pressure) from VD to increase the rate of the hydrogen-based active species, etc. Good.

With the polycrystalline semiconductor thin film obtained by the process of the present invention, a channel, a source and a drain region, a wiring, a resistor, a capacitor, an electron emitter and the like of a MOSTFT can be formed. In this case, after the channel, source and drain regions are formed, if these regions are subjected to the catalytic AHA treatment, the ion activation of the n-type or p-type impurities can be performed.

In order to reduce the invasion of oxygen from the outside into the polycrystalline semiconductor thin film such as polycrystalline silicon, for example, a crystal is formed from the gate insulating film side to the outside in the polycrystalline silicon thin film or the like. It is preferable to increase the density by reducing the particle size, or to cover the polycrystalline silicon thin film with an amorphous silicon film or a microcrystal-containing amorphous silicon film. In this case, the microcrystalline silicon or amorphous silicon thin film can be removed by general-purpose photolithography and etching techniques to form source and drain electrodes in contact with the polycrystalline silicon thin film.

The present invention relates to a silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated device. Circuit device, liquid crystal display device, organic or inorganic electroluminescence (EL) display device, field emission display (FE)
D) It is suitable for forming thin films for devices, light-emitting polymer displays, light-emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, and solar cell devices.

In this case, when manufacturing a semiconductor device having an internal circuit and a peripheral circuit, a solid-state image pickup device, an electro-optical device, etc., the channel, source and drain regions of the MOSTFT constituting at least a part of these devices are replaced with the polycrystalline semiconductor. It may be formed of a thin film, or may be a structure integrated with peripheral circuits such as a driving circuit, a video signal processing circuit, and a memory circuit.

Further, under the organic or inorganic electroluminescent layer (EL layer) for each color,
An EL element structure having a cathode or an anode connected to the drain or the source of the TFT is preferable.

In this case, if the cathode covers the active elements such as the MOSTFT and the diode, the light emitting area is increased in the structure having the anode on the upper side, and the emitted light is blocked by the light shielding action of the cathode. To generate a leak current. Further, if the cathode or the anode is attached to each of the organic or inorganic EL layers for the respective colors and the entire surface between the respective layers, the organic EL which is vulnerable to moisture is covered by the entire surface with the cathode or the anode. Long life, high quality, and high reliability can be prevented by preventing layer deterioration and electrode oxidation. Also, when covered with the cathode, the heat dissipation effect is enhanced, so the structural change of the thin film due to heat generation (melting or recrystallization) , And a long life, high quality, and high reliability can be achieved. Further, since a high-precision, high-quality, full-color organic EL layer can be formed with high productivity, the cost can be reduced.

The organic or inorganic EL for each of the colors
When a black mask layer of chromium, chromium dioxide, or the like is formed between layers, light leakage between colors or between pixels is prevented, and contrast is improved.

When the present invention is applied to a field emission display (FED) device, its emitter (field emission cathode) is connected to the drain of the MOSTFT via the polycrystalline semiconductor thin film and Numerous fine projection structures (eg, carbon) formed on the surface of an n-type polycrystalline semiconductor film, a polycrystalline diamond film, a nitrogen-containing or non-containing carbon thin film, or a nitrogen-containing or non-containing carbon thin film grown on the thin film. Nanotubes) or the like.

In this case, a metal shielding film having a ground potential is formed on the active element such as the MOSTFT or the diode by using the same material and the same process as the gate lead-out electrode of the FED device. In this case, the gas in the hermetic container is positively ionized by the electrons emitted from the emitter and charged up on the insulating layer, and this positive charge is unnecessary for the active element below the insulating layer to invert the inversion. A runaway of an emitter current caused by forming a layer or an excess current flowing through the inversion layer can be prevented. Also, when the phosphor emits light due to the collision of electrons emitted from the emitter, this light causes TF
It is also possible to prevent generation of electrons and holes in the T gate channel to cause a leak current.

Next, the present invention will be described in more detail with reference to preferred embodiments.

First Embodiment A first embodiment of the present invention will be described with reference to FIGS.

In this embodiment, a top gate type polycrystalline silicon CMOS (Complementary MOS) T
This is applied to FT.

<Catalytic CVD Method and Apparatus> First, the catalytic CVD method and the catalytic AHA treatment used in the present embodiment will be described. In the catalytic CVD method, a reactive gas composed of a hydrogen-based carrier gas and a raw material gas such as silane gas is brought into contact with a heated catalyst such as tungsten, and the radical deposition species or its precursor generated thereby and activated hydrogen ions are generated. Giving high energy to hydrogen-based active species such as
A low-crystalline semiconductor thin film such as amorphous or microcrystalline silicon or a polycrystalline semiconductor thin film such as a polycrystalline silicon thin film is vapor-phase grown on a substrate. Then, after the film formation, the supply of the raw material gas is stopped, and only the hydrogen-based carrier gas is supplied to perform, for example, the catalytic AHA treatment of the lower crystalline silicon thin film or the polycrystalline silicon thin film (that is,
Silicon or the like having an amorphous structure is selectively reduced and etched by hydrogen-based active species such as high-temperature hydrogen-based molecules, hydrogen-based atoms, and activated hydrogen ions) to form silicon ultrafine particles, or to seed these silicon ultrafine particles ( As a core, polycrystalline silicon or the like is grown to a large grain size. By repeating the catalytic AHA treatment and the bias or non-bias catalytic CVD, a polycrystalline semiconductor thin film such as a polycrystalline silicon thin film having a higher crystallization rate, a larger grain size and a predetermined thickness is obtained.
In the present specification, the above-mentioned “bias” refers to a DC and / or AC electric field under conditions where plasma discharge does not occur,
And / or and / or applying a biased kinetic energy by a magnetic field.

The biased or non-biased catalytic CVD and the catalytic AHA treatment are carried out using an apparatus as shown in FIGS.

According to this apparatus, a hydrogen-based carrier gas, a raw material gas such as silicon hydride (for example, monosilane, disilane, trisilane), N ₂ O, NO ₂ , NO or N ₂ , and ammonia (B ₂ A reaction gas 40 comprising a doping gas such as H ₆ or PH ₃ ) is supplied to the supply conduit 4.
1 is introduced into the film forming chamber 44 through a supply port (not shown) of the shower head 42. Inside the film forming chamber 44, a susceptor 45 for supporting the substrate 1 such as glass, and a shower head 42 having good heat resistance (preferably made of a material having a melting point equal to or higher than that of the catalyst body 46) are provided. For example, a coiled catalyst body 46 such as tungsten and a shutter 47 that can be opened and closed are provided. Although not shown, a magnetic seal is provided between the susceptor 45 and the film forming chamber 44, and the film forming chamber 44 follows the front chamber for performing the pre-process, and is provided via a valve by a turbo molecular pump or the like. Exhausted.

Then, the substrate 1 is heated by a heating means such as a heater wire in the susceptor 45, and the catalyst body 46 is, for example, a resistance wire having a melting point or less (especially 800 to 2000 ° C., and about 1600 to 1800 ° C. for tungsten). Is activated by heating. Both terminals of the catalyst body 46 are connected to a DC or AC catalyst power supply 48, and are heated to a predetermined temperature by energization from the power supply.

In order to carry out the catalytic CVD method, the degree of vacuum in the film forming chamber 44 is set to 1.33 × 10 ^{−4 to} 1.3 in the state shown in FIG.
3 × 10 ⁻⁶ Pa, for example, a hydrogen-based carrier gas of 50 to
After constantly supplying 100 SCCM and heating the catalyst to a predetermined temperature to activate the catalyst, 1 to 10 SCCM of silicon hydride (for example, monosilane) gas (and B ₂ H if necessary)
₆ and also includes an appropriate amount doping gas such as PH _3. ), H ₂ O
Alternatively, a reaction gas 40 composed of 0.1 to 0.2 SCCM of He diluted O ₂ , a nitrogen-based gas such as nitrogen or ammonia, and a nitrogen oxide gas of 1 to 10 SCCM such as N ₂ O, NO ₂ , NO is supplied from a supply conduit 41. Supply port 4 of shower head 42
3 and gas pressure of 0.133-13.3P
a, for example, 1.33 Pa. Here, the hydrogen-based carrier gas is hydrogen, hydrogen + argon, hydrogen + helium, hydrogen + neon, hydrogen + xenon, hydrogen + krypton, etc.
Any gas may be used as long as an appropriate amount of hydrogen is mixed with an inert gas (the same applies hereinafter). Note that the hydrogen-based carrier gas is not necessarily required depending on the type of the raw material gas or the material of the catalyst.

Then, as shown in FIG. 6, the shutter 47 is opened, and at least a part of the hydrogen-based carrier gas and the reaction gas 40 is brought into contact with the catalyst 46 to be catalytically decomposed. A group of reactive species such as ions and radicals such as silicon and ions having high energy (that is, deposited species or a precursor thereof and radical hydrogen ions) is formed. The reactive species 50, such as ions and radicals, generated in this manner are subjected to SiO _x (0 <x) on the substrate 1 held at a high energy and a temperature below the strain point of the substrate, for example, 200 to 800 ° C. (eg, 300 to 400 ° C.). ≦ 2) and / or vapor phase growth of a predetermined film of amorphous silicon, microcrystalline silicon, or the like containing a particulate product of SiN _y (0.1 <y <1.4).

Thus, without generating plasma,
Since the catalytic action of the catalyst body 46 and the energy by the thermal energy are given to the reactive species, the reactive gas can be efficiently converted to the reactive species and uniformly deposited on the substrate 1 by thermal CVD.

Further, since the energy of the deposited species is large even when the substrate temperature is lowered, a desired high-quality film can be obtained. Therefore, the substrate temperature can be further lowered as described above, and a large and inexpensive insulating substrate ( Glass substrates such as borosilicate glass and aluminosilicate glass, and heat-resistant resin substrates such as polyimide)
Can be used, and the cost can be reduced in this respect as well.

Further, needless to say, since there is no generation of plasma, there is no damage by the plasma, a low stress generated film can be obtained, and a much simpler and less expensive device can be realized as compared with the plasma CVD method. I do.

In this case, under reduced pressure (for example, 0.133
The operation can be performed at 1.33 Pa) or normal pressure, but a simpler and cheaper device is realized with the normal pressure type than with the reduced pressure type. And even the normal pressure type, the conventional normal pressure CVD
A high quality film having better density, uniformity and adhesion can be obtained. Also in this case, the normal pressure type has higher throughput, higher productivity, and cost reduction than the reduced pressure type.

The above-described biased or non-biased catalytic CVD
In the above, the substrate temperature rises due to the secondary heat generated by the catalyst body 46. However, as described above, the substrate heating heater 51 may be provided as necessary. Further, the catalyst body 46 has a coil shape (a mesh, a wire, or a perforated plate may be used in addition to the above shape). Is good. Note that, in this CVD, the substrate 1 is
Is disposed above the shower head 42 on the lower surface of the substrate 1, so that particles generated in the film forming chamber 44 do not fall and adhere to the substrate 1 or the film thereon.

<Catalyst AHA Treatment and its Apparatus> In the present embodiment, the above apparatus is used as it is, and after the vapor phase growth by catalytic CVD, the supply of the source gas such as monosilane is stopped. only hydrogen-based carrier gas is supplied into the film forming chamber 44 in many flow, SiO _x
Or / and subjected to catalytic AHA treatment against the microcrystalline silicon thin film or the like of the SiN _y particulate product containing, for etching to polycrystalline silicon of the amorphous structure by selective reduction action of the hydrogen-based active species Is annealed,
The catalyst CVD and the catalyst AHA treatment are repeated a predetermined number of times to form a polycrystalline semiconductor thin film such as a polycrystalline silicon thin film having a desired film thickness.

In the catalytic AHA treatment, the amorphous silicon is selectively etched by a large amount of high-temperature hydrogen-based active species generated by catalytic decomposition of a hydrogen-based carrier gas by a heated catalyst, and the like. In addition to generating fine particles, in the case of a semiconductor material thin film, it is easy to polycrystallize using silicon ultrafine particles as a seed, and has a high crystallization rate and a large grain size (particularly, a grain size of several hundred nm or more).
This is a process for facilitating the formation of a polycrystalline-based thin film and activating carrier impurities in the film.
The catalyst temperature is 1600 to 1800 ° C., the distance between the substrate and the catalyst is 20 to 50 mm, the substrate temperature is 300 to 400 ° C., and the hydrogen-based carrier gas is hydrogen or hydrogen and an inert gas (argon, helium, Xenon, krypton, radon, etc.), and in the case of a mixed gas, the oxidative deterioration of the catalyst can be prevented by setting the hydrogen content to 50 mol% or more. Further, the hydrogen or the hydrogen-containing gas used at the time of the catalyst AHA treatment may be the same as the hydrogen-based carrier gas at the time of the vapor phase growth.
1000 SCCM, gas pressure as large as 10 to 50 Pa (0.1 to 0.1 in case of bias or non-bias catalytic CVD)
Several Pa), it is preferable to increase the heat conduction by the gas and increase the generation amount of hydrogen-based active species and the like.

FIG. 7 shows the introduction time and timing of the hydrogen-based carrier gas and the source gas in the above-mentioned catalytic CVD and catalytic AHA treatment in the case of forming a polycrystalline silicon thin film. FIG. 8 shows a flow meter (MFC). ) And a gas introduction system incorporating a regulating valve.

First, before film formation, the substrate 1 is carried into a chamber (film formation chamber) 44 through a gate valve, and is placed on a susceptor 45. Then, the inside of the chamber 44 is activated by operating an exhaust system. Exhaust to the pressure and
The substrate 1 is heated to a predetermined temperature by operating a heater incorporated in the substrate 5.

Then, depending on the gas introduction system, first, a hydrogen-based carrier gas of 300 to 1000 SCCM, for example, 500
The SCCM is introduced into the chamber 1. A part of the introduced hydrogen gas becomes a hydrogen-based active species such as activated hydrogen ions by a catalytic decomposition reaction by the heating catalyst 46, reaches the substrate surface, and cleans the surface of the substrate 1. Thereafter, the hydrogen-based carrier gas is set to 150 SCCM.

As described above, while the hydrogen-based carrier gas is being supplied into the chamber 44, the gas introduction system is operated, and the source gas (monosilane 15 SCCM), H ₂ O or He-diluted O ₂ 0.1 to 0 is used. .2SCCM, N ₂ O or the like 10
The SCCM is introduced into the chamber 44. Deposited species are generated from the introduced source gas and the like by a thermal catalytic reaction and a thermal decomposition reaction of the heating catalyst body 46, and SiO _x (0 <x ≦ 2) and / or SiN _y (0.1 <y <1. 4) Vapor-phase growth on the substrate surface as a low-crystalline silicon thin film containing a particulate product comprising 4).

Thereafter, the introduction of the source gas or the like is stopped, the source gas or the like is discharged from the chamber 44, and only the hydrogen-based carrier gas is supplied at 300 to 1000 SCCM, for example, 50 SCCM.
Introduce at a flow rate of 0 SCCM. As a result, hydrogen-based active species such as activated hydrogen ions generated by the catalytic cracking reaction by the heated catalyst act on the lower crystalline silicon thin film and the like (catalyst AHA treatment) to convert the amorphous silicon into silicon. Selectively etching to form silicon ultrafine particles from which amorphous components have been removed, and further, SiO _x contained in this film is decomposed into Si, SiO, H ₂ O, etc.
Further, SiN _y is decomposed into Si and NH ₃ to form ultrafine silicon particles, which are used as seeds, and crystallization is further promoted by the above-mentioned catalytic CVD, so that a high crystallization rate and a large crystallinity are obtained. Obtain a silicon thin film.

The polycrystalline silicon thin film thus obtained is further subjected to a catalyst AHA treatment, and the above-mentioned catalytic CVD is performed thereon again, and a polycrystalline silicon thin film is grown thereon using the polycrystalline silicon thin film as a seed. Further catalytic AHA treatment,
By repeatedly performing the catalytic CVD, it is possible to control the thickness of the polycrystalline silicon thin film and finally form a polycrystalline silicon thin film having a high crystallization rate and a large grain size with a desired thickness. it can.

As described above, due to the radical action of the hydrogen-based active species, the thermal energy moves to the film to locally raise the temperature, and the lower crystalline silicon thin film is formed by selectively etching amorphous structure silicon. The formation of a thin film of polycrystalline silicon having a large grain size can be achieved, and a high-crystallinity silicon film having high carrier mobility and high quality can be obtained. When a substance is present, it undergoes a reduction reaction with
Since O and the like are generated and evaporated and removed, silicon oxide on or in the film can be reduced / removed, and a high-carrier mobility, high-quality polycrystalline silicon film or the like can be obtained.

The amorphous silicon-containing amorphous silicon or the amorphous silicon-containing microcrystalline silicon thin film is polycrystallized by using the underlying silicon ultrafine particles as a seed. A polycrystalline silicon film having a large grain size at a conversion rate is formed.
Moreover, since the amorphous silicon contained in the film is etched by the action of the hydrogen-based active species, a polycrystalline silicon thin film having a high crystallization rate and a large grain size is formed.

At the time of the catalytic AHA treatment, the carrier impurities present in the semiconductor thin film are activated at a high temperature,
An optimum carrier impurity concentration can be obtained in each region, and a large amount of high-temperature hydrogen-based active species (hydrogen molecules, hydrogen atoms and activated hydrogen ions) are used for cleaning (adsorbed gas and organic residue on a substrate or the like). Can be reduced), and the catalyst body is also oxidized and deteriorated, and it becomes difficult. Further, by hydrogenation, for example, silicon dangling bonds in the semiconductor film are eliminated, and the characteristics are improved.

By repeating the annealing by the catalytic AHA treatment and the vapor phase growth of the semiconductor thin film by the catalytic CVD until the target film thickness is obtained, the semiconductor thin film is formed on the base film already polycrystallized by the catalytic AHA treatment. It is easy to grow in a state where polycrystallization is easily performed, and a desired high crystallinity and high quality polycrystalline semiconductor thin film can be obtained with a predetermined thickness. That is, for example, a multi-catalyst AHA process in which a catalyst CVD and a catalyst AHA process are repeated to form, for example, amorphous silicon containing amorphous silicon or a thin film of amorphous silicon and polycrystalline silicon containing microcrystal silicon formed by the catalyst CVD in a polycrystalline manner by the catalyst AHA process. Since the polycrystalline silicon thin film is made into a crystalline silicon thin film and the polycrystalline silicon thin film is made to have a high crystallization rate, and the vapor phase growth of the polycrystalline silicon thin film is further performed by catalytic CVD using the polycrystalline silicon thin film as a seed, and further, the catalytic AHA treatment is repeated, A polycrystalline silicon thin film having a crystallization ratio and a large grain size can be formed.

Since both the above-mentioned catalytic CVD and catalytic AHA treatment can be performed without generation of plasma, a plasma-damaged film without damage by plasma can be obtained, and is simpler than the plasma CVD method. An inexpensive device can be realized.

FIG. 9 shows Raman spectra of a polycrystalline silicon thin film obtained by the above-described multi-catalyst AHA treatment (repetition of catalytic CVD and catalytic AHA treatment) according to the present embodiment according to the number of repetitions and the like. It is. According to this result, deposition of silicon by catalytic CVD (de
The gas flow rate at the time of po) is SiH ₄ : H ₂ = 5: 500 SCC
M, catalyst temperature = 1800-2000 ° C., substrate temperature = 40
When the temperature was set to 0 ° C., the conditions of the catalyst AHA treatment were various, and the number of repetitions was changed, the number of repetitions was increased, the treatment time was lengthened, and the hydrogen flow rate during the treatment was increased.
In the order of samples # 1 → # 2 → # 3 → # 4, amorphous (amorphous) silicon and microcrystalline silicon decrease, and polycrystalline silicon increases (ie, increase in grain size and high crystallization). ) Is obvious. Here, AHA1 is a cleaning process of the substrate surface before film formation, and the original catalyst A
HA processing is AHA2-4.

FIG. 10 shows the crystallization ratio of each sample in comparison with the presence or absence of polycrystal in the polycrystalline silicon thin film. According to this, it is understood that the crystallization ratio increases in the order of samples # 1 → # 2 → # 3 → # 4, and that the ratio including microcrystals (Im) increases.

These results show that the treatment according to the present invention is a very excellent method for forming a polycrystalline semiconductor thin film having a high crystallization rate and a large grain size.

In the present embodiment, in the above-mentioned catalytic CVD, the purity of the catalyst of 0.4 mmφ tungsten wire and the support of 0.8 mmφ molybdenum wire (not shown) supporting the same is obtained. Although there is a problem, the conventional purity: 3N (99.9 wt%) is changed to 4N.
(99.99 wt%) or more, preferably 5N (99.9 wt%).
99 wt%) or higher,
It has been demonstrated that heavy metal contamination such as iron, nickel and chromium in a polycrystalline silicon thin film by catalytic CVD can be reduced. FIG. 11 (A) shows the concentration of heavy metals such as iron, nickel and chromium in the film at a purity of 3N. By increasing this to 5N, heavy metals such as iron, nickel and chromium as shown in FIG. It has been found that the concentration can be significantly reduced. Thereby, the TFT characteristics can be improved.

<Manufacture of Top Gate Type CMOS TFT>
Next, the top gate type CMOSTF according to the present embodiment
The production example of T is shown.

First, plasma CVD, biased or non-biased catalytic CVD is performed on at least a TFT forming region of an insulating substrate 1 such as quartz glass, crystallized glass, borosilicate glass, or aluminosilicate glass shown in FIG. Then, an underlying protective film (not shown) composed of a laminated film of a protective silicon nitride film and a silicon oxide film is formed under the following conditions by a vapor phase growth method such as low pressure CVD (the same applies hereinafter).

In this case, a glass material is properly used depending on the process temperature of TFT formation. In the case of a low temperature of 200 to 500 ° C .: A glass substrate (500 × 600 × 0.5 to 1.1 μm thick) such as borosilicate or aluminosilicate glass, or a heat-resistant resin substrate may be used. High temperature of 600 to 1000 ° C .: A heat-resistant glass substrate (6 to 12 inches φ, 700 to 800 μm thick) such as quartz glass or crystallized glass may be used. The silicon nitride film for the protective film is formed to stop Na ions from the glass substrate, but is not required when using synthetic quartz glass.

Also, biased or non-biased catalytic CVD
In the case of using the catalyst, the same device as that shown in FIGS. 5 and 6 can be used. However, in order to prevent the catalyst from being oxidized and deteriorated, a hydrogen-based carrier gas is supplied to bring the catalyst into a predetermined temperature (about 160
After the film formation, the catalyst body needs to be cooled to a temperature at which there is no problem to cut off the hydrogen-based carrier gas.

The film forming conditions are as follows: a hydrogen-based carrier gas (hydrogen, argon + hydrogen, helium + hydrogen,
Neon + hydrogen, etc.) is constantly flowed, and the flow rate, pressure, and susceptor temperature are controlled to the following predetermined values. Chamber pressure: about 1 to 15 Pa, for example, 10 Pa Susceptor temperature: 300 to 400 ° C. Hydrogen carrier gas flow rate (in the case of mixed gas, hydrogen is 70
-90 mol%): 50-150 SCCM

The silicon nitride film has a thickness of 50
It is formed to a thickness of 200 nm. Hydrogen (H ₂ ) is used as a carrier gas, and monosilane (SiH ₄ ) is mixed with ammonia (NH ₃ ) at an appropriate ratio as a source gas. H ₂ flow rate: 50 to 150 SCCM, SiH ₄ flow rate: 1 to 20 SCCM, NH ₃ flow rate: 5 to 60 SCCM

The silicon oxide film has a thickness of 50
It is formed to a thickness of about 100 nm. Hydrogen (H ₂ ) is used as a carrier gas and a raw material gas, and monosilane (SiH ₄ ) is used for He.
Formed by mixing diluted O ₂ in appropriate ratio. H ₂ flow rate: 50 to 150 SCCM, SiH ₄ flow rate: 1 to 20 SCCM, He diluted O ₂ flow rate: 1 to ₂ SCCM

Next, as shown in FIG. 1 (1), SiO _x (0 <x ≦ 2) and / or SiN was formed on the protective film by the catalytic CVD method or the like based on the present invention under the following conditions.
_y (0.1 <y <1.4) Lower crystalline silicon (eg, amorphous silicon) 1 containing a particulate product
00A is formed to a thickness of 5 to 10 nm.

The amorphous silicon film containing SiO _x (0 <x ≦ 2) is formed to a thickness of 5 to 10 nm. Hydrogen (H ₂ ) is used as a carrier gas and a source gas, and monosilane (Si) is used.
H ₄ ), H ₂ O or He diluted O ₂ is formed by mixing an appropriate ratio. Flow rate of H _2; 50~100SCCM, SiH ₄ flow rate; 1~20SCCM, H ₂ O or He diluted O ₂ flow rate; 0.1～0.2SCCM

The amorphous silicon film containing SiN _y (0.1 <y <1.4) is formed to a thickness of 5 to 10 nm. Hydrogen (H ₂ ) is used as a carrier gas and a raw material gas is formed by mixing monosilane (SiH ₄ ) with N ₂ or ammonia in an appropriate ratio. Flow rate of H _2; 50~100SCCM, SiH ₄ flow rate; 1~10SCCM, N ₂ or ammonia flow rate; 1～10SCCM

SiO _x (0 <x ≦ 2) and SiN _y (0.
1 <y <1.4) Mixed amorphous silicon film
It is formed to a thickness of 10 nm. It is formed by mixing monosilane (SiH ₄ ) with N ₂ O or NO ₂ at an appropriate ratio as hydrogen (H ₂ ) as a carrier gas and a source gas. Flow rate of H _2; 50~100SCCM, SiH ₄ flow rate; 1~10SCCM, N ₂ O or NO ₂ or NO flow rate; 1～10SCCM

Next, as shown in FIG. 1B, the silicon having an amorphous structure is selectively etched from the above-described amorphous silicon film 100A containing SiO _x and / or SiN _y by a continuous catalytic AHA treatment. Further, by decomposing SiO _x contained in the film into Si, SiO and H ₂ O, and / or decomposing SiN _y into Si, NH _{3 and the} like, silicon ultrafine particles are deposited and formed. An ultrafine particle layer 100B is formed.

This catalytic AHA treatment is a treatment method in which a raw material gas is not supplied in the catalytic CVD method. Specifically, a hydrogen-based carrier gas is supplied under reduced pressure to bring the catalyst to a predetermined temperature (about 1600). １1800 ° C., for example, about 17
(Set to 00 ° C), for example, 300 to 1000 SCC
A hydrogen-based carrier gas of M is supplied to a gas pressure of 10 to 50 Pa to generate a large amount of high-temperature hydrogen-based active species (eg, activated hydrogen ions), and these are formed on a substrate, for example, SiO _x ( 0 <x ≦ 2) and / or SiN _y (0.1
It is sprayed on the amorphous or microcrystalline silicon film 100A containing the particulate product of <y <1.4). As a result, the high thermal energy of a large amount of high-temperature hydrogen-based active species (eg, activated hydrogen ions) is transferred to those films, and the film temperatures are locally increased, and the amorphous or microcrystalline silicon film 100A The existing amorphous silicon is selectively etched, and the S contained in the film is further removed.
By decomposing io _x into Si and SiO and H ₂ O and / or decomposing SiN _y into Si and NH _{3 and the} like, silicon ultra-fine particles are deposited and formed, and used as a nucleus for polycrystalline silicon growth. .

Then, as shown in FIG. 1C, for example, a group IV element of the periodic table, for example, tin, for example, is subjected to a catalytic CVD method (or a multi-catalyst AHA treatment) at 10 ¹⁵ atom.
ms / cc or more, preferably 10 ¹⁸ to 10 ²⁰ atoms
/ Cc doped (this may be doped by CVD or ion implantation after film formation).
Vapor phase growth is performed to a thickness of 0 nm, for example, 50 nm. However,
This tin doping is not always necessary (the same applies hereinafter).

At this time, if necessary, n is added to the monosilane.
-Type impurities (phosphorus, arsenic, antimony) or p-type impurities (boron, etc.) are added in an appropriate amount, for example, 10 ¹⁵ to 10 ¹⁸ atoms.
/ Cc to form an n-type or p-type polycrystalline silicon thin film. Also, silicon ultra fine particles 100B
After growing a microcrystalline silicon or polycrystalline silicon thin film to a thickness of 10 to 30 nm by bias or non-bias catalytic CVD, a catalytic AHA treatment is performed thereon, and then polycrystalline silicon by bias or non-bias catalytic CVD. Is grown to a thickness of 10 to 30 nm, further treated with a catalyst AHA, and further grown on the amorphous or microcrystalline silicon or polycrystalline silicon thin film by a biased or non-biased catalytic CVD to a thickness of 10 to 30 nm. May be processed. According to this method, a polycrystalline silicon thin film having a higher crystallization ratio and a larger thickness and a larger thickness can be formed.

In this case, for example, tin-doped polycrystalline silicon is vapor-phase grown under the following conditions by the above-described biased or non-biased catalytic CVD using the apparatus shown in FIGS. The catalyst AHA treatment is performed and annealed to make the polycrystalline silicon thin film more polycrystalline, and these biased or non-biased catalytic CVD and the catalyst AHA treatment are repeated to form a polycrystalline silicon thin film 7 having a thickness of 50 nm. Good. For example, a film having a thickness of 10 to 30 nm is grown by biased or non-biased catalytic CVD, and a film having a thickness of 10 to 30 nm is grown by biased or non-biased catalytic CVD after the catalytic AHA treatment. 10 to 30 by bias catalytic CVD
A film having a thickness of nm is grown to finally obtain a polycrystalline silicon film having a desired film thickness.

Film formation of tin-containing polycrystalline silicon by catalytic CVD: formed by mixing hydrogen (H ₂ ) as a carrier gas and monosilane (SiH ₄ ), tin hydride (SnH ₄ ) and the like in an appropriate ratio as a raw material gas. . H ₂ flow rate: 50~150SCC
M, SiH ₄ flow rate: 1 to 20 SCCM, SnH ₄ flow rate: 1
~ 20 SCCM. At this time, by mixing an appropriate amount of n-type phosphorus, arsenic, antimony, or the like, or a suitable amount of p-type boron, etc., into a silane-based gas (silane, disilane, trisilane, or the like) as a raw material gas, Alternatively, a tin-containing polycrystalline silicon thin film having a p-type impurity carrier concentration may be formed. In the case of n-type conversion: phosphine (PH ₃ ), arsine (As)
H _3), stibine (SbH ₃₎ for p-type: diborane (B ₂ H ₆₎

Catalytic AHA treatment: Catalytic AHA treatment is a method in which a raw material gas is not supplied in catalytic CVD. Specifically, a hydrogen-based carrier gas is supplied at a gas flow rate of 30 under reduced pressure.
The catalyst is heated at a predetermined temperature (about 1600 to 1800 ° C., for example, about 1700 ° C.) by supplying the catalyst at 0 to 1000 SCCM and a gas pressure of 10 to 50 Pa, and a large amount of high-temperature hydrogen-based active species (hydrogen molecules, hydrogen atoms, active Hydrogen ions and the like are sprayed onto, for example, a polycrystalline silicon film formed on the substrate. As a result, the thermal energy of the hydrogen-based active species (hydrogen molecules, hydrogen atoms, activated hydrogen ions, etc.) moves to those films and raises their film temperatures, and in the case of amorphous silicon or microcrystalline silicon thin films, The amorphous structure silicon is selectively etched by the reduction action of hydrogen-based active species, and these are polycrystallized. The polycrystalline silicon thin film is highly crystallized, and the tin-containing polycrystal having a high crystallization rate and a large grain size is obtained. A silicon film is formed, and irregularities and stress existing at the crystal grain boundaries are reduced by the effect of a group IV element such as tin, so that a tin-containing polycrystalline silicon thin film having high carrier mobility and high quality can be formed.

The above-mentioned hydrogen-based active species and the like, when a silicon oxide is present on or in a thin film of polycrystalline silicon or the like, undergo a reduction reaction with the silicon oxide to produce SiO or the like, which is removed by evaporation. , Silicon oxide on or in those films can be reduced / removed, and a high carrier mobility and high quality polycrystalline silicon thin film can be formed. If this catalytic AHA treatment is performed after the formation of the gate channel / source / drain described later, a large amount of high-temperature hydrogen-based active species and the like transfer heat energy to the films, raise the film temperatures, and cause crystallization. Gate channel at the same time as promotion /
Carrier impurities (phosphorus, arsenic, boron, etc.) implanted in the source / drain regions are ion-activated.

When each of the above films is formed in the same chamber, a hydrogen-based carrier gas is constantly supplied, the catalyst is heated to a predetermined temperature, and a standby is performed. Good.

Mixing monosilane with ammonia at an appropriate ratio
To form a silicon nitride film of a predetermined thickness,
After fully draining, continuously dilute monosilane and He
O_TwoAre mixed in an appropriate ratio to form a silicon oxide film of a predetermined thickness.
After forming and exhausting the previous raw material gas etc.
Monosilane and SnH_FourOr monosilane and H_TwoO,
N _Two, N_TwoO and the like are mixed in an appropriate ratio to form
_xOr / and SiN_yAmorphous or particulate products
Is a microcrystalline silicon thin film or a tin-containing polycrystalline material with a predetermined thickness
Formed a silicon thin film and exhausted the previous source gas sufficiently
Later, the raw material gas is cut continuously for catalytic AHA treatment
The silicon thin film is made into ultrafine silicon particles or contains tin.
Higher crystallization of polycrystalline silicon thin film
After the previous source gas has been sufficiently exhausted,
Silane and He diluted O_TwoAre mixed in an appropriate ratio and
A silicon oxide film is formed. After film formation, cut the source gas
And cool the catalyst to a temperature that does not cause a problem.
Cut off the gas. At this time, the source gas for forming the insulating film is
Increasing or decreasing the slope, as an insulating film for the slope junction
Is also good.

Alternatively, when formed in independent chambers, a hydrogen-based carrier gas may be constantly supplied into each chamber, the catalyst may be heated to a predetermined temperature, and a standby may be performed. . The wafer is transferred to the chamber A, and ammonia is mixed with monosilane in an appropriate ratio to form a silicon nitride film having a predetermined thickness. Next, the chamber is moved to the B chamber, and He-diluted O ₂ is mixed with monosilane at an appropriate ratio to form a silicon oxide film. Next, the mixture is transferred to a C chamber, and monosilane and SnH ₄ , or monosilane and H ₂ O, N ₂ , N ₂ O, etc. are mixed at an appropriate ratio, and amorphous or microcrystalline silicon containing SiO _x or SiN _y particulate products is mixed. A thin film or a tin-containing polycrystalline silicon thin film is formed, and continuously (or in another chamber) is subjected to catalytic AHA treatment with a hydrogen-based carrier gas to form ultrafine silicon particles, or a tin-containing polycrystalline silicon thin film. Higher crystallization. Then, the silicon oxide film is transferred to the chamber B if necessary, and He diluted O ₂ is mixed with monosilane at an appropriate ratio to form a silicon oxide film. After the film formation, the raw material gas is cut, and the catalyst body is cooled to a temperature at which there is no problem to cut the hydrogen-based carrier gas. At this time, the hydrogen-based carrier gas and the respective source gases may be constantly supplied into the respective chambers so as to be in a standby state.

Next, a MOSTFT using the polycrystalline silicon thin film 7 as a source, channel and drain region
Is made.

That is, as shown in (4) of FIG. 2, after the polycrystalline silicon thin film 7 is formed into islands by general-purpose photolithography and etching, the threshold (V _th) by controlling the impurity concentration of the channel region for the nMOS TFT is obtained. )
In order to optimize the above, the pMOSTFT portion is masked with a photoresist 9 and a p-type impurity ion (for example, boron ion) 10 is doped by ion implantation or ion doping at a dose of, for example, 5 × 10 ¹¹ atoms / cm ² . The acceptor concentration is set to 1 × 10 ¹⁷ atoms / cc, and the polycrystalline silicon thin film 7 is made to be a p-type polycrystalline silicon thin film 11.

Next, as shown in (5) of FIG.
By controlling the impurity concentration of the channel region for the OSTFT
V_thIn order to optimize the
Mask with photoresist 12 and perform ion implantation or ion doping.
N-type impurity ions (eg, phosphorus ions) 13
For example 1 × 10¹²atoms / cm^TwoOf dose
2 × 10¹⁷Donors concentration of atoms / cc
And the conductivity type of the polycrystalline silicon thin film 7 is changed to n-type.
The polycrystalline silicon thin film 14 is obtained. In addition, polycrystalline silicon
If there is a silicon oxide film on the thin film 7, remove it.
And the threshold (V _th) Optimization of ion implantation or ion
It may be doped.

Next, as shown in FIG. 3 (6), if necessary, the above-mentioned catalytic AHA treatment is performed to promote crystallization and activate the impurities in the film, and then the gate insulating film is subjected to catalytic CVD or the like. silicon oxide film after forming the 50nm thickness 8, of the Rindopudo polycrystalline silicon film 15 as a gate electrode material, such 2~20SCCM PH ₃ and 20S of
Catalyst CV as described above under supply of CCM monosilane
It is deposited to a thickness of, for example, 400 nm by the D method.

Next, as shown in FIG. 3 (7), a photoresist 16 is formed in a predetermined pattern, and the photoresist 16 is used as a mask to pattern the phosphorus-doped polycrystalline silicon film 15 into a gate electrode shape. After removing the photoresist 16, a silicon oxide film 17 as a gate electrode protective film is formed to a thickness of 20 to 30 nm by, for example, catalytic CVD or the like, as shown in FIG.

Next, as shown in (9) of FIG.
The OSTFT portion is masked with a photoresist 18 and, for example, phosphorus ions 19 which are n-type impurities are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms / cm ^2.
2 × 10 ²⁰ atoms / c
By setting the donor concentration to c, the n ⁺ -type source region 20 and the drain region 21 of the nMOS TFT are formed.

Next, as shown in FIG. 4 (10), n
The MOSTFT portion is masked with a photoresist 22, and for example, boron ions 23, which are p-type impurities, are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms / cm 2.
doping with a dose of cm ² , and 2 × 10 ²⁰ atoms
An acceptor concentration of s / cc is set, and p ⁺ -type source region 24 and drain region 25 of the pMOS TFT are formed.

The gate, the source, and the drain are formed in this manner, and these can be formed by a method other than the above-described process.

That is, after the step (3) in FIG. 1, the polycrystalline silicon thin film 7 is made into islands in pMOSTFT and nMOSTFT regions, and n-type impurities, for example, phosphorus ions are implanted into the pMOSTFT region by ion implantation or ion doping.
Doping is performed at a dose of × 10 ¹² atoms / cm ² , a donor concentration of 2 × 10 ¹⁷ atoms / cc is set, and a p-type impurity, for example, boron ion is dosed at a dose of 5 × 10 ¹¹ atoms / cm ² in the nMOSTFT region. To set the acceptor concentration to 1 × 10 ¹⁷ atoms / cc, and to control the impurity concentration of each channel region,
V _th is optimized.

Then, each source / drain region is formed by a general-purpose photolithography technique using a photoresist mask. In the case of an nMOSTFT, an n-type impurity, for example, arsenic or phosphorus ions is doped at a dose of 1 × 10 ¹⁵ atoms / cm ² by ion implantation or ion doping to set a donor concentration of 2 × 10 ²⁰ atoms / cc. In the case of a pMOS TFT, a p-type impurity, for example, boron ion is doped at a dose of 1 × 10 ¹⁵ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 2 × 10 ²⁰ atoms / cc.

Thereafter, if necessary, a catalytic AHA treatment is performed to activate impurities in the film, and then a silicon oxide film is formed as a gate insulating film. A silicon oxide film is formed. That is,
If necessary, a silicon oxide film 8 is formed in a thickness of 20 to 30 nm by mixing a hydrogen-based carrier gas and monosilane with He diluted O ₂ at an appropriate ratio by a bias or non-bias catalytic CVD method continuously after the catalyst AHA treatment. Then, if necessary, a hydrogen-based carrier gas and monosilane are mixed with NH ₃ at an appropriate ratio to form a silicon nitride film with a thickness of 10 to 20 nm, and further, a silicon oxide film with a thickness of 20 to 30 nm under the above conditions.
It is formed thick. Thereafter, the same general-purpose catalyst CV as described above is used.
A gate electrode is formed by a method D or a photolithography technique.

After the formation of the gate, source and drain, as shown in FIG. 4 (11), the hydrogen-based carrier gas 150 SC is formed on the entire surface by the same catalytic CVD method as described above.
With the common CM, the silicon oxide film 26 is formed to a thickness of, for example, 100 to 200 nm under the supply of O ₂ diluted with 1 to ₂ SCCM of helium gas and 15 to ₂₀ SCCM of monosilane.
A phosphine silicate glass (PSG) film 27 is formed by supplying ₂₀ SCCM PH ₃ , 1-2 SCCM helium diluted O ₂ , and 15-20 SCCM monosilane.
Formed to a thickness of 400 nm, with NH _{3 of} 50-60 SCCM,
The silicon nitride film 28 is formed to a thickness of, for example, 100 to 200 nm under a supply of monosilane of 15 to 20 SCCM to form a laminated insulating film. Then, for example, at about 1000 ° C. for 20 minutes
Ions are activated by RTA (Rapid Thermal Anneal) treatment for up to 30 seconds, and the carrier impurity concentration is set in each region.

Next, as shown in (12) of FIG. 4, a contact window is opened at a predetermined position of the insulating film, and an electrode material such as aluminum containing 1% Si is sputtered on the entire surface including each contact hole by sputtering or the like. To a thickness of 1 μm,
By patterning this, pMOSTFT and nMOS
A source or drain electrode 29 (S or D) and a gate extraction electrode or wiring 30 (G) of each TFT are formed to form a top gate type CMOS TFT. Thereafter, hydrogenation and sintering are performed at 400 ° C. for 1 hour in a forming gas.

Note that instead of forming the gate electrode,
Sputtered film 40 of heat-resistant metal such as Mo-Ta alloy on the entire surface
A thickness of 0 to 500 nm is formed, and nMOSTFT and pMOS are formed by general-purpose photolithography and etching technology.
A gate electrode of a TFT may be formed.

As described above, according to the present embodiment,
The following excellent effects (a) to (m) can be obtained.

(A) The above catalyst AHA treatment is
Under a hydrogen-based carrier gas pressure of 0 Pa, a hydrogen-based carrier gas is supplied to a high-temperature catalyst (for example, tungsten,
(00 ° C.) to form a large amount of high-temperature hydrogen-based active species (hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc.), and form SiO _x and / or SiN _y on the insulating substrate.
When sprayed on an amorphous or microcrystalline silicon thin film containing a particulate product (at a substrate temperature of 300 to 400 ° C.), a high-energy, high-temperature hydrogen-based active species is obtained as compared with conventional RF / VHF plasma hydrogen treatment or ECR plasma hydrogen treatment. A large amount of heat energy of the film or the like efficiently moves to the film or the like, and increases the temperature of the film or the like efficiently and uniformly. As a result, the amorphous silicon film, the microcrystalline silicon film, and the like are selectively etched away at a high etching rate by the reduction action of the hydrogen-based active species, and the silicon contained in the film is further removed.
_x decomposes into Si and SiO, H ₂ O and the like, and SiN _y contained in the film decomposes into Si and NH _{3 and the} like to efficiently form high-quality silicon ultrafine particles. It can effectively work as a nucleus (seed) for crystal growth of polycrystalline silicon or the like. At this time, the ultrafine silicon particles have a particle size of 1 nm or more, preferably 1 to 10 nm, and the number is 1 / μ.
m ² or more, preferably 1 to 100 / μm ² .

(B) The catalyst AHA treatment is performed using the conventional RF / V
Compared with HF plasma hydrogen treatment or ECR plasma hydrogen treatment, amorphous silicon is etched at a higher etching rate to form a large-diameter polycrystalline silicon film, and the carrier mobility can be improved. That is, the catalyst A
Using the silicon ultrafine particles obtained by the HA treatment as a seed, a semiconductor material thin film is easily grown thereon as a polycrystalline semiconductor thin film (as a polycrystalline semiconductor thin film). In particular, the following catalyst AHA treatment and vapor phase growth Thus, crystallization of a silicon film or the like grown by vapor phase on the polycrystalline semiconductor thin film is promoted using the polycrystalline semiconductor thin film as a seed,
It is possible to obtain a target high crystallization rate and high quality polycrystalline semiconductor thin film. That is, if the amorphous silicon is present in the microcrystalline silicon film formed by, for example, biased or non-biased catalytic CVD by the catalytic AHA treatment, this is etched away by hydrogen-based active species to form silicon ultrafine particles. The silicon film to be vapor-grown thereon is seeded (nucleated) with the underlying silicon ultrafine particles.
It is easier to form a polycrystalline silicon film, and further, when the same catalyst AHA treatment and vapor phase growth are repeated, a large amount of heat energy of a high-temperature hydrogen-based active species or the like moves to the film or the like, The temperature of the film or the like is raised, and the amorphous silicon or microcrystalline silicon thin film is polycrystallized by the reducing action of the hydrogen-based active species, and the polycrystalline silicon thin film is highly crystallized, and has a high crystallization rate and a large grain size. A crystalline silicon thin film can be formed.

(C) The catalyst AHA treatment reacts with silicon oxide when silicon oxide is present on the polycrystalline silicon thin film formed on the substrate, in the film or at the grain boundary, as compared with the conventional plasma hydrogen treatment. By forming SiO and the like efficiently by evaporation, silicon oxide in the film or the like can be efficiently reduced / removed, and carrier mobility can be improved.

(D) In the catalytic AHA treatment, cleaning with hydrogen-based active species such as activated hydrogen ions (reduction and removal of adsorbed gas and organic residue on a substrate or the like) is possible.
The catalyst is also less susceptible to oxidative degradation (this effect also occurs because the hydrogen-based carrier gas is used during the above-described biased or non-biased catalytic CVD).

(E) In the catalytic AHA treatment, for example, silicon dangling bonds in the semiconductor film are eliminated by the hydrogenation of hydrogen-based active species such as activated hydrogen ions, and the characteristics are improved.

(F) During the catalytic AHA treatment, the carrier impurities present in the lower crystalline or polycrystalline semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration is obtained in each region.

(G) Catalyst AH after film formation by catalytic CVD
When performing the A treatment, the type and temperature of the catalyst body, the substrate heating temperature, the vapor deposition conditions, the type of the source gas, and the n or p to be added
A polycrystalline silicon thin film having a wide range of n or p type impurity concentration can be easily obtained depending on the type impurity concentration and the like.
Since the polycrystalline silicon thin film having a large grain size and a high crystallization rate can be formed by the A treatment, high carrier mobility, easy _Vth adjustment, and high-speed operation with low resistance are possible.

(H) A polycrystalline silicon thin film containing, for example, 10 ¹⁸ to 10 ²⁰ atoms / cc of tin is formed by catalytic CVD, high-density catalytic CVD, or the like, and a crystal irregularity existing at the polycrystalline silicon grain boundary is formed. Is reduced to reduce the internal stress, so that a tin-containing polycrystalline silicon thin film having high carrier mobility can be formed. Further, in the case of the catalyst AHA treatment after the film formation by the catalyst CVD, the type and temperature of the catalyst body, the substrate heating temperature, the vapor phase film formation conditions, the type of the source gas, and the n
Alternatively, depending on the p-type impurity concentration, tin having a wide range of arbitrary n- or p-type impurity concentrations, for example, tin at 10 ¹⁸ to 10 ²⁰ atoms /
A cc-containing polycrystalline silicon thin film can be easily obtained, and a polycrystalline silicon thin film having a large particle size is formed by the catalytic AHA treatment, thereby reducing the crystal irregularity existing at the polycrystalline silicon grain boundary and reducing the internal stress. Therefore, _Vth adjustment is easy with high carrier mobility and high-speed operation with low resistance is possible.

(I) When the catalyst AHA treatment is performed after the film formation by plasma CVD (high-frequency or low-frequency plasma CVD, etc.), the hydrogen contained in the amorphous silicon film by plasma CVD is reduced by 10 to 20% by the catalyst AHA treatment. /
Since it is removed and a polycrystalline silicon thin film having a large grain size is formed, a polycrystalline silicon thin film having a large carrier mobility can be formed. Further, the substrate heating temperature, the vapor deposition conditions, the type of the source gas, the catalyst AHA treatment conditions,
Alternatively, a polycrystalline silicon thin film having a wide range of n or p-type impurity concentration can be easily obtained depending on the p-type impurity concentration, so that _Vth adjustment can be easily performed with high carrier mobility, and high-speed operation with low resistance can be performed.

(J) In addition to the top gate type, bottom gate type and dual gate type MOS TFTs, a polycrystalline silicon thin film with high carrier mobility, large grain size and high crystallization ratio can be obtained. , A high-speed, high-current-density semiconductor device, an electro-optical device, and a highly efficient solar cell using the polycrystalline silicon thin film.

(K) Since the catalyst AHA treatment can be performed without generating plasma, there is no damage by plasma, and a simple and inexpensive apparatus can be realized as compared with the plasma AHA treatment.

(L) Even if the temperature of the substrate is lowered, the energy of the hydrogen-based active species is large, so that silicon ultrafine particles of a desired size and number can be obtained stably.
In addition, since a polycrystalline silicon film can be formed, the substrate temperature can be lowered particularly to 300 to 400 ° C., so that a large and inexpensive low-strain-point insulating substrate (glass substrate, heat-resistant resin substrate, etc.) It can be used, and the cost can be reduced in this respect as well.

(M) The catalytic CVD apparatus can be used for the ion activation of the n-type or p-type impurities added to the gate channel / source / drain regions in the catalytic AHA treatment depending on the conditions. The cost can be reduced by improving the performance.

Second Embodiment <Manufacturing Example 1 of LCD> In this embodiment, the present invention is applied to an LCD (Liquid Crystal Display) using a polycrystalline silicon MOSTFT by a high-temperature process. The production example is shown in FIG.
The present invention can be similarly applied to a display device such as an ED).

First, as shown in FIG. 12A, in the pixel portion and the peripheral circuit portion, a heat-resistant insulating substrate 61 (strain point of about 800 to 1100) made of quartz glass, crystallized glass or the like is used.
° C., on one main surface of a 50 micron thick to several mm), by catalytic CVD method as described above, after formation of the base protective film (not shown), particulate comprised of SiO _x or / and SiN _y on this An amorphous or microcrystalline silicon thin film 100A containing a product is formed.

Next, as shown in FIG. 12B, the silicon thin film 100A is reformed into the silicon ultrafine particle layer 100B by the above-mentioned catalytic AHA treatment.

Then, as shown in FIG. 12C, the silicon ultrafine particle layer 1 is formed by the above-described catalytic CVD method or the like.
00B as a seed and a polycrystalline silicon thin film 67 of, for example, 5
It is formed to a thickness of 0 nm. This polycrystalline silicon thin film may be formed by the above-described multi-catalyst AHA treatment.

Next, as shown in FIG. 13D, a polycrystalline silicon thin film 67 is formed using a photoresist mask.
(Islanding), for example, the nMOSTFT part in the display area and the nMOSTF in the peripheral drive circuit area
Active layers of transistors such as a T section and a pMOS TFT section, active elements such as diodes, and passive elements such as resistors, capacitors, and inductances are formed.

Next, the channel of the transistor active layer 67 is
V by controlling the impurity concentration in the tunnel region _thFor optimization
Ion injection of specified impurities such as boron or phosphorus as described above
After the insertion, as shown in (5) of FIG.
Polycrystalline silicon by the same catalytic CVD method as above
A gate insulating film having a thickness of, for example, 50 nm on the surface of the thin film 67.
A silicon oxide film 68 is formed. By catalytic CVD method etc.
When forming a silicon oxide film 68 for a gate insulating film,
Substrate temperature and catalyst temperature are the same as above
However, the oxygen gas flow rate is 1-2 SCCM, monosilane gas flow
The amount is 15 to 20 SCCM, and the hydrogen-based carrier gas is 150
It may be SCCM. The impurity concentration of the channel region
Before or after controlling, for example, at about 1000 ° C. for 30 minutes
Silicon oxide film 6 for gate insulating film by high temperature thermal oxidation
8 may be formed.

Next, as shown in FIG. 13 (6), as a material for the gate electrode and the gate line, for example, Mo-
A Ta alloy is deposited to a thickness of, for example, 400 nm by sputtering, or a phosphorus-doped polycrystalline silicon film is deposited, for example, in a hydrogen-based carrier gas of 150 SCCM, 2-2.
0 SCCM phosphine (PH ₃ ) and 20 SCCM
Catalytic CVD as described above under supply of monosilane gas
It is deposited to a thickness of, for example, 400 nm by a method or the like. Then, the gate electrode material layer is patterned into the shape of the gate electrode 75 and the gate line by general-purpose photolithography and etching technology. In the case of a phosphorus-doped polycrystalline silicon film, a protective silicon oxide film (10 to 20 nm thick) may be formed on the surface by catalytic CVD or the like.

Next, as shown in FIG. 14 (7), p
The MOSTFT portion is masked with a photoresist 78, and an n-type impurity such as arsenic (or phosphorus) ion 79 is, for example, 1 × 10 ¹⁵ a by ion implantation or ion doping.
doping at a dose of toms / cm ² , 2 × 10
The donor concentration was set to ²⁰ atoms / cc and the nMOST
An FT n ⁺ type source region 80 and a drain region 81 are formed.

Next, as shown in FIG. 14 (8), n
The MOSTFT portion is masked with a photoresist 82 and, for example, boron ions 83 which are p-type impurities are ion-implanted or ion-doped, for example, at 1 × 10 ¹⁵ atoms.
/ Cm ^{2 at} a dose of 2 × 10 ^{20 at}
ms / cc acceptor concentration, pMOSTFT
The p ⁺ type source region 84 and the drain region 85 are respectively formed.

Next, as shown in FIG. 14 (9), a hydrogen-based carrier gas of 150 to 200 SCCM is commonly used for the entire surface by the same catalytic CVD method or the like as described above.
The silicon oxide film is formed, for example, under the supply of He diluted O ₂ of ２2 SCCM and monosilane of 15 to ₂₀ SCCM, for example, from 100 to 20 SCCM.
0 nm thickness, 1-20 SCCM phosphine (PH ₃ ), 1-2 SCCM He diluted O ₂ , 15-20
A phosphine silicate glass (PSG) film is formed to a thickness of 300 to 400 nm under SCCM monosilane supply,
Ammonia 50~60SCCM (NH _3), 15~2
A silicon nitride film is formed to a thickness of, for example, 100 to 200 nm while supplying monosilane at 0 SCCM. An interlayer insulating film 86 is formed by stacking these insulating films. Note that such an interlayer insulating film may be formed by another ordinary method different from the above. After this, for example 900 ° C., annealing or 1000 ° C. in 5 min N _2, in N ₂ for 20-30 seconds RT
The ions are activated by the A treatment, and the carrier impurity concentration is set in each region.

Next, as shown in (10) of FIG.
A contact window is opened at a predetermined position of the insulating film 86, and an electrode material such as aluminum is deposited to a thickness of 1 μm on the entire surface including each contact hole by a sputtering method or the like, and is patterned to form an nMOS TFT of a pixel portion. Source electrode 87, data line, pMOST of peripheral circuit section
Source electrodes 88 and 90 and drain electrodes 89 and 91 of FT and nMOSTFT and wiring are formed, respectively. Thereafter, for example, hydrogenation and sintering are performed at 400 ° C. for 1 hour in a forming gas to improve the interface state and the ohmic contact.

Next, after an interlayer insulating film 92 such as a silicon oxide film is formed on the surface by a CVD method or the like, (1) in FIG.
As shown in 1), contact holes are formed in the interlayer insulating films 92 and 86 in the nMOSTFT drain region of the pixel portion, and for example, ITO (Indium) having a thickness of 130 to 150 nm is formed.
A tin oxide (a transparent electrode material in which tin is doped into indium oxide) is deposited on the entire surface by a vacuum evaporation method or the like, and is patterned to form a transparent pixel electrode 93 connected to the drain region 81 of the nMOS TFT. Thereafter, annealing is performed, for example, in a forming gas at 250 ° C. for 1 hour to obtain I
Improve ohmic contact with TO and improve transparency of ITO film.

Thus, an active matrix substrate (hereinafter, referred to as a TFT substrate) is manufactured, and a transmission type LCD can be manufactured. This transmission type LCD has an alignment film 9 on a transparent pixel electrode 93 as shown in FIG.
4, liquid crystal 95, alignment film 96, transparent electrode 97, counter substrate 9
8 are laminated.

The above-described steps can be similarly applied to the manufacture of a reflective LCD. FIG. 20A shows an example of this reflection type LCD.
Reference numeral 1 denotes a reflection film deposited on the roughened insulating film 92, which is connected to the drain of the MOSTFT.

When the liquid crystal cell of this LCD is manufactured by surface assembly (suitable for medium / large liquid crystal panels of 2 inch size or more), first, the TFT substrate 61 and the solid I
Counter substrate 9 provided with TO (Indium Tin Oxide) electrode 97
On the element formation surface of No. 8, polyimide alignment films 94 and 96 are formed. This polyimide alignment film is formed to a thickness of 50 to 100 nm by roll coating, spin coating, etc.
Cure for 2 hours.

Next, the TFT substrate 61 and the counter substrate 98 are subjected to rubbing or optical alignment processing. Rubbing buff materials include cotton and rayon, but cotton is more stable in terms of buff residue (garbage) and retardation.
Photoalignment is a technique for aligning liquid crystal molecules by non-contact linearly polarized ultraviolet irradiation. In addition, the orientation other than rubbing,
A polymer alignment film can be formed by obliquely entering polarized light or non-polarized light (such a polymer compound includes, for example, a polymethyl methacrylate-based polymer having azobenzene).

Next, after cleaning, a common agent is applied to the TFT substrate 61 side, and a sealing agent is applied to the counter substrate 98 side.
Wash with water or IPA (isopropyl alcohol) to remove rubbing buff debris. Common agent is acrylic or epoxy acrylate containing conductive filler,
Alternatively, the sealant may be an acrylic adhesive, an epoxy acrylate, or an epoxy adhesive. Any of heat curing, ultraviolet irradiation curing, ultraviolet irradiation curing and heat curing can be used, but from the viewpoint of overlay accuracy and workability, the ultraviolet irradiation curing and heat curing type is preferable.

Next, spacers for obtaining a predetermined gap are scattered on the counter substrate 98 side, and are superposed on the TFT substrate 61 at a predetermined position. After the alignment mark on the counter substrate 98 and the alignment mark on the TFT substrate 61 are precisely aligned, the sealant is temporarily cured by irradiating with ultraviolet light, and then heat-cured collectively.

Next, a scribe break is performed to
A single liquid crystal panel in which the substrate 61 and the counter substrate 98 are overlapped is created.

Next, the liquid crystal 95 is injected into the gap between the substrates 61-98, and the injection port is sealed with an ultraviolet adhesive, and then subjected to IPA cleaning. Any type of liquid crystal may be used, but for example, a high-speed response TN (twisted nematic) mode using a nematic liquid crystal is generally used.

Next, the liquid crystal 95 is oriented by heating and quenching.

Next, a flexible wiring is connected to the panel electrode take-out portion of the TFT substrate 61 by thermocompression bonding of an anisotropic conductive film, and a polarizing plate is bonded to the counter substrate 98.

Also, in the case of a single liquid crystal panel surface assembly (suitable for a small liquid crystal panel having a size of 2 inches or less), a polyimide alignment film 94 is formed on the element forming surfaces of the TFT substrate 61 and the counter substrate 98 in the same manner as described above. , 96, and both substrates are subjected to rubbing or non-contact linear polarization ultraviolet light alignment treatment.

Next, the TFT substrate 61 and the opposing substrate 98 are divided into single pieces by dicing or scribe break, and washed with water or IPA. A common agent is applied to the TFT substrate 61, a sealing agent containing a spacer is applied to the counter substrate 98,
Lay both substrates together. Subsequent processes follow the above.

In the above-mentioned LCD, the counter substrate 98 is a CF (color filter) substrate, in which a color filter layer (not shown) is provided below the ITO electrode 97. The incident light from the counter substrate 98 side may be efficiently reflected by, for example, the reflection film 93 and may be emitted from the counter substrate 98 side.

On the other hand, when the TFT substrate 61 is a TFT substrate having an on-chip color filter (OCCF) structure in which a color filter is provided on the TFT substrate 61, the counter substrate 98 is provided with a solid ITO electrode (or a black mask). The ITO electrode is solid).

In the case of a transmissive LCD, an on-chip color filter (OCCF) structure and an on-chip black (OCB) structure can be manufactured as follows.

That is, as shown in FIG. 15 (13), the insulating film 8 of phosphine silicate glass / silicon oxide
The drain portion of No. 6 was also opened to form an aluminum buried layer for the drain electrode, and then a photoresist 99 in which each color of R, G, and B was dispersed in a pigment for each segment to a predetermined thickness (1 to 1.5 μm). After the formation, the color filter layers 99 (R), 99 (G), and 99 are patterned by a general-purpose photolithography technique to leave only predetermined positions (each pixel portion).
(B) is formed (on-chip color filter structure).
At this time, the window of the drain part is also opened. In addition, an opaque ceramic substrate, glass with low transmittance, and a heat-resistant resin substrate cannot be used.

Next, in a contact hole communicating with the drain of the display TFT, a light-shielding layer 100 'serving as a black mask layer is formed by metal patterning over the color filter layer. For example, a molybdenum film having a thickness of 200 to 250 nm is formed by sputtering,
Patterning into a predetermined shape that covers T and shields light (on-chip black structure).

Next, a flattening film 92 made of a transparent resin is formed, and an ITO transparent electrode 93 is formed in a through hole provided in the flattening film so as to be connected to the light shielding layer 100 '.

As described above, by forming the color filter 99 and the black mask 100 'on the display array portion, the aperture ratio of the liquid crystal display panel is improved, and the power consumption of the display module including the backlight is reduced. Is realized.

FIG. 16 shows the above-mentioned top gate type MOST.
1 schematically shows the entirety of an active matrix liquid crystal display device (LCD) configured with a drive circuit integrated by incorporating an FT. This active matrix LCD has a flat panel structure in which a main substrate 61 (which constitutes an active matrix substrate) and a counter substrate 98 are bonded via a spacer (not shown).
Liquid crystal (not shown) is sealed between 1-98. On the surface of the main substrate 61, a display unit including pixel electrodes 93 arranged in a matrix, a switching element for driving the pixel electrodes, and a peripheral drive circuit unit connected to the display unit are provided. .

The switching element of the display unit is n
It is composed of a MOS, pMOS or CMOS top-gate MOSTFT having an LDD structure. In the peripheral drive circuit section, the above-mentioned top gate type M
OSTFT CMOS or nMOS or pMOSTFT
Alternatively, a mixture of these is formed. Note that one of the peripheral drive circuit units is a horizontal drive circuit that supplies a data signal to drive the TFT of each pixel for each horizontal line, and the other peripheral drive circuit unit connects the gate of the TFT of each pixel for each scan line. , And are usually provided on both sides of the display unit. These drive circuits can be configured in either a dot-sequential analog system or a line-sequential digital system.

As shown in FIG. 17, at the intersection of the orthogonal gate bus line and data bus line, the MOSTF
T is disposed, and a liquid crystal capacitance (C
_LC ) Writes image information and holds the charge until the next information comes. In this case, it is not enough to hold the TFT channel resistance alone. To compensate for this, a storage capacitor (auxiliary capacitor) (C _S ) is added in parallel with the liquid crystal capacitor to compensate for a decrease in the liquid crystal voltage due to leak current. May be. In such a MOSTFT for LCDs, the required performance differs between the characteristics of the TFT used for the pixel portion (display portion) and the characteristics of the TFT used for the peripheral drive circuit. Is an important issue. For this reason, by providing a TFT having an LDD structure as described later in the display portion, an effective electric field applied to the channel region is reduced as a structure in which an electric field is hardly applied between the gate and the drain, and an off current is reduced. Can be reduced. However, the process becomes complicated, the element size becomes large, and problems such as a decrease in on-current occur. Therefore, an optimum design is required for each purpose of use.

Usable liquid crystals include TN liquid crystal (nematic liquid crystal used for TN mode of active matrix driving), STN (super twisted nematic), GH (guest / host), PC
(Phase change), FLC (ferroelectric liquid crystal), A
Liquid crystals for various modes such as FLC (antiferroelectric liquid crystal) and PDLC (polymer dispersed liquid crystal) may be employed.

<Manufacturing Example 2 of LCD> Next, a manufacturing example of an LCD (liquid crystal display device) using a polycrystalline silicon MOSTFT of a low-temperature process according to the present embodiment will be described. The present invention is similarly applicable to a display device of an FED and the like.

In this manufacturing example, aluminosilicate glass, borosilicate glass or the like is used as the substrate 61 in the above-described manufacturing example 1, and (1), (2) and (3) in FIG.
Is performed in the same manner. That is, a tin-containing (or non-containing) polycrystalline silicon thin film 67 is formed on the substrate 61 by catalytic CVD and catalytic AHA treatment to form an island, and the nMOS TFT portion in the display region and the nMO TFT in the peripheral drive circuit region are formed.
An STFT section and a pMOSTFT section are formed. In this case, at the same time, regions such as a diode, a capacitor, an inductance, and a resistor are formed.

Next, as shown in (1) of FIG. 18 (however, the silicon ultrafine particle layer 100B is not shown; the same applies hereinafter), V _th is optimized by controlling the carrier impurity concentration of each MOSTFT gate channel region. In order to achieve this, the nMOSTFT part in the display area and the nMOSTT in the peripheral drive circuit area
The FT portion is covered with a photoresist 82, and an n-type impurity 79 such as phosphorus or arsenic is added to the pMOSTFT portion in the peripheral drive circuit region by ion implantation or ion doping.
Doping is performed at a dose of × 10 ¹² atoms / cm ² , the donor concentration is set to 2 × 10 ¹⁷ atoms / cc, and as shown in FIG. Then, a p-type impurity 83 such as boron, for example, is implanted into the nMOSTFT portion of the display region and the nMOSTFT portion of the peripheral drive circuit region by 5 × 10 ¹¹ by ion implantation or ion doping.
doping at a dose of atoms / cm ² , 1 × 1
0 ¹⁷ Set the acceptor concentration of atoms / cc.

Next, as shown in (3) of FIG. 18, an n ^- type LDD (Lightly D
In order to form an oped drain) portion, the gate portion of the nMOSTFT in the display region and all the pMOSTFTs and nMOSTFTs in the peripheral driving region are covered with a photoresist 82 by a general-purpose photolithography technique, and n in the exposed display region is formed.
An n-type impurity 7 such as phosphorus is implanted into the source / drain region of the MOSTFT by ion implantation or ion doping.
9 is doped at a dose of 1 × 10 ¹³ atoms / cm ² and the donor concentration is set to 2 × 10 ¹⁸ atoms / cc to form an n ⁻ -type LDD portion.

Next, as shown in FIG. 19D, the nMOSTFT portion in the display region and the nM TFT in the peripheral drive circuit region are used.
The entire OSTFT portion is covered with a photoresist 82,
A p-type impurity 83 such as boron, for example, is ion-implanted or ion-doped into the source and drain regions exposed by covering the gate portion of the pMOSTFT portion of the peripheral drive circuit region with the photoresist 82 at 1 × 10 ¹⁵ atoms / s.
doping with a dose of cm ² , and 2 × 10 ²⁰ atoms
A source portion 84 and a drain portion 85 of p ⁺ type are formed at an acceptor concentration of s / cc.

Next, as shown in FIG. 19 (5), the pMOSTFT portion in the peripheral drive circuit region is
2, the gate of the nMOSTFT in the display area and the LDD part and the gate part of the nMOSTFT part in the peripheral drive circuit area are covered with a photoresist 82, and the exposed source and drain areas of the nMOSTFT in the display area and the peripheral drive area are For example, an n-type impurity 79 such as phosphorus or arsenic is doped with 1 × 10 ¹⁵ atoms by ion implantation or ion doping.
ion doping at a dose of s / cm ² ,
^At a donor concentration of ²⁰ atoms / cc, an n ⁺ -type source portion 80 and a drain portion 81 are formed.

Next, as shown in FIG. 19 (6), plasma CVD, TEOS plasma CVD, catalytic CVD
As a gate insulating film 68, a silicon oxide film 40 to 50 nm thick, a silicon nitride film 10 to 20 nm thick,
A silicon oxide film having a thickness of 40 to 50 nm is formed.
Then, RTA treatment with a halogen lamp or the like is performed, for example, at about 1000 ° C. for 10 to 30 seconds, and the added n or p-type impurities are ion-activated to obtain each set carrier impurity concentration.

Thereafter, an aluminum sputtered film containing 1% Si with a thickness of 400 to 500 nm is formed on the entire surface, and gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching. Further, thereafter, an insulating film 86 composed of a stacked film having a silicon oxide film thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film of 200 to 300 nm, and a silicon nitride film of 100 to 200 nm thickness by plasma CVD, catalytic CVD, or the like.
To form

Next, the windows of the source / drain portions of all the TFT portions of the peripheral drive circuit and the source portions of the display nMOSTFT portion are opened by general-purpose photolithography and etching techniques. The silicon nitride film is plasma-etched with CF ₄ , and the silicon oxide film and the phosphosilicate glass film are etched with a hydrofluoric acid-based etchant.

Next, as shown in FIG. 19 (7), an aluminum sputtered film containing 1% Si with a thickness of 400 to 500 nm is formed on the entire surface, and the source of all the TFTs of the peripheral drive circuit is formed by general-purpose photolithography and etching techniques. ,
At the same time as forming the drain electrodes 88, 89, 90 and 91, the source electrode 87 and the data line of the display nMOSTFT are formed.

Next, although not shown, the plasma CV
D, silicon oxide films 100 to 2 by catalytic CVD, etc.
00 nm thick phosphine silicate glass film (PSG
Film) 200 to 300 nm thick, silicon nitride films 100 to 3
A 00 nm thickness is formed on the entire surface as an interlayer insulating film (92 described above), and hydrogenation and sintering are performed in a forming gas at about 400 ° C. for 1 hour. After that, the display nMOST
A window for contacting the drain portion of the FT is opened.

Here, when the LCD is of the transmission type, the silicon oxide film, the phosphine silicate glass film and the silicon nitride film at the pixel opening are removed.
It is not necessary to remove the silicon oxide film, the phosphine silicate glass film, and the silicon nitride film in the pixel openings and the like (this is the same in the above-described or later-described LCD).

In the case of the transmission type, as in (10) of FIG. 15, an acrylic transparent resin flattening film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and display is performed by general-purpose photolithography and etching techniques. After forming a transparent resin window opening on the drain side of the TFT for
An ITO sputtered film with a thickness of nm is formed, and nMOSTF for display is formed by general-purpose photolithography and etching technology.
An ITO transparent electrode in contact with the drain of T is formed. Further heat treatment (200 to 25 in forming gas)
0 ° C., 1 hour) to reduce contact resistance and reduce IT
O To improve transparency.

In the case of the reflection type, a photosensitive resin film having a thickness of 2 to 3 μm is formed on the entire surface by spin coating or the like, and a concavo-convex pattern is formed on at least the pixel portion by general-purpose photolithography and etching techniques. To form a concave and convex reflecting lower portion. At the same time, a photosensitive resin window opening at the drain of the display nMOS TFT is formed. Thereafter, an aluminum sputtered film containing 1% Si with a thickness of 300 to 400 nm is formed on the entire surface, the aluminum film other than the pixel portion is removed by general-purpose photolithography and etching technology, and the irregularities connected to the drain electrode of the display nMOS TFT are formed. An aluminum reflector having a shape is formed. Then,
Sintering is performed at 300 ° C. for 1 hour in a forming gas.

In the above, if the catalyst AHA treatment is performed after the source and drain of the nMOS TFT are formed, the film temperature of the polycrystalline silicon thin film is locally increased, and the crystallization is further promoted, and the high mobility and high mobility can be obtained. Form a high quality polycrystalline silicon thin film. At the same time, the thermal energy of high-temperature hydrogen molecules, hydrogen atoms, activated hydrogen ions, etc. moves to the film and locally raises the film temperature,
Phosphorus, arsenic, boron ions and the like implanted in the gate channel / source / drain regions are activated.

When an amorphous silicon-containing microcrystalline silicon thin film or the like is formed by the plasma CVD method, the film contains 10 to 20% of hydrogen.
The polycrystalline silicon film can be reduced / removed by the HA treatment to form a polycrystalline silicon film, and a high-mobility and high-quality polycrystalline silicon thin film can be formed. Further, when silicon oxide is present on or in a film such as a polycrystalline silicon thin film, the silicon oxide is generated by a reduction reaction with the silicon oxide and is evaporated and removed. An object can be reduced / removed, and a high mobility and high quality polycrystalline silicon thin film can be formed.

<Bottom Gate Type or Dual Gate Type M
For example, in an LCD incorporating OSTFT> MOSTFT, a transmissive type L composed of a bottom gate type and a dual gate type MOSTFT is used instead of the above-described top gate type.
An example of manufacturing a CD will be described (however, the same applies to a reflective LCD).

As shown in FIG. 20B, a bottom gate type nMOSTFT is provided in the display portion and the peripheral portion.
Alternatively, as shown in FIG. 20C, dual gate type nMOSTFTs are provided in the display portion and the peripheral portion, respectively. Of these bottom gate type and dual gate type MOS TFTs, especially in the case of the dual gate type, the driving capability is improved by the upper and lower gate portions, suitable for high-speed switching, and selectively using one of the upper and lower gate portions. Depending on the case, it can be operated as a top gate type or a bottom gate type.

The bottom gate type MOSTF shown in FIG.
In the figure, reference numeral 102 denotes a gate electrode made of a Mo—Ta alloy or the like, 103 denotes a silicon nitride film, and 104 denotes a silicon oxide film to form a gate insulating film. A channel region and the like using a polycrystalline silicon thin film 67 similar to the MOSTFT are formed. Further, the dual gate type M shown in FIG.
In the OSTFT, the lower gate portion is a bottom gate type M
Similar to the OSTFT, except that the upper gate portion is formed by forming a gate insulating film 106 with a laminated film of a silicon oxide thin film and a silicon nitride film, and further, if necessary, a silicon oxide film, and providing an upper gate electrode 75 thereon. I have.

<Manufacture of Bottom Gate Type MOSTFT> First, a 300-400 nm-thick Mo-Ta alloy sputtered film is formed on the entire surface of a glass substrate 61, and is formed by general-purpose photolithography and etching techniques to form a 20-45 nm thick sputtered film.
The gate line is formed at the same time as the bottom gate electrode 102 is formed at least in the TFT formation region by taper etching. The selection of the glass material is in accordance with the above-mentioned top gate type.

Next, a silicon nitride film 103 and a silicon oxide film 104 for a gate insulating film and a protective film are formed by a vapor phase growth method such as plasma CVD, TEOS plasma CVD, bias or non-bias catalytic CVD, and low pressure CVD.
Is converted to SiO 2 by bias or non-bias catalytic CVD or the like.
_x or to form an amorphous silicon or microcrystalline silicon thin film of SiN _y particulate product containing, a silicon ultrafine particles by catalytic AHA treatment. Using this as a seed, a polycrystalline silicon thin film containing or not containing tin is formed by bias or non-bias catalytic CVD or the like, and a catalyst AHA treatment is repeated to form a large grain size polycrystalline silicon thin film 67 having a high crystallization rate. I do. These vapor deposition conditions are based on the above-mentioned top gate type. Note that the bottom gate insulating film and the silicon nitride film for the protective film are provided in expectation of the Na ion stopper function from the glass substrate, but are unnecessary in the case of synthetic quartz glass. The silicon ultrafine particle layer is omitted in FIG.

The subsequent processes are the same as those described above. However, since the gate electrode has already been formed in the above-described steps, the steps of forming a polycrystalline silicon film for a gate electrode, forming a gate electrode, and oxidizing a gate polycrystalline silicon are performed here. Is unnecessary.

Then, as described above, the pMOS
The TFT and nMOS TFT regions are made islands (however,
Only one region is shown: the same applies hereinafter), and an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping to control the carrier impurity concentration in each channel region to optimize _Vth . Later, each MOSTF
In order to form T source and drain regions, an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping. Thereafter, annealing of the catalyst AHA treatment or RTA treatment is performed to activate the impurities.

The subsequent processes are the same as those described above.

<Manufacture of Dual Gate MOSTFT>
Similarly to the above bottom gate type, the bottom gate electrode 10
2. The gate insulating films 103 and 104, and the polycrystalline silicon thin film 67 having a high crystallization rate and a large grain size formed by using ultrafine silicon particles as seeds, respectively. However, the silicon nitride film 103 for the bottom gate insulating film and the protective film is provided in expectation of the Na ion stopper function from the glass substrate, but is unnecessary in the case of synthetic quartz glass.

Then, as described above, the pMOS
In order to optimize the V _th by controlling the carrier impurity concentration of each channel region by forming the islands of the TFT and nMOS TFT regions, an appropriate amount of n-type or p-type impurities are mixed by ion implantation or ion doping, and then, Each M
In order to form the source and drain regions of the OSTFT, an appropriate amount of n-type or p-type impurities is mixed by ion implantation or ion doping.

Next, a stacked film of a silicon oxide film and a silicon nitride film for the top gate insulating film 106 and, if necessary, a silicon oxide film are further formed. The vapor phase growth conditions are based on the above-mentioned top gate type. After that, RTA annealing is performed to activate the impurities.

Thereafter, an aluminum sputtered film containing 1% Si with a thickness of 400 to 500 nm is formed on the entire surface, and top gate electrodes 75 and gate lines of all TFTs are formed by general-purpose photolithography and etching techniques. Thereafter, an insulating film 86 made of a silicon oxide film having a thickness of 100 to 200 nm, a phosphine silicate glass (PSG) film having a thickness of 200 to 300 nm, or the like is formed by plasma CVD, catalytic CVD, or the like. Next, using general-purpose photolithography and etching technology, all MOS
TFT source / drain electrode part, display part nMO
A window is opened in the source electrode portion of the STFT.

Next, a 400-500 nm thick 1
An aluminum sputtered film containing% Si is formed, and source and drain aluminum electrodes 87, 88 and 89, a source line and a wiring are formed by general-purpose photolithography and etching techniques. Next, plasma C
VD, catalytic CVD method, etc.
200 nm thick phosphine silicate glass film (PS
G film) 200-300 nm thick, silicon nitride film 100-
A 300 nm thick interlayer insulating film 92 is formed on the entire surface, and is subjected to hydrogenation and sintering at about 400 ° C. for 1 hour in a forming gas. Thereafter, a drain contact window of the display nMOSTFT is opened to form a pixel electrode 93 of ITO or the like.

As described above, according to the present embodiment,
As in the first embodiment described above, the bias or non-bias catalytic CVD and the catalytic AHA treatment are used to form the high channel mobility, the gate channel, the source and the drain region of the MOSTFT of the LCD and the peripheral drive circuit. Thus, it is possible to form a polycrystalline silicon thin film having a high crystallization ratio and a large grain size, which facilitates _Vth adjustment and enables high-speed operation with low resistance. Top gate, bottom gate or dual gate type MOSTF using this polycrystalline silicon thin film
A liquid crystal display device using T integrates a display unit having an LDD structure with high switching characteristics and low leakage current, a CMOS or nMOS or pMOS peripheral driving circuit with high driving capability, a video signal processing circuit, a memory circuit, and the like. This makes it possible to realize a high-quality, high-definition, narrow frame, high-efficiency, and inexpensive liquid crystal panel.

Further, since it can be formed at a low temperature (300 to 400 ° C.), it is possible to use a low strain point glass which is inexpensive and can be easily enlarged, and the cost can be reduced. In addition, by forming a color filter and a black mask on the array portion, the aperture ratio and luminance of the liquid crystal display panel are improved, a color filter substrate is not required, and cost reduction is achieved by improving productivity and the like.

Third Embodiment In the present embodiment, the present invention is applied to an organic or inorganic electroluminescence (EL) display device, for example, an organic EL display device. An example of the structure and a manufacturing example are shown below.

<Structural Example I of Organic EL Element> FIG.
As shown in (A) and (B), according to this structural example I,
The gate channel 117 and the source of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed on a substrate 111 made of glass or the like by a polycrystalline silicon thin film having a high crystallization rate and a large grain size formed by the method described above according to the present invention. A region 120 and a drain region 121 are formed. Then, the gate electrode 11 is formed on the gate insulating film 118.
5. A source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. MOS
The drain of TFT1 and the gate of MOSTFT2 are connected via a drain electrode 128, and
A capacitor C is formed between the source electrode 127 of the TFT 2 and the insulating film 136, and the drain electrode 131 of the MOS TFT 2 extends to the cathode 138 of the organic EL element.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133,
Further, a red organic light emitting layer (not shown) is formed, an anode (first layer) 134 is formed so as to cover the organic light emitting layer, and a common anode (second layer) 135 is formed on the entire surface. In addition, a peripheral driving circuit composed of a CMOS TFT,
The method of manufacturing the video signal processing circuit, the memory circuit, and the like conforms to the above-described liquid crystal display device (the same applies hereinafter).

In the organic EL display section having this structure, the organic EL light emitting layer is connected to the drain of the current driving MOSTFT 2 and the cathode (Li-Al, Mg-Ag, etc.) 138 is attached to the surface of the substrate 111 such as glass. Then, the anodes (ITO films and the like) 134 and 135 are provided on the upper portion thereof, and therefore, the top emission 136 ′ is obtained. The cathode is MOSTF
In the case where T is covered, the light emitting area becomes large. At this time, the cathode serves as a light-shielding film, and the emitted light does not enter the MOSTFT, so that no leak current is generated and the TFT characteristics are not deteriorated.

Further, as shown in FIG. 21C, a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion.
Is formed, light leakage (such as crosstalk) can be prevented, and the contrast can be improved.

It is to be noted that the green, blue and red colors are displayed in the pixel display section.
Either a method using a color light-emitting layer, a method using a color conversion layer, or a method using a color filter for a white light-emitting layer can realize a good full-color EL display device, and a polymer that is a light-emitting material for each color. Long-life, high-precision, high-quality, high-reliability full-color organic EL even in compound spin coating or metal complex vacuum evaporation
Since the parts can be created with high productivity, the cost can be reduced (the same applies hereinafter).

A conventional organic EL of this type uses an amorphous or microcrystalline silicon MOSTFT.
_{Even if th} fluctuates, the current value easily fluctuates, and the image quality fluctuates easily. In addition, since the mobility is low, the current that can be driven with high speed response is limited, and it is difficult to form a p-channel, and even a small-scale CMOS circuit configuration is difficult. Therefore, it is preferable to use a polycrystalline silicon MOSTFT which can be relatively easily formed in a large area, has high reliability, has high carrier mobility, and can form a CMOS circuit. An amorphous silicon film is formed by a plasma CVD method at 300 to 400 [deg.] C. and excimer laser annealing is performed to form a polycrystalline silicon film. 2) 430-500 ° C amorphous silicon film
Formed by LPCVD method at 600 ° C./5
Solid phase growth is carried out at 20 hours and 850 ° C./0.5 to 3 hours to form a polycrystalline silicon film.

However, 1) adopts an expensive excimer laser device, and a TFT caused by instability of the excimer laser.
Cost increases due to characteristic unevenness, quality problems, and reduced productivity. 2) The general-purpose glass substrate cannot be used due to the long-term heat treatment at 600 ° C. or higher and 15 to 20 hrs,
Since quartz glass is used, the cost is increased. In the full-color organic EL layer, in the microfabrication process, the electrode is oxidized, the organic EL material is exposed to oxygen and moisture, or the structure is changed by heating (dissolution or recrystallization).
Therefore, it is difficult to form each color light emitting region with high accuracy.

Next, the manufacturing process of the organic EL device according to the present embodiment will be described. First, as shown in FIG. 22A, the source region 120 made of a polycrystalline silicon thin film is formed through the above-described steps. After forming the channel region 117 and the drain region 121, a gate insulating film 118 is formed, and the gate electrodes 11 of the MOSTFTs 1 and 2 are formed thereon.
5 is formed by sputtering a Mo—Ta alloy or the like, photolithography and etching techniques.
A gate line connected to the gate electrode of the STFT 1 is formed by sputtering film formation, photolithography, and etching technology (the same applies hereinafter). Then, the overcoat film (silicon oxide or the like) 137 is applied to the bias catalyst CV.
D and the like, and then 100
Ion activation is performed by RTA treatment at 0 ° C. for 10 to 30 seconds. Then, a source electrode 127 and an earth line of the MOSTFT 2 are formed, and an overcoat film (silicon oxide / silicon nitride laminated film) 136 is further formed.

Next, as shown in (2) of FIG.
After opening the windows of the source / drain portion of the OSTFT1 and the gate portion of the MOSTFT2, as shown in (3) of FIG.
1% S between the drain electrode of
connected with the Al wiring 128 containing i,
Source electrode and A containing 1% Si connected to this electrode.
1 is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130 is formed, and a MOS
Open the window of the drain part of TFT2, MOSTFT2
The cathode 138 of the light-emitting part connected to the drain part of FIG.

Next, as shown in FIG. 22D, an organic light emitting layer 132 and the like and anodes 134 and 135 are formed.

In the above description, the green (G) light emitting organic EL layer, the blue (B) light emitting organic EL layer, and the red (R) light emitting organic EL layer are formed to have a thickness of 100 to 200 nm, respectively. The layer is formed by a vacuum heating evaporation method in the case of a low molecular weight compound, and in the case of a high molecular weight compound, a method of arranging R, G, B light emitting polymers by an application method such as dipping coating or spin coating or an inkjet method is used. . In the case of a metal complex, a sublimable material is formed by a vacuum heating evaporation method.

The organic EL layer includes a single-layer type, a two-layer type, a three-layer type, and the like. Here, an example of a low-molecular compound three-layer type is shown. Single layer type; anode / bipolar light emitting layer / cathode, double layer type; anode / hole transporting layer / electron transporting light emitting layer / cathode, or anode / hole transporting light emitting layer / electron transporting layer / cathode, three layer type; Anode / hole transporting layer / light emitting layer / electron transporting layer / cathode, or anode / hole transporting light emitting layer / carrier blocking layer / electron transporting light emitting layer / cathode

In the element of FIG. 21B, if a known light emitting polymer is used instead of the organic light emitting layer, it can be configured as a light emitting polymer display device (LEPD) driven by a passive matrix or an active matrix (hereinafter, referred to as LEPD). And similar).

<Structural Example II of Organic EL Element> FIG.
As shown in (A) and (B), according to this structural example II,
On a substrate 111 made of glass or the like, similar to the above structure example I,
The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT1 and the current driving MOSTFT2 are formed by the polycrystalline silicon thin film having a high crystallization rate and a large grain size formed by the above-described method according to the present invention. Have been. And the gate insulating film 1
A gate electrode 115 is formed on the source electrode 18, and a source electrode 127 and drain electrodes 128 and 131 are formed on the source and drain regions. MOSTFT1 drain and MOST
The gate of the FT2 is connected via the drain electrode 128 and the drain electrode 131 of the MOSTFT2.
And a capacitor C is formed via an insulating film 136, and the source electrode 127 of the MOSTFT 2 is an organic
It extends to the anode 144 of the L element.

Each MOSTFT is covered with an insulating film 130,
On the insulating film, for example, a green organic light emitting layer 132 (or a blue organic light emitting layer 133,
Further, a red organic light emitting layer (not shown) is formed, a cathode (first layer) 141 is formed so as to cover the organic light emitting layer, and a common cathode (second layer) 142 is formed on the entire surface.

In the organic EL display section having this structure, the organic EL light emitting layer is connected to the source of the current driving MOSTFT 2,
An organic EL light emitting layer is formed so as to cover the anode 144 attached to the surface of the substrate 111 such as glass, a cathode 141 is formed so as to cover the organic EL light emitting layer, and a cathode 142 is formed over the entire surface. Therefore, bottom emission 136 'is obtained. Further, the cathode covers the organic EL light emitting layer and the MOSTFT. That is, after forming, for example, a green light emitting organic EL layer on the entire surface by a vacuum heating evaporation method or the like, the green light emitting organic EL layer is formed.
The portion is formed by photolithography and dry etching, and a blue and red light-emitting organic EL portion is continuously formed in the same manner. Finally, a cathode (electron injection layer) 141 is entirely formed of a magnesium: silver alloy or aluminum: lithium alloy. Form. Since the entire surface is sealed with a cathode (electron injection layer) further formed, the invasion of moisture from the outside to the organic EL layer is particularly prevented by the cathode 142 deposited on the entire surface, and the deterioration of the organic EL layer which is weak to moisture and the electrode are prevented. Prevents oxidation, long life,
High quality and high reliability are possible (the same is true for the structural example I in FIG. 21 because the entire surface is covered with the anode). In addition, since the heat radiation effect is enhanced by the cathodes 141 and 142, a structural change (melting or recrystallization) of the thin film due to heat generation is reduced, and a long life, high quality, and high reliability can be achieved. In addition, since a high-precision, high-quality, full-color organic EL layer can be produced with high productivity, the cost can be reduced.

Further, as shown in FIG. 23C, a black mask portion (chromium, chromium dioxide, etc.) 140 is formed around each pixel portion.
Is formed, light leakage (such as crosstalk) can be prevented, and the contrast can be improved. Note that the black mask portion 140 is covered with a silicon oxide film 143 (this may be formed simultaneously with the gate insulating film 118 using the same material).

Next, the manufacturing process of the organic EL device will be described. First, as shown in FIG. 24A, a polycrystalline silicon thin film having a high crystallization rate and a large grain size is formed through the above-described steps. Source region 120 and channel region 117
After forming the drain region 121 and the bias catalyst C
A gate insulating film 118 is formed by a vapor phase growth method such as VD, and sputtering is performed using a Mo-Ta alloy or the like, and M is formed thereon by general-purpose photolithography and etching techniques.
The gate electrodes 115 of the OSTFTs 1 and 2 are formed.
A gate line connected to the gate electrode of the MOSTFT 1 is formed by sputtering film formation of an o-Ta alloy or the like and general-purpose photolithography and etching techniques. Then, after forming an overcoat film (silicon oxide or the like) 137 by a vapor phase growth method such as catalytic CVD, 1000 ° C., 10 ° C.
Activate ions by RTA treatment for ~ 30 seconds. MOSTF is formed by sputtering film formation of Al containing 1% Si and general-purpose photolithography and etching technology.
A drain electrode 131 of T2 and a _Vdd line are formed, and an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by a vapor phase growth method such as bias catalytic CVD.
To form

Next, as shown in FIG. 24B, the MOS is formed by general-purpose photolithography and etching techniques.
After opening the windows of the source / drain portion of the TFT 1 and the gate portion of the MOSTFT2, as shown in FIG.
The drain of FT1 and the gate of MOSTFT2 are 1% Si
A source line made of Al containing 1% Si and connected to the source of the MOSTFT 1 at the same time is formed. Then, an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film, etc.) 130 is formed, a window of the source portion of the MOSTFT 2 is opened by general-purpose photolithography and etching technology, and sputtering such as ITO and general-purpose photolithography are performed. And MOSTFT2 by etching technology
The anode 144 of the light emitting portion connected to the source portion of the light emitting device is formed.

Next, as shown in FIG. 24D, the organic light emitting layer 132 and the cathodes 141 and 142 are formed as described above.
To form

The constituent materials and forming method of each layer of the organic EL described below are applied to the example of FIG. 23, but may be similarly applied to the example of FIG.

In the case where a low molecular compound is used for the green light emitting organic EL layer, an I (contact) source which is in contact with a source portion of a current driving MOSTFT which is an anode (hole injection layer) on a glass substrate.
It is formed on the TO transparent electrode by a continuous vacuum heating evaporation method. 1) The hole transport layer is made of an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is made of tris (8-hydroxyxylino) Al which is a green light emitting material Complex (Alq), etc. 3) The electron transport layer is made of 1,3,4-oxadiazole derivative (OXD), 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, 10 to 30 nm thickness of a 10: 1 (atomic ratio) magnesium: silver alloy 10 to 30 nm thickness of an aluminum: lithium (concentration: 0.5 to 1%) alloy Here, silver has an adhesive property with an organic interface. 1 to 10 atomic% is added to magnesium for increasing, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a green pixel portion, a green pixel portion is formed.
Mask with photoresist and CCl _FourGas plasma
The aluminum of the electron injection layer which is the cathode by the etching:
Remove the lithium alloy, continuously electron transport layer, light emitting layer,
The low-molecular compound and the photoresist in the hole transport layer are acidified.
Removed by elementary plasma etching to form a green pixel part
You. At this time, the aluminum under the photoresist:
Photoresist is etched due to lithium alloy
There is no problem if it is done. At this time, the electron transport layer,
Layer and the hole transport layer
Area larger than the ITO transparent electrode of
Electron injection layer of the cathode 142 (magnesium: silver
Alloy, etc.).

Next, when the blue light-emitting organic EL layer is formed of a low-molecular compound, the blue light-emitting organic EL layer is continuously formed on the ITO transparent electrode in contact with the source of the current driving TFT which is the anode (hole injection layer) on the glass substrate. And formed by vacuum heating evaporation. 1) The hole transport layer is an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is a distyryl derivative such as DTVBi which is a blue light emitting material 3) The electron transport layer is composed of a 1,3,4-oxadiazole derivative (TAZ), a 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, 10 to 30 nm thickness of a 10: 1 (atomic ratio) magnesium: silver alloy 10 to 30 nm thickness of an aluminum: lithium (concentration: 0.5 to 1%) alloy Here, silver has an adhesive property with an organic interface. 1 to 10 atomic% is added to magnesium for increasing, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

In order to form a blue pixel portion, the blue pixel portion
Mask with photoresist and CCl _FourGas plasma
Of the electron injection layer which is the cathode in the etching: Li
Alloy, and the electron transport layer, light emitting layer,
Oxygen-transporting the low molecular weight compound and photoresist in the
It is removed by plasma etching to form a blue pixel portion. This
At the time of the photoresist under the aluminum: Lithium
The photoresist is etched
No problem. At this time, the electron transport layer, the light emitting layer,
The low-molecular compound layer of the hole transport layer is made of ITO of the hole injection layer.
Make the area larger than the transparent electrode and form it over the entire surface in a later process
Electron injection layer of the cathode 142 (magnesium: silver alloy, etc.)
And electrical shorts.

When the red light-emitting organic EL layer is formed of a low-molecular compound, the red light-emitting organic EL layer is continuously formed on the ITO transparent electrode in contact with the source of the current driving TFT which is the anode (hole injection layer) on the glass substrate. Formed by vacuum heating evaporation. 1) The hole transport layer is made of an amine compound (for example, a triarylamine derivative, an arylamine oligomer, an aromatic tertiary amine, etc.) 2) The light emitting layer is made of Eu (Eu (DBM)) which is a red light emitting material
₃ ) (Phen)) 3) The electron transport layer is made of a 1,3,4-oxadiazole derivative (OXD), a 1,2,4-triazole derivative (TA
Z) etc. 4) The electron injection layer serving as the cathode is preferably made of a material having a work function of 4 eV or less. For example, a 10: 1 (atomic ratio) magnesium: silver alloy having a thickness of 10 to 30 nm, an aluminum: lithium (concentration of 0.5 to 1%) alloy having a thickness of 10 to 30 nm, silver is used to increase the adhesion to an organic interface. 1 to 10 atomic% is added to magnesium, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization.

To form a red pixel portion, the red pixel portion
Mask with photoresist and CCl _FourGas plasma
Of the electron injection layer which is the cathode in the etching: Li
Alloy, and the electron transport layer, light emitting layer,
Oxygen-transporting the low molecular weight compound and photoresist in the
It is removed by plasma etching to form a red pixel portion. This
At the time of the photoresist under the aluminum: Lithium
The photoresist is etched
No problem. At this time, the electron transport layer, the light emitting layer,
The low-molecular compound layer of the hole transport layer is made of ITO of the hole injection layer.
Make the area larger than the transparent electrode and form it over the entire surface in a later process
Electron injection layer of the cathode 142 (magnesium: silver alloy, etc.)
And electrical shorts. After this, the common
The electron injection layer (magnesium: silver alloy, etc.) of the cathode 142
Formed over the entire surface.

The electron injection layer serving as a cathode is preferably made of a material having a work function of 4 eV or less. For example,
10 to 3 of 10: 1 (atomic ratio) magnesium: silver alloy
0 nm thick, or aluminum: lithium (concentration is 0.5
１1%) The thickness of the alloy is 10 to 30 nm. Here, silver is added to magnesium in magnesium in order to increase adhesiveness with an organic interface.
10 atomic% is added, and lithium is added to aluminum at a concentration of 0.5 to 1% for stabilization. Note that the film may be formed by sputtering.

Fourth Embodiment In this embodiment, the present invention is applied to a field emission type (field emission) display device (FED: Field Emission).
Display). An example of the structure and a manufacturing example are shown below.

<Structure Example I of FED> FIG.
As shown in (B) and (C), according to this structural example I,
The gate channel 117 and the source of the switching MOSTFT 1 and the current driving MOSTFT 2 are formed on a substrate 111 made of glass or the like by a polycrystalline silicon thin film having a high crystallization rate and a large grain size formed by the method described above according to the present invention. A region 120 and a drain region 121 are formed. Then, the gate electrode 11 is formed on the gate insulating film 118.
5. A source electrode 127 and a drain electrode 128 are formed on the source and drain regions. MOSTFT1
And the gate of the MOSTFT2 are connected via a drain electrode 128, and the MOSTFT2
A capacitor C is formed between the source electrode 127 and the source electrode 127 via an insulating film 136, and the drain region 121 of the MOSTFT 2 is extended as it is to the FEC (field emission cathode) of the FED element and functions as an emitter region 152. ing.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, an FEC gate lead electrode 150 is formed.
A metal shielding film 151 for grounding is formed of the same material and in the same step, and covers each MOSTFT. In the FEC, an emitter region 1 made of a polycrystalline silicon thin film is used.
An n-type polycrystalline silicon film 153 serving as a field emission emitter is formed on 52, and insulating films 118 and 13 are formed so as to have openings for partitioning into m × n emitters.
7, 136 and 130 are patterned, and a gate lead-out electrode 150 is deposited on the upper surface thereof.

A substrate 157 such as a glass substrate formed with a phosphor 156 having a back metal 155 as an anode is provided facing the FEC, and a high vacuum is maintained between the FEC and the FEC.

In the FEC having this structure, the n-type polycrystalline silicon film 153 grown on the polycrystalline silicon thin film 152 formed according to the present invention is exposed below the opening of the gate extraction electrode 150. , Each function as a thin-film type emitter that emits electrons 154. That is, the polycrystalline silicon thin film 152 serving as the base of the emitter
Is composed of grains having a large grain size (a grain size of 100 nm or more). When the n-type polycrystalline silicon film 153 is grown thereon by bias or non-bias catalytic CVD, etc. The crystalline silicon film 153 grows with a larger grain size, and is formed such that the surface has fine irregularities 158 that are advantageous for electron emission. At this time, a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, and an electron emitter (emitter) having a large number of fine projection structures (for example, carbon nanotubes) on the surface of a carbon thin film containing or not containing nitrogen.
It may be.

Therefore, since the emitter is of a surface emission type composed of a thin film, it can be easily formed, the emitter performance is stabilized, and the life can be extended.

A ground potential metal shielding film 151 (this metal shielding film is formed of a gate lead-out electrode 150) is placed on top of all active elements (including a peripheral driving circuit and a MOSTFT and a diode of a pixel display section). The same material (Nb, Ti / Mo, etc.) is formed in the same step, which is convenient for the process.) Therefore, the following (1),
The advantage of (2) can be obtained.

(1) The gas in the airtight container is the emitter 1
The electrons emitted from the electrons 53 are positively ionized and charged up on the insulating layer.
An unnecessary inversion layer is formed in the OSTFT, and an extra current flows through an unnecessary current path including the inversion layer.
Runaway of the emitter current occurs. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT and dropped to the ground potential, charge-up can be prevented, and runaway of the emitter current can be prevented.

(2) The phosphor 156 emits light due to the collision of the electrons emitted from the emitter 153, and this light generates electrons and holes in the gate channel of the MOSTFT, resulting in a leak current. However, since the metal shielding film 151 is formed on the insulating layer on the MOSTFT, the MOST
Light incidence on the FT is prevented, and no operation failure of the MOSTFT occurs.

In addition, biased or non-biased catalytic CVD
As a result, an electron emitter such as an n-type polycrystalline silicon film is formed at least continuously to the drain region of the polycrystalline silicon MOSTFT. Characteristic becomes possible.

If the electron emitter (emitter) region of one pixel display section is divided into a plurality of parts and each of them is connected to a MOSTFT of a switching element, one MOS
Even if the TFT fails, the other MOSTFT operates, so that one pixel display unit always emits electrons, so that high quality, high yield, and cost reduction can be achieved. or,
Among these MOSTFTs, there is no problem with the MOSTFT having an electrically open defect,
Since TFTs can be separated by laser repair, high quality, high yield, and cost reduction can be achieved.

On the other hand, in the conventional FED, since a silicon single crystal substrate is used, the substrate cost is high, and it is difficult to increase the area over the wafer size. It has been proposed to form an electron emitter by forming a conductive polycrystalline silicon film on the cathode electrode surface by low pressure CVD or the like and forming a crystalline diamond film on the surface by plasma CVD or the like. Film forming temperature during low pressure CVD is 63
Since the temperature is as high as 0 ° C. and a glass substrate cannot be employed, cost reduction is difficult. Then, the polycrystalline silicon film formed by the low pressure CVD has a small particle size, and the crystalline diamond film on the polycrystalline silicon film also has a small particle size, so that the characteristics of the electron emitter are not good. Furthermore, since plasma CVD has insufficient reaction energy, it is difficult to obtain a good crystalline diamond film.
In addition, since the bonding property between the conductive polycrystalline silicon film and the transparent electrode or the cathode electrode of a metal such as Al, Ti, and Cr is poor,
Good electron emission characteristics cannot be obtained.

Next, the manufacturing process of the FED according to the present embodiment will be described. First, as shown in FIG.
17 are formed, MOSTFT1, MOSTFT2, and an emitter region are formed into islands by general-purpose photolithography and etching techniques.
A protective silicon oxide film 159 is formed on the entire surface by a VD method or the like.

Next, in order to optimize V _th by controlling the gate channel impurity concentration of the MOSTFTs 1 and 2,
The whole surface is doped with boron ions 83 at a dose of 5 × 10 ¹¹ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 1 × 10 ¹⁷ atoms / cc.

Next, as shown in FIG. 26 (2), using the photoresist 82 as a mask, 1 × 10 5 phosphorus ions 79 are applied to the source / drain portions and the emitter regions of the MOSTFTs 1 and 2 by ion implantation or ion doping. ^Fifteen
doping at a dose of atoms / cm ² , 2 × 1
After setting the donor concentration to 0 ²⁰ atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the silicon oxide film for protecting the emitter region is removed by general-purpose photolithography and etching techniques.

Next, as shown in (3) of FIG. 26, monosilane and a dopant such as PH ₃ are mixed at an appropriate ratio using a polycrystalline silicon thin film 152 for forming an emitter region by bias or non-bias catalytic CVD as a seed. The surface has fine irregularities 158, and the dopant is, for example, 5 × 1
An n-type polycrystalline silicon film 153 containing 0 ²⁰ to 1 × 10 ²¹ atoms / cc is formed in the emitter region to a thickness of 1 to 5 μm, and at the same time, the other silicon oxide film 159 and the n-type amorphous silicon The membrane 160
It is formed to a thickness of 5 μm.

Next, as shown in FIG. 26D, the amorphous silicon film 160 is selectively etched away by the action of the hydrogen-based active species during the above-described catalytic AHA treatment, and the silicon oxide film 159 is etched. Gate insulating film (silicon oxide film etc.) by catalytic CVD etc. after removal
Form 118.

Next, as shown in (5) of FIG. 27, the gate electrodes 115 of the MOSTFTs 1 and 2 are formed using a heat-resistant metal such as a Mo-Ta alloy by a sputtering method.
After a gate line connected to the gate electrode of the FT1 is formed and an overcoat film (silicon oxide film or the like) 137 is formed, ion activation treatment such as RTA treatment is performed at 1000 ° C. for 10 to 20 seconds. Then, after opening the source window of the MOSTFT 2, Mo-Ta by sputtering is used.
The source electrode 12 of the MOSTFT 2 is made of a heat-resistant metal such as an alloy.
7 and an earth line are formed. Furthermore, plasma CV
D. Overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by catalytic CVD or the like.

Next, as shown in (6) of FIG.
Source / drain part of OSTFT1 and MOSTFT2
Of the gate of the MOSTFT1 and the gate of the MOSTFT2 are connected to the Al wiring 12 containing 1% Si.
8 and at the same time, a source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.

Next, as shown in FIG. 27 (7), after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130, a GND line window is opened, As shown in (8), the gate extraction electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode portion is opened to expose the emitter 153. At the same time as cleaning with a hydrogen-based active species, fine irregularities are made remarkable by a selective etching action of the hydrogen-based active species.

<Structure Example II of FED> FIG.
As shown in (B) and (C), according to this structural example II,
On a substrate 111 made of glass or the like, similar to the above structure example I,
The gate channel 117, the source region 120, and the drain region 121 of the switching MOSTFT1 and the current driving MOSTFT2 are formed by the polycrystalline silicon thin film having a high crystallization rate and a large grain size formed by the above-described method according to the present invention. Have been. Then, the gate insulating film 1
, A source electrode 127 and a drain electrode 128 are formed on the source and drain regions. The drain of the MOSTFT1 and the gate of the MOSTFT2 are connected via a drain electrode 128, and a capacitor C is formed between the drain of the MOSTFT2 and the source electrode 127 of the MOSTFT2 via an insulating film 136.
The drain region 121 of the OSTFT 2 extends as it is to the FEC (field emission cathode) of the FED element, and functions as the emitter region 152.

Each MOSTFT is covered with an insulating film 130,
On this insulating film, an FEC gate lead electrode 150 is formed.
A metal shielding film 151 for grounding is formed of the same material and in the same step, and covers each MOSTFT. In the FEC, an emitter region 1 made of a polycrystalline silicon thin film is used.
An n-type polycrystalline diamond film 163 serving as a field emission emitter is formed on 52, and insulating films 118, 1 are formed so as to have openings for partitioning into m × n emitters.
37, 136 and 130 are patterned, and a gate extraction electrode 150 is attached on the upper surface thereof.

A substrate 157 such as a glass substrate formed with a phosphor 156 having a back metal 155 as an anode is provided opposite to the FEC, and a high vacuum is maintained between the substrate and the FEC.

In the FEC having this structure, an n-type polycrystalline diamond film 163 grown on a polycrystalline silicon thin film 152 formed according to the present invention is exposed below the opening of the gate lead electrode 150, and this is exposed. Each electronic 154
Function as a thin-film emitter that emits light. In other words, since the polycrystalline silicon film 152 serving as the base of the emitter is composed of grains having a large grain size (a grain size of 100 nm or more), the n-type polycrystalline diamond film 163 is used as a seed on the catalyst to form a catalyst. When grown by CVD or the like, the polycrystalline diamond film 163 also grows with a large grain size, and the surface is formed so as to generate fine irregularities 168 advantageous for electron emission. At this time, an electron emitter (emitter) having a large number of fine projection structures (for example, carbon nanotubes) on the surface of a carbon thin film containing or not containing nitrogen and a carbon thin film containing or not containing nitrogen.
It may be.

Therefore, since the emitter is of a surface emission type composed of a thin film, it can be easily formed, the emitter performance is stabilized, and the life can be extended.

A ground potential metal shielding film 151 (this metal shielding film is formed of a gate lead-out electrode 150) is placed on top of all active elements (including a peripheral driving circuit and a MOSTFT and a diode of a pixel display section). The same material (Nb, Ti / Mo, etc.) is formed in the same step, which is convenient for the process.) As described above, the metal shielding film 151 is formed on the insulating layer on the MOSTFT as described above. To the ground potential to prevent charge-up, to prevent runaway of the emitter current.
Since the metal shielding film 151 is formed on the insulating layer on the FT, light is prevented from being incident on the MOSTFT.
Does not occur.

Next, the manufacturing process of this FED will be described. First, as shown in FIG. 29 (1), a polycrystalline silicon thin film 117 is formed on the entire surface through the above-described steps, and then general-purpose photolithography and An island is formed in the MOSTFT1 and MOSTFT2 and the emitter region by an etching technique, and a protective silicon oxide film 159 is formed on the entire surface by plasma CVD, catalytic CVD or the like.

Next, in order to optimize V _th by controlling the gate channel impurity concentration of the MOSTFTs 1 and 2,
The whole surface is doped with boron ions 83 at a dose of 5 × 10 ¹¹ atoms / cm ² by ion implantation or ion doping to set an acceptor concentration of 1 × 10 ¹⁷ atoms / cc.

Next, as shown in FIG. 29 (2), using the photoresist 82 as a mask, phosphorus ions 79 are implanted into the source / drain portions and the emitter regions of the MOSTFTs 1 and 2 by 1 × 10 5 by ion implantation or ion doping. ^Fifteen
doping at a dose of atoms / cm ² , 2 × 1
After setting the donor concentration to 0 ²⁰ atoms / cc and forming the source region 120, the drain region 121, and the emitter region 152, the silicon oxide film for protecting the emitter region is removed by general-purpose photolithography and etching techniques.

Next, as shown in (3) of FIG. 29, monosilane, methane (CH ₄ ) and an appropriate ratio of dopant are used as seeds with the polycrystalline silicon thin film 152 forming the emitter region by bias or non-bias catalytic CVD. After mixing, an n-type polycrystalline diamond film 163 having fine irregularities 168 on the surface is formed in the emitter region. At the same time, an n-type amorphous diamond film 170 is formed on the other silicon oxide film 159 and the glass substrate 111.

Next, as shown in (4) of FIG. 29, the amorphous diamond film 170 is selectively etched away by the action of the hydrogen-based active species during the above-described catalytic AHA treatment, and the silicon oxide film 159 is etched. After the removal, a gate insulating film (silicon oxide film or the like) 118 is formed by catalytic CVD or the like.

Next, as shown in FIG. 30 (5), the gate electrodes 115 of the MOSTFTs 1 and 2 are formed using a heat-resistant metal such as a Mo—Ta alloy by a sputtering method.
After a gate line connected to the gate electrode of the FT1 is formed and an overcoat film (silicon oxide film or the like) 137 is formed, ion activation treatment such as RTA at 1000 ° C. for 10 to 20 seconds is performed. Thereafter, after opening the window of the source of the MOSTFT 2, the source electrode 127 and the ground line of the MOSTFT 2 are formed of a heat-resistant metal such as a Mo-Ta alloy by a sputtering method. Further, an overcoat film (silicon oxide / silicon nitride laminated film) 136 is formed by plasma CVD, catalytic CVD, or the like.

Next, as shown in (6) of FIG.
Source / drain part of OSTFT1 and MOSTFT2
Of the gate of the MOSTFT1 and the gate of the MOSTFT2 are connected to the Al wiring 12 containing 1% Si.
8 and at the same time, a source electrode of the MOSTFT 1 and a source line 127 connected to the source are formed.

Next, as shown in FIG. 30 (7), after forming an overcoat film (silicon oxide / phosphine silicate glass / silicon nitride laminated film) 130, the window of the GND line is opened and the window shown in FIG. As shown in (8), the gate lead-out electrode 150 and the metal shielding film 151 are formed by etching after Nb deposition, and the field emission cathode portion is opened to expose the emitter 163. At the same time as cleaning with active species, fine irregularities are made more pronounced by the selective etching action of active species such as hydrogen.

In the above, when forming the polycrystalline diamond film 163, the carbon-containing compound used as a source gas is, for example, 1) a paraffinic hydrocarbon such as methane, ethane, propane or butane, 2) acetylene. , Allylene-based acetylene-based hydrocarbons 3) olefin-based hydrocarbons such as ethylene, propylene, butylene 4) di-olefin-based hydrocarbons such as butadiene 5) cyclopropane, cyclobutane, cyclopentane,
Alicyclic hydrocarbons such as cyclohexane 6) Aromatic hydrocarbons such as cyclobutadiene, benzene, toluene, xylene and naphthalene 7) Ketones such as acetone, diethyl ketone and benzophenone 8) Alcohols such as methanol and ethanol 9) Trimethylamine And amines such as triethylamine. 10) It may be a substance consisting of only carbon atoms such as graphite, coal, coke, etc., and these may be used alone or in combination of two or more.

Further, usable inert gases are, for example, argon, helium, neon, krypton, xenon and radon. As the dopant, for example, a compound containing boron, lithium, nitrogen, phosphorus, sulfur, chlorine, arsenic, selenium, beryllium, or a simple substance can be used, and the doping amount may be 10 ¹⁶ atoms / cc or more.

Fifth Embodiment In the present embodiment, the present invention is applied to a solar cell as a photoelectric conversion device. The production example is shown below.

First, as shown in FIG. 31A, after forming a base protective film (not shown) on a metal substrate 111 such as stainless steel by the above-described bias or non-bias catalytic CVD method, etc. Amorphous or microcrystalline silicon thin film 10 containing particulate SiO _x or SiN _y product
OA is formed.

Next, as shown in FIG. 31B, the silicon thin film 100A is
Is transformed into a silicon ultrafine particle layer 100B.

Next, as shown in FIG. 31C, the silicon ultrafine particle layer 1 is formed by the above-described catalytic CVD method or the like.
An n-type polycrystalline silicon film 7 is formed using 00B as a seed. This n-type polycrystalline silicon film 7 may be formed by the above-mentioned multi-catalyst AHA treatment, and contains a single crystal or a mixture of tin or another group IV element (Ge, Pb) having a high crystallization rate and a large particle diameter. 100 to 200 as an n-type polycrystalline silicon film
It is formed to a thickness of nm. An n-type impurity such as phosphorus is supplied to the n-type polycrystalline silicon film 7 together with monosilane as PH ₃ or the like, for example, from 1 × 10 ¹⁷ to 1 × 10 ¹⁸ atoms.
s / cc.

Next, as shown in FIG. 32 (4), n
An i-type polycrystalline silicon film 180 containing tin or another group IV element (Ge, Pb) alone or in a mixture by bias or non-bias catalytic CVD or the like using the polycrystalline silicon film 7 as a seed, Tin or other group IV element (Ge, P
b) A p-type polycrystalline silicon film 1 containing a single or mixture thereof
81 and the like are grown to form a photoelectric conversion layer.

For example, a biased or non-biased catalyst CV
D, tin hydride (SnH ₄ ) is mixed with monosilane in an appropriate ratio to grow an i-type tin-containing polycrystalline silicon film 180 having a large grain size to a thickness of 2 to 5 μm. -Type impurity boron (B ₂ H ₆ etc.) and tin hydride (Sn
H ₄ ) in an appropriate ratio, for example, 1 × 10 ¹⁷ to 1 × 1
A tin-containing polycrystalline silicon film 181 having a large grain size of p-type and containing 0 ¹⁸ atoms / cc is formed to a thickness of 100 to 200 nm. At this time, tin or other group IV element (Ge, Pb) alone or in a mixture, for example, tin is added to each film at 1 × 10 4
¹⁶ atoms / cc or more, preferably 1 × 10 ¹⁸ to 1 ×
By containing 10 ²⁰ atoms / cc, the crystal irregularity and stress existing at the crystal grain boundaries are reduced, so that the carrier mobility can be improved (this is because the n-type or p-type polycrystalline silicon film 7, 181 is similarly formed).

Also, the above-described multi-catalyst AHA treatment may be performed. For example, biased or non-biased catalytic CVD
The n-type or p-type tin-containing polycrystalline silicon thin film in 20 to
After growing to a thickness of 50 nm, a catalytic AHA treatment is performed, and an n-type or p-type tin-containing polycrystalline silicon film is grown to a thickness of 20 to 50 nm by biased or non-biased catalytic CVD,
After the treatment with the catalyst AHA, further bias or non-bias catalyst C
VD is applied to the n-type or p-type tin-containing polycrystalline silicon thin film.
After growing the film to a thickness of 0 to 50 nm, a film may be formed by a method of repeating the respective processes a required number of times such that the catalyst AHA process is performed (this is the same for the i-type polycrystalline silicon film 180). By this method, a tin-containing polycrystalline silicon film having a higher crystallization rate and a larger grain size can be formed. In addition, a high-speed film formation may be performed by increasing the supply amount of the source gas during the film formation.

Next, as shown in FIG. 32 (5), a transparent layer is formed on the entire surface of the tin-containing polycrystalline silicon film having a high crystallization rate and a large grain size of the nip junction formed by the above method. Electrode 18
Form 2 For example, a transparent electrode 182 such as an ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) film for antireflection coating is formed to a thickness of 130 to 150 nm by a general-purpose sputtering technique. And on this,
Using a general-purpose sputtering technique, a comb-shaped electrode 183 of silver or the like is formed in a predetermined area by using a metal mask by 100 to 15
It is formed to a thickness of 0 nm.

The above film does not necessarily need to contain tin or another group IV element, but can be manufactured in the same manner as described above. In addition to the above nip junction structure, a pin junction, a pn junction, an np
A structure such as bonding can be similarly manufactured.

In the solar cell according to this embodiment, a photoelectric conversion thin film having high carrier mobility and high conversion efficiency can be formed by the polycrystalline silicon film having a high crystallization rate and a large grain size according to the present invention. Since the surface texture structure and the back surface texture structure are formed, a photoelectric conversion thin film having a high light confinement effect and a high conversion efficiency can be formed. This is also
The present invention can be advantageously used not only for a solar cell but also for a thin-film photoelectric conversion device such as a photosensitive drum for electrophotography.

On the other hand, in this type of conventional photoelectric conversion device, an amorphous carbon thin film is formed by RF plasma CVD, VHF plasma CVD, or the like, and ultrafine carbon particles are formed by plasma hydrogen treatment. A large grain polycrystalline silicon film is formed as a nucleus for crystal growth. An n-type polycrystalline silicon layer, an i-type polycrystalline silicon active layer and a p-type polycrystalline silicon layer are continuously formed, and an ITO film is formed on the entire surface. And finally form a comb-shaped electrode,
A thin-film polycrystalline silicon solar cell having a thickness of about 2 μm has been obtained.

However, this conventional method cannot avoid the following disadvantages. 1) Since a crystalline silicon-based thin film formed at a low temperature by RF plasma CVD, VHF plasma CVD, or the like has low energy, the chemical decomposition reaction of the source gas and the plasma hydrogen treatment are likely to be insufficient, and the crystal grain size is small. Because it ’s small
Mobility is small, and excessive current due to local electrical short or leakage is likely to occur due to the large number of grain boundaries or pinholes, and when deposited to a thickness of several μm required as a photoelectric conversion layer. The internal stress and strain of the film increase,
In the worst case, there is a problem that the film is peeled off.
As a result, the production yield and the reliability of the photoelectric conversion layer are significantly reduced, which is a great obstacle to the practical use of a photoelectric conversion device including the same. 2) Since the plasma CVD method such as the RF plasma CVD and the VHF plasma CVD has low energy, the utilization efficiency of the source gas is as low as 5 to 10%. For this reason, productivity is low and cost reduction is difficult.

The embodiments of the present invention described above can be variously modified based on the technical concept of the present invention.

For example, the number of repetitions and each condition of the above-mentioned bias or non-bias catalytic CVD method and the catalytic AHA treatment may be variously changed, and the material of the substrate and the like to be used is not limited to the above.

The present invention also relates to an internal circuit such as a display unit, a peripheral driving circuit, a video signal processing circuit, and an MO such as a memory.
Although it is suitable for STFTs, it is also possible to form an active region of an element such as a diode and a passive region such as a resistor, a capacitance (capacitance), a wiring, and an inductance with a polycrystalline silicon thin film according to the present invention. It is possible.

[0280]

According to the present invention, as described above, when a polycrystalline semiconductor thin film is formed on a substrate, S
iO _x (0 <x ≦ 2) and / or SiN _y (0.1 <y <
Forming a lower crystalline semiconductor thin film containing a particulate product consisting of 1.4), bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst, and allowing the hydrogen-based active species generated thereby to produce the lower crystalline semiconductor; The semiconductor thin film is annealed to act on the semiconductor thin film to form silicon ultrafine particles, and the silicon ultrafine particles are used as seeds (nuclei) for crystal growth, and the semiconductor material thin film is vapor-phase grown. A remarkable function and effect as shown in 3) can be obtained.

(1) Since high-temperature hydrogen-based molecules, hydrogen-based atoms, active hydrogen ions, and other hydrogen-based active species are caused to act on the lower crystalline semiconductor thin film by spraying the catalyst AHA treatment, The following remarkable effects are exhibited by the addition of the heating of the heating catalyst body by radiant heat.

[0282] 1. In the catalyst AHA treatment, hydrogen is brought into contact with a high-temperature catalyst body (800 to 2000 ° C. lower than the melting point, for example, 1500 to 2000 ° C. for tungsten) under reduced pressure (for example, a hydrogen-based carrier gas pressure of 10 to 50 Pa). When a large amount of high-temperature active hydrogen-based species (hydrogen-based molecules / hydrogen-based atoms / activated hydrogen ions, etc.) are generated and sprayed onto an amorphous or microcrystalline silicon thin film formed on a substrate (however, the substrate temperature Is particularly 300 to 400 ° C.). Compared to conventional RF / VHF plasma hydrogen treatment or ECR plasma hydrogen treatment, a large amount of heat energy of high-energy, high-temperature hydrogen-based active species is efficiently transferred to the film or the like. Thus, the temperature of the film or the like is increased efficiently and uniformly. As a result, the amorphous silicon film, the microcrystalline silicon film, and the like are removed by etching of the amorphous structure silicon at a high etching rate by the reducing action of the hydrogen-based active species, and SiO _x is decomposed into Si, SiO, H ₂ O, and the like. In addition, SiN _y contained in the film is decomposed into Si and NH ₃ to efficiently form high-quality silicon ultrafine particles, which are effective as seeds for the next growth of polycrystalline silicon or the like. Can work to. At this time, the ultrafine silicon particles have a grain size of 1 nm or more, preferably 1 to 1 nm.
0 nm, the number is 1 / μm ² or more, preferably 1 to 10
It is desirable that the dots are scattered at 0 / μm ² .

[0283] 2. The catalyst AHA treatment is the same as the conventional RF / VH
Compared to F plasma hydrogen treatment and ECR plasma hydrogen treatment,
Amorphous silicon is etched at a high etching rate to form a large grain polycrystalline silicon film, and the carrier mobility thereof can be improved. That is, using the silicon ultrafine particles obtained by the catalyst AHA treatment as a seed, a semiconductor material thin film is easily grown thereon (as a polycrystalline silicon thin film) in a state where it is easily polycrystallized.
By the HA treatment and the vapor phase growth, the crystallization of the silicon film or the like vapor-grown on the above-mentioned polycrystalline silicon thin film is promoted by using the polycrystalline silicon thin film as a seed. A high-quality polycrystalline silicon thin film can be obtained. In other words, if the amorphous silicon film or the microcrystalline silicon film formed by, for example, biased or non-biased catalytic CVD, exists in the amorphous silicon film by the catalytic AHA treatment, this is selectively etched by the hydrogen-based active species. The silicon ultra-fine particles are formed by removing the silicon ultra-fine particles, and the silicon film to be vapor-grown thereon is easily formed into a polycrystalline silicon film by using the silicon ultra-fine particles of the base as seeds (nuclei). When the vapor phase growth is repeated, the thermal energy of the high-temperature hydrogen-based active species moves to the film and the like, and the temperature of the film and the like is increased, and amorphous silicon or microcrystalline silicon is reduced by the reduction action of the hydrogen-based active species. The polycrystalline silicon thin film is polycrystallized, and the polycrystalline silicon thin film is highly crystallized to form a polycrystalline silicon thin film having a high crystallization rate and a large grain size. Door can be. As a result, not only the top gate type but also the bottom gate type and the dual gate type MOS TFT can obtain a polycrystalline silicon thin film having a high crystallinity with a high carrier (electron / hole) mobility and a large grain size. In addition, a high-speed, high-current-density semiconductor device, an electro-optical device, and a high-efficiency solar cell using the high-performance semiconductor thin film such as polycrystalline silicon can be manufactured.

[0284] 3. The catalytic AHA treatment is different from the conventional plasma hydrogen treatment in that when silicon oxide is present on amorphous silicon, microcrystalline silicon, or polycrystalline silicon thin film formed on a substrate, in a film, or at a grain boundary, SiO 2 reacts with the silicon oxide. Is formed and is efficiently evaporated and removed, so that silicon oxide in the film or the like can be efficiently reduced / removed, and carrier mobility can be improved.

[0285] 4. In the catalyst AHA treatment, cleaning with hydrogen-based active species such as activated hydrogen ions (reduction and removal of adsorbed gas and organic residue on a substrate or the like) is possible, and the catalyst body is also less likely to be oxidized and deteriorated (as described above). The effect is
The same applies to the above-described bias or non-bias catalytic CVD because a hydrogen-based carrier gas is used.)

[0286] 5. In the catalytic AHA treatment, for example, silicon dangling bonds in the semiconductor film are eliminated by the hydrogenation of hydrogen-based active species such as activated hydrogen ions, and the characteristics are improved.

[0287] 6. During the catalytic AHA treatment, the carrier impurities present in the lower crystalline or polycrystalline semiconductor thin film are activated at a high temperature, and an optimum carrier impurity concentration is obtained in each region.

(2) Since the catalyst AHA treatment can be performed without generating plasma, there is no damage by plasma, and a simpler and less expensive apparatus can be realized as compared with plasma treatment.

(3) Even if the substrate temperature is lowered, the energy of the hydrogen-based active species is large, so that the desired silicon ultrafine particles can be obtained stably. Even when the temperature is lowered, the polycrystalline silicon thin film grows efficiently using the ultrafine silicon particles as seeds, so that a large-sized and inexpensive insulating substrate (glass substrate, heat-resistant resin substrate, etc.) having a low strain point can be used. However, cost reduction becomes possible.

[Brief description of the drawings]

FIG. 1 shows a MOSTFT according to a first embodiment of the present invention.
3 is a cross-sectional view showing the manufacturing process in order of steps.

FIG. 2 is a cross-sectional view showing a manufacturing process in the order of steps.

FIG. 3 is a sectional view showing the manufacturing process in the order of steps.

FIG. 4 is a sectional view showing the manufacturing process in the order of steps.

FIG. 5 is a schematic cross-sectional view of one state of an apparatus for catalytic CVD and catalytic AHA treatment used in the production.

FIG. 6 is a schematic sectional view of the same device in another state.

FIG. 7 is a timing chart of a gas flow rate during processing using this apparatus.

FIG. 8 is a schematic diagram of a gas supply system of the apparatus.

FIG. 9 is a graph showing a comparison of Raman spectra of the semiconductor films obtained by this processing.

FIG. 10 is a graph showing the crystallization ratios of the semiconductor thin films in comparison.

FIG. 11 is a graph showing the comparison of the heavy metal concentration in the membrane depending on the purity of the catalyst and the support.

FIG. 12 is a cross-sectional view showing a manufacturing process of the LCD according to the second embodiment of the present invention in the order of steps.

FIG. 13 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 14 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 15 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 16 is a perspective view showing a schematic layout of the whole LCD.

FIG. 17 is an equivalent circuit diagram of the LCD.

FIG. 18 is a cross-sectional view showing another manufacturing process of the LCD in the order of steps.

FIG. 19 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 20 is a cross-sectional view showing various types of MOSTFTs of the LCD.

FIG. 21 is an equivalent circuit diagram (A) of an essential part of the organic EL display device according to the third embodiment of the present invention, an enlarged sectional view (B) of the essential part, and a sectional view (C) of the peripheral part of the pixel. It is.

FIG. 22 is a cross-sectional view showing a manufacturing process of the organic EL display device in the order of steps.

FIG. 23 is an equivalent circuit diagram (A) of a main part of another organic EL display device, an enlarged cross-sectional view (B) of the main part, and a cross-sectional view (C) of a peripheral part of the pixel.

FIG. 24 is a cross-sectional view showing a manufacturing process of the organic EL display device in the order of steps.

FIG. 25 is an equivalent circuit diagram (A) of a main part of an FED according to a fourth embodiment of the present invention, an enlarged sectional view (B) of the main part, and a schematic plan view (C) of the main part.

FIG. 26 is a cross-sectional view showing a manufacturing process of the FED in the order of steps.

FIG. 27 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 28 is an equivalent circuit diagram (A) of a main part of another FED,
It is the expanded sectional view (B) of the principal part, and the top view (C) of the principal part.

FIG. 29 is a cross-sectional view showing a manufacturing process of the FED in the order of steps.

FIG. 30 is a cross-sectional view showing the manufacturing process in the order of steps.

FIG. 31 is a sectional view illustrating the manufacturing process of the solar cell according to the fifth embodiment of the present invention in the order of steps.

FIG. 32 is a cross-sectional view showing the manufacturing process in the order of steps.

[Explanation of symbols]

1, 61, 98, 111, 157: substrate, 7, 67: polycrystalline silicon thin film, 14, 67, 117: channel, 15, 75, 102, 105, 115: gate electrode, 8, 68, 103, 104 , 106, 118 ... gate insulating film, 20, 21, 80, 81, 120, 121 ...
n ⁺ type source or drain regions, 24, 25, 84, 8
5 ... p ⁺ type source or drain region, 27, 28, 8
6, 92, 130, 136, 137 ... insulating films, 29, 3
0, 87, 88, 89, 90, 91, 93, 97, 12
7, 128, 131 ... electrode, 40 ... source gas, 42 ... shower head, 44 ... film forming chamber, 45 ... susceptor, 46 ...
Catalyst body, 47 ... shutter, 48 ... catalyst body power supply, 94,
96: alignment film, 95: liquid crystal, 99: color filter layer,
100A: amorphous or microcrystalline silicon thin film containing a particulate product of SiO _x or SiO _y , 100B: ultrafine silicon particle layer, 100 ′, 140: black mask layer, 1
32, 133 ... organic light emitting layer, 134, 135, 144 ...
Anode, 138, 141, 142, 171 ... cathode, 150
.., Gate extraction electrode (gate line), 151, shielding film, 152, emitter, 153, n-type polycrystalline silicon film, 155, back metal, 156, phosphor, 158,
168: fine irregularities; 163, n-type polycrystalline diamond film; 180, i-type polycrystalline silicon film; 181, p-type polycrystalline silicon film; 182, transparent electrode; 183, comb-type electrode

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/20 H01L 21/20 5F051 21/205 21/205 5F052 27/08 331 27/08 331E 5F110 29 / 786 29/78 618A 21/336 618B 31/04 618F 618E 619B 627G 31/04 A X F-term (reference) 2H092 JA26 KA04 KA05 KB25 MA05 MA08 MA15 MA19 MA27 MA29 MA30 NA26 NA27 NA29 PA02 PA06 PA08 PA09 QA07 4K030 A AA18 BA09 BA29 BA37 BA40 BA44 BB04 CA06 DA09 FA17 LA15 LA16 LA18 5C094 AA07 AA08 AA25 AA43 AA53 BA03 BA12 BA27 BA32 BA34 BA43 CA19 CA24 DA09 DA13 DB01 DB04 EA04 EA05 EA10 EB02 ED03 ED15 FA01 AC14 GB01 FB05 AC15 AC16 AC17 AC18 AC19 AD07 AE01 AE29 AF07 BB08 BB16 CA09 CA15 DP05 EB02 EC01 5F048 AA09 AB1 0 AC04 BA16 BC06 BG07 5F051 AA03 CB12 DA03 DA04 FA02 FA04 GA02 5F052 AA11 CA04 CA10 DA02 DB01 GA02 JA01 KA05 KA06 5F110 AA01 AA16 AA19 AA28 BB02 BB04 CC02 CC08 DD01 DD02 DD03 DD13 DD14 DD17 EE04 EE23 EE04 EE04 FF10 FF23 FF29 GG01 GG02 GG03 GG13 GG14 GG15 GG16 GG19 GG25 GG32 GG33 GG34 GG44 GG45 GG51 GG52 HJ01 HJ04 HJ12 HJ13 HJ23 HL03 QNN NN06 NN03 NN04 NN05 NN04 NN05 NN04 NN05 NN04 NN05

Claims (50)

[Claims] When forming a polycrystalline semiconductor thin film on a substrate, SiO _x (0 <x ≦ 2) and / or Si
Forming a lower crystalline semiconductor thin film containing a particulate product comprising N _y (0.1 <y <1.4); and contacting hydrogen or a hydrogen-containing gas with the heated catalyst.
A step of forming the silicon ultra-fine particles by applying the hydrogen-based active species generated thereby to the lower crystalline semiconductor thin film to anneal, and growing the semiconductor material thin film in a vapor phase by using the silicon ultra-fine particles as a nucleus of crystal growth. Forming a polycrystalline semiconductor thin film through the steps described above. 2. When manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a substrate, SiO _x (0 <x ≦ 2) and / or Si
Forming a lower crystalline semiconductor thin film containing a particulate product comprising N _y (0.1 <y <1.4); and contacting hydrogen or a hydrogen-containing gas with the heated catalyst.
A step of forming the silicon ultra-fine particles by applying the hydrogen-based active species generated thereby to the lower crystalline semiconductor thin film to anneal, and growing the semiconductor material thin film in a vapor phase by using the silicon ultra-fine particles as a nucleus of crystal growth. And a step of obtaining the polycrystalline semiconductor thin film through a process. 3. The method according to claim 1, wherein the lower crystalline semiconductor thin film is formed by a vapor deposition method, and the semiconductor material thin film is formed by a vapor deposition method. 4. A raw material gas and at least a part of hydrogen or a hydrogen-containing gas are brought into contact with a heated catalyst to be catalytically decomposed, and reactive species such as radicals and ions generated thereby are deposited on a substrate. The method according to claim 1, wherein the lower crystalline semiconductor thin film and / or the semiconductor material thin film is vapor-grown. 5. After the vapor-phase growth of the semiconductor material thin film, hydrogen or a hydrogen-containing gas is brought into contact with a heated catalyst to generate high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, etc. The method according to claim 4, wherein annealing is performed by causing a hydrogen-based active species to act on the semiconductor material thin film, and if necessary, vapor-phase growth of the same semiconductor material thin film as the semiconductor material thin film and the annealing are repeated. 6. A method in which at least a part of the hydrogen or the hydrogen-containing gas is brought into contact with the heating catalyst, and a high-temperature hydrogen-based molecule, a hydrogen-based atom, an activated hydrogen ion or other hydrogen-based active species is generated. 3. The method according to claim 1, wherein the annealing is performed by acting on the lower crystalline semiconductor thin film or the semiconductor material thin film. 7. The heated catalyst body is brought into contact with at least a part of a raw material gas and a hydrogen-based carrier gas to be catalytically decomposed, and the generated reactive species such as radicals and ions are heated. After the lower crystalline semiconductor thin film or the semiconductor material thin film is deposited on a substrate and vapor-phase grown, the supply of the source gas is stopped, and at least a part of the hydrogen-based carrier gas is heated to the heated catalyst. The method according to claim 1, wherein the annealing is performed by causing the high-temperature hydrogen-based molecules, hydrogen-based atoms, activated hydrogen ions, or other hydrogen-based active species generated thereby to act on the lower crystalline semiconductor thin film or the semiconductor material thin film. The method described in 2 or 5. 8. The method according to claim 7, wherein a supply amount of hydrogen or a hydrogen-containing gas during the annealing is set to be larger than a supply amount of hydrogen or a hydrogen-containing gas during the vapor phase growth. 9. The catalyst body is made of at least one material selected from the group consisting of tungsten, tria-containing tungsten, molybdenum, platinum, palladium, vanadium, silicon, alumina, ceramics to which metal is attached, and silicon carbide. A method according to claim 1 or 2, wherein the method comprises: 10. The purity of the catalyst and the support supporting the catalyst is 99.99 wt% or more, preferably 99.99 wt%.
3. The method according to claim 1, wherein the amount is 9 wt% or more. 11. The lower crystalline semiconductor thin film is made of amorphous silicon, microcrystalline silicon-containing amorphous silicon film, microcrystalline silicon (amorphous silicon-containing microcrystalline silicon) film, amorphous silicon and microcrystalline silicon-containing polycrystalline silicon film, amorphous germanium. , microcrystalline germanium-containing amorphous germanium film, shown in microcrystalline germanium (amorphous germanium containing microcrystalline germanium) film, an amorphous germanium and microcrystalline germanium containing polycrystalline germanium film, or _{Si x Ge 1-x (0} <x <1) 3. The method according to claim 1, wherein the amorphous silicon germanium film is formed and the hydrogen or the hydrogen-containing gas is hydrogen or a mixed gas of hydrogen and an activated gas. 4. 12. The polycrystalline semiconductor thin film comprises a polycrystalline silicon thin film, a polycrystalline germanium thin film, a polycrystalline silicon-germanium thin film, a polycrystalline silicon carbide thin film, and the hydrogen or the hydrogen-containing gas is 3. The method according to claim 1, comprising hydrogen or a mixed gas of hydrogen and an inert gas.
The method described in. 13. The method according to claim 12, wherein the semiconductor thin film contains at least one kind of a group IV element such as tin in an appropriate amount, and the annealing is performed in this state. 14. A thin film insulated gate field effect transistor according to claim 1, wherein said polycrystalline semiconductor thin film forms a channel, a source and a drain region, a wiring, a resistor, a capacitor or an electron emitter. Way. 15. After forming the channel, source, and drain regions, a hydrogen-based active species generated by bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst is applied to these regions. 14. The method according to 14. 16. The polycrystalline semiconductor thin film, wherein the crystal grain size is reduced from the gate insulating film side toward the outside to increase the density, or the polycrystalline semiconductor thin film or the amorphous semiconductor thin film containing microcrystals is used as the polycrystalline semiconductor thin film. The method according to claim 1, wherein the conductive semiconductor thin film is coated. 17. The method according to claim 16, wherein the alpha-mos semiconductor thin film or the microcrystalline-containing amorphous semiconductor thin film is removed to form source and drain electrodes in contact with the polycrystalline semiconductor thin film. 18. A silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated circuit device. , Liquid crystal display,
Manufacturing thin films for organic or inorganic electroluminescent displays, field emission displays (FED) devices, light emitting polymer displays, light emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. 3. The method according to 1 or 2. 19. When manufacturing a semiconductor device, a solid-state imaging device, an electro-optical device, or the like having an internal circuit and a peripheral circuit, a channel, a source, and a drain region of a thin-film insulated gate field-effect transistor constituting at least a part thereof are formed. The method according to claim 18, wherein the method is formed by the polycrystalline semiconductor thin film. 20. The method according to claim 19, further comprising a cathode or an anode connected to a drain or a source of the thin film insulated gate field effect transistor, respectively, below the organic or inorganic electroluminescent layer for each color. 21. The cathode also covers the active element including the thin-film insulated gate field-effect transistor, or the cathode or the anode is provided on each layer of the organic or inorganic electroluminescent layer for each color and on the entire surface between each layer. 21. The method of claim 20, wherein the method comprises manufacturing the device being deposited. 22. A black mask layer is formed between the organic or inorganic electroluminescent layers for each color.
The method according to claim 20. 23. An n-type polysilicon grown on the polycrystalline semiconductor thin film while connecting an emitter of the field emission display device to the drain of the thin film insulated gate field effect transistor via the polycrystalline semiconductor thin film. 20. A crystalline semiconductor film, a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, or a plurality of fine projection structures (for example, carbon nanotubes) formed on the surface of a carbon thin film containing or not containing nitrogen. The method described in. 24. The method according to claim 23, wherein a ground potential metal shielding film is formed on the active device including the thin film insulated gate field effect transistor. 25. The method according to claim 24, wherein the metal shielding film is formed by the same process using the same material as the gate extraction electrode of the field emission display device. 26. An apparatus for forming a polycrystalline semiconductor thin film on a substrate, comprising: SiO _x (0 <x ≦ 2) and / or SiN _y (0.1 <y
Means for forming a lower crystalline semiconductor thin film containing a particulate product comprising <1.4); hydrogen or a hydrogen-containing gas supply means; and means for supplying a source gas for a semiconductor material thin film to be the polycrystalline semiconductor thin film An apparatus for forming a polycrystalline semiconductor thin film, comprising: a catalyst body; a catalyst body heating means; and a substrate heating means. 27. An apparatus for manufacturing a semiconductor device having a polycrystalline semiconductor thin film on a base, comprising: SiO _x (0 <x ≦ 2) and / or SiN _y (0.1 <y
Means for forming a lower crystalline semiconductor thin film containing a particulate product comprising <1.4); hydrogen or a hydrogen-containing gas supply means; and means for supplying a source gas for a semiconductor material thin film to be the polycrystalline semiconductor thin film An apparatus for manufacturing a semiconductor device, comprising: a catalyst body; a catalyst body heating unit; and a substrate heating unit. 28. The apparatus according to claim 26, wherein the lower crystalline semiconductor thin film is formed by a vapor deposition method, and the semiconductor material thin film is formed by a vapor deposition method. 29. A raw material gas and at least a part of hydrogen or a hydrogen-containing gas are brought into contact with a heated catalyst body to be catalytically decomposed, and reactive species such as radicals and ions generated thereby are deposited on a substrate. Growing the lower crystalline semiconductor thin film and / or the semiconductor material thin film in vapor phase,
Apparatus according to claim 26 or 27. 30. A raw material gas and at least a part of hydrogen or a hydrogen-containing gas are brought into contact with the heated catalyst to decompose catalytically, and reactive species such as radicals and ions generated on the substrate are deposited on the substrate. After the vapor deposition of the lower crystalline semiconductor thin film or the semiconductor material thin film by deposition, the supply of the raw material gas is stopped, and at least a part of hydrogen or a hydrogen-containing gas is brought into contact with the heated catalyst body. Performing an annealing step of causing a hydrogen-based active species such as a high-temperature hydrogen-based molecule, a hydrogen-based atom, or an activated hydrogen ion to act on the lower crystalline semiconductor thin film or the semiconductor material thin film. In order to repeat the thin film annealing process and the semiconductor material thin film vapor phase growth process similar to the semiconductor material thin film, the raw material gas supply unit and the hydrogen or 30. The apparatus according to claim 29, further comprising control means for controlling the hydrogen-containing gas supply means. 31. The heating catalyst body is brought into contact with at least a part of the hydrogen or the hydrogen-containing gas, and a high-temperature hydrogen-based molecule, a hydrogen-based atom, an activated hydrogen ion or other hydrogen-based active species generated by the contact is generated. 3. The annealing is performed by acting on the lower crystalline semiconductor thin film or the semiconductor material thin film.
28. The apparatus according to 6 or 27. 32. The heated catalyst body is brought into contact with at least a part of a raw material gas and a hydrogen-based carrier gas to be catalytically decomposed, and the generated reactive species such as radicals and ions are heated. After the lower crystalline semiconductor thin film or the semiconductor material thin film is deposited on a substrate and vapor-phase grown, the supply of the source gas is stopped, and at least a part of the hydrogen-based carrier gas is heated to the heated catalyst. 27. Annealing is performed by contacting and causing a hydrogen-based active species such as a high-temperature hydrogen-based molecule, a hydrogen-based atom, or an activated hydrogen ion generated thereby to act on the lower crystalline semiconductor thin film or the semiconductor material thin film. , 27, 30 or 31. 33. The supply amount of hydrogen or a hydrogen-containing gas at the time of the annealing is larger than the supply amount of hydrogen or a hydrogen-containing gas during vapor phase growth of the lower crystalline semiconductor thin film or the semiconductor material thin film. The device described in 1. 34. The catalyst body is made of at least one material selected from the group consisting of tungsten, tungsten containing thoria, molybdenum, platinum, palladium, vanadium, silicon, alumina, a ceramic to which a metal is attached, and silicon carbide. Apparatus according to claim 26 or 27, wherein the apparatus is formed. 35. The purity of the catalyst and the support supporting the catalyst is 99.99 wt% or more, preferably 99.99 wt%.
28. The device according to claim 26 or 27, wherein the content is 9 wt% or more. 36. The low-crystalline semiconductor thin film is made of amorphous silicon, microcrystalline silicon-containing amorphous silicon film, microcrystalline silicon (amorphous silicon-containing microcrystalline silicon) film, amorphous silicon and microcrystalline silicon-containing polycrystalline silicon film, microcrystal. germanium-containing amorphous germanium film, an amorphous germanium, represented by the microcrystalline germanium (amorphous germanium containing microcrystalline germanium) film, an amorphous germanium and microcrystalline germanium containing polycrystalline germanium film, or _{Si x Ge 1-x (0} <x <1) 28. The apparatus according to claim 26, wherein the amorphous silicon germanium film is formed, and the hydrogen or the hydrogen-containing gas is hydrogen or a mixed gas of hydrogen and an activated gas. 37. The polycrystalline semiconductor thin film comprises a polycrystalline silicon thin film, a polycrystalline germanium thin film, a polycrystalline silicon-germanium film, a polycrystalline silicon carbide thin film, and the hydrogen or the hydrogen-containing gas is 27. A gas comprising hydrogen or a mixed gas of hydrogen and an inert gas.
7. The apparatus according to 7. 38. The apparatus according to claim 37, wherein the polycrystalline semiconductor thin film contains at least one kind of a group IV element such as tin in an appropriate amount, and the annealing is performed in this state. 39. The polycrystalline semiconductor thin film forms a channel, a source and a drain region of a thin film insulated gate field effect transistor, or a wiring, a resistor, a capacitor, an electron emitter, or the like. Equipment. 40. After the formation of the channel, source and drain regions, an active species or the like generated by bringing hydrogen or a hydrogen-containing gas into contact with a heated catalyst body is applied to these regions. The device described in 1. 41. In the polycrystalline semiconductor thin film, the crystal grain size is reduced from the gate insulating film side to the outside to increase the density, or the polycrystalline semiconductor thin film or the amorphous semiconductor thin film containing microcrystals is used as the polycrystalline semiconductor thin film. The device according to claim 26 or 27, which coats a conductive semiconductor thin film. 42. The method according to claim 41, wherein the amorphous semiconductor thin film or the microcrystalline-containing amorphous semiconductor thin film is removed to form source and drain electrodes in contact with the polycrystalline semiconductor thin film. 43. A silicon semiconductor device, a silicon semiconductor integrated circuit device, a silicon-germanium semiconductor device, a silicon-germanium semiconductor integrated circuit device, a compound semiconductor device, a compound semiconductor integrated circuit device, a silicon carbide semiconductor device, and a silicon carbide semiconductor integrated circuit device. , Liquid crystal display,
Manufacturing thin films for organic or inorganic electroluminescent displays, field emission displays (FED) devices, light emitting polymer displays, light emitting diode displays, CCD area / linear sensor devices, MOS sensor devices, solar cell devices. 28. The apparatus according to 26 or 27. 44. When manufacturing a semiconductor device, a solid-state imaging device, an electro-optical device, and the like having an internal circuit and a peripheral circuit, a channel, a source and a drain region of a thin-film insulated gate field-effect transistor constituting at least a part of these devices. 44. The device according to claim 43, wherein said device is formed by said polycrystalline semiconductor thin film. 45. The device according to claim 44, wherein a device having a cathode or an anode connected to a drain or a source of the thin-film insulated gate field effect transistor, respectively, is manufactured below the organic or inorganic electroluminescent layer for each color. The described device. 46. The cathode also covers an active element including the thin-film insulated gate field effect transistor, or the cathode or anode is provided on each layer of the organic or inorganic electroluminescent layer for each color and on the entire surface between each layer. 46. The device of claim 45, wherein the device manufactures the device being deposited. 47. forming a black mask layer between the organic or inorganic electroluminescent layers for each color,
An apparatus according to claim 45. 48. An emitter of the field emission display device is connected to the drain of the thin-film insulated gate field effect transistor via the polycrystalline semiconductor thin film, and the n-type polycrystalline semiconductor is grown on the polycrystalline semiconductor thin film. 45. The film is formed of a crystalline semiconductor film, a polycrystalline diamond film, a carbon thin film containing or not containing nitrogen, or a plurality of fine projection structures (for example, carbon nanotubes) formed on the surface of a carbon thin film containing or not containing nitrogen. The device described in 1. 49. The apparatus according to claim 48, wherein a ground potential shielding film is formed on the active element including the thin film insulated gate field effect transistor. 50. The device according to claim 49, wherein the shielding film is formed of the same material and in the same process as the gate extraction electrode of the field emission display device.