JPS62221160A - Manufacture of thin film transistor - Google Patents

Abstract

PURPOSE:To reduce an OFF current and to improve the quality of a TFT (thin film transistor) by a method wherein, when an a-Si layer is formed using a P-CVD (chemical vapor deposition) method, the adding quantity of diborane to silane is increased gradually, and the a-Si layer is deformed slowly into intrinsic conductive type from the original electronic conductive type. CONSTITUTION:An ON current is left unchanged and an OFF current is reduced by bringing the side close to a channel protecting layer 5 into the state of high resistance in a semiconductor layer 4. When the semiconductor layer 4 is formed by performing a P-CVD method, a trivalent element is introduced into SiH4 little, and the intrinsic conductive type is obtained at the final stage of the layer formation. To be more precise, a P-CVD method is performed by feeding SiH4 as reactive gas into a P-CVD device, the addition of diborane (B2H6) is started from the stage where about one half of the expected film thickness is grown. The resistivity of the growing a-Si layer is increased by gradually increasing the adding quantity of the diborane, and the intrinsic conductive body is obtained in the final stage. Through the above-mentioned procedures, the OFF current can be reduced by having the current value when the TFT is in OFF state is determined by the resistance of the semiconductor layer 4 which is contacted to the channel protecting layer 5.

Description

[Detailed Description of the Invention] [Summary] In order to improve the ON/OFF ratio of an inverted staggered thin film transistor, the amount of diborane added to silane is gradually increased when forming an amorphous silicon layer by plasma chemical vapor deposition. A method of forming an amorphous silicon layer in which the conductivity type of the amorphous silicon layer is gradually changed from an electronic conductivity type to an intrinsic conductivity type.

[Industrial application field]

The present invention relates to a method for manufacturing a thin film transistor with reduced OFF current.

Thin film transistors (abbreviated as TPT) are amorphous transistors formed on insulating substrates such as glass using thin film forming techniques such as plasma chemical vapor deposition (abbreviated as P-CVD) and vacuum evaporation.
A semiconductor layer made of silicon (hereinafter abbreviated as a-Si), an insulating layer made of silicon nitride or silicon dioxide, a metal layer, etc. are formed, and a fine pattern is selectively etched by combining this with photolithography. It is made by doing.

TPTs are used as switching elements in active matrix liquid crystal display panels and electroluminescent (abbreviated as EL) display panels because such technology allows transistor arrays to be formed over a wide area.

In such applications, each transistor must be defect-free and have an excellent ON/OFF ratio.

[Conventional technology]

Many of the TPTs used in active matrix type liquid crystal display panels and EL display panels are of the inverted staggered type.

FIG. 2 shows the cross-sectional structure of an inverted staggered TPT, and the manufacturing method will be briefly explained as follows.

Chrome (Cr) is deposited on the glass substrate 1 by vacuum evaporation method.
A gate electrode 2 is formed to have a thickness of about 1000 mm, and a gate electrode 2 is patterned using photolithography.

Next, a gate insulating layer 3 is formed by forming a silicon nitride layer (SiN layer) to a thickness of approximately 3000 nm using the P-CVD method.

Next, a-Si was deposited on top of this using the same P-CVD method.
After forming a semiconductor layer 4 with a thickness of approximately 1000 nm, silicon dioxide (
A St(h) layer is formed to a thickness of about 1000 nm, and is used as the channel protection layer 5.

Next, after forming a resist pattern directly above the gate electrode 2, chemical etching is performed to remove the Si02 layer leaving only the channel protective layer 5, and then the N+AII layer is formed using the p-cvo method in that state. The contact layer 6 is formed to a thickness of approximately 500 mm.

Next, after forming aluminum (An) to a thickness of about 1,000 by vacuum evaporation on this, a channel protective layer 5 is formed.
Dissolve and remove the resist on top.

Next, only the TPT formation region is coated with resist, and using this as a mask, the A1 layer, n+a-8i layer, a-SL layer, and Si
By sequentially etching the N layer and performing element isolation,
An inverted staggered TFT having a drain electrode 7 and a source electrode 8 on top is formed.

In such a staggered TPT, in the ON state, current flows between the source electrode 8 and the drain electrode 7 through the semiconductor layer 4 formed on the gate electrode 2, but it does not react with silane (SiH). The a-Si layer, which is formed by plasma decomposition as a gas, is a semiconductor whose conductivity type is n-type as it is, so even in the OFF state, the resistance between the electrodes is not sufficiently high (but not in the ON state).・The OFF ratio can only be about 6 to 7 digits, and there has been a demand for improvement.

[Problem that the invention seeks to solve]

As described above, the problem with conventional TPTs is that the OFF current is not small enough, so the ON-OFF ratio is not high during switching.

[Means for solving problems]

The above problem occurs when forming the a-3i layer by P-CVD in the manufacturing process of inverted staggered TPT.
This can be solved by gradually increasing the amount of diborane added to silane to gradually change the conductivity type of the a-5iN from the initial electronic conductivity type to the intrinsic conductivity type. .

[Effect]

The present invention is realized by increasing the resistance of the semiconductor layer 4 on the side closer to the channel protection layer 5 as a method of reducing the OFF current while leaving the ON current unchanged.

That is, when a voltage is applied between the gate electrode 2 and the ground, a channel is formed in the semiconductor layer 4, and the connection between the drain electrode 7 and the source electrode 8 is turned on, whereas when no voltage is applied to the gate electrode, it is turned off. However, Silane (S
Since the a-5i semiconductor layer obtained by plasma decomposition of iH4) originally exhibits n-type conductivity, albeit slightly, the OFF current cannot be made sufficiently low.

Therefore, the present invention introduces a trivalent element into Sin little by little when forming the semiconductor layer 4 by the P-CVD method.
It is designed to become an intrinsic conductive type at the stage where layer formation is completed.

That is, P-CVD was performed by supplying SiH4 as a reaction gas to the P-CVD apparatus, and when the film was grown to the planned film thickness of about 172 mm, the addition of diborane (B, 1I6) was started, and this amount was gradually increased. This increases the resistivity of the growing a-5i layer and makes it an intrinsic conductor in the final stage.

In this way, since the current value when the TPT is OFF is determined by the resistance of the semiconductor layer 4 in contact with the channel protection layer 5, the OFF ii current can be reduced.

〔Example〕

In manufacturing an inverted staggered TPT, until now the semiconductor layer has been formed by setting the substrate to be processed on which the gate insulating layer 3 has been formed into a P-CVD apparatus, using hydrogen (1 gas as a carrier, and SiHm at a concentration of 10%). Increase the flow rate to 200 (SCCM)
5standard Cubic Centimete
(abbreviation for r)).

Therefore, in the present invention, the introduction of BtHh at a concentration of 0.01% is started at the stage when a-5t has grown to a film thickness of about 500 people, which is the planned thickness of 172 of 1000 people, and at the final stage. Set the flow rate to 0. I changed it to OISCCM.

In this way, in the final stage, B
, I+ , the addition amount is 0.5ppo+, which is a −3i
is an intrinsic conductive type.

FIG. 1 shows an example showing the relationship between the amounts of SiH4, B, and H added to the processing time, and the horizontal axis shows the plasma CV
The processing time of D is shown, and the vertical axis shows the flow rate of SiH4 and B2H.
The flow rate of No. 4 is shown below.

The a-Si formed in this way has a thickness of 1000
When we measured the ON current and OFF current by applying a voltage of IOV to the gate electrode and 10 V to the drain electrode for a TPT with a gate length of 10 μm and a gate width of 200 μm, we found that the ON current was 10-'A, which is lower than the conventional TPT. However, the OFF current was 10-''A, an improvement of 2Hi compared to the conventional 10-''A.

As described above, by implementing the present invention, the ON/OFF ratio could be improved to eight digits.

〔Effect of the invention〕

As described above, by implementing the present invention, the OFF current can be reduced and the quality of TPT can be improved.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram showing the formation conditions of the a-St semiconductor layer, FIG. 2 is a cross-sectional structural diagram of an inverted staggered TPT. In the figure,

Claims (1)

[Claims] In the manufacturing process of inverted staggered thin film transistors, when forming an amorphous silicon layer by plasma chemical vapor deposition, the amount of diborane added to silane is gradually increased to change the conductivity type of the amorphous silicon layer to the original electron A method for manufacturing a thin film transistor, characterized in that the conductivity type is gradually changed to an intrinsic conductivity type.