JP3325664B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor and a method of manufacturing the same, and more particularly, to a polycrystalline silicon thin film transistor using a polycrystalline silicon layer as a semiconductor active layer and a method of manufacturing the same. In recent years, thin film transistors have been used as driving elements for active matrix type liquid crystal display panels and electroluminescence. In particular, liquid crystal display panels are used as thin liquid crystal televisions and information terminals, and polycrystalline silicon thin film transistors have attracted attention and are being developed for higher definition and higher performance.

[0002]

2. Description of the Related Art A conventional method for manufacturing a polycrystalline silicon thin film transistor will be described with reference to FIG. A semiconductor active layer 72 made of a polycrystalline silicon layer is formed on a transparent insulating substrate 70 made of a glass substrate or the like by a plasma CVD (vapor phase growth) method using, for example, a SiH ₄ (silane) gas as a source gas.

Next, after a gate electrode 76 is formed on the semiconductor active layer 72 via a gate insulating film 74, for example, a group V impurity atom is added to the semiconductor active layer 72 using the gate electrode 76 as a mask. N on the surface of the active layer 72
The + source region 78 and the n + drain region 80 are formed to face each other. Next, after depositing an interlayer insulating film 82 on the entire surface, a contact window is opened, and the n + type source region 78 and the n + type drain region 8 are opened through the contact window.
Then, a source electrode 84 and a drain electrode 86 connected to 0 are formed. Thus, a polycrystalline silicon thin film transistor as shown in FIG. 10 is manufactured.

[0004]

By the way, in the above-mentioned conventional method of manufacturing a polycrystalline silicon thin film transistor,
Plasma CV on a transparent insulating substrate 70 which is an amorphous substrate
When a polycrystalline silicon layer serving as the semiconductor active layer 72 is grown by the method D, the crystallinity is poor near the transparent insulating substrate 70 due to the influence of the underlayer, and the crystallinity is improved as the film thickness increases. And shows a saturation tendency at a certain film thickness.

In general, the semiconductor active layer 72 has poor crystallinity and is disadvantageous for use in devices as the mobility of carriers is small, and the better the crystallinity, the better the characteristics of the thin film transistor. The active layer 72 is grown to a thickness as large as about 500 nm. But,
When the thickness of the semiconductor active layer 72 is increased in order to improve the crystallinity, the same carrier as that of the channel conductivity type flows in a region far from the gate electrode 76 where voltage control is not effective. I will.

A liquid crystal display used as an information terminal is always in an environment where external light or backlight light is incident unless special measures such as forming a light-shielding film in a channel portion are used. External light enters the semiconductor active layer 72 from the back surface of the insulating substrate 70 or the like. In such a case, a light leakage current occurs, which causes an increase in the off current of the thin film transistor. However, the light leakage current increases as the thickness of the semiconductor active layer 72 increases.

As described above, if the film thickness of the semiconductor active layer 72 is small, good on-current characteristics cannot be obtained. If the film thickness is increased to improve the on-current characteristics, on the contrary, the off-current characteristics Deteriorates. Therefore, it has been difficult to obtain a high quality thin film transistor having a large on / off ratio. As a method for solving this problem, there is a method in which amorphous silicon is grown by a low pressure CVD method or the like, and then polycrystalline silicon is solid-phase grown by annealing with heat or laser.
In this case, the dependence of the crystallinity in the thickness direction is small, and the required characteristics can be satisfied even with a polycrystalline silicon layer having a thickness of about 50 nm to 100 nm.

However, since the annealing temperature is required to be about 600 ° C., an expensive substrate such as quartz must be used as a transparent insulating substrate usable at this temperature, which poses a cost problem. Further, although annealing by laser is possible at low temperature, it is difficult in terms of reproducibility to uniformly crystallize each element over a large area. Accordingly, an object of the present invention is to provide a thin film transistor capable of improving an on-current characteristic and greatly reducing an off-current, thereby increasing an on / off ratio, and a method for manufacturing the same.

[0009]

The object of the present invention is to provide a transparent insulating substrate, a semiconductor active layer formed on the transparent insulating substrate, and a source region and a drain region formed facing the surface of the semiconductor active layer. A thin film transistor comprising a gate electrode formed on the semiconductor active layer interposed between the source region and the drain region via a gate insulating film, wherein the semiconductor active layer is formed on the transparent insulating substrate. An off-current reducing layer made of the first polycrystalline silicon layer, and a second layer stacked on the off-current reducing layer.
A channel layer made of a polycrystalline silicon layer, wherein the source region and the drain region are respectively formed in the channel layer, and the off-current reduction layer is formed of water.
Using a raw material and atmosphere gas containing no silicon
The first polycrystalline silicon layer formed on the edge substrate
Wherein the channel layer is made of a material or atmosphere containing hydrogen.
A second gas formed on the off-current reduction layer using a gas;
This is achieved by a thin film transistor characterized by comprising a polycrystalline silicon layer .

[0010]

Also, a transparent insulating substrate, and the transparent insulating substrate
A semiconductor active layer formed thereon and a surface of the semiconductor active layer
Source and drain regions formed opposite to each other;
The half sandwiched between the source region and the drain region
Gate formed on conductor active layer via gate insulating film
A thin film transistor comprising:
A first active layer formed on the transparent insulating substrate;
An off-current reducing layer made of a crystalline silicon layer;
From the second polycrystalline silicon layer laminated on the flow reduction layer.
The source region and the drain
Are formed in the channel layer, respectively.
The off-current reducing layer is formed of a first polycrystalline silicon layer having an impurity-doped layer to which impurities of a channel conductivity type and a conductivity type are added, and the channel layer is made of a material containing hydrogen or an atmosphere gas. Ri Do from the second polycrystalline silicon layer formed on the impurity-doped layer by using the
The source region and the drain region in a channel layer;
The impurity-doped layer of the off-current reduction layer is 30 n
This is achieved by a thin film transistor having a spacing of at least m .

[0012] Further, the above-mentioned problems, a transparent insulating substrate, a semiconductor active layer formed on said transparent insulating substrate, a source region and a drain region formed relative to the semiconductor active layer surface, wherein the source In a method for manufacturing a thin film transistor comprising a gate electrode formed on a semiconductor active layer interposed between a region and the drain region with a gate insulating film interposed therebetween, on the transparent insulating substrate, a raw material containing no hydrogen, A first step of forming a first polycrystalline silicon layer using an atmospheric gas, and a step of forming hydrogen on the first polycrystalline silicon layer without exposing the surface of the first polycrystalline silicon layer to the atmosphere. A second step of forming a second polycrystalline silicon layer using a raw material or an atmosphere gas containing
The first and second polycrystalline silicon layers are patterned into a predetermined shape, and the off-current reducing layer made of the first polycrystalline silicon layer and the channel layer made of the second polycrystalline silicon layer are formed. A third step of forming the semiconductor active layer, which is sequentially stacked, and forming the gate electrode on the channel layer of the semiconductor active layer via the gate insulating film, and then sandwiching the gate electrode. Forming a source region and a drain region in the channel layer by adding a predetermined impurity to a semiconductor active layer.

A transparent insulating substrate; a semiconductor active layer formed on the transparent insulating substrate; a source region and a drain region formed facing the surface of the semiconductor active layer;
In a method for manufacturing a thin film transistor, comprising: a gate electrode formed on a semiconductor active layer interposed between the source region and the drain region via a gate insulating film; A first step of forming a first polycrystalline silicon layer of the opposite conductivity type, and exposing the surface of the first polycrystalline silicon layer to the atmosphere;
A second step of forming a second polycrystalline silicon layer on the first polycrystalline silicon layer by using a hydrogen-containing raw material or an atmospheric gas; and forming the first and second polycrystalline silicon layers. Is patterned into a predetermined shape to form the semiconductor active layer in which the off-current reduction layer made of the first polysilicon layer and the channel layer made of the second polysilicon layer are sequentially stacked. A third step of forming the gate electrode on the channel layer of the semiconductor active layer via the gate insulating film, and then adding a predetermined impurity to the semiconductor active layer sandwiching the gate electrode. , and a fourth step of forming the source region and the drain region to the channel layer, the first step, before
A non-doped polycrystalline silicon layer is formed on the transparent insulating substrate.
After the formation, the channel conductivity type and the reverse conductivity type
Forming a pure doped layer, wherein said non-doped polycrystalline silicon
A first connection layer in which a conductive layer and the impurity-doped layer are sequentially stacked.
This is achieved by a method for manufacturing a thin film transistor, which is a step of forming a crystalline silicon layer .

Also, a transparent insulating substrate, and the transparent insulating substrate
A semiconductor active layer formed thereon and a surface of the semiconductor active layer
Source and drain regions formed opposite to each other;
The half sandwiched between the source region and the drain region
Gate formed on conductor active layer via gate insulating film
And a method of manufacturing a thin film transistor having an electrode.
On the transparent insulating substrate, a channel conductivity type and a reverse conductivity type.
A first step of forming a first polycrystalline silicon layer of
Without exposing the surface of the first polycrystalline silicon layer to the atmosphere,
A raw material containing hydrogen on the first polycrystalline silicon layer
Alternatively, the second polycrystalline silicon layer is formed using an atmospheric gas.
Forming a second step, and the first and second polycrystalline silicon
The first multiple bonding is performed by patterning the
The off-current reducing layer made of a crystalline silicon layer and the second
The channel layer made of a polycrystalline silicon layer is sequentially stacked
A third step of forming the formed semiconductor active layer;
A gate insulating film on the channel layer of the semiconductor active layer;
After forming the gate electrode through, the gate electrode
A predetermined impurity is added to the semiconductor active layer sandwiching the
The source region and the drain region in the channel layer;
And forming a fourth step of forming the semiconductor active layer.
Forming the channel layer by adding a certain impurity.
Controlling the junction depth of the source region and the drain region;
The source region and the drain region and the off-state
The distance from the flow reduction layer should be 30 nm or more.
And a method of manufacturing a thin film transistor.
Is done.

In the above-described method of manufacturing a thin film transistor, the first step is a step of forming the first polycrystalline silicon layer to a thickness of 100 nm or more, and the second step is a step of forming the first polycrystalline silicon layer to a thickness of 100 nm or more. 2 polycrystalline silicon layers to 100
It is desirable that the process be performed so as to have a thickness of nm or less.
Further, in the method for manufacturing a thin film transistor described above, a predetermined impurity is added to the semiconductor active layer to control a junction depth of the source region and the drain region formed in the channel layer, and the source region and the drain region are formed. It is desirable that the distance between the drain region and the off-current reduction layer be 30 nm or more.

[0016]

According to the present invention, the first and second polycrystalline silicon layers are continuously grown on a transparent insulating substrate without being exposed to the air on the way, and the thickness of the first polycrystalline silicon layer is reduced. 1
By setting the thickness to not less than 00 nm and by growing the second polycrystalline silicon layer in a source gas containing hydrogen, the second polycrystalline silicon layer can have good crystallinity. Therefore, the channel layer made of the second polycrystalline silicon layer can obtain good electrical characteristics with large mobility.

On the other hand, by growing a first polycrystalline silicon layer on a transparent insulating substrate in a hydrogen-free raw material and an atmosphere gas, the first polycrystalline silicon layer has a grain size of polycrystalline silicon in the first polycrystalline silicon layer. Many defects due to dangling bonds and the like exist in the grain boundaries. For this reason, the light leakage current generated when light from the outside enters the off-current reduction layer formed of the first polycrystalline silicon layer is recombined immediately due to a large number of defects, and does not flow to the outside. Almost no increase in the film thickness to 100 nm or more does not contribute to an increase in light leakage current.

Alternatively, a first polycrystalline silicon layer or a non-doped polycrystalline silicon layer having a channel conductivity type and a reverse conductivity type and an impurity doped layer having a channel conductivity type and a reverse conductivity type are laminated on a transparent insulating substrate. By growing the first polycrystalline silicon layer, a layer of the opposite conductivity type comes into contact below the channel layer, so that the same carrier as that of the channel conductivity type is formed in a region far from the gate electrode and where voltage control is not effective. It can be prevented from flowing and off-state current can be reduced.

In this manner, an off-current reducing layer that prevents outflow of light leakage current due to the existence of a large number of defects, and prevents expansion of a leakage path due to the presence of a layer of channel conductivity type and reverse conductivity type; By forming a semiconductor active layer from a channel layer having high mobility due to good crystallinity, it is possible to reduce an off-current while improving an on-current characteristic.
The off ratio can be increased.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be specifically described based on embodiments shown in the drawings. FIG. 1 is a sectional view showing a polycrystalline silicon thin film transistor according to a first embodiment of the present invention. A thickness 10 formed on a transparent insulating substrate 10 made of a glass substrate or the like by using a hydrogen-free raw material and an atmospheric gas;
An off-current reducing layer 12 made of a polycrystalline silicon layer having a thickness of 0 nm or more, for example, 450 nm, and a channel layer 14 made of a polycrystalline silicon layer having a thickness of 100 nm or less, for example, 50 nm formed using a hydrogen-containing material or an atmospheric gas.
Are sequentially stacked, and a semiconductor active layer 26 is constituted by the off-current reduction layer 12 and the channel layer 14.

On the surface of the channel layer 14 of the semiconductor active layer 26, an n + type source region 22 and an n + type drain region 24 are formed facing each other. Here, the n + -type source region 22 and the n + -type drain region 24 are formed in the channel layer 14 and do not reach the off-current reduction layer 12. n + type source region 22 and n + type drain region 24
This is because when reaches the off-current reduction layer 12, a large number of defects in the off-current reduction layer 12 have an adverse effect of increasing the off-current.

On the channel layer 14 sandwiched between the n + -type source region 22 and the n + -type drain region 24, a gate insulating film 16 made of, for example, a 150 nm thick SiO ₂ (silicon oxide) film is interposed. Thus, a gate electrode 18 made of, for example, an Al (aluminum) film having a thickness of 300 nm is formed. In addition, for example, a 400 nm thick S
An interlayer insulating film 28 made of an iN _x (silicon nitride) film is formed. Further, through the contact window opened in the interlayer insulating film 28, the n + type source region 22 and the n + type
Each having a thickness of, for example, 60
A source electrode 30 and a drain electrode 32 made of a 0 nm Al film are formed.

Next, the polycrystalline silicon thin film transistor shown in FIG.
The manufacturing method of the star will be described with reference to the process charts shown in FIGS.
explain. First, Ar (Al) is placed on the transparent insulating substrate 10.
Gon) High pressure using silicon target in atmosphere
Substrate temperature 450 ° C, pressure 5 × 1 by frequency sputtering
0 ^-3Under the condition of Torr, the polycrystalline silicon layer 12a is 450 n
m.

Subsequently, the transparent insulating substrate 10 is moved from the sputtering apparatus to the CVD apparatus without exposing the polycrystalline silicon layer 12a to the atmosphere, and then, is subjected to a plasma CVD method.
SiH ₄ gas at a flow rate of 10 sccm as a raw material gas and a flow rate of 5
Using H ₂ (hydrogen) gas of 00 sccm, substrate temperature 450
5 ° C., a pressure of 0.5 Torr, and a discharge power of 200 W, the polycrystalline silicon layer 14 a was
It is grown to a thickness of 0 nm (see FIG. 2A).

Next, a 150 nm thick SiO ₂ film 16a is formed on the polycrystalline silicon layer 14a by plasma CVD.
Then, an Al film 18a is deposited to a thickness of 300 nm on the SiO ₂ film 16a by sputtering. Then, a resist 20 patterned into a predetermined shape is formed on the Al film 18a (see FIG. 2B).

Next, using the resist 20 as a mask, the Al film 18a and the SiO ₂ film 16a are sequentially etched to form the gate electrode 18 made of the Al film 18a and the SiO ₂ film 16a.
_A gate insulating film 16 composed of _two films 16a is formed. Subsequently, after the resist 20 is removed by stripping, for example, P (phosphorus) as a group V impurity atom is introduced only into the polycrystalline silicon layer 14a by an ion shower method using the gate electrode 18 as a mask. N + type source region 22 and n +
The mold drain region 24 is formed to face each other (see FIG. 2C).

Next, the polysilicon layer 14a and the polysilicon layer 12a are patterned into a predetermined shape,
The off-current reducing layer 12 made of the polycrystalline silicon layer 14a and the polycrystalline silicon layer 12a is formed, and the semiconductor active layer 26 made of the channel layer 14 and the off-current reducing layer 12 is formed. Then, on the whole surface,
The the SiN _x film is grown to a thickness of 400 nm, SiN _x
An interlayer insulating film 28 made of a film is formed (see FIG. 3D).

Next, after opening a contact window in the interlayer insulating film 28 on the n + type source region 22 and the n + type drain region 24, the n + type source region 22 and the n + type drain A source electrode 30 and a drain electrode 32 made of an Al film having a thickness of 600 nm connected to the regions 24 are formed. Thus, the polycrystalline silicon thin film transistor shown in FIG. 1 is completed (FIG. 3E).
reference).

As described above, according to the present embodiment, the transparent insulating substrate 10 is formed using high-frequency sputtering in an Ar atmosphere.
By depositing the polycrystalline silicon layer 12a thereon, that is, by forming the polycrystalline silicon layer 12a in a hydrogen-free raw material and in an atmosphere gas, the polycrystalline silicon layer 12a hardly contains hydrogen. Since the temperature is as low as 450 ° C., there are many defects due to dangling bonds and the like at the grain boundaries of the polycrystalline silicon grains in the polycrystalline silicon layer 12a.

Therefore, the off-current reduction layer 12 made of the polycrystalline silicon layer 12a has poor electric characteristics,
Light leakage current generated by light incident from the outside is
Immediate recombination occurs due to defects such as dangling bonds present at the grain boundaries of the grains, so that they hardly flow to the outside. Therefore, even if the off-current reduction layer 12 made of the polycrystalline silicon layer 12a is as thick as 450 nm, it does not contribute to an increase in the light leakage current.

The crystallinity of the polycrystalline silicon layer 12a grown on the transparent insulating substrate 10 increases as the film thickness increases, and the surface of the polycrystalline silicon layer 12a having a film thickness of 100 nm or more is improved. Since good crystallinity can be obtained in the vicinity, the polycrystalline silicon layer 14a can be continuously grown on the polycrystalline silicon layer 12a having improved crystallinity without being exposed to the air on the way. The crystallinity of the crystalline silicon layer 14a can be improved.

Moreover, the polycrystalline silicon layer 14a
By growing by a plasma CVD method using SiH ₄ gas and H ₂ gas, that is, by forming in a source gas containing hydrogen, hydrogen radicals and hydrogen atoms decomposed by plasma are taken into the polycrystalline silicon layer 14a. In addition, since hydrogen is terminated by dangling bonds existing at the grain boundaries of grains, defects are reduced.

Therefore, the channel layer 14 made of the polycrystalline silicon layer 14a has a high carrier mobility and can obtain good electric characteristics, and thus can improve on-current characteristics. The increase in the light leakage current generated in the channel layer 14 can be suppressed by reducing the film thickness to 100 nm or less, for example, about 50 nm.

Thus, the off-current reducing layer 12 made of the polycrystalline silicon layer 12a for preventing the outflow of the light leak current due to the existence of a large number of defects, and the polycrystalline silicon layer 14a having a large mobility due to good crystallinity. Since the semiconductor active layer 26 is composed of the channel layer 14, the light leakage current is reduced by about 1 /
It was able to be reduced to 10.

Thus, it is possible to increase the on / off ratio of the polycrystalline silicon thin film transistor, improve the characteristics of the active matrix, and realize a high quality liquid crystal display and the like. Further, the polycrystalline silicon layer 12
Since the a and the polycrystalline silicon layer 14a are formed at a substrate temperature of 500 ° C. or less, an expensive quartz substrate may not be used as the transparent insulating substrate 10, which can contribute to a reduction in manufacturing cost.

In the first embodiment, the polycrystalline silicon layer 12a is deposited by high frequency sputtering in an Ar atmosphere. However, the present invention is not limited to this method. For example, a vacuum evaporation method or SiCl ₄ Plasma CV using
The D method or the like may be used. Also, the polycrystalline silicon layer 14a
Is not limited to the plasma CVD method using SiH ₄ gas and H ₂ gas, but may be, for example, a high frequency sputtering method in a mixed gas atmosphere of Ar and H ₂ .

Next, a polycrystalline silicon thin film transistor according to a second embodiment of the present invention will be described with reference to FIG.
FIG. 4 is a sectional view showing a polycrystalline silicon thin film transistor according to the second embodiment. The same components as those of the polycrystalline silicon thin film transistor shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

This embodiment is different from the first embodiment in that the non-doped polycrystalline silicon layer is replaced with the off-current reducing layer 12 composed of the polycrystalline silicon layer 12a formed by using a hydrogen-free raw material and an atmospheric gas. And an p-type polycrystalline silicon layer in that order. That is, a non-doped polycrystalline silicon layer 34 having a thickness of 100 nm is formed on the transparent insulating substrate 10.
a and a 100 nm-thick p-type polycrystalline silicon layer 36 a to which impurities of the channel conductivity type and the opposite conductivity type are added are sequentially laminated to form an off-current reduction layer 40. On the off-current reducing layer 40, a channel layer 38 of a 100-nm-thick polycrystalline silicon layer formed using a hydrogen-containing material or an atmospheric gas is stacked.
The off-current reduction layer 40 and the channel layer 38 form a semiconductor active layer 42.

On the surface of the channel layer 38 of the semiconductor active layer 42, as in the case of FIG.
2 and n + type drain regions 24 are formed opposite to each other. Here, these n + type source regions 22 and n +
The junction depth of the drain region 24 is controlled to be less than 70 nm. Therefore, the distance between the n + -type source region 22 and the n + -type drain region 24 and the p-type polysilicon layer 36a of the off-current reduction layer 40 is 30 nm. That is all. If this interval is smaller than 30 nm, the n + type source region 2
This is because the slope of the energy band at the pn junction between the 2 and n + -type drain regions 24 and the p-type polycrystalline silicon layer 36a becomes steep, which may cause a leak current due to a tunnel current.

Also, as in the case of FIG.
+ Type source region 22 and n + type drain region 24.
On the channel layer 38 thus formed, for example, a 300 nm thick S
iO _TwoThrough the gate insulating film 16 made of a film, for example,
A gate electrode 18 made of an Al film having a thickness of 1500 nm is formed.
Have been. Furthermore, the entire surface is covered with SiN_xInterlayer consisting of film
An insulating film 28 is formed, and an opening is formed in interlayer insulating film 28.
N + source region 22 and n +
+ Type drain region 24.
Source electrode 30 and drain electrode 32 are formed.
You.

Next, a method of manufacturing the polycrystalline silicon thin film transistor of FIG. 4 will be described with reference to the process chart shown in FIG. First, SiH ₄ gas at a flow rate of 10 sccm and H ₂ gas at a flow rate of 500 sccm were introduced as raw material gases onto the transparent insulating substrate 10 by plasma CVD, and the substrate temperature was set to 450 ° C.
A non-doped polycrystalline silicon layer 34a is grown at a temperature of 0.5 ° C., a pressure of 0.5 Torr, and a discharge power of 200 W.

The non-doped polycrystalline silicon layer 3
When the film thickness of 4a becomes 100 nm, the flow rate is further increased by 1.
A sccm B ₂ H ₆ (diborane) gas is introduced, and a p-type polycrystalline silicon layer 36a is continuously laminated to a thickness of 100 nm on the non-doped polycrystalline silicon layer 34a. Then, B
The introduction of the ₂ H ₆ gas is stopped, and the polycrystalline silicon layer 38 a is continuously laminated on the p-type polycrystalline silicon layer 36 a to a thickness of 100 nm using only the SiH ₄ gas and the H ₂ gas (FIG. 5A). reference).

Next, in the same manner as the steps shown in FIGS. 2B to 2C, an S layer is formed on the polycrystalline silicon layer 38a.
After sequentially growing an iO ₂ film and an Al film, using a resist patterned into a predetermined shape on the Al film as a mask,
The Al film and the SiO ₂ film are sequentially etched to form the gate electrode 18 made of the Al film and the gate insulating film 16 made of the SiO ₂ film.

Subsequently, after the resist is peeled off, for example, P is introduced only into the polycrystalline silicon layer 38a by an ion shower method using the gate electrode 18 as a mask, so that the surface of the polycrystalline silicon layer 38a is n + type. The source region 22 and the n + type drain region 24 are formed facing each other (FIG. 5).
(B)). At this time, the acceleration voltage of the ion shower is controlled so that the junction depth of the n + -type source region 22 and the n + -type drain region 24 is controlled to be less than 70 nm. n + type drain region 2
4 and the p-type polysilicon layer 36a of the off-current reduction layer 40
Note that the distance between is larger than 30 nm.

Next, the polysilicon layer 38a, the p-type polysilicon layer 36a, and the non-doped polysilicon layer 34a are formed into a predetermined shape in the same manner as in the steps shown in FIGS. By patterning, a channel layer 38 composed of a polycrystalline silicon layer 38a, a p-type polycrystalline silicon layer 36a and a non-doped polycrystalline silicon layer 34
An off-current reducing layer 40 made of a is formed, and a semiconductor active layer 44 made of the channel layer 38 and the off-current reducing layer 40 is formed.

Subsequently, an interlayer insulating film 28 made of a SiN _x film is formed on the entire surface, a contact window is opened in the interlayer insulating film 28, and then the n + -type source region 22 and n + Electrode 30 and drain electrode 3 made of an Al film respectively connected to the drain region 24
Form 2 Thus, the polycrystalline silicon thin film transistor shown in FIG. 4 is completed (see FIG. 5C).

As described above, according to the present embodiment, the non-doped polycrystalline silicon layer 34a having a thickness of 100 nm is formed on the transparent insulating substrate 10 by the plasma CVD method using the SiH ₄ gas and the H ₂ gas as the source gas. By continuously growing a 100 nm-thick p-type polysilicon layer 36a and a 100 nm-thick polysilicon layer 38a, as in the case of the polysilicon layer 14a in the first embodiment,
Since the polycrystalline silicon layer 38a can have good crystallinity, the channel layer 38 having high mobility and good electrical characteristics can be formed similarly to the channel layer 14 composed of the polycrystalline silicon layer 14a. You can get
The on-current characteristics of the thin film transistor can be improved.

Under the channel layer 38, an off-current reducing layer 40 in which a non-doped polycrystalline silicon layer 34a and a p-type polycrystalline silicon layer 36a are sequentially laminated is formed, and the p-type polycrystalline silicon layer 36a is formed. Channel layer 38
, The spread of the leak path is prevented, so that the off-current is prevented from flowing through the off-current reduction layer 40 grown thick on the transparent insulating substrate 10, and the off-current of the thin film transistor is reduced. Can be.

As described above, the p-type polycrystalline silicon layer 36a in contact with the channel layer 38 comprises the off-current reducing layer 40 for preventing the off-current from flowing, and the polycrystalline silicon layer 38a having high mobility due to good crystallinity. Since the semiconductor active layer 44 is constituted by the channel layer 38, only the off current can be reduced by one digit without changing the on current.

Thus, as in the first embodiment, the on / off ratio of the thin film transistor is increased,
It is possible to improve the characteristics of the active matrix and realize a high-quality liquid crystal display or the like. In the second embodiment, the p-type polysilicon layer 36a
Although B ₂ H ₆ is used as an impurity to be introduced when the compound is formed, the present invention is not limited to such a hydride of a Group III impurity element. For example, a halide such as BCl ₃ or BBr ₃ may be used.

The above is the case where the polycrystalline silicon thin film transistor is an n-channel type. However, when the polycrystalline silicon thin film transistor is a p-channel type, a polycrystalline silicon layer to which an impurity of the conductivity type opposite to the channel conductivity type is added is formed. to, for example, hydrides of group V impurity element PH ₃ or the like, using a halide such as PCl ₃ as an impurity may be an n-type polycrystalline silicon layer.

Next, a polycrystalline silicon thin film transistor according to a third embodiment of the present invention will be described with reference to FIG.
FIG. 6 is a sectional view showing a polycrystalline silicon thin film transistor according to the third embodiment. The same components as those of the polycrystalline silicon thin film transistor shown in FIG. 4 are denoted by the same reference numerals, and description thereof is omitted.

This embodiment is different from the second embodiment in that the off-current reduction layer 40 in which the non-doped polysilicon layer 34a and the p-type polysilicon layer 36a are sequentially stacked is replaced with a p-type polysilicon layer. Is characterized in that an off-current reduction layer made of That is, an off-current reducing layer 46 made of a 200 nm-thick p-type polycrystalline silicon layer and a 100 nm-thick polycrystalline silicon formed using a hydrogen-containing raw material or an atmosphere gas are formed on a transparent insulating substrate 10. A channel layer 48 composed of layers is stacked, and the semiconductor active layer 50 is constituted by the off-current reduction layer 46 and the channel layer 48.

The n + -type source region 22 and the n + -type drain region 24 having a junction depth of less than 70 nm are formed on the surface of the channel layer 48 of the semiconductor active layer 50 as in the case of FIG.
Are formed opposite to each other, and these n + -type source regions 22 and n
On the channel layer 48 sandwiched between the + type drain region 24, the gate electrode 18 is formed via the gate insulating film 16.

Further, an interlayer insulating film 28 is formed on the entire surface, and the n + -type source region 22 and the n + -type drain region 2 are formed through contact windows opened in the interlayer insulating film 28.
4, a source electrode 30 and a drain electrode 32 are formed. Next, a method of manufacturing the polycrystalline silicon thin film transistor of FIG. 6 will be described with reference to the process chart shown in FIG.

First, SiH ₄ gas, H ₂ gas, and B ₂ H ₆ gas are introduced as raw material gases onto the transparent insulating substrate 10 by a plasma CVD method to form a p-type polycrystalline silicon layer 46a having a thickness of 200 nm. Let it grow. Then, B ₂
The introduction of the H ₆ gas is stopped, and a polycrystalline silicon layer 48a is continuously stacked on the p-type polycrystalline silicon layer 46a to a thickness of 100 nm only by the SiH ₄ gas and the H ₂ gas (see FIG. 7A). ).

Next, after forming the gate electrode 18 and the gate insulating film 16 on the polycrystalline silicon layer 48a in the same manner as the steps shown in FIGS. 5B to 5C, the gate electrode 18 is masked. The n + -type source region 22 and the n + -type drain region 24 having a junction depth of less than 70 nm are formed on the surface of the polycrystalline silicon layer 48a.

Subsequently, the polycrystalline silicon layer 48a and the p-type polycrystalline silicon layer 46a are patterned into predetermined shapes, and the channel layer 48 composed of the polycrystalline silicon layer 48a and the off-current composed of the p-type polycrystalline silicon layer 46a are formed. The reduction layer 46 is formed, and the semiconductor active layer 50 including the channel layer 48 and the off-current reduction layer 46 is formed. continue,
After an interlayer insulating film 28 is formed on the entire surface, a source electrode 30 and a drain electrode 32 connected to the n + -type source region 22 and the n + -type drain region 24 through contact windows opened in the interlayer insulating film 28, respectively. To form Thus, the polycrystalline silicon thin film transistor shown in FIG. 6 is completed (see FIG. 7B).

As described above, according to the present embodiment, on the transparent insulating substrate 10, the off-current reducing layer 46 made of the p-type polycrystalline silicon layer 46a having a thickness of 200 nm and the thickness of 100 nm
By forming the channel layer 48 of the polycrystalline silicon layer 48a by continuous growth, the same effect as in the case of the second embodiment can be obtained. When this embodiment is compared with the second embodiment, the non-doped polysilicon layer 34a and the p-type polysilicon layer 36a of the off-current reduction layer 40 in the second embodiment are sequentially stacked. Although the structure is complicated, the thickness of the p-type polycrystalline silicon layer 36a is smaller than the thickness of the p-type polycrystalline silicon layer 46a in this embodiment, so that the amount of gas used is reduced and the production cost is reduced. The second embodiment is preferred in terms of reducing the amount of waste gas and reducing unnecessary waste gas.

Next, a polycrystalline silicon thin film transistor according to a fourth embodiment of the present invention will be described with reference to FIG.
FIG. 8 is a sectional view showing a polycrystalline silicon thin film transistor according to the third embodiment. The same components as those of the polycrystalline silicon thin film transistor shown in FIGS. 1 and 4 are denoted by the same reference numerals, and description thereof is omitted.

This embodiment is different from the first embodiment in that the off-current reduction layer 12 made of the polycrystalline silicon layer 12a formed using the hydrogen-free raw material and the atmospheric gas is used.
The off-current reduction layer is formed by combining the off-current reduction layer 40 in which the non-doped polysilicon layer 34a and the p-type polysilicon layer 36a in the second embodiment are sequentially stacked. There is.

That is, the thickness 3 formed on the transparent insulating substrate 10 by using a hydrogen-free raw material and an atmospheric gas.
00 nm non-doped polycrystalline silicon layer 52a and thickness 1
A 00 nm p-type polycrystalline silicon layer 54a is sequentially stacked to form an off-current reduction layer 58. On this off-current reduction layer 58, a channel layer 56 made of a 100-nm-thick polycrystalline silicon layer 56a formed using a hydrogen-containing material or an atmospheric gas is laminated.
The off-current reduction layer 58 and the channel layer 56 constitute a semiconductor active layer 60.

The n + -type source region 22 and the n + -type drain region 24 having a junction depth of less than 70 nm are formed on the surface of the channel layer 56 of the semiconductor active layer 50, as in the case of FIG.
Are formed opposite to each other, and these n + -type source regions 22 and n
On the channel layer 56 sandwiched between the + type drain region 24, the gate electrode 18 is formed via the gate insulating film 16.

Further, an interlayer insulating film 28 is formed on the entire surface, and the n + -type source region 22 and the n + -type drain region 2 are formed through contact windows opened in the interlayer insulating film 28.
4, a source electrode 30 and a drain electrode 32 are formed. Next, a method for manufacturing the polycrystalline silicon thin film transistor of FIG. 8 will be described with reference to the process chart shown in FIG.

First, a plasma CVD method using SiCl ₄ or the like as a source gas is formed on the transparent insulating substrate 10 by a plasma CVD method.
A non-doped polycrystalline silicon layer 52a is grown to a thickness of 300 nm. Then, the source gas is changed from SiCl ₄ or the like to Si.
In addition to switching to H ₄ or the like, B ₂ H ₆ gas is further introduced, and p is continuously formed on the non-doped polycrystalline silicon layer 52a.
The polycrystalline silicon layer 54a is laminated to a thickness of 100 nm.

Subsequently, introduction of the B ₂ H ₆ gas was stopped, and Si
A polycrystalline silicon layer 56a is continuously laminated on the p-type polycrystalline silicon layer 54a to a thickness of 100 nm only by the H ₄ gas or the like (see FIG. 9A). Next, FIG.
After the gate electrode 18 and the gate insulating film 16 are formed on the polycrystalline silicon layer 56a in the same manner as in the steps shown in (b) to (c), the gate electrode 18 and the gate insulating film 16 are formed by an ion shower method using the gate electrode 18 as a mask. On the surface of the crystalline silicon layer 56a,
N + -type source regions 22 and n having a junction depth of less than 70 nm
The + type drain region 24 is formed to face each other.

Subsequently, the polycrystalline silicon layer 56a, the p-type polycrystalline silicon layer 54a and the non-doped polycrystalline silicon layer 52a are patterned into predetermined shapes to form a channel layer 56 made of the polycrystalline silicon layer 56a and the p-type polycrystalline silicon layer. Forming an off-current reducing layer 58 comprising a silicon layer 54a and a non-doped polycrystalline silicon layer 52a; and forming a semiconductor active layer 60 comprising these channel layer 56 and off-current reducing layer 58.
To form

Subsequently, after an interlayer insulating film 28 is formed on the entire surface, the n + -type source region 22 and the n + -type drain region 2 are formed through a contact window opened in the interlayer insulating film 28.
4, a source electrode 30 and a drain electrode 32 are formed, respectively. Thus, the polycrystalline silicon thin film transistor shown in FIG. 8 is completed (see FIG. 9B). As described above, according to the present embodiment, the S
A non-doped polycrystalline silicon layer 52a having a thickness of 300 nm formed by a plasma CVD method using a hydrogen-free raw material such as iCl ₄ and an atmosphere gas, and a p-type polysilicon having a thickness of 100 nm to which impurities of a channel conductivity type and a conductivity type are added. A thickness of 10 by a plasma CVD method using a crystalline silicon layer 54a, a hydrogen-containing material such as SiH _4, and an atmosphere gas;
By continuously growing the 0-nm polycrystalline silicon layer 56a, the polycrystalline silicon layer 52a for preventing outflow of light leakage current due to the presence of a large number of defects and the p-type polycrystalline silicon layer 54a for preventing expansion of a leak path are sequentially formed. A stacked off-current reduction layer 58 is formed, a channel layer 56 made of a polycrystalline silicon layer 56a having high mobility with good crystallinity is formed, and a semiconductor formed of the off-current reduction layer 58 and the channel layer 56 is formed. Active layer 6
Since 0 is formed, an effect obtained by combining the first and second embodiments can be obtained. That is, while improving the on-current characteristics, the light leakage current can be reduced, and the other leakage currents can also be reduced.

[0069]

As described above, according to the present invention,
By forming a first polycrystalline silicon layer and a second polycrystalline silicon layer continuously on a transparent insulating substrate without being exposed to the air on the way, the second polycrystalline silicon layer contains hydrogen. By forming the second polycrystalline silicon layer in a source gas, the second polycrystalline silicon layer can have good crystallinity. Therefore, the channel layer including the second polycrystalline silicon layer can obtain good electric characteristics. .

On the other hand, by forming a first polycrystalline silicon layer on a transparent insulating substrate in a hydrogen-free raw material and in an atmosphere gas, the first polycrystalline silicon layer has a grain size of polycrystalline silicon in the first polycrystalline silicon layer. Since many defects due to dangling bonds and the like are present in the grain boundaries, light leakage current generated by light incident from the outside is immediately recombined by many defects, and thus, the first polycrystalline silicon layer The off-current reduction layer does not contribute to an increase in light leakage current.

Alternatively, a first polycrystalline silicon layer or a non-doped polycrystalline silicon layer of the opposite conductivity type to the channel conductivity type and an impurity doped layer of the opposite conductivity type to the channel conductivity type are stacked on the transparent insulating substrate. The formation of the polycrystalline silicon layer prevents the same carrier as that of the channel conductivity type from flowing in a region far from the gate electrode and where voltage control is not effective because the layer of the opposite conductivity type is in contact with the lower portion of the channel layer. In addition, off current can be reduced.

That is, an off-current reduction layer that prevents outflow of light leakage current due to the presence of a large number of defects, and prevents expansion of a leakage path due to the presence of a layer of the channel conductivity type and the opposite conductivity type; Since the semiconductor active layer is composed of a channel layer having a large mobility depending on the property, the off-current can be reduced while the on-current characteristics are improved, so that the on / off ratio of the thin film transistor can be increased. it can.

As a result, it is possible to increase the on / off ratio of the polycrystalline silicon thin film transistor, improve the characteristics of the active matrix, and realize a high quality liquid crystal display or the like.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a polycrystalline silicon thin film transistor according to a first embodiment of the present invention.

FIG. 2 is a process chart (1) for explaining a method for manufacturing the polycrystalline silicon thin film transistor of FIG.

FIG. 3 is a process diagram (part 2) for describing the method for manufacturing the polycrystalline silicon thin film transistor of FIG.

FIG. 4 is a sectional view showing a polycrystalline silicon thin film transistor according to a second embodiment of the present invention.

5 is a process chart for explaining a method of manufacturing the polycrystalline silicon thin film transistor of FIG.

FIG. 6 is a sectional view showing a polycrystalline silicon thin film transistor according to a third embodiment of the present invention.

FIG. 7 is a process chart illustrating a method for manufacturing the polycrystalline silicon thin film transistor of FIG.

FIG. 8 is a sectional view showing a polycrystalline silicon thin film transistor according to a fourth embodiment of the present invention.

FIG. 9 is a process chart illustrating a method for manufacturing the polycrystalline silicon thin film transistor of FIG.

FIG. 10 is a cross-sectional view illustrating a conventional polycrystalline silicon thin film transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 ... Transparent insulating substrate 12a ... Polycrystalline silicon layer formed using hydrogen-free raw material and atmospheric gas 12 ... Off-current reduction layer 14a ... Polycrystalline formed using hydrogen-containing raw material or atmospheric gas Silicon layer 14 channel layer 16a SiO ₂ film 16 gate insulating film 18a Al film 18 gate electrode 20 resist 22 n + type source region 24 n + type drain region 26 semiconductor active layer 28 interlayer insulation Film 30 source electrode 32 drain electrode 34a non-doped polycrystalline silicon layer 36a p-type polycrystalline silicon layer 38a polycrystalline silicon layer 38 channel layer 40 off-current reduction layer 42 semiconductor active layer 44 semiconductor active layer 46a: p-type polycrystalline silicon layer 46: off-current reduction layer 48a: polycrystalline silicon layer 48: channel layer 50 Semiconductor active layer 52a: non-doped polycrystalline silicon layer formed using hydrogen-free raw material and atmospheric gas 54a: p-type polycrystalline silicon layer 56a: polycrystalline formed using hydrogen-containing raw material or atmospheric gas Silicon layer 56 channel layer 58 off-current reducing layer 60 semiconductor active layer 70 transparent insulating substrate 72 semiconductor active layer 74 gate insulating film 76 gate electrode 78 n + source region 80 n + drain Region 82: interlayer insulating film 84: source electrode 86: drain electrode

Continuation of the front page (56) References JP-A-4-369271 (JP, A) JP-A-64-49221 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29 / 786 H01L 21/336

Claims (7)

(57) [Claims] 1. A transparent insulating substrate, a semiconductor active layer formed on the transparent insulating substrate, a source region and a drain region formed facing the surface of the semiconductor active layer, the source region and the drain region And a gate electrode formed on the semiconductor active layer with a gate insulating film interposed therebetween, wherein the semiconductor active layer is formed on the transparent insulating substrate by first polycrystalline silicon. An off-current reduction layer made of a layer, and a channel layer made of a second polycrystalline silicon layer laminated on the off-current reduction layer, wherein the source region and the drain region are respectively formed in the channel layer. is formed, the off current reduction layer does not contain a hydrogen feedstock and Kiri囲
A first insulating layer formed on the transparent insulating substrate using a gaseous gas;
A polycrystalline silicon layer, wherein the channel layer is a raw material or an atmosphere gas containing hydrogen;
A second junction formed on the off-current reduction layer by using
A thin film transistor comprising a crystalline silicon layer . 2. A method according to claim 1 , wherein said transparent insulating substrate is provided on said transparent insulating substrate.
The formed semiconductor active layer and the surface of the semiconductor active layer
A source region and a drain region formed for the
The semiconductor sandwiched between a source region and the drain region
Gate electrode formed on active layer via gate insulating film
In thin film transistor including bets, the semiconductor active layer, formed on said transparent insulating substrate
An off-current reduction layer made of a first polycrystalline silicon layer;
Second polycrystalline silicon laminated on the off-current reduction layer
A source layer and the drain region, respectively.
An off-current reduction layer formed in a channel layer, the off-current reduction layer including a first polycrystalline silicon layer having an impurity-doped layer doped with an impurity of a channel conductivity type and an opposite conductivity type; Ri Do from the second polycrystalline silicon layer formed on the impurity-doped layer by using the raw material or the atmosphere gas containing the source region and the drain territory of the channel layer
Region and the impurity-doped layer of the off-current reduction layer are 3
A thin film transistor having an interval of 0 nm or more . 3. A transparent insulating substrate, a semiconductor active layer formed on the transparent insulating substrate, a source region and a drain region formed facing the surface of the semiconductor active layer, the source region and the drain region. A thin film transistor comprising a gate electrode formed on the semiconductor active layer interposed between the semiconductor active layer and a gate insulating film, using a hydrogen-free raw material and an atmosphere gas on the transparent insulating substrate. A first step of forming a first polycrystalline silicon layer; a raw material containing hydrogen on the first polycrystalline silicon layer without exposing the surface of the first polycrystalline silicon layer to the atmosphere; A second step of forming a second polycrystalline silicon layer using an atmospheric gas; and patterning the first and second polycrystalline silicon layers into a predetermined shape to form the first polycrystalline silicon layer. A third step of forming the semiconductor active layer in which the off-current reduction layer made of a recon layer and the channel layer made of the second polycrystalline silicon layer are sequentially stacked; and the channel layer of the semiconductor active layer After forming the gate electrode with the gate insulating film interposed therebetween, a predetermined impurity is added to the semiconductor active layer sandwiching the gate electrode to form the source region and the drain region in the channel layer. A method of manufacturing a thin film transistor. 4. A transparent insulating substrate, a semiconductor active layer formed on the transparent insulating substrate, a source region and a drain region formed facing the surface of the semiconductor active layer, the source region and the drain region. And a gate electrode formed on the semiconductor active layer with a gate insulating film interposed therebetween. The method according to claim 1, further comprising: forming a first conductive type and a reverse conductive type on the transparent insulating substrate. A first step of forming a polycrystalline silicon layer, and using a hydrogen-containing raw material or an atmosphere gas on the first polycrystalline silicon layer without exposing the surface of the first polycrystalline silicon layer to the atmosphere. A second step of forming a second polycrystalline silicon layer, and patterning the first and second polycrystalline silicon layers into a predetermined shape to form a second polycrystalline silicon layer before forming the first polycrystalline silicon layer. A third step of forming the semiconductor active layer in which the off-current reduction layer and the channel layer made of the second polycrystalline silicon layer are sequentially stacked; and forming the semiconductor active layer on the channel layer. After forming the gate electrode with a gate insulating film interposed therebetween, a predetermined impurity is added to the semiconductor active layer sandwiching the gate electrode to form the source region and the drain region in the channel layer. and a step, the first step, the transparent insulating substrate, an undoped
After forming a polycrystalline silicon layer,
Forming an impurity doped layer of a conductivity type and a reverse conductivity type,
The doped polycrystalline silicon layer and the impurity-doped layer
Forming a first polycrystalline silicon layer laminated on the substrate.
A method of manufacturing the thin film transistor, characterized in that that. 5. A transparent insulating substrate, and a transparent insulating substrate on the transparent insulating substrate.
The formed semiconductor active layer and the surface of the semiconductor active layer
A source region and a drain region formed for the
The semiconductor sandwiched between a source region and the drain region
Gate electrode formed on active layer via gate insulating film
In the method for manufacturing a thin film transistor including bets, the transparent insulating substrate, the first channel conductivity type opposite conductivity type
A first step of forming one polycrystalline silicon layer, and exposing a surface of the first polycrystalline silicon layer to the atmosphere.
And containing hydrogen on the first polycrystalline silicon layer.
A second polycrystalline silicon layer using a raw material or an atmospheric gas;
A second step of forming the first and second polycrystalline silicon layers into a predetermined shape.
Turning, comprising the first polycrystalline silicon layer
From said second polycrystalline silicon down layer and the off-current reducing layer
The semiconductor active layer in which the channel layer is sequentially stacked
A third step of forming a layer; and forming the gate insulating layer on the channel layer of the semiconductor active layer.
After forming the gate electrode via an edge film, the gate
Adding a predetermined impurity to the semiconductor active layer sandwiching the electrode;
The source region and the drain in the channel layer.
Forming a channel region by adding a predetermined impurity to the semiconductor active layer.
The source region and the drain region formed in a metal layer
Controlling the junction depth of the source region and the drain
Distance between the active region and the off-current reduction layer is 30 nm or more.
A method for manufacturing a thin film transistor. 6. A manufacturing method of a thin film transistor according to any one of claims 3 to 5, wherein the first step, the first polysilicon layer 10
Forming the second polycrystalline silicon layer to a thickness of at least 0 nm.
A method for manufacturing a thin film transistor, which is a step of forming the film to a thickness of 0 nm or less. 7. The method of manufacturing a thin film transistor according to claim 4 , wherein a predetermined impurity is added to the semiconductor active layer to control a junction depth of the source region and the drain region formed in the channel layer. And a distance between the source region and the drain region and the off-current reduction layer is 30 nm or more.