JPH0564862B2 - - Google Patents
Info
- Publication number
- JPH0564862B2 JPH0564862B2 JP6124585A JP6124585A JPH0564862B2 JP H0564862 B2 JPH0564862 B2 JP H0564862B2 JP 6124585 A JP6124585 A JP 6124585A JP 6124585 A JP6124585 A JP 6124585A JP H0564862 B2 JPH0564862 B2 JP H0564862B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- semiconductor thin
- amorphous
- microcrystalline semiconductor
- band width
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 claims description 84
- 239000004065 semiconductor Substances 0.000 claims description 55
- 230000005669 field effect Effects 0.000 claims description 8
- 230000004888 barrier function Effects 0.000 claims description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 239000010408 film Substances 0.000 description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000003287 optical effect Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 229910006404 SnO 2 Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Description
［産業上の利用分野］
本発明は薄膜電界効果素子の改良に関する。
［従来の技術］
アモルフアスまたは微結晶半導体薄膜を用いた
薄膜電界効果素子は、大面積液晶デイスプレイの
マトリツクスや周辺駆動回路への応用の供されて
いるが、その基本構造は、従来、金属−絶縁物−
半導体（Metal−Insulator−Semiconductor：以
下、MISと称する）接合を有する電界効果トラン
ジスタであつた。
［発明が解決しようとする課題］
しかし、アモルフアスまたは微結晶半導体薄膜
のMIS接合は、導電性ゲートの上に絶縁膜を作る
のでピンホールが多く、結晶半導体のMIS接合に
比べ、一般にリーク電流が多かつた。このため、
：液晶デイスプレイのマトリツクスに応用した
とき、信号電荷の保持特性が低下する。
：キヤリアリークが原因となつて広い禁制帯幅
を持つ薄膜層の絶縁破壊や特性劣化が生ずる。
：絶縁膜を薄くすることができないためにトラ
ンスコンダクタンスが小さい。
等の問題があつた。
［課題を解決するための手段］
本発明は上述の課題を解決するために、導電性
ゲートに接するように第一のアモルフアスまたは
微結晶半導体薄膜を設け、これに接するように広
い禁制帯幅を持つ薄膜を設ける。
さらにこの薄膜に接するようにして、上記した
第一のアモルフアスまたは微結晶半導体薄膜との
間でバリアを形成する第二のアモルフアスまたは
微結晶半導体薄膜を設けた上で、導電性のソー
ス、ドレイン領域を、それぞれこの第二のアモル
フアスまたは微結晶半導体薄膜の上または中に設
ける。
［実施例］
第１図には本発明により構成される薄膜電界効
果素子の概略的な断面構成が示されている。後述
の作製例に認められるように、例えばガラス等の
基板１００の上に、第一のアモルフアスまたは微
結晶半導体薄膜１（以下、第一半導体薄膜１と言
う）を導電性ゲート２に接して設ける。この第一
半導体膜１の厚さは100Å程度あれば十分である。
この第一の半導体薄膜に接して広い禁制帯幅を有
する薄膜３を設け、さらにこの薄膜３に接して第
二のアモルフアスまたは微結晶半導体薄膜４（以
下、これを第二の半導体薄膜４と言う）を設け
る。そして、この第二の薄膜４の上か中に、それ
ぞれ導電性のソース領域（以下、単にソース電
極）５と導電性のドレイン領域（同様に、以下単
にドレイン電極）６を設ける。
こうした本発明素子の基本的な動作自体は従来
のMIS型薄膜電界効果素子と同様で、ソース電極
５とドレイン電極６との間にソース・ドレイン電
圧を印加し、このときソース・ドレイン電極５，
６間（ないしそれらに個々に対応する実効的なソ
ース・ドレイン領域間）に流れる電流を導電性ゲ
ート２に印加するゲート電圧で制御する。
ただし、第一の半導体薄膜１は第二の半導体薄
膜４との間にバリアを形成する特性を有するもの
である。これにより、第二の半導体薄膜４と広い
禁制帯幅を有する薄膜３との間で形成される接合
のリーク電流が大きくても、第二の半導体薄膜４
から広い禁制帯幅を有する薄膜３に流入したキヤ
リアは、このバリアのため、ゲート２には到達せ
ず、
ゲート２／第一半導体薄膜１／広い禁制帯幅を
有する薄膜３／第二半導体薄膜４
で構成される多層接合全体としてのリーク電流は
大幅に低減される。
また、アモルフアスシリコン系の薄膜上に形成
した絶縁膜は一般にピンホールが少なく、リーク
電流が小さいので、第一半導体薄膜１としてアモ
ルフアスシリコンを用い、その上に広い禁制帯幅
を有する薄膜３としてシリコンオキサイド、シリ
コンナイトライド、シリコンオキシナイトライド
等の絶縁物薄膜を形成して第１図示構造の素子を
実現した場合には、第二半導体薄膜２と広い禁制
帯幅を有する薄膜３（この場合、上記の絶縁層）
との接合のリーク電流も低減される。
導電性ゲート２としては、ニツケル、アルミニ
ウム等の金属材料や、SnO2、ITO等の透明導電
性酸化物を使用できる。第一半導体薄膜１の伝導
型は、第二半導体薄膜４の伝導型と逆にするか、
原子組成または組成比を変えてヘテロ接合を形成
するようにし、第一半導体薄膜１が第二半導体薄
膜４に対し、バリアを形成するようにする。すな
わち、第二半導体薄膜２がｎ型の伝導型を有する
ときには第一半導体薄膜１はｐ型の伝導型を有す
るようにし、第二半導体薄膜２がｐ型の伝導型を
有するときには第一半導体薄膜１はｎ型の伝導型
を有するようにするか、あるいは両者が同一の伝
導型であつてもそれらの間にバリアの形成される
ヘテロ接合とする。
第一、第二の半導体薄膜１，２は、シラン、ジ
シラン、四弗化シリコン、ゲルマン等の原料ガス
を用いたプラズマCVD（化学気相成長法）、光
CVD、熱CVD等で成長させ得る。一方、広い禁
制帯幅を有する薄膜３としては、光CVDまたは
プラズマCVD等で作製したシリコンオキサイド、
シリコンナイトライド、シリコンオキシナイトラ
イド、ボロンナイトライド等の絶縁膜や、同様に
光CVDまたはプラズマCVD等で作製したアモル
フアスシリコンカーバイド、ダイハイドライド結
合の水素を多量に含んだ水素化アモルフアスシリ
コン等、禁制帯幅の広いアモルフアス半導体を用
い得る。第二半導体薄膜４の上か中に設けられる
ソース電極５やドレイン電極６としては、ニツケ
ル、アルミニウム等の金属材料を使用することが
できる。なお、必要に応じ、ソース電極５と第二
半導体薄膜４との間、及びドレイン電極６と第二
半導体薄膜４との間に、それぞれ不純物濃度の高
いドープ層を挿入し、オーミツク性の向上を図る
のも良い。
次に、第２図に即し、上述した本発明素子の一
作製工程例につき説明する。なお、第２図の枝番
(a)〜(e)と、下記工程番号(a)〜(e)は、それぞれ一対
一で対応している。
工程(a) ガラス等の基板１００上に導電性ゲート
２をニツケル、アルミニウム等の金属の真空蒸
着、電子ビーム蒸着で形成する。金属の代わり
にSnO2を導電性ゲートとして用いるときは、
SnCl4、SbCl2、H2Oの混合ガスを用いた熱
CVD、またはSnCl4・5H2OとSbCl3のHCl溶液
によるスプレー法等でSnO2薄膜２を基板上に
付着させる。こうした導電性ゲート２の平面形
状は、公知既存のフオトエツチング技術、マス
ク蒸着技術等により所定形状に整形する。
工程(b) モノシランまたはジシランとジボランガ
スのプラズマCVD、光CVD、熱CVD等によ
り、第一半導体薄膜１を構成するｐ型アモルフ
アスシリコンを少なくとも導電性ゲート２の上
に形成する。
工程(c) 第一半導体薄膜１（この場合、ｐ型アモ
ルフアスシリコン）の上に、広い禁制帯幅を有
する薄膜３として、N2Oとシランの混合ガス
を用いたプラズマCVDか光CVDにより、シリ
コンオキシナイトライド膜を形成する。
工程(d) 上述の薄膜３の上に、第二の半導体薄膜
４を工程(a)において述べたと同様の公知手法に
より所定寸法に形成するが、この第二半導体薄
膜５は、シランまたはジシランを用いたプラズ
マCVD、光CVD、熱CVDにより、ノンドープ
水素化アモルフアスシリコン膜として得る。こ
うした薄膜４は、一般に弱いｎ型の伝導型を有
するので、上述の工程(b)で形成した第一半導体
薄膜１に対し、バリアを形成する。
工程(e) 第二半導体薄膜４であるノンドープアモ
ルフアスシリコン上に、それぞれ導電性のソー
ス電極５とドレイン電極６となるニツケル、ア
ルミニウム等の金属薄膜を工程(a)にて述べてと
同様の公知手法により所定形状に形成し、これ
により、第１図に示したと同様の断面構造の本
発明素子を得る。
以上のような工程例に加え、素子の安定度を増
すために、第２図(e)中に仮想線で示されているよ
うに、第二半導体薄膜４に接して、熱CVD、光
CVD、プラズマCVD等によりシリコンナイトラ
イド、シリコンオキシナイトライド等から成る薄
膜７を形成し、これを保護膜７とすることもでき
る。
また、ソース、ドレイン電極５，６に接してい
る第二半導体薄膜の部分４ｓ，４ｄには、チヤネ
ルの伝導型に応じてｐまたはｎの不純物をイオン
注入またはプラズマドーピング等で選択的に導入
するとか、これらの不純物を含む半導体薄膜を第
二半導体薄膜４と両電極５，６の間に挿入するこ
とにより、当該各電極５，６とチヤネルのオーミ
ツク接触を良好にすることができる。
なお、本発明者の実験によれば、第一半導体薄
膜１がｐ型アモルフアスシリコンの場合、工程(b)
の後にその表面を100℃で10分間酸化して数10Å
程度の酸化薄膜３を形成しただけでも、その後に
水素プラズマ処理をしてノンドープのアモルフア
スシリコン薄膜４を堆積させた場合には、ゲート
２と当該アモルフアスシリコン薄膜４との間には
1Vで10-10A／cm2以下のリーク電流しか流れない
ことが確認された。
［効果］
本発明によれば、導電性ゲートと第二半導体薄
膜との間のリーク電流が大いに低減される。した
がつて、本発明素子を液晶デイスプレイのマトリ
ツクスに応用すると、従来に比して信号電荷の保
持特性が向上し、また、リーク電流が原因となつ
て生ずる、広い禁制帯幅を有する薄膜３の特性劣
化や絶縁破壊が抑制される効果がある。
さらに、ゲート絶縁膜を従来より薄くすること
ができるので、電界効果素子としてのトランスコ
ンダクタンスが大幅に向上し、液晶表示パネル等
の動作速度が飛躍的に改善されると共に、動作電
圧の低電圧化が可能となり、電力消費も低減され
る外、結局は全体的な信頼性が増す。
[Industrial Field of Application] The present invention relates to improvements in thin film field effect devices. [Prior Art] Thin-film field effect devices using amorphous or microcrystalline semiconductor thin films have been applied to large-area liquid crystal display matrices and peripheral drive circuits, but their basic structure has conventionally been metal-insulating. thing-
It was a field effect transistor with a semiconductor (Metal-Insulator-Semiconductor: hereinafter referred to as MIS) junction. [Problems to be Solved by the Invention] However, MIS junctions using amorphous or microcrystalline semiconductor thin films have many pinholes because an insulating film is formed on the conductive gate, and generally have a higher leakage current than MIS junctions using crystalline semiconductors. It was a lot. For this reason: When applied to a liquid crystal display matrix, the signal charge retention characteristics deteriorate. : Carrier leakage causes dielectric breakdown and property deterioration of thin film layers with a wide forbidden band width. : Transconductance is small because the insulating film cannot be made thin. There were other problems. [Means for Solving the Problems] In order to solve the above-mentioned problems, the present invention provides a first amorphous or microcrystalline semiconductor thin film in contact with a conductive gate, and a wide forbidden band width in contact with the first amorphous or microcrystalline semiconductor thin film. Provide a thin film that holds the Further, a second amorphous or microcrystalline semiconductor thin film is provided in contact with this thin film to form a barrier between the first amorphous or microcrystalline semiconductor thin film, and conductive source and drain regions are provided. are provided on or in the second amorphous or microcrystalline semiconductor thin film, respectively. [Example] FIG. 1 shows a schematic cross-sectional configuration of a thin film field effect device constructed according to the present invention. As seen in the fabrication examples described below, a first amorphous or microcrystalline semiconductor thin film 1 (hereinafter referred to as the first semiconductor thin film 1) is provided on a substrate 100 made of glass or the like in contact with a conductive gate 2. . A thickness of about 100 Å is sufficient for the first semiconductor film 1.
A thin film 3 having a wide forbidden band width is provided in contact with this first semiconductor thin film, and a second amorphous or microcrystalline semiconductor thin film 4 (hereinafter referred to as the second semiconductor thin film 4) is further provided in contact with this thin film 3. ) will be established. Then, on or in this second thin film 4, a conductive source region (hereinafter simply referred to as a source electrode) 5 and a conductive drain region (hereinafter simply referred to as a drain electrode) 6 are provided, respectively. The basic operation of the device of the present invention is similar to that of a conventional MIS type thin film field effect device, in which a source-drain voltage is applied between the source electrode 5 and the drain electrode 6.
The current flowing between the conductive gates 6 (or between the effective source and drain regions corresponding to these regions) is controlled by the gate voltage applied to the conductive gate 2. However, the first semiconductor thin film 1 has a property of forming a barrier between it and the second semiconductor thin film 4. As a result, even if the leakage current of the junction formed between the second semiconductor thin film 4 and the thin film 3 having a wide forbidden band width is large, the second semiconductor thin film 4
Because of this barrier, the carriers flowing into the thin film 3 having a wide forbidden band width do not reach the gate 2, and are gate 2/first semiconductor thin film 1/thin film 3 having a wide forbidden band width/second semiconductor thin film. The leakage current of the entire multilayer junction composed of 4 is significantly reduced. In addition, since an insulating film formed on an amorphous silicon thin film generally has few pinholes and a small leakage current, amorphous silicon is used as the first semiconductor thin film 1, and a thin film 3 having a wide forbidden band width is applied thereon. When an insulating thin film such as silicon oxide, silicon nitride, silicon oxynitride, etc. is formed as a thin film of silicon oxide, silicon nitride, silicon oxynitride, etc. to realize the element having the structure shown in the first diagram, the second semiconductor thin film 2 and the thin film 3 having a wide forbidden band width (this (insulating layer above)
Leakage current at the junction with the oxide film is also reduced. As the conductive gate 2, metal materials such as nickel and aluminum, and transparent conductive oxides such as SnO 2 and ITO can be used. The conductivity type of the first semiconductor thin film 1 is opposite to that of the second semiconductor thin film 4, or
The atomic composition or composition ratio is changed to form a heterojunction, and the first semiconductor thin film 1 forms a barrier to the second semiconductor thin film 4. That is, when the second semiconductor thin film 2 has an n-type conductivity type, the first semiconductor thin film 1 has a p-type conductivity type, and when the second semiconductor thin film 2 has a p-type conductivity type, the first semiconductor thin film 1 has a p-type conductivity type. 1 has an n-type conductivity type, or even if both have the same conductivity type, a heterojunction is formed in which a barrier is formed between them. The first and second semiconductor thin films 1 and 2 are formed by plasma CVD (chemical vapor deposition) using raw material gases such as silane, disilane, silicon tetrafluoride, and germane.
It can be grown by CVD, thermal CVD, etc. On the other hand, as the thin film 3 having a wide forbidden band width, silicon oxide produced by optical CVD or plasma CVD, etc.
Insulating films such as silicon nitride, silicon oxynitride, and boron nitride, amorphous silicon carbide similarly produced by photoCVD or plasma CVD, hydrogenated amorphous silicon containing a large amount of dihydride bonded hydrogen, etc. , an amorphous semiconductor with a wide forbidden band width can be used. As the source electrode 5 and drain electrode 6 provided on or in the second semiconductor thin film 4, a metal material such as nickel or aluminum can be used. Note that, if necessary, a doped layer with a high impurity concentration is inserted between the source electrode 5 and the second semiconductor thin film 4 and between the drain electrode 6 and the second semiconductor thin film 4 to improve the ohmic property. It's good to plan. Next, an example of the manufacturing process of the above-described device of the present invention will be explained with reference to FIG. In addition, the branch number in Figure 2
(a) to (e) and the following step numbers (a) to (e) correspond one-to-one, respectively. Step (a) A conductive gate 2 is formed on a substrate 100 made of glass or the like by vacuum evaporation or electron beam evaporation of a metal such as nickel or aluminum. When using SnO2 as a conductive gate instead of metal,
Heat using a mixed gas of SnCl 4 , SbCl 2 , and H 2 O
The SnO 2 thin film 2 is deposited on the substrate by CVD or a spray method using an HCl solution of SnCl 4 .5H 2 O and SbCl 3 . The planar shape of the conductive gate 2 is shaped into a predetermined shape using a known and existing photoetching technique, mask vapor deposition technique, or the like. Step (b) P-type amorphous silicon constituting the first semiconductor thin film 1 is formed on at least the conductive gate 2 by plasma CVD, optical CVD, thermal CVD, etc. using monosilane or disilane and diborane gas. Step (c) A thin film 3 having a wide forbidden band width is formed on the first semiconductor thin film 1 (in this case, p-type amorphous silicon) by plasma CVD or optical CVD using a mixed gas of N 2 O and silane. , forming a silicon oxynitride film. Step (d) A second semiconductor thin film 4 is formed on the above-mentioned thin film 3 to a predetermined size by a known method similar to that described in step (a), but this second semiconductor thin film 5 is made of silane or disilane. A non-doped hydrogenated amorphous silicon film is obtained by plasma CVD, optical CVD, and thermal CVD. Since such a thin film 4 generally has a weak n-type conductivity type, it forms a barrier for the first semiconductor thin film 1 formed in the above step (b). Step (e) On the non-doped amorphous silicon, which is the second semiconductor thin film 4, metal thin films such as nickel, aluminum, etc., which will become conductive source electrodes 5 and drain electrodes 6, respectively, are formed in the same manner as described in step (a). It is formed into a predetermined shape by a known method, thereby obtaining an element of the present invention having a cross-sectional structure similar to that shown in FIG. In addition to the above-mentioned process examples, in order to increase the stability of the device, thermal CVD, optical
It is also possible to form a thin film 7 made of silicon nitride, silicon oxynitride, etc. by CVD, plasma CVD, etc., and use this as the protective film 7. Furthermore, p or n impurities are selectively introduced into the portions 4s and 4d of the second semiconductor thin film in contact with the source and drain electrodes 5 and 6 by ion implantation, plasma doping, etc., depending on the conductivity type of the channel. By inserting a semiconductor thin film containing these impurities between the second semiconductor thin film 4 and both electrodes 5 and 6, it is possible to improve the ohmic contact between the respective electrodes 5 and 6 and the channel. According to the inventor's experiments, when the first semiconductor thin film 1 is p-type amorphous silicon, step (b)
After that, the surface was oxidized at 100℃ for 10 minutes to form a surface of several tens of Å.
Even if only a small oxide thin film 3 is formed, if a non-doped amorphous silicon thin film 4 is subsequently deposited by hydrogen plasma treatment, there will be a gap between the gate 2 and the amorphous silicon thin film 4.
It was confirmed that a leakage current of less than 10 -10 A/cm 2 flows at 1 V. [Effects] According to the present invention, leakage current between the conductive gate and the second semiconductor thin film is greatly reduced. Therefore, when the device of the present invention is applied to a matrix of a liquid crystal display, the signal charge retention characteristics are improved compared to the conventional device, and the thin film 3 having a wide forbidden band width, which is caused by leakage current, is improved. This has the effect of suppressing characteristic deterioration and dielectric breakdown. Furthermore, since the gate insulating film can be made thinner than before, the transconductance as a field effect element is significantly improved, dramatically improving the operating speed of liquid crystal display panels, etc., and lowering the operating voltage. This reduces power consumption and ultimately increases overall reliability.
第１図は本発明に従つて構成される薄膜電界効
果素子の一実施例の概略的な断面図、第２図は本
発明素子の作製工程例の説明図、である。
図中、１は第一のアモルフアスまたは微結晶半
導体薄膜、２は導電性ゲート、３は広い禁制帯幅
を有する薄膜、４は第二のアモルフアスまたは微
結晶半導体薄膜、５は導電性ソース領域ないしソ
ース電極、６は導電性どれ領域ないしドレイン電
極、７は保護膜、１００は基板、である。
FIG. 1 is a schematic cross-sectional view of one embodiment of a thin film field effect device constructed according to the present invention, and FIG. 2 is an explanatory diagram of an example of the manufacturing process of the device of the present invention. In the figure, 1 is a first amorphous or microcrystalline semiconductor thin film, 2 is a conductive gate, 3 is a thin film with a wide forbidden band width, 4 is a second amorphous or microcrystalline semiconductor thin film, and 5 is a conductive source region or A source electrode, 6 a conductive region or drain electrode, 7 a protective film, and 100 a substrate.
Claims (1)
ルフアスまたは微結晶半導体薄膜と； 該第一のアモルフアスまたは微結晶半導体薄膜
に接して設けられ、広い禁制帯幅を持つ薄膜と； 該広い禁制帯幅を持つ薄膜に接して設けられ、
上記第一のアモルフアスまたは微結晶半導体薄膜
との間でバリアを形成する第二のアモルフアスま
たは微結晶半導体薄膜と； 該第二のアモルフアスまたは微結晶半導体薄膜
の上または中に設けられた導電性ソース、ドレイ
ン領域と； を有して成る薄膜電界効果素子。[Scope of Claims] 1 A conductive gate; A first amorphous or microcrystalline semiconductor thin film provided in contact with the conductive gate; A wide conductive gate provided in contact with the first amorphous or microcrystalline semiconductor thin film; a thin film having a forbidden band width; provided in contact with the thin film having a wide forbidden band width;
a second amorphous or microcrystalline semiconductor thin film forming a barrier between the first amorphous or microcrystalline semiconductor thin film; a conductive source provided on or in the second amorphous or microcrystalline semiconductor thin film; , a drain region; and a thin film field effect device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6124585A JPS61220369A (en) | 1985-03-26 | 1985-03-26 | Thin-film field-effect element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6124585A JPS61220369A (en) | 1985-03-26 | 1985-03-26 | Thin-film field-effect element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220369A JPS61220369A (en) | 1986-09-30 |
| JPH0564862B2 true JPH0564862B2 (en) | 1993-09-16 |
Family
ID=13165652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6124585A Granted JPS61220369A (en) | 1985-03-26 | 1985-03-26 | Thin-film field-effect element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220369A (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
| US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
| US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
| US5032883A (en) * | 1987-09-09 | 1991-07-16 | Casio Computer Co., Ltd. | Thin film transistor and method of manufacturing the same |
| JPH01217421A (en) * | 1988-02-26 | 1989-08-31 | Seikosha Co Ltd | Amorphous silicon thin film transistor array substrate and its production |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| JP2839529B2 (en) * | 1989-02-17 | 1998-12-16 | 株式会社東芝 | Thin film transistor |
-
1985
- 1985-03-26 JP JP6124585A patent/JPS61220369A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61220369A (en) | 1986-09-30 |
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