JPS61220369A - Thin-film field-effect element - Google Patents
Thin-film field-effect elementInfo
- Publication number
- JPS61220369A JPS61220369A JP6124585A JP6124585A JPS61220369A JP S61220369 A JPS61220369 A JP S61220369A JP 6124585 A JP6124585 A JP 6124585A JP 6124585 A JP6124585 A JP 6124585A JP S61220369 A JPS61220369 A JP S61220369A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor layer
- thin film
- thin
- amorphous
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 44
- 230000005669 field effect Effects 0.000 title claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 56
- 230000004888 barrier function Effects 0.000 abstract description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 15
- 239000010408 film Substances 0.000 description 13
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 229910052582 BN Inorganic materials 0.000 description 1
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、薄膜電界効果素子に関するものである。[Detailed description of the invention] [Industrial application field] The present invention relates to a thin film field effect device.
、〔従来の技術〕
アモルファスまたは微結晶半導体薄膜を用いた薄膜電界
効果素子は大面積液晶ディスプレイのマトリクスや周辺
駆動回路への応用に供せられている。従来のこの素子の
基本構造は金属−絶縁物一半導体（Ｍｅｔａｌ −Ｉｎ
ｓｕｌａｔｏｒ−８ｅｍｉｃｏｎｄｕｃｔｏｒ以下ＭＩ
Ｓと称する）接合を有する電界効果トランジスタであっ
た。しかし、アモルファスまたは微結晶半導体のＭＩＳ
接合は導電性ゲートの上に絶縁膜を作るため、ピンホー
ルが多く、結晶半導体のＭＩＳ接合に比べ一般にリーク
電流が大きかった。このため、
１ 液晶ディスプレイのマトリックスに応用した時の信
号電荷の保持特性が低下する。, [Prior Art] Thin film field effect devices using amorphous or microcrystalline semiconductor thin films are used for applications in matrices and peripheral drive circuits of large area liquid crystal displays. The basic structure of this conventional element is metal-insulator-semiconductor (Metal-Insulator).
sulator-8emiconductor MI
It was a field effect transistor with a junction (referred to as S). However, MIS of amorphous or microcrystalline semiconductor
Since the junction creates an insulating film on top of the conductive gate, there are many pinholes, and the leakage current is generally larger than that of MIS junctions made of crystalline semiconductors. For this reason, (1) the signal charge retention characteristics deteriorate when applied to the matrix of a liquid crystal display.
２ キャリアリークが原因となって広い禁制帯幅を有す
る薄膜層の絶縁破壊や特性劣化が生ずる。2. Carrier leakage causes dielectric breakdown and characteristic deterioration of a thin film layer with a wide forbidden band width.
３ 絶縁膜を薄くすることができないためにトランスコ
ンダクタンスが小さい。3. Transconductance is small because the insulating film cannot be made thin.
等の問題があった。There were other problems.
本発明の薄膜電界効果素子は新構造の採用によシ、上記
のリーク電流の低減とゲート絶縁膜の薄膜化によるトラ
ンスコンダクタンスの改良を目的とするものである。以
下、本発明について図面に基づき説明する。The thin film field effect device of the present invention aims to reduce the above-mentioned leakage current and improve transconductance by making the gate insulating film thinner by adopting a new structure. Hereinafter, the present invention will be explained based on the drawings.
第１図は、本発明の薄膜電界効果素子の構成概略図であ
る。第１のアモルファスまたは微結晶半導体層１（以下
第１の半導体層という）を広い禁制帯幅を有する薄膜層
３を第１の半導体層１に接して設ける。この薄膜層３に
接しそ第２のアモルファスまたは微結晶半導体薄膜層４
（以下第２の半導体層という）を設ける。この第２の半
導体層４上または中に導電性のソース領域５、ドレイン
領域６を設ける。FIG. 1 is a schematic diagram of the structure of a thin film field effect device of the present invention. A first amorphous or microcrystalline semiconductor layer 1 (hereinafter referred to as a first semiconductor layer) is provided in contact with a thin film layer 3 having a wide forbidden band width. A second amorphous or microcrystalline semiconductor thin film layer 4 is in contact with this thin film layer 3.
(hereinafter referred to as a second semiconductor layer) is provided. A conductive source region 5 and a conductive drain region 6 are provided on or in this second semiconductor layer 4 .
この素子の基本的な動作は従来型のＭＩＳＷ薄膜電界効
果素子と同様で、ソース領域５とドレイン領域６の間に
ソース・ドレイン電圧を印加し、この時ソース・ドレイ
ン間に流れる電流を導電性ゲート電極２に印加するゲー
ト電圧で制御する。第１の半導体層１は第２の半導体層
４との間にバリアを形成する特性を有するものとする。The basic operation of this device is similar to a conventional MISW thin film field effect device, in which a source-drain voltage is applied between the source region 5 and the drain region 6, and the current flowing between the source and drain is made conductive. It is controlled by the gate voltage applied to the gate electrode 2. It is assumed that the first semiconductor layer 1 has a characteristic of forming a barrier between the first semiconductor layer 1 and the second semiconductor layer 4.
このため、第２の半導体層４と広い禁制帯幅を有する薄
膜層３で形成される接合のリーク電流が大きくても、第
２の半導体層４から広い禁制帯幅を有する層３に流入し
たキャリアはこのバリアのためゲート電極２には到達せ
ず、ゲート電極／第１の半導体層／広い禁制帯幅を有す
る薄膜層／第２の半導体層で構成される多層接合全体と
してのリーク電流は大幅に低減される。また、アモルフ
ァスシリコン系薄膜上に形成した絶縁膜は、一般にピン
ホールが少なくリーク電流が小さいため、第１の半導体
層１としてアモルファスシリコンを用い、その上に広い
禁制帯幅を有する層３としてシリコンオキサイド、シリ
コンナイトライド、シリコンオキシナイトライド等の絶
縁物薄膜層を形成して、第１図の素子構造を実現した場
合には第２の半導体層４と広い禁制帯幅を有する薄膜層
３（この場合、上記絶縁膜層）との接合のリーク電流も
低減される。Therefore, even if the leakage current of the junction formed between the second semiconductor layer 4 and the thin film layer 3 having a wide forbidden band width is large, the leakage current flows from the second semiconductor layer 4 to the layer 3 having a wide forbidden band width. Because of this barrier, carriers do not reach the gate electrode 2, and the leakage current of the entire multilayer junction composed of the gate electrode/first semiconductor layer/thin film layer with a wide forbidden band width/second semiconductor layer is significantly reduced. In addition, since an insulating film formed on an amorphous silicon thin film generally has few pinholes and low leakage current, amorphous silicon is used as the first semiconductor layer 1, and silicon is used as the layer 3 having a wide forbidden band on top of the amorphous silicon. When the device structure shown in FIG. 1 is realized by forming an insulating thin film layer of oxide, silicon nitride, silicon oxynitride, etc., the second semiconductor layer 4 and the thin film layer 3 (having a wide forbidden band width) are formed. In this case, leakage current at the junction with the above-mentioned insulating film layer is also reduced.
導電性ゲート電極２には、ニッケル、アルミニウム等の
金属材料または５ｎ（ｈ、ＩＴＯ等の透明導電性酸化物
を使用する。第１の半導体層１の伝導型は 第２の半導
体層４の伝導型と逆にするか、原子組成または組成比を
変えてヘテロ接合を構成するようにし、第１の半導体層
１が第２の半導体層４に対しバリアを形成する様にする
。即ち、第２の半導体層４が３型の伝導型を有する時は
第１の半導体層１はｐ型の伝導型を有し、第２の半導体
層４がＰ型の伝導型を有する時は第１の半導体層１は旙
型の伝導型を有するものとする。また、同一伝導型でも
バリアが形成されるようなヘテロ接合とする。第１およ
び第２のアモルファスまたは微結晶半導体層はシラン、
ジシラン、四弗化シリコン、ゲルマン等の原料ガスのプ
ラズマＣＶＤ、光ＣＶＤ、熱ＣＶＤ等で成長させる。広
い禁制帯幅を有する薄膜層３には光ＣＶＤ法またはプラ
ズマＣＶＤ法等で作成したシリコンオキサイド、シリコ
ンナイトライド、シリコンオキシナイトライド、ボロン
ナイトライド等の絶縁膜や、同様に光Ｃ−ＶＤ法、プラ
ズマＣＶＤ法で作成したアモルファスシリコンカーバイ
ド、ダイハイドライド結合の水素を多量に含んだ水素化
アモルファスシリコン等の禁制帯幅の広いアモルファス
半導体を用いる。第２の半導体層４上または中に設ける
導電性のソース領域５、ドレイン領域６にはニッケル、
アルミニウム等の金属材料を使用する。また、必要に応
じてソース電極と第２の半導体層４の間およびドレイン
電極と第２の半導体層４０間にそれぞれ、不純物濃度の
高いドープ層を挿入し、オーミック性の向上をはかる。For the conductive gate electrode 2, a metal material such as nickel or aluminum or a transparent conductive oxide such as 5N(h, ITO, etc.) is used.The conductivity type of the first semiconductor layer 1 is the conductivity type of the second semiconductor layer 4. The first semiconductor layer 1 forms a barrier to the second semiconductor layer 4 by reversing the type or by changing the atomic composition or composition ratio to form a heterojunction. When the semiconductor layer 4 has a 3-type conductivity type, the first semiconductor layer 1 has a p-type conductivity type, and when the second semiconductor layer 4 has a p-type conductivity type, the first semiconductor layer 1 has a p-type conductivity type. Layer 1 has a conductivity type of Akebono type.Also, it is a heterojunction in which a barrier is formed even if the conductivity type is the same.The first and second amorphous or microcrystalline semiconductor layers are made of silane,
Growth is performed by plasma CVD, optical CVD, thermal CVD, etc. using a raw material gas such as disilane, silicon tetrafluoride, or germane. The thin film layer 3 having a wide forbidden band width is an insulating film made of silicon oxide, silicon nitride, silicon oxynitride, boron nitride, etc., made by a photo-CVD method or a plasma CVD method, or an insulating film made by a photo-CVD method. , amorphous silicon carbide prepared by plasma CVD method, hydrogenated amorphous silicon containing a large amount of dihydride bonded hydrogen, and other amorphous semiconductors with a wide forbidden band width are used. The conductive source region 5 and drain region 6 provided on or in the second semiconductor layer 4 include nickel,
Use metal materials such as aluminum. Further, if necessary, doped layers with high impurity concentrations are inserted between the source electrode and the second semiconductor layer 4 and between the drain electrode and the second semiconductor layer 40, respectively, to improve ohmic properties.
次に、本発明の薄膜電界効果素子の製造工程例を第２図
に基づき説明する。Next, an example of the manufacturing process of the thin film field effect device of the present invention will be explained based on FIG. 2.
工程（６） ガラス等の基板１００上に導電性ゲート
２をニッケル、アルミニウム等の金
属の真空蒸着、電子ビーム蒸着で形成
するの金属の代シにＳｎｏｗを導電性ゲート２に用いる
時は、５ｎＣ１４，５ｂＣ１ｚ 、ＨｚＯの混合ガスの
熱ＣＶＤまたは５ｎＣ１４・５Ｈ！Ｏと５ｂＣ１ｎのＨ
ＣＩ溶液のスプレー法等でＳｎＯ意を基板上に耐着させ
る。導電性ゲート
２の平面寸法は所定の形状にホトエツ
チング技術、マスク蒸着技術等によシ
整形する。Step (6) Form the conductive gate 2 on the substrate 100 made of glass or the like by vacuum evaporation or electron beam evaporation of metal such as nickel or aluminum. When using Snow as the conductive gate 2 instead of the metal, 5nC14 is used. , 5bC1z, HzO mixed gas thermal CVD or 5nC14・5H! O and H of 5bC1n
The SnO film is made to adhere to the substrate by spraying a CI solution or the like. The planar dimensions of the conductive gate 2 are shaped into a predetermined shape by photoetching technology, mask vapor deposition technology, or the like.
工程（ｂ） モノシランまたはジシランとジボランガ
スのプラズマＣＶＤ、光ＣＶＤ、
熱ＣＶＤ等によシ第１図の第１の半導
体層１に相当するｐ型アモルファスシ
リコンを少なくとも導電性ゲート２の
上に成長させる。Step (b) Grow p-type amorphous silicon corresponding to the first semiconductor layer 1 in FIG. 1 on at least the conductive gate 2 by plasma CVD, optical CVD, thermal CVD, etc. using monosilane or disilane and diborane gas. .
工程（ｃ） 第１の半導体層（この例ではＰ型アモル
ファスシリコン）の上に広い禁制
帯幅を有する薄膜層３として、Ｎ１３とシランの混合ガ
スのプラズマＣＶＤ、
光ＣＶＤでシリコンオキシナイトライ
ドを形成する。Step (c) Silicon oxynitride is formed on the first semiconductor layer (P-type amorphous silicon in this example) by plasma CVD and photoCVD using a mixed gas of N13 and silane as a thin film layer 3 having a wide forbidden band width. Form.
工程（ｄ） 広い禁制帯幅を有する薄ｊＩ３ （この
場合シリコンオキシナイトライド）上
に第２の半導体層４を所定の寸法に形
成する。所定の寸法にする手法は工程
（ａ）に述べたものと同様である。シランまたはジシラ
ンのプラズマＣＶＤ、光
ＣＶＤ、熱ＣＶＤでノンドープ水素化
アモルファスシリコンヲ得る。ノンド
ープ水素化アモルファスシリコンは、
一般に弱い５型の伝導型を有するので、工程（ｂ）で形
成したｐ型アモルファスシリコンはこのノンドープアモ
ルファス
シリコンに対しバリアを形成する。Step (d) A second semiconductor layer 4 is formed to a predetermined size on a thin film (silicon oxynitride in this case) having a wide forbidden band width. The method for achieving the predetermined dimensions is the same as that described in step (a). Non-doped hydrogenated amorphous silicon is obtained by plasma CVD, photo CVD, or thermal CVD of silane or disilane. Since undoped hydrogenated amorphous silicon generally has a weak type 5 conductivity, the p-type amorphous silicon formed in step (b) forms a barrier to this undoped amorphous silicon.
工程（ｅ） 第２の半導体層４である上記ノンドープ
アモルファスシリコン上に導電性
のソース領域５、ドレイン領域６とな
るニッケル、アルミニウム等の金属薄
膜を工程（ａ）に述べた方法で所定の形状に形成し、第
１図に示した実施例と等
価な素子を得る。Step (e) A metal thin film such as nickel or aluminum that will become the conductive source region 5 and drain region 6 is formed into a predetermined shape on the non-doped amorphous silicon that is the second semiconductor layer 4 by the method described in step (a). A device equivalent to the embodiment shown in FIG. 1 is obtained.
さらに、素子の安定度を増すために
半導体薄膜４に接して熱ＣＶＤ、光Ｃ
ＶＤ、プラズマＣＶＤ等によりシリコ
ンナイトライド、シリコンオキシナイ
トライド等からなる保護膜７を設ける
こともできる。また、ソース、ドレイ
ン電極５．６に接している半導体薄膜
４部分にチャネル型に応じてｐまたは
ル形不純物をイオン注入またはプラズ
マドーピング等で選択的に導入するか、゛ これら
の不純物を含む半導体薄膜を第２の半導体層４と電極５
．６の間に挿
入することによシ、電極５．６とチャ
ネルのオーム性接触を良好にすること
ができる。Furthermore, in order to increase the stability of the device, a protective film 7 made of silicon nitride, silicon oxynitride, etc. can be provided in contact with the semiconductor thin film 4 by thermal CVD, optical CVD, plasma CVD, or the like. In addition, depending on the channel type, p- or le-type impurities are selectively introduced into the portion of the semiconductor thin film 4 that is in contact with the source and drain electrodes 5.6 by ion implantation or plasma doping, or a semiconductor containing these impurities is added. The thin film is formed into a second semiconductor layer 4 and an electrode 5.
．． By inserting the channel between the electrodes 5 and 6, good ohmic contact between the electrode 5 and the channel can be achieved.
工程（ｂ）の後に半導体薄膜１がＰ形アモルファスシリ
コンの場合はその表面
を１００℃で１０分酸化して数１０Ａの酸化膜３を形成
しただけでも、その後水素
プラズマ処理をしてノンドープのアモ
ルファスシリコン薄膜４を堆積した場
合、ゲートとアモルファスシリコン膜
４との間に１ｖで１ＯＡ／ｌ１ｍ”以下の電流しか流れ
ないことが確認された。If the semiconductor thin film 1 is made of P-type amorphous silicon after step (b), even if the surface is oxidized at 100° C. for 10 minutes to form an oxide film 3 of several tens of amperes, it is then treated with hydrogen plasma to form a non-doped amorphous silicon. It has been confirmed that when the silicon thin film 4 is deposited, only a current of less than 1OA/l1m" flows between the gate and the amorphous silicon film 4 at 1V.
以上詳細に説明したように、本発明の薄膜電界効果素子
は導電性ゲート２と広い禁制帯幅を有する薄膜層３の間
に、電界効果素子のチャネル部として動作する第２の半
導体層４に対し、バリアを形成する様な第１の半導体層
１を挿入するもので、これによシ、導電性ゲート２と第
２の半導体層４０間のリーク電流が低減され、この結果
、本発明の薄膜電界効果素子を液晶ディスプレイのマト
リクスに応用した時の信号電荷の保持特性が向上し、ま
た、リーク電流が原因となって生ずる広い禁制帯幅を有
する薄膜層３の特性劣化や絶縁破壊が抑制されるという
効果がある。As described above in detail, the thin film field effect device of the present invention has a second semiconductor layer 4 between the conductive gate 2 and the thin film layer 3 having a wide forbidden band width, which acts as a channel portion of the field effect device. On the other hand, the first semiconductor layer 1 that forms a barrier is inserted, thereby reducing the leakage current between the conductive gate 2 and the second semiconductor layer 40, and as a result, the present invention When thin film field effect elements are applied to the matrix of liquid crystal displays, the signal charge retention characteristics are improved, and the characteristic deterioration and dielectric breakdown of the thin film layer 3, which has a wide forbidden band width, caused by leakage current are suppressed. It has the effect of being
さらに、ゲート絶縁膜を従来より薄くすることができる
ので、電界効果素子のトランスコンダクタンスが大幅に
改善され、液晶表示パネル等の動作速度が大幅に改善さ
れると共に動作電圧の低電圧化が可能となシ、全体の信
頼性、電力消費が改善される。Furthermore, since the gate insulating film can be made thinner than before, the transconductance of field effect elements is greatly improved, which greatly improves the operating speed of liquid crystal display panels, etc., and enables lower operating voltages. This improves overall reliability and power consumption.
第１図は本発明の薄膜電界効果素子の構成概略図、第２
図は本発明の薄膜電界効果素子の製造工程例を説明する
ための図である。
図中、１．４はそれぞれ第１、第２のアモルファスまた
は微結晶半導体層、２は導電性ゲート電極、３は広い禁
制帯幅を有する薄膜層、５は導電性ソース領域、６は導
電性ドレイン領域、７は保護膜、１００は基板である。
；：′−−
ｊ 、！、。
指定代理人 電子技術総合研究所長 佐 藤 孝 干ｔ
＋ヶ□〜、番
第１図
第２図
第２図
ｓ ２
手続ネ市正書（自発）
昭和６１年 ４月１０日FIG. 1 is a schematic diagram of the structure of the thin film field effect device of the present invention, and FIG.
The figure is a diagram for explaining an example of the manufacturing process of the thin film field effect device of the present invention. In the figure, 1.4 are the first and second amorphous or microcrystalline semiconductor layers, 2 is a conductive gate electrode, 3 is a thin film layer with a wide forbidden band width, 5 is a conductive source region, and 6 is a conductive layer. A drain region, 7 a protective film, and 100 a substrate. ;:′−− j,! ,. Designated Agent: Takashi Sato, Director, Electronics Technology Research Institute
＋ Month □ ～, Number 1 Figure 2 Figure 2 Figure s 2 Procedural City Official Book (Voluntary) April 10, 1986
Claims (1)
られた第１のアモルファスまたは微結晶半導体薄膜と、
該第１のアモルファスまたは微結晶半導体薄膜に接して
設けられた広い禁制帯幅を有する薄膜と、該広い禁制帯
幅を有する薄膜に接して設けられた第２のアモルファス
または微結晶半導体薄膜と、該第２のアモルファスまた
は微結晶半導体薄膜上または中に設けられた導電性ソー
ス、ドレイン領域とから成る薄膜電界効果素子。a conductive gate electrode; a first amorphous or microcrystalline semiconductor thin film provided in contact with the conductive gate electrode;
a thin film having a wide forbidden band width provided in contact with the first amorphous or microcrystalline semiconductor thin film; a second amorphous or microcrystalline semiconductor thin film provided in contact with the thin film having a wide forbidden band width; A thin film field effect device comprising conductive source and drain regions provided on or in the second amorphous or microcrystalline semiconductor thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6124585A JPS61220369A (en) | 1985-03-26 | 1985-03-26 | Thin-film field-effect element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6124585A JPS61220369A (en) | 1985-03-26 | 1985-03-26 | Thin-film field-effect element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61220369A true JPS61220369A (en) | 1986-09-30 |
| JPH0564862B2 JPH0564862B2 (en) | 1993-09-16 |
Family
ID=13165652
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6124585A Granted JPS61220369A (en) | 1985-03-26 | 1985-03-26 | Thin-film field-effect element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61220369A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5101242A (en) * | 1989-02-17 | 1992-03-31 | International Business Machines Corporation | Thin film transistor |
| US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
| US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
| US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
-
1985
- 1985-03-26 JP JP6124585A patent/JPS61220369A/en active Granted
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5055899A (en) * | 1987-09-09 | 1991-10-08 | Casio Computer Co., Ltd. | Thin film transistor |
| US5166085A (en) * | 1987-09-09 | 1992-11-24 | Casio Computer Co., Ltd. | Method of manufacturing a thin film transistor |
| US5229644A (en) * | 1987-09-09 | 1993-07-20 | Casio Computer Co., Ltd. | Thin film transistor having a transparent electrode and substrate |
| US5327001A (en) * | 1987-09-09 | 1994-07-05 | Casio Computer Co., Ltd. | Thin film transistor array having single light shield layer over transistors and gate and drain lines |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5101242A (en) * | 1989-02-17 | 1992-03-31 | International Business Machines Corporation | Thin film transistor |
| US5221631A (en) * | 1989-02-17 | 1993-06-22 | International Business Machines Corporation | Method of fabricating a thin film transistor having a silicon carbide buffer layer |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0564862B2 (en) | 1993-09-16 |
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| EXPY | Cancellation because of completion of term |