JPH01128573A - Thin film transistor - Google Patents
Thin film transistorInfo
- Publication number
- JPH01128573A JPH01128573A JP28706087A JP28706087A JPH01128573A JP H01128573 A JPH01128573 A JP H01128573A JP 28706087 A JP28706087 A JP 28706087A JP 28706087 A JP28706087 A JP 28706087A JP H01128573 A JPH01128573 A JP H01128573A
- Authority
- JP
- Japan
- Prior art keywords
- silicon film
- polycrystalline silicon
- drain
- electrode
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims description 28
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 42
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 59
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000011159 matrix material Substances 0.000 abstract description 4
- 239000000969 carrier Substances 0.000 abstract description 3
- 239000013078 crystal Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 210000001015 abdomen Anatomy 0.000 description 1
- RBFQJDQYXXHULB-UHFFFAOYSA-N arsane Chemical compound [AsH3] RBFQJDQYXXHULB-UHFFFAOYSA-N 0.000 description 1
- 229910000070 arsenic hydride Inorganic materials 0.000 description 1
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 description 1
- 229910010277 boron hydride Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000002538 fungal effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、薄膜トランジスタに関するものであυ、特に
アクティブマトリックス形平面デイスプレィ表示パネル
における各画素の選択スイッチング素子に用いられる多
結晶シリコン薄膜トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to thin film transistors, and more particularly to polycrystalline silicon thin film transistors used as selective switching elements for each pixel in an active matrix flat display panel.
近年大面積、高精細、高機能なアクティブマトリックス
形平面デイスプレィの実現を狙いに多結晶シリコン薄膜
トランジスタの開発が進められている。このような平面
デイスプレィ表示パネルにおける各画素の選択スイッチ
ング用薄膜トランジスタに対しては、フリッカやクロス
トークがなくコントラスト比が大きい良好な表示品質を
得るたメｉＣＯＦＦ電流が小さく、電流Ｏ０Ｎ１０ＦＦ
比が１０’以上であることが要求されている。In recent years, polycrystalline silicon thin film transistors have been developed with the aim of realizing large-area, high-definition, and highly functional active matrix flat displays. In order to obtain good display quality with no flicker or crosstalk and a high contrast ratio, the thin film transistor for selective switching of each pixel in such a flat display panel has a small current of 0N10FF.
It is required that the ratio is 10' or more.
第２図Ｋｓｐ形または・ｎ形不純物を導入することによ
ル低抵抗化された微結晶シリコン膜、多結晶シリコン膜
あるいはアモルファスシリコン膜を前記多結晶シリコン
膜上に積層し形成されたソース電極及びドレイン電極を
有する多結晶シリコン薄膜トランジスタの断面図を示す
。２０１は基板、ＺＯ２は多結晶シリコン膜、２０３は
ゲート絶縁膜、２０４はゲート電極、２０５はソース電
極、２０６はドレイン電極、２０７は眉間絶縁膜、２０
８は配線である。Figure 2: A source electrode formed by laminating a microcrystalline silicon film, a polycrystalline silicon film, or an amorphous silicon film whose resistance has been reduced by introducing Ksp-type or n-type impurities on the polycrystalline silicon film. 1 shows a cross-sectional view of a polycrystalline silicon thin film transistor having a drain electrode and a drain electrode. 201 is a substrate, ZO2 is a polycrystalline silicon film, 203 is a gate insulating film, 204 is a gate electrode, 205 is a source electrode, 206 is a drain electrode, 207 is an insulating film between the eyebrows, 20
8 is wiring.
前記構造を有する多結晶シリコン薄膜トランジスタでは
、オフ（ＯＦＦ）になった時、すなわち、ｎチャネルト
ランジスタにおいて負のゲート電圧が印加され、ｎチャ
ネルトランジスタにおいて正のゲート電圧が印加された
時、印加されたゲート電圧、ドレイン電圧による電界が
ドレイン接合部２０９に集中する。このように電界が強
くなると、ドレイン接合付近の結晶粒界中のトラップを
介してキャリアが移動するため、ゲートを圧、ドレイン
電圧に依存して大きなリーク電流が流れる。従ってＯＦ
Ｆ電流が犬きくなシ、かつ電流の０Ｎ１０ＦＦ比が小さ
くなるという問題があった。In the polycrystalline silicon thin film transistor having the above structure, when turned off (OFF), that is, when a negative gate voltage is applied to the n-channel transistor, and when a positive gate voltage is applied to the n-channel transistor, the applied An electric field due to the gate voltage and drain voltage is concentrated at the drain junction 209. When the electric field becomes stronger in this way, carriers move through traps in the crystal grain boundaries near the drain junction, so a large leakage current flows through the gate depending on the voltage and drain voltage. Therefore OF
There was a problem that the F current was too weak and the 0N10FF ratio of the current was small.
この発明の目的は、多結晶シリコン薄膜トランジスタの
ＯＦＦ ’ＩＥ流を低減し０Ｎ１０ＦＦ比を増加せしめ
た多結晶シリコン薄膜トランジスタを提供することにあ
る。An object of the present invention is to provide a polycrystalline silicon thin film transistor that reduces the OFF'IE current of the polycrystalline silicon thin film transistor and increases the 0N10FF ratio.
本発明の多結晶シリコン薄膜トランジスタは、多結晶シ
リコン膜上にたとえばプラズマＣＶＤ法によって３００
℃程度の温度で堆積された低抵抗な微結晶シリコン膜、
多結晶シリコン膜またはアそル７アスシリコン膜をソー
ス電極、ドレイン電極に用い、さらに、多結晶シリコン
膜と少なくともドレイン電極との間に、たとえばプラズ
マＣＶＤ法にとって３００℃程度の温度で堆積された前
記ソース電極、ドレイン電極よりも不純物濃度が低い微
結晶シリコン膜、多結晶シリコン膜、あるいはアモルフ
ァスシリコン膜を有することを特徴とする。The polycrystalline silicon thin film transistor of the present invention can be manufactured by depositing 300% on a polycrystalline silicon film by, for example, a plasma CVD method.
A low-resistance microcrystalline silicon film deposited at a temperature of around °C.
A polycrystalline silicon film or an athosilicon film is used as a source electrode and a drain electrode, and the film is deposited between the polycrystalline silicon film and at least the drain electrode at a temperature of about 300° C. for plasma CVD, for example. It is characterized by having a microcrystalline silicon film, a polycrystalline silicon film, or an amorphous silicon film that has a lower impurity concentration than the source electrode and drain electrode.
具体的には、該微結晶シリコン膜、多結晶シリコン膜、
あるいはアモルファスシリコン膜のキャリア濃度が１×
１０ｃＷ１ 以下で該微結晶シリコン膜、多結晶シリ
コン膜、あるいはアモルファスシリコン膜の膜厚が７０
０Å以上であることを特徴とする。Specifically, the microcrystalline silicon film, the polycrystalline silicon film,
Or, if the carrier concentration of the amorphous silicon film is 1×
When the thickness of the microcrystalline silicon film, polycrystalline silicon film, or amorphous silicon film is 70 cm or less at 10 cW1 or less,
It is characterized by having a thickness of 0 Å or more.
従来技術とはゲート電極の直下の多結晶シリコン膜と少
なくともドレイン電極との間に前記ソース電極、ドレイ
ン電極よりも不純物濃度が低い領域を有することが異な
る。The difference from the conventional technology is that there is a region between the polycrystalline silicon film immediately below the gate electrode and at least the drain electrode, the impurity concentration of which is lower than that of the source and drain electrodes.
第１図は、本発明の薄膜トランジスタの実施例の断面図
である。１０１は基板、１０２は多結晶シリコン膜、１
０３はゲート絶縁膜、１０４はゲート電極、１０５は不
純物濃度が低い領域、１０６はソース電極、４０７はド
レイン電極、１ｏｓは眉間絶縁膜、１０９は前記構造を
有する多結晶シリコン薄膜トランジスタでは、従来構造
の多結晶シリコン薄膜トランジスタとは異なシ、ゲート
の直下のシリコン膜とソース電極及びドレイン電極との
間に不純物濃度が低い領域を有する。この構造によると
ＯＦＦ’ Ｋなった時、すなわち、ｎチャネルトランジ
スタにおいて負のゲート電圧が印加され、ｎチャネルト
ランジスタにおいて正のゲート電圧が印加された時、印
加されるゲート電圧、ドレイン電圧による電界が前記不
純物濃度が低い領域内で分散される。このため、ドレイ
ン接合部の電界強度が弱まり、ドレイン接合付近の結晶
粒界中のトラップを介して移動するキャリアが少なくな
る。従って、ゲート電圧、ドレイン電圧に依存するリー
ク電流を抑制できる。FIG. 1 is a cross-sectional view of an embodiment of a thin film transistor of the present invention. 101 is a substrate, 102 is a polycrystalline silicon film, 1
03 is a gate insulating film, 104 is a gate electrode, 105 is a region with low impurity concentration, 106 is a source electrode, 407 is a drain electrode, 1os is an eyebrow insulating film, and 109 is a polycrystalline silicon thin film transistor having the above structure. Unlike a polycrystalline silicon thin film transistor, it has a region with a low impurity concentration between the silicon film directly under the gate and the source and drain electrodes. According to this structure, when OFF' K is applied, that is, when a negative gate voltage is applied to the n-channel transistor and a positive gate voltage is applied to the n-channel transistor, the electric field due to the applied gate voltage and drain voltage is The impurity concentration is dispersed within the low concentration region. Therefore, the electric field strength at the drain junction is weakened, and fewer carriers move through traps in the grain boundaries near the drain junction. Therefore, leakage current depending on the gate voltage and drain voltage can be suppressed.
第３図に、従来構造の薄膜トランジスタと本発明による
薄膜トランジスタのゲート電圧に対するドレイン電流の
変化を示す。本発明による薄膜トランジスタでは、ゲー
ト電圧−２０ＶでのＯＦＦ を流１／１０００であシ、
従来構造の薄膜トランジスタの０Ｎ１０ＦＦ比よ９２桁
以上大きい０Ｎ１０ＦＦ比が得られる。このため、容易
に１０５以上の０Ｎ１０ＦＦ比を得ることができる。FIG. 3 shows changes in drain current with respect to gate voltage of a thin film transistor with a conventional structure and a thin film transistor according to the present invention. In the thin film transistor according to the present invention, the OFF current at a gate voltage of -20V is 1/1000;
An 0N10FF ratio that is 92 orders of magnitude higher than the 0N10FF ratio of a thin film transistor with a conventional structure can be obtained. Therefore, an 0N10FF ratio of 105 or more can be easily obtained.
しかし、第４図に示すようにドレイン接合部の電界強度
とリーク電流の関係を調べた結果ドレイン接合部電界強
度が３Ｍｖ／ｃｍ以上で急激にリーク電流が増加するこ
とがわかった。このため、ドレイン接合部の電界強度ｆ
３ＭＶ／Ｃｒｎ以下にするには不純物濃度が低い領域
の膜厚ｉ ７００ Ａ以上、キャリア濃度ｉ１Ｘ１０ｍ
以下に設定すればよく、この菌性の下でＯＦＦ ｓ
流の低減効果を得ることができる。However, as shown in FIG. 4, as a result of examining the relationship between the electric field strength at the drain junction and the leakage current, it was found that the leakage current increases rapidly when the electric field strength at the drain junction exceeds 3 Mv/cm. Therefore, the electric field strength f at the drain junction is
To make it 3MV/Crn or less, the film thickness in the region with low impurity concentration must be 700 A or more, and the carrier concentration must be i1×10m.
All you have to do is set it as below, and it will turn OFF under this fungal condition.
The effect of reducing flow can be obtained.
また、前記薄膜トランジスタの製造工程の実施例では、
プラズマＣＶＤ法によって形成されたシリコン膜を用い
たが、この方法に限ることはなく光ＣＶＤ法、スパッタ
法等でもよい。またシリコン膜を低抵抗化するために不
純物源としてＰＨ８’ｉ用いたが、これに限ることはな
く、ボロン水素化物、ヒ素水素化物でもよい。Further, in the embodiment of the manufacturing process of the thin film transistor,
Although a silicon film formed by a plasma CVD method is used, the method is not limited to this method, and a photo-CVD method, a sputtering method, or the like may be used. Further, although PH8'i is used as an impurity source to lower the resistance of the silicon film, the impurity source is not limited to this, and boron hydride or arsenic hydride may also be used.
以上説明したように、本発明によれば、多結晶シリコン
薄膜トランジスタのＯＦＦ を流を低減でき、かつ十分
な０Ｎ１０ＦＦ比を有する多結晶シリコン薄膜トランジ
スタを実現できる。これによシ、アクティブマトリック
ス形平面デイスプレィ表示ノ（ネルの大面積化、高精細
化が可能となる。As described above, according to the present invention, it is possible to reduce the OFF current of a polycrystalline silicon thin film transistor and to realize a polycrystalline silicon thin film transistor having a sufficient 0N10FF ratio. This makes it possible to display an active matrix type flat display (larger area and higher resolution).
第１図は、本発明の多結晶シリコン薄膜トランジスタの
構造である。
第２図は、従来の多結晶シリコン薄膜トランジスタの構
造である。
第３図は、従来の多結晶シリコン薄膜トランジスタと本
発明の多結晶シリコン薄膜トランジスタのゲート電圧に
よるドレイン電流の変化の測定結果である。
第４図は、ドレイン接合部の電界強度とリーク電流の関
係である。
１０１・・・絶縁基板
１０２・・・多結晶シリコン膜
１０３・・・ゲート絶縁膜
１０４・・・ゲート電極
１０５・・・不純物濃度が低い微結晶シリコン膜、多結
晶シリコン膜あるいはアモルファスシリコン膜
１０６・・・低抵抗な微結晶シリコン膜、多結晶シリコ
ン膜あるいはアモルファスシリコン膜によるソース電極
１０７・・・低抵抗な微結晶シリコン膜、多結晶シリコ
ン膜あるいはアモルファスシリコン膜によるドレイン電
極
１０８・・・層間絶縁膜
１０９・・・配線
２０１・・・絶縁基板
２０２・・・多結晶シリコン膜
２０３・・・ゲート絶縁膜
２０４・・・ゲート電極
２０５・・・ソース電極
２０６・・・ドレイン電極
２０７・・・層間絶縁膜
２０８・・・配線
２０９・・・ドレイン接合部
特許出願人 日本電信電話株式会社
代 理 人 弁理士玉蟲久五部（外２名）本発明の多結
晶シリコン薄膜トランジスタの構造第 １ 図
従来の多結晶シリうン薄腹トランジスタの構造第 ２
８ｉａ
ドレイン接合部の電圧 （Ｖ／ｃ ｍ ）ドレイン接合
部の電界殖とリーク電流の関係第 ４ 図FIG. 1 shows the structure of a polycrystalline silicon thin film transistor of the present invention. FIG. 2 shows the structure of a conventional polycrystalline silicon thin film transistor. FIG. 3 shows measurement results of changes in drain current depending on gate voltage of a conventional polycrystalline silicon thin film transistor and a polycrystalline silicon thin film transistor of the present invention. FIG. 4 shows the relationship between electric field strength and leakage current at the drain junction. 101... Insulating substrate 102... Polycrystalline silicon film 103... Gate insulating film 104... Gate electrode 105... Microcrystalline silicon film, polycrystalline silicon film, or amorphous silicon film with low impurity concentration 106... ...Source electrode 107 made of low resistance microcrystalline silicon film, polycrystalline silicon film or amorphous silicon film...Drain electrode 108 made of low resistance microcrystalline silicon film, polycrystalline silicon film or amorphous silicon film...Interlayer insulation Film 109...Wiring 201...Insulating substrate 202...Polycrystalline silicon film 203...Gate insulating film 204...Gate electrode 205...Source electrode 206...Drain electrode 207...Interlayer Insulating film 208...Wiring 209...Drain junction Patent applicant: Nippon Telegraph and Telephone Corporation Agent: Patent attorney Gobe Tamamushi (two others) Structure of polycrystalline silicon thin film transistor of the present invention Fig. 1 Conventional Structure of polycrystalline silicon thin belly transistor Part 2
8ia Drain junction voltage (V/cm) Relationship between electric field multiplication and leakage current at drain junction Figure 4
Claims (2)
たはｎ形不純物を導入した微結晶シリコン膜、多結晶シ
リコン膜あるいはアモルファスシリコン膜を前記多結晶
シリコン膜上に積層し形成されたソース電極及びドレイ
ン電極と、前記多結晶シリコン膜に積層されたゲート絶
縁膜を介して設けられたゲート電極とを具備した薄膜ト
ランジスタにおいて、前記多結晶シリコン膜と少なくと
もドレイン電極との間に、前記ソース電極、ドレイン電
極よりも不純物濃度が低い微結晶シリコン膜、多結晶シ
リコン膜、あるいはアモルファスシリコン膜を有するこ
とを特徴とする薄膜トランジスタ。(1) A polycrystalline silicon film formed on a substrate and a microcrystalline silicon film doped with p-type or n-type impurities, a polycrystalline silicon film, or an amorphous silicon film are stacked on the polycrystalline silicon film. In a thin film transistor comprising a source electrode, a drain electrode, and a gate electrode provided through a gate insulating film laminated on the polycrystalline silicon film, the source electrode is provided between the polycrystalline silicon film and at least the drain electrode. A thin film transistor characterized by having a microcrystalline silicon film, a polycrystalline silicon film, or an amorphous silicon film that has a lower impurity concentration than an electrode or a drain electrode.
が低い微結晶シリコン膜、多結晶シリコン膜、あるいは
アモルファスシリコン膜の膜厚が７００Å以上であり、
かつそのキャリア濃度が１×１０＾１＾７ｃｍ＾−＾３
以下であることを特徴とする特許請求の範囲第１項記載
の薄膜トランジスタ。(2) The thickness of the microcrystalline silicon film, polycrystalline silicon film, or amorphous silicon film having a lower impurity concentration than the source electrode and drain electrode is 700 Å or more,
And its carrier concentration is 1×10^1^7cm^-^3
The thin film transistor according to claim 1, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28706087A JPH0828513B2 (en) | 1987-11-13 | 1987-11-13 | Thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28706087A JPH0828513B2 (en) | 1987-11-13 | 1987-11-13 | Thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01128573A true JPH01128573A (en) | 1989-05-22 |
| JPH0828513B2 JPH0828513B2 (en) | 1996-03-21 |
Family
ID=17712532
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP28706087A Expired - Fee Related JPH0828513B2 (en) | 1987-11-13 | 1987-11-13 | Thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0828513B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04155735A (en) * | 1990-10-18 | 1992-05-28 | Nec Corp | Fluorescent display device |
| JPH04163837A (en) * | 1990-10-26 | 1992-06-09 | Nec Kagoshima Ltd | Fluorescent display device |
| US6153893A (en) * | 1993-11-05 | 2000-11-28 | Sony Corporation | Thin film semiconductor device for display |
| JP2010022377A (en) * | 2009-10-30 | 2010-02-04 | Akamatsu Kasei Kogyo Kk | Packaged filled bean curd |
-
1987
- 1987-11-13 JP JP28706087A patent/JPH0828513B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04155735A (en) * | 1990-10-18 | 1992-05-28 | Nec Corp | Fluorescent display device |
| JPH04163837A (en) * | 1990-10-26 | 1992-06-09 | Nec Kagoshima Ltd | Fluorescent display device |
| US6153893A (en) * | 1993-11-05 | 2000-11-28 | Sony Corporation | Thin film semiconductor device for display |
| JP2010022377A (en) * | 2009-10-30 | 2010-02-04 | Akamatsu Kasei Kogyo Kk | Packaged filled bean curd |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0828513B2 (en) | 1996-03-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |