JP2675587B2 - Matrix type liquid crystal display panel - Google Patents
Matrix type liquid crystal display panelInfo
- Publication number
- JP2675587B2 JP2675587B2 JP20086488A JP20086488A JP2675587B2 JP 2675587 B2 JP2675587 B2 JP 2675587B2 JP 20086488 A JP20086488 A JP 20086488A JP 20086488 A JP20086488 A JP 20086488A JP 2675587 B2 JP2675587 B2 JP 2675587B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- contact layer
- liquid crystal
- channel
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 18
- 239000011159 matrix material Substances 0.000 title claims description 15
- 239000010408 film Substances 0.000 claims description 64
- 239000010410 layer Substances 0.000 claims description 39
- 230000001681 protective effect Effects 0.000 claims description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 18
- 239000010409 thin film Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 description 8
- 238000001259 photo etching Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 230000004913 activation Effects 0.000 description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 4
- SBEQWOXEGHQIMW-UHFFFAOYSA-N silicon Chemical compound [Si].[Si] SBEQWOXEGHQIMW-UHFFFAOYSA-N 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 229910020776 SixNy Inorganic materials 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010790 dilution Methods 0.000 description 1
- 239000012895 dilution Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78663—Amorphous silicon transistors
- H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
Description
【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体膜にアモルファスシリコン（以下
「ａ−Si」と略す）膜を用いた薄膜トランジスタ（以下
「TFT」と略す）をアドレス素子としてマトリックス表
示を行なうマトリックス型液晶表示パネルに関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention uses a thin film transistor (hereinafter abbreviated as “TFT”) using an amorphous silicon (hereinafter abbreviated as “a-Si”) film as a semiconductor film as an address element. The present invention relates to a matrix type liquid crystal display panel that performs matrix display.
〈従来の技術〉 従来、この種の液晶表示パネルに用いられる逆スタガ
型のTFTとして、例えば第１図（便宜上第１図を用い
る）に示す構造のものがある。このTFTは、絶縁性基板
１の上にまず基板保護膜２を形成し、次にゲート電極3,
ゲート絶縁膜4,チャネル部ｉ型ａ−Si膜5,チャネル部保
護絶縁膜6,コンタクト層たる導電率10-4〜10-2S/cmのn+
型ａ−Si膜17,ソース・ドレイン電極８・８′，絵素電
極9,保護絶縁膜10を順次積層し、パターン化することに
よって形成される。そして、上記TFTを用いた液晶表示
パネルは、第２図（便器上第２図を用いる）に示すよう
な配列になっている。即ち、パネル表示部の画素に相当
する上記絵素電極９は、ゲート電極３に連なる各ゲート
バスバー３およびソース電極８に連なるソースバスバー
11の交差部においてTFTのドレイン電極８′と接続され
ており、ソースバスバー11に画像信号を、ゲートバスバ
ーに走査信号を夫々入力してTFTをスイッチング動作さ
せ、各絵素電極９に夫々同期した画像信号電流を充電し
て液晶を駆動している。<Prior Art> Conventionally, as an inverted stagger type TFT used in this type of liquid crystal display panel, there is, for example, a structure shown in FIG. 1 (for convenience, FIG. 1 is used). In this TFT, the substrate protection film 2 is first formed on the insulating substrate 1, and then the gate electrode 3,
Gate insulating film 4, channel i-type a-Si film 5, channel protective insulating film 6, conductivity of contact layer 10 −4 to 10 −2 S / cm n +
It is formed by sequentially laminating the type a-Si film 17, the source / drain electrodes 8 and 8 ', the pixel electrode 9, and the protective insulating film 10 and patterning them. The liquid crystal display panel using the above TFT is arranged as shown in FIG. 2 (using FIG. 2 on the toilet bowl). That is, the pixel electrodes 9 corresponding to the pixels of the panel display unit are the source bus bars connected to the respective gate bus bars 3 connected to the gate electrodes 3 and the source electrodes 8.
It is connected to the drain electrode 8 ′ of the TFT at the intersection of 11 and the image signal is input to the source bus bar 11 and the scanning signal is input to the gate bus bar to perform the switching operation of the TFT, which is synchronized with each pixel electrode 9. The liquid crystal is driven by charging the image signal current.
〈発明が解決しようとする課題〉 ところが、上記従来のTFTのチャネル部のｉ型ａ−Si
膜５とソース・ドレイン電極８・８′間のコンタクト層
17は、n+型ａ−Si膜で形成されているため、電子と正孔
の移動度端で挾まれた易動ギャップ中にキャリアの高濃
度な局在状態密度が存在し、リンを１％以上ドープして
もバンド端近くでフェルミ準位がくぎずけされる。その
ため、導電率が10-2〜10-4S/cmと低くなり、活性化エネ
ルギも0.2eV程度で飽和してしまって、電極８・８′と
の間で良好なオーミック接触が得られないという欠点が
ある。さらに、上記従来のTFTは、絶縁性基板１上に細
かいピッチで配置された線幅数十μｍ程度のゲート配線
３上に形成され、各層のコンタクト面もゲート線幅で制
約されるため、コンタクト領域でのオーミック接触抵抗
や面抵抗といった直列抵抗成分が増大し、スイッチング
素子たるTFTのオン−オフ特性に悪影響を及ぼす。即
ち、上記直列抵抗成分の増大により、各絵素電極９に十
分な画像信号電流が充電されず、液晶の駆動に支障をき
たし、表示パネルの画質低下をもたらすという欠点があ
る。<Problems to be Solved by the Invention> However, the i-type a-Si of the channel portion of the conventional TFT described above is used.
Contact layer between film 5 and source / drain electrodes 8 and 8 '
Since No. 17 is formed of an n + -type a-Si film, there is a high density of localized states of carriers in the mobility gap sandwiched by the mobility edges of electrons and holes, and phosphorus of 1 %, The Fermi level is cleaved near the band edge even if doped. Therefore, the conductivity becomes as low as 10 -2 to 10 -4 S / cm, and the activation energy is saturated at about 0.2 eV, and good ohmic contact cannot be obtained with the electrodes 8 and 8 '. There is a drawback that. Further, the conventional TFT is formed on the gate wiring 3 having a line width of several tens of μm and arranged on the insulating substrate 1 at a fine pitch, and the contact surface of each layer is also restricted by the gate line width. The series resistance components such as ohmic contact resistance and surface resistance in the area increase, which adversely affects the on-off characteristics of the TFT, which is a switching element. That is, due to the increase of the series resistance component, each pixel electrode 9 is not charged with a sufficient image signal current, which hinders the driving of the liquid crystal and causes the deterioration of the image quality of the display panel.
そこで、本発明の目的は、チャネル部のａ−Si膜とソ
ース・ドレイン電極との間にコンタクト層を新規な組成
にすることによって、コンタクト領域の直列抵抗成分を
低減し、TFTのオン−オフ特性を改善し、画質を向上さ
せることができるマトリックス型液晶表示パネルを提供
することである。Therefore, an object of the present invention is to reduce the series resistance component of the contact region by providing a novel composition of the contact layer between the a-Si film of the channel portion and the source / drain electrodes, thereby turning on / off the TFT. An object of the present invention is to provide a matrix type liquid crystal display panel capable of improving characteristics and improving image quality.
〈課題を解決するための手段〉 上記目的を達成するため、本発明のマトリックス型液
晶表示パネルは、アモルファスシリコン膜をチャネル部
に用いた薄膜トランジスタをアドレス素子としてマトリ
ックス表示を行なうマトリックス型液晶表示パネルにお
いて、上記薄膜トランジスタのチャネル部の中央表面に
形成されたチャネル部保護絶縁膜と、上記チャネル部お
よび上記チャネル部保護絶縁膜を覆い、かつ上記チャネ
ル部保護絶縁膜上で左右に分離されて並設され、導電率
が100S/cm以上の微結晶ｎ型シリコン膜によって形成さ
れた一対のコンタクト層と、上記一方のコンタクト層上
に形成されたソース電極と、上記他方のコンタクト層上
に形成されたドレイン電極とを備え、上記チャネル部の
表面には、上記チャネル部保護絶縁膜との間でシリコン
−絶縁体接合が形成され、上記一対のコンタクト層との
間でシリコン−シリコン系接合が形成されていることを
特徴とする。なお、上記微結晶ｎ型シリコン膜は、より
好ましくはプラズマCVD法で形成される微結晶ｎ型Si膜
である。<Means for Solving the Problems> In order to achieve the above object, a matrix type liquid crystal display panel of the present invention is a matrix type liquid crystal display panel for performing matrix display using a thin film transistor using an amorphous silicon film as a channel portion as an address element. A channel part protective insulating film formed on the central surface of the channel part of the thin film transistor, and covering the channel part and the channel part protective insulating film, and being juxtaposed side by side on the channel part protective insulating film. a pair of contact layers conductivity formed by 10 0 S / cm or more microcrystalline n-type silicon film, a source electrode formed on one of the contact layer described above is formed on the other contact layer And a drain electrode, and on the surface of the channel section, between the channel section protective insulating film and A silicon-insulator bond is formed, and a silicon-silicon based bond is formed between the pair of contact layers. The microcrystalline n-type silicon film is more preferably a microcrystalline n-type Si film formed by a plasma CVD method.
〈作用〉 コンタクト層である微結晶ｎ型シリコン膜は、活性化
エネルギが0.02eV程度と低いうえ、導電率が100S/cm以
上と従来のn+型ａ−Si膜に比べて２桁以上高いので、ソ
ース・ドレイン電極相互のコンタクト層材料としてより
良好なオーミック接触が得られる。従って、コンタクト
領域でのオーミック接触抵抗や面抵抗といった直列抵抗
成分を従来よりも格段に低減することができ、半導体層
界面のキャリア移動能力が高く維持されるので、TFTの
オン−オフ特性や画質を著しく向上させることができ
る。<Action> microcrystalline n-type silicon film is a contact layer, upon the activation energy is lower and about 0.02 eV, conductivity is 10 0 S / cm or more and two orders of magnitude as compared with the conventional n + -type a-Si film Since it is higher than the above, a better ohmic contact can be obtained as a contact layer material between the source and drain electrodes. Therefore, the series resistance components such as ohmic contact resistance and surface resistance in the contact region can be significantly reduced as compared with the conventional one, and the carrier transfer capability at the semiconductor layer interface can be maintained high, so that the TFT on-off characteristics and image quality can be improved. Can be significantly improved.
また、アモルファスシリコン膜からなるチャネル部の
中央表面にチャネル部保護絶縁膜が形成されている（即
ち、チャネル部界面がシリコン−絶縁体異種接合となっ
ている）ので、製造工程でコンタクト層の積層の際にチ
ャネル部への不純物の拡散が阻止され、続いてソース・
ドレイン電極を分離する際、エッチング液が上記チャネ
ル部保護絶縁膜で阻止されてチャネル部に接触せず、動
作時にキャリアの主通路となるチャネル部の表層がエッ
チングされないので、TFTの動作特性を良好に維持する
ことができる。In addition, since the channel protective insulating film is formed on the central surface of the channel made of the amorphous silicon film (that is, the interface of the channel is a silicon-insulator heterojunction), the contact layers are laminated in the manufacturing process. Diffusion of impurities to the channel is blocked during the
When the drain electrode is separated, the etching liquid is blocked by the channel protection insulating film and does not come into contact with the channel, and the surface layer of the channel, which is the main passage of carriers during operation, is not etched, resulting in good TFT operating characteristics. Can be maintained at.
〈実施例〉 以下、本発明を図示の実施例により詳細に説明する。<Example> Hereinafter, the present invention will be described in detail with reference to an illustrated example.
第１図は本発明のマトリックス型液晶表示パネルに用
いられるTFTの一例を示す構造断面図であり、このTFT
は、次の手順で製造される。まず、ガラス製の絶縁性基
板１上に、スパッタリングで五酸化タンタルからなる基
板保護膜２を3000Åの厚さに形成する。次に、この上に
スパッタリングでタンタルを3000Åの厚さに積層し、フ
ォトエッチングによってゲート電極３を形成する。この
ゲート電極３上にプラズマCVDによって窒化膜（SixNy
膜）を4000Åの厚さに形成してゲート絶縁膜４とし、続
いてｉ型ａ−Si膜を150ÅさらにSixNy膜を2000Å積層し
た後、両者をフォトエッチングでパターン化して夫々チ
ャネル部半導体膜５およびチャネル部保護絶縁膜６を形
成する。FIG. 1 is a structural sectional view showing an example of a TFT used in the matrix type liquid crystal display panel of the present invention.
Is manufactured by the following procedure. First, a substrate protection film 2 made of tantalum pentoxide having a thickness of 3000 Å is formed on a glass-made insulating substrate 1 by sputtering. Next, tantalum is deposited thereon to a thickness of 3000 Å by sputtering, and the gate electrode 3 is formed by photoetching. A nitride film (SixNy) is formed on the gate electrode 3 by plasma CVD.
Film) to have a thickness of 4000 Å to form the gate insulating film 4, then 150 Å of an i-type a-Si film and 2000 Å of a SixNy film are laminated, and both are patterned by photoetching to form a channel portion semiconductor film 5 respectively. Then, the channel portion protective insulating film 6 is formed.
本発明の主要部たるコンタクト層７は、圧力を1Torr
以下、モノシランに対するホスヒンガス濃度を１％以
上、かつ水素希釈量をモノシランガスに対して30倍以上
にしたチャンバー内に基板を300℃以下に保持し、RFパ
ワー密度0.05W/cm2以上のプラズマCVD法によって、上記
チャネル部半導体膜５およびチャネル部保護絶縁膜６上
に導電率100S/cm以上の微結晶ｎ型Si膜を400Åの厚さに
形成し、フォトエッチングでパターン化して作られる。The contact layer 7, which is a main part of the present invention, has a pressure of 1 Torr.
Below, the plasma CVD method with RF power density of 0.05 W / cm 2 or more is performed by keeping the substrate at 300 ° C. or less in a chamber in which the concentration of phosphine gas with respect to monosilane is 1% or more and the hydrogen dilution amount is 30 times or more with respect to monosilane gas. Accordingly, the electric conductivity 10 0 S / cm or more microcrystalline n-type Si layer on the channel-region semiconductor film 5 and the channel portion protective insulating film 6 is formed to a thickness of 400 Å, is made by patterning by photo-etching.
さらに、このコンタクト層７上にスパッタリングまた
は電子ビーム蒸着によってTi,Mo,W等の金属膜を3000Å
の厚さに形成し、フォトエッチングでパターン化するこ
とによりソースおよびドレイン電極8,8′とし、次に同
じスパッタリングまたは電子ビーム蒸着によって酸化イ
ンジウムを主成分とする透明導電膜を1000Åの厚さに形
成し、これをフォトエッチングでパターン化して表示用
絵素電極９を形成する。最後に、これら各層の全表面に
プラズマCVD法によってSixNy膜を5000Åの厚さに積層し
て保護絶縁膜10とする。Furthermore, a metal film of Ti, Mo, W, etc. is deposited on the contact layer 7 by sputtering or electron beam evaporation at a rate of 3000Å.
To the source and drain electrodes 8 and 8'by patterning by photo-etching, and then the same conductive film mainly composed of indium oxide with a thickness of 1000Å by the same sputtering or electron beam evaporation. It is formed and patterned by photoetching to form the display pixel electrode 9. Finally, a SixNy film having a thickness of 5000 Å is laminated on the entire surface of each of these layers by the plasma CVD method to form the protective insulating film 10.
なお、上記実施例の各層の積層形態は、従来のTFTと
何ら異ならないので、コンタクト層７以外の各層には同
じ番号を付している。また、上記TFTの集合体たるマト
リックス型液晶表示パネルの形態も、第２図に示すよう
に実施例と従来例で同じである。Since the laminated form of each layer in the above-mentioned embodiment is no different from that of the conventional TFT, each layer other than the contact layer 7 is denoted by the same reference numeral. The form of the matrix type liquid crystal display panel, which is an aggregate of the TFTs, is the same in the embodiment and the conventional example as shown in FIG.
第４図は、上記実施例の微結晶ｎ型Si膜からなるコン
タクト層７の導電特性を、従来例のn+型ａ−Si膜からな
るコンタクト層17のそれと比較して示している。同図の
横軸には、第３図に示すチャネル部のｉ型ａ−Si膜５と
コンタクト層7,17の接触長さｌ（＝l1＋l2）をとり、縦
軸にはTFTのオン電流をとっている。図から明らかなよ
うに、曲線Ｂで示すn+型ａ−Si膜を用いた従来のTFTで
はオン電流がコンタクト長ｌに依存するのに対して、曲
線Ａで示す微結晶ｎ型Si膜を用いた本実施例のTFTでは
オン電流がコンタクト長ｌにほとんど依存しておらず、
電流値も高い。これは、微結晶ｎ型Si膜では、活性化エ
ネルギが0.02eVとｎ型ａ−Si膜の0.2eVよりも１桁低
く、導電率も101〜100S/cmとn+型ａ−Si膜の10-2〜10-4
S/cmよりも３桁程度高いため、コンタクト領域でのオー
ミック接触抵抗や面抵抗が著しく低くなって、TFTのオ
ン−オフ特性に悪影響を及ぼさなくなったからである。
従って、TFTのパターン上でコンタクト層の面積が規制
されても、微結晶ｎ型Si膜によってコンタクト領域での
直列抵抗成分を著しく低減することができ、TFTのオン
−オフ特性やこれを用いマトリックス型液晶表示パネル
の画質を格段に向上させることができるのである。FIG. 4 shows the conductive characteristics of the contact layer 7 made of the microcrystalline n-type Si film of the above-mentioned embodiment in comparison with that of the contact layer 17 made of the n + -type a-Si film of the conventional example. The abscissa of the figure shows the contact length l (= l 1 + l 2 ) between the i-type a-Si film 5 of the channel portion and the contact layers 7 and 17 shown in FIG. 3, and the ordinate shows the TFT It is taking on current. As is clear from the figure, in the conventional TFT using the n + -type a-Si film shown by the curve B, the on-current depends on the contact length l, whereas the microcrystalline n-type Si film shown by the curve A is used. In the TFT of this embodiment used, the on-current hardly depends on the contact length l,
The current value is also high. This is because the microcrystalline n-type Si layer, an order of magnitude lower than 0.2eV activation energy of 0.02eV and the n-type a-Si film, the conductivity also 10 1 ~10 0 S / cm and the n + -type a- Si film 10 -2 to 10 -4
Since it is higher than S / cm by about three digits, ohmic contact resistance and surface resistance in the contact region are remarkably reduced, and the on-off characteristics of the TFT are not adversely affected.
Therefore, even if the area of the contact layer is regulated on the TFT pattern, the series resistance component in the contact region can be significantly reduced by the microcrystalline n-type Si film. The image quality of the liquid crystal display panel can be significantly improved.
なお、本発明が図示の実施例に限られないのはいうま
でもない。It goes without saying that the present invention is not limited to the illustrated embodiment.
〈発明の効果〉 以上の説明で明らかなように、本発明のマトリックス
型液晶表示パネルは、アモルファスシリコン膜をチャネ
ル部に用いた薄膜トランジスタをアドレス素子としてマ
トリックス表示を行なうマトリックス型液晶表示パネル
において、上記薄膜トランジスタのチャネル部の中央表
面に形成されたチャネル部保護絶縁膜と、上記チャネル
部および上記チャネル部保護絶縁膜を覆い、かつ上記チ
ャネル部保護絶縁膜上で左右に分離されて並設され、導
電率が100S/cm以上の微結晶ｎ型シリコン膜によって形
成された一対のコンタクト層と、上記一方のコンタクト
層上に形成されたソース電極と、上記他方のコンタクト
層上に形成されたドレイン電極とを備え、上記チャネル
部の表面には、上記チャネル部保護絶縁膜との間でシリ
コン−絶縁体接合が形成され、上記一対のコンタクト層
との間でシリコン−シリコン系接合が形成されているの
で、コンタクト層の活性化エネルギを低減し、導電率を
増加して、コンタクト領域での直列抵抗成分を格段に低
減することができて、TFTのオン電流がコンタクト長の
変動に影響されることなく一定の高値を示し、薄膜トラ
ンジスタのオン−オフ特性やパネルの画質を著しく向上
させ、あるいは小型化によりコンタクト層の面積が規制
される場合は、オン−オフ特性やパネルの画質を良好に
維持することができる。なお、チャネル部界面がシリコ
ン−絶縁体接合とシリコン−シリコン系接合で構成さ
れ、シリコン−シリコン系接合のエリアが少なくなる即
ちキャリアの移動領域が縮減される分だけ、コンタクト
領域の抵抗を上述の如く下げることによって補償してい
る。<Effects of the Invention> As is apparent from the above description, the matrix type liquid crystal display panel of the present invention is a matrix type liquid crystal display panel for performing matrix display using a thin film transistor using an amorphous silicon film as a channel portion as an address element. A channel portion protective insulating film formed on the central surface of the channel portion of the thin film transistor, and covering the channel portion and the channel portion protective insulating film, and arranged side by side on the channel portion protective insulating film to be electrically conductive. a pair of contact layers rate is formed by 10 0 S / cm or more microcrystalline n-type silicon film, a source electrode formed on one of the contact layer on the drain which is formed on the other contact layer An electrode, and on the surface of the channel portion, silicon between the channel portion protective insulating film and Since the insulator junction is formed and the silicon-silicon based junction is formed between the pair of contact layers, the activation energy of the contact layer is reduced, the conductivity is increased, and the series in the contact region is increased. The resistance component can be significantly reduced, the on-current of the TFT shows a constant high value without being affected by the fluctuation of the contact length, and the on-off characteristic of the thin film transistor and the image quality of the panel are remarkably improved, or the size is small. When the area of the contact layer is regulated by the optimization, the on-off characteristics and the image quality of the panel can be maintained well. The interface of the channel portion is composed of the silicon-insulator junction and the silicon-silicon junction, and the area of the silicon-silicon junction is reduced, that is, the carrier moving area is reduced. It is compensated by lowering it.
第１図は、本発明の一実施例および従来例の薄膜トラン
ジスタ（TFT）に示す構造断面図、第２図は本発明およ
び従来のマトリックス型液晶表示パネルのTFT配列の一
例を示す図、第３図はチャネル部とソース・ドレイン電
極とのコンタクト長を説明するためのTFT平面図、第４
図は実施例および従来例のTFTオン電流の特性を比較し
て示す図である。 １…絶縁性基板、２……基板保護膜、３……ゲート電
極，ゲートバスバー、 ４……ゲート絶縁層、５……チャネル部半導体膜（ｉ型
ａ−Si膜）、 ６……チャネル部保護絶縁膜、７……コンタクト層（微
結晶ｎ型Si膜） 8,8′……ソース電極，ドレイン電極、９……表示用絵
素電極、10……保護絶縁膜、 11……ソースバスバー。FIG. 1 is a structural cross-sectional view showing a thin film transistor (TFT) according to an embodiment of the present invention and a conventional example, FIG. 2 is a view showing an example of a TFT arrangement of a matrix type liquid crystal display panel according to the present invention, and FIG. The figure is a TFT plan view for explaining the contact length between the channel portion and the source / drain electrodes.
The figure compares the characteristics of the TFT on-currents of the example and the conventional example. 1 ... Insulating substrate, 2 ... Substrate protective film, 3 ... Gate electrode, gate busbar, 4 ... Gate insulating layer, 5 ... Channel semiconductor film (i-type a-Si film), 6 ... Channel part Protective insulating film, 7 ... Contact layer (microcrystalline n-type Si film) 8,8 '... Source electrode, drain electrode, 9 ... Display pixel electrode, 10 ... Protective insulating film, 11 ... Source bus bar .
───────────────────────────────────────────────────── フロントページの続き (72)発明者 庄司 元 大阪府大阪市阿倍野区長池町22番22号 シャープ株式会社内 (56)参考文献 特開 昭61−65477（ＪＰ，Ａ) 特開 昭59−49580（ＪＰ，Ａ) ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shoji Gen 22-22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation (56) References JP-A-61-65477 (JP, A) JP-A-59- 49580 (JP, A)
Claims (1)
いた薄膜トランジスタをアドレス素子としてマトリック
ス表示を行なうマトリックス型液晶表示パネルにおい
て、 上記薄膜トランジスタのチャネル部の中央表面に形成さ
れたチャネル部保護絶縁膜と、 上記チャネル部および上記チャネル部保護絶縁膜を覆
い、かつ上記チャネル部保護絶縁膜上で左右に分離され
て並設され、導電率が100S/cm以上の微結晶ｎ型シリコ
ン膜によって形成された一対のコンタクト層と、 上記一方のコンタクト層上に形成されたソース電極と、 上記他方のコンタクト層上に形成されたドレイン電極と
を備え、上記チャネル部の表面には、上記チャネル部保
護絶縁膜との間でシリコン−絶縁体接合が形成され、上
記一対のコンタクト層との間でシリコン−シリコン系接
合が形成されていることを特徴とするマトリックス型液
晶表示パネル。1. A matrix type liquid crystal display panel for performing matrix display using a thin film transistor using an amorphous silicon film as a channel part as an address element, and a channel part protective insulating film formed on a central surface of the channel part of the thin film transistor, channel section and covers the channel portion protective insulating film, and is separated into right and left on the channel section protection insulating film is arranged, the conductivity is formed by 10 0 S / cm or more microcrystalline n-type silicon film A pair of contact layers, a source electrode formed on the one contact layer, and a drain electrode formed on the other contact layer, and the channel part protective insulating film on the surface of the channel part. And a silicon-insulator junction is formed between the contact layer and the contact layer, and a silicon-silicon bond is formed between the contact layer and the contact layer. A matrix-type liquid crystal display panel, characterized in that a liquid crystal-based junction is formed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20086488A JP2675587B2 (en) | 1988-08-09 | 1988-08-09 | Matrix type liquid crystal display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20086488A JP2675587B2 (en) | 1988-08-09 | 1988-08-09 | Matrix type liquid crystal display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0247633A JPH0247633A (en) | 1990-02-16 |
| JP2675587B2 true JP2675587B2 (en) | 1997-11-12 |
Family
ID=16431495
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20086488A Expired - Lifetime JP2675587B2 (en) | 1988-08-09 | 1988-08-09 | Matrix type liquid crystal display panel |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2675587B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03289629A (en) * | 1990-04-06 | 1991-12-19 | Matsushita Electron Corp | Image display device and its manufacture |
| US5473168A (en) * | 1993-04-30 | 1995-12-05 | Sharp Kabushiki Kaisha | Thin film transistor |
| JPH08201851A (en) * | 1995-01-31 | 1996-08-09 | Sharp Corp | Active matrix substrate |
| JP3416723B2 (en) * | 1995-05-25 | 2003-06-16 | 独立行政法人産業技術総合研究所 | Amorphous silicon thin film transistor and method of manufacturing the same |
| JP3440291B2 (en) * | 1995-05-25 | 2003-08-25 | 独立行政法人産業技術総合研究所 | Microcrystalline silicon thin film transistor |
| US7968880B2 (en) * | 2008-03-01 | 2011-06-28 | Semiconductor Energy Laboratory Co., Ltd. | Thin film transistor and display device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0746728B2 (en) * | 1984-09-07 | 1995-05-17 | 松下電器産業株式会社 | Method for manufacturing semiconductor device |
-
1988
- 1988-08-09 JP JP20086488A patent/JP2675587B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0247633A (en) | 1990-02-16 |
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