JPH04360583A - Thin film transistor - Google Patents

Thin film transistor

Info

Publication number
JPH04360583A
JPH04360583A JP3163612A JP16361291A JPH04360583A JP H04360583 A JPH04360583 A JP H04360583A JP 3163612 A JP3163612 A JP 3163612A JP 16361291 A JP16361291 A JP 16361291A JP H04360583 A JPH04360583 A JP H04360583A
Authority
JP
Japan
Prior art keywords
layer
electrode
semiconductor layer
teeth
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3163612A
Other languages
Japanese (ja)
Inventor
Yasumitsu Ota
泰光 太田
Shusuke Mimura
秀典 三村
Koichi Kitamura
公一 北村
Masakazu Katsuno
正和 勝野
Toshirou Futaki
二木 登史郎
Noboru Otani
昇 大谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Nippon Steel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Steel Corp filed Critical Nippon Steel Corp
Priority to JP3163612A priority Critical patent/JPH04360583A/en
Publication of JPH04360583A publication Critical patent/JPH04360583A/en
Withdrawn legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Shift Register Type Memory (AREA)

Abstract

PURPOSE:To prevent an increase in an OFF current due to back light at the time of using a thin film transistor having electrodes of a comblike structure, as a pixel switch of a liquid crystal display without complicated structure. CONSTITUTION:In a thin film transistor having a gate electrode 2 formed on an insulating board 1, a gate insulating film 3, a semiconductor layer 4, and source, drain electrodes made of ohmic layer 5 and metal layer 6 of a comblike structure, the comb teeth of the source/drain electrode do not cross the electrode 2, and the teeth edges are disposed on the electrode 2. Even if an electric resistance of the semiconductor layer except the gate electrode is reduced due to back light, if the edges of the teeth of the source/drain electrodes are disposed on the gate electrode, a leakage current at the time of OFF is not increased.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、アクティブマトリクス
型液晶表示装置に用いられる薄膜トランジスタ(以下T
FTと略す。)の形状に関するものである。
[Industrial Application Field] The present invention relates to thin film transistors (hereinafter referred to as T) used in active matrix liquid crystal display devices.
Abbreviated as FT. ).

【0002】0002

【従来の技術】近年、ガラス等の絶縁基板上に薄膜トラ
ンジスタ(以下TFTと略す。)を形成し、これを用い
て各画素に印加する電圧を制御して液晶を駆動する、い
わゆるアクティブマトリクス型液晶ディスプレイ(以下
LCDと略す。)に関する研究開発が活発に行われてい
る。
[Prior Art] In recent years, so-called active matrix liquid crystals have been developed in which thin film transistors (hereinafter abbreviated as TFTs) are formed on insulating substrates such as glass, and are used to drive liquid crystals by controlling the voltage applied to each pixel. Research and development regarding displays (hereinafter abbreviated as LCD) are actively being conducted.

【0003】図2に最も一般的にアクティブマトリクス
型LCDに応用されている逆スタガード型TFTの断面
構造を示す。図2で、11はガラスなどの絶縁基板、1
2はCrやTa、あるいは表面を陽極酸化したTaやA
lなどで形成されたゲート電極層、13はゲート絶縁膜
層、14は非晶質シリコン等の半導体からなるチャネル
層、15はオーミックコンタクト層、16はソースまた
はドレイン電極、17は画素電極となる透明導電膜であ
る。この逆スタガード型TFTは、ゲート絶縁層13と
半導体からなるチャネル層14が連続堆積でき比較的良
質な界面が容易に得られ、また図2に示すように半導体
チャネル層14に対してゲート電極層12がバックライ
トの遮光層となるので、別述に遮光層を形成しなくても
良いという長所がある。このため、逆スタガード型TF
Tは最も一般的なTFT構造として知られている。しか
し、この逆スタガード型TFTには、LCDに応用した
場合、アライメントのずれに対する許容度が小さく、大
面積のLCDを歩留り良く作成することは困難であると
いう短所があった。また、アライメントの許容度を大き
くとるためには、ソース・ドレイン電極とゲート電極の
重なりを大きくするという方法もあるが、この場合TF
Tの寄生容量が大きくなってしまうため、やはり高精細
な大面積LCDを実現することは困難であった。
FIG. 2 shows a cross-sectional structure of an inverted staggered TFT that is most commonly applied to active matrix LCDs. In FIG. 2, 11 is an insulating substrate such as glass;
2 is Cr or Ta, or Ta or A with anodized surface
13 is a gate insulating film layer, 14 is a channel layer made of a semiconductor such as amorphous silicon, 15 is an ohmic contact layer, 16 is a source or drain electrode, and 17 is a pixel electrode. It is a transparent conductive film. In this inverted staggered TFT, the gate insulating layer 13 and the channel layer 14 made of a semiconductor can be successively deposited, and a relatively high-quality interface can be easily obtained, and as shown in FIG. Since the numeral 12 serves as a light-shielding layer for the backlight, there is an advantage that there is no need to form a light-shielding layer separately. For this reason, an inverted staggered TF
T is known as the most common TFT structure. However, when applied to an LCD, this inverted staggered TFT has a disadvantage in that tolerance for misalignment is small and it is difficult to produce a large-area LCD with a high yield. In addition, in order to increase the alignment tolerance, there is a method of increasing the overlap between the source/drain electrode and the gate electrode, but in this case, the TF
Since the parasitic capacitance of T becomes large, it is still difficult to realize a high-definition, large-area LCD.

【0004】一方、寄生容量を増大させずにアライメン
トのずれに対する冗長性をもたせ、大面積基板上に均一
に高特性なTFTを作るための技術として櫛形電極TF
T(特開平2−27567号公報)がある。図3(a)
にこの櫛形電極TFTの上面図を、また図3(b)にそ
の断面構造図を示す。図3で21はガラスなどの絶縁基
板、22はCrやTa、あるいは表面を陽極酸化したT
aやAlなどで形成されたゲート電極層、23はゲート
絶縁膜、24は半導体からなるチャネル層、25はオー
ミックコンタクト層、26はソースまたはドレイン電極
である。
On the other hand, a comb-shaped electrode TF is used as a technology to provide redundancy against misalignment without increasing parasitic capacitance and to fabricate TFTs with uniformly high characteristics on a large-area substrate.
There is T (Japanese Unexamined Patent Publication No. 2-27567). Figure 3(a)
shows a top view of this comb-shaped electrode TFT, and FIG. 3(b) shows its cross-sectional structure. In Fig. 3, 21 is an insulating substrate such as glass, and 22 is Cr, Ta, or T whose surface is anodized.
23 is a gate insulating film, 24 is a channel layer made of semiconductor, 25 is an ohmic contact layer, and 26 is a source or drain electrode.

【0005】[0005]

【発明が解決しようとする課題】しかし、この櫛形電極
TFTでは、ソース・ドレイン電極層26がゲート電極
22を完全に横断しているため、ゲート電極22の同じ
側のゲート電極22の無い部分で、基板21の直接上に
積層された半導体層上にソース電極とドレイン電極が接
触しているため、LCDに応用して、ゲート電極層側か
らバックライトが入射した場合に、ソース電極とドレイ
ン電極の間の半導体層に光が当たりオフ時の電流量が増
大してしまうという欠点があった。また、これを解決す
るためには別途遮光層を設ける等の措置があるが、そう
すると結果的にプロセスが複雑になり歩留りが低下する
という問題点があった。
[Problems to be Solved by the Invention] However, in this comb-shaped electrode TFT, since the source/drain electrode layer 26 completely crosses the gate electrode 22, the portion of the gate electrode 22 on the same side where the gate electrode 22 is not , since the source electrode and the drain electrode are in contact with the semiconductor layer stacked directly on the substrate 21, when applied to an LCD and backlight is incident from the gate electrode layer side, the source electrode and the drain electrode The drawback is that light hits the semiconductor layer between them, increasing the amount of current when they are off. Further, in order to solve this problem, there are measures such as providing a light shielding layer separately, but this results in a problem that the process becomes complicated and the yield decreases.

【0006】本発明は、アライメントに対する冗長性が
高く、大面積に均一な特性のTFTが作成できるという
櫛形電極TFTの長所を活かしたまま、LCDに応用し
た場合でも特にゲート電極層側から入射するバックライ
トに対する遮光層を設ける必要のないTFTを提供する
ものである。
[0006] The present invention takes advantage of the advantages of the comb-shaped electrode TFT, which has high alignment redundancy and can create a TFT with uniform characteristics over a large area, and even when applied to an LCD, it is possible to avoid light incident from the gate electrode layer side. The present invention provides a TFT that does not require a light shielding layer for a backlight.

【0007】[0007]

【課題を解決するための手段】本発明は、絶縁基板上に
、ゲート電極層、ゲート絶縁膜、半導体層、一対のオー
ミック層と金属電極層からなるソース・ドレイン電極を
順に積層してなる逆スタガード型積層構造薄膜トランジ
スタにおいて、前記一対のソース・ドレイン電極のそれ
ぞれが複数本の歯を有する櫛形構造であり、この歯が前
記半導体上で互いに非接触の状態で組み合わされ、かつ
その歯の先端がゲート電極上の半導体層上にあることを
特徴とするものである。また、本発明は絶縁基板上に金
属電極層とオーミック層からなる一対のソース・ドレイ
ン電極、半導体層、ゲート絶縁膜、ゲート電極層を順に
積層してなるスタガード型積層構造薄膜トランジスタに
おいて、前記一対のソース・ドレイン電極層のそれぞれ
が複数本の歯を有する櫛形構造であり、この歯が前記半
導体上で互いに非接触の状態で組み合わされ、かつその
歯の先端がゲート電極下の半導体層の下にあることを特
徴とするものである。
[Means for Solving the Problems] The present invention provides an inverse structure in which source/drain electrodes consisting of a gate electrode layer, a gate insulating film, a semiconductor layer, a pair of ohmic layers, and a metal electrode layer are sequentially laminated on an insulating substrate. In the staggered stacked structure thin film transistor, each of the pair of source/drain electrodes has a comb-shaped structure having a plurality of teeth, the teeth are combined on the semiconductor in a non-contact state, and the tips of the teeth are It is characterized by being located on the semiconductor layer above the gate electrode. The present invention also provides a staggered laminated structure thin film transistor in which a pair of source/drain electrodes, a semiconductor layer, a gate insulating film, and a gate electrode layer, each consisting of a metal electrode layer and an ohmic layer, are laminated in this order on an insulating substrate. Each of the source/drain electrode layers has a comb-shaped structure having a plurality of teeth, and the teeth are combined on the semiconductor in a non-contact state, and the tips of the teeth are placed under the semiconductor layer below the gate electrode. It is characterized by certain things.

【0008】本発明の半導体層としては、透明絶縁基板
上に薄膜堆積技術によって作成することのできる半導体
薄膜として、光感度の大きい非晶質シリコンを用いた場
合が特に有効であるが、光感度の小さい多結晶シリコン
を用いた場合にも当然有効である。
As the semiconductor layer of the present invention, it is particularly effective to use amorphous silicon, which has high photosensitivity, as a semiconductor thin film that can be formed on a transparent insulating substrate by thin film deposition technology. Naturally, this is also effective when using polycrystalline silicon with a small .

【0009】本発明はまた、半導体層が、電気伝導を制
御するために硼素、燐のいずれかの不純物が混入された
非晶質シリコン層である薄膜トランジスタの場合やバン
ドギャップを制御するために炭素、窒素、酸素、ゲルマ
ニウムからなる群から選ばれたいずれかの不純物が混入
された非晶質シリコン層である薄膜トランジスタの場合
にも当然有効である。
The present invention is also applicable to thin film transistors in which the semiconductor layer is an amorphous silicon layer doped with impurities such as boron or phosphorus to control electrical conduction, or in which carbon is added to control the band gap. Of course, this method is also effective in the case of a thin film transistor which is an amorphous silicon layer mixed with any impurity selected from the group consisting of nitrogen, oxygen, and germanium.

【0010】0010

【作用】本発明の薄膜トランジスタにおいては、オーミ
ック電極層および金属層で構成されるソース・ドレイン
電極のそれぞれが複数本の歯を有する櫛形構造であり、
この歯が前記半導体層上で互いに非接触の状態で組み合
わされ、かつその歯の先端がゲート電極上の半導体層上
にある。本発明の薄膜トランジスタでは、バックライト
はゲート電極層側から入射するように配置される。ソー
ス・ドレイン櫛形電極の櫛歯の先端がゲート電極上の半
導体層上にある構造にすると、ゲート電極層側から入射
したバックライトにより、光の当たった半導体層部分の
電気抵抗が低下しても、通常の櫛形電極薄膜トランジス
タのようにソース・ドレイン電極間に半導体層の光電導
による漏れ電流が流れず、トランジスタのオフ特性が劣
化しない。従ってゲート電極層側に特別に遮光層を設け
る必要がなくなり、櫛形電極薄膜トランジスタの長所を
活かしたままプロセスを簡略化することができる。
[Operation] In the thin film transistor of the present invention, each of the source and drain electrodes composed of an ohmic electrode layer and a metal layer has a comb-shaped structure having a plurality of teeth,
The teeth are assembled on the semiconductor layer in a non-contact state, and the tips of the teeth are on the semiconductor layer above the gate electrode. In the thin film transistor of the present invention, the backlight is arranged so that it enters from the gate electrode layer side. If the tips of the comb teeth of the source/drain comb-shaped electrodes are placed on the semiconductor layer above the gate electrode, even if the backlight that enters from the gate electrode layer side reduces the electrical resistance of the part of the semiconductor layer that is illuminated by the light, Unlike ordinary comb-shaped electrode thin film transistors, leakage current does not flow between the source and drain electrodes due to photoconduction in the semiconductor layer, and the off-state characteristics of the transistor do not deteriorate. Therefore, there is no need to provide a special light-shielding layer on the gate electrode layer side, and the process can be simplified while taking advantage of the advantages of the comb-shaped electrode thin film transistor.

【0011】[0011]

【実施例】以下、本発明の詳細を図示の実施例によって
説明する。図1に、逆スタガード型櫛形電極TFTに本
発明を適用した例を示す。図1(a)は本発明のTFT
の構造の上面図であり、図1(b)はその断面図である
。図1で1はコーニング7059ガラス基板、2は電子
ビーム蒸着で成膜したCr膜をウェットエッチングして
形成したゲート電極層、3はプラズマCVD法で作成し
た窒化シリコン膜からなるゲート絶縁膜、4は同じくプ
ラズマCVDで作成したa−Si:Hからなる半導体チ
ャネル層、5は同じくプラズマCVDで作成したn+型
a−Si:Hからなるオーミックコンタクト層であり、
6は2と同様に電子ビーム蒸着で成膜しウェットエッチ
ングで形成したソースおよびドレイン電極層である。図
1の3から5のプラズマCVDによる成膜は界面の劣化
を防ぐために多室プラズマCVD装置により真空をやぶ
らずに連続に行った。本実施例の櫛歯の幅と櫛歯の間隔
は共に10μmで、櫛歯の数は片側各10本の合計20
本とした。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to illustrated embodiments. FIG. 1 shows an example in which the present invention is applied to an inverted staggered comb-shaped electrode TFT. Figure 1(a) shows the TFT of the present invention.
FIG. 1(b) is a top view of the structure of FIG. In FIG. 1, 1 is a Corning 7059 glass substrate, 2 is a gate electrode layer formed by wet etching a Cr film formed by electron beam evaporation, 3 is a gate insulating film made of a silicon nitride film made by plasma CVD method, 4 5 is a semiconductor channel layer made of a-Si:H also created by plasma CVD, and 5 is an ohmic contact layer made of n + type a-Si:H also created by plasma CVD.
Reference numeral 6 denotes source and drain electrode layers formed by electron beam evaporation and wet etching in the same manner as 2. Film formation by plasma CVD from 3 to 5 in FIG. 1 was performed continuously using a multi-chamber plasma CVD apparatus without breaking the vacuum in order to prevent deterioration of the interface. In this example, the width of the comb teeth and the interval between the comb teeth are both 10 μm, and the number of comb teeth is 10 on each side, totaling 20.
I made it into a book.

【0012】図4(a),(b)にそれぞれ本発明の櫛
形電極TFTと「特開平2−27567号公報」記載の
従来型櫛形電極TFTとにバックライトとしてゲート電
極層側から750[lx]の光を入射したときのI−V
特性を示す。図4(b)の普通の櫛形電極TFTでは、
バックライトによりオフ電流が増大しオン−オフ比が1
〜2桁程度しかとれずLCD用のTFTとして不十分な
特性となってしまうが、本発明の櫛形電極TFTでは、
バックライトによる影響はほとんど無く、オン対オフ比
も5桁以上と、LCD用のTFTとして充分な特性を有
していることがわかる。
FIGS. 4(a) and 4(b) show a comb-shaped electrode TFT according to the present invention and a conventional comb-shaped electrode TFT described in ``JP-A-2-27567'' as a backlight from the gate electrode layer side. ] I-V when the light is incident
Show characteristics. In the ordinary comb-shaped electrode TFT shown in FIG. 4(b),
The backlight increases the off-state current and reduces the on-off ratio to 1.
However, in the comb-shaped electrode TFT of the present invention, the characteristics are insufficient as a TFT for LCD.
It can be seen that there is almost no influence from the backlight, and the on-to-off ratio is more than 5 digits, indicating that it has sufficient characteristics as a TFT for LCD.

【0013】[0013]

【発明の効果】本発明は、TFTにおけるソース・ドレ
イン電極を櫛形構造にした「特開平2−275672号
公報」記載の櫛形電極TFTの長所を活かしたまま、そ
の櫛歯をゲート電極を横断させずにその先端がゲート電
極上にとどまるようにして、櫛形TFTをLCDに応用
した場合に問題となるバックライトによるオフ特性の劣
化を、特別な遮光層を設けることなしに防止したもので
ある。これによりアクティブマトリクス型液晶表示装置
の作成プロセスを簡略化することができ、歩留りをより
向上させることが可能となる。
Effects of the Invention The present invention utilizes the advantages of the comb-shaped electrode TFT described in ``Japanese Unexamined Patent Publication No. 2-275672'' in which the source and drain electrodes in the TFT have a comb-shaped structure, while making the comb teeth cross the gate electrode. This prevents deterioration of off-characteristics due to backlight, which is a problem when comb-shaped TFTs are applied to LCDs, without providing a special light-shielding layer. This makes it possible to simplify the manufacturing process of an active matrix type liquid crystal display device and further improve the yield.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の新型櫛形電極TFTの構造で、(a)
はその上面図、(b)はその断面図である。
FIG. 1 shows the structure of the new comb-shaped electrode TFT of the present invention, (a)
is its top view, and (b) is its cross-sectional view.

【図2】LCDに応用した場合の通常の逆スタガード型
TFTの断面図である。
FIG. 2 is a cross-sectional view of a normal inverted staggered TFT when applied to an LCD.

【図3】通常の櫛形電極TFT(特開平2−27567
2号公報)の構造で、(a)はその上面図、(b)はそ
の断面図である。
[Figure 3] Ordinary comb-shaped electrode TFT (Japanese Patent Application Laid-Open No. 2-27567
(a) is a top view thereof, and (b) is a sectional view thereof.

【図4】(a)は750[lx]のバックライトを当て
た場合の本発明櫛形電極TFTのI−V特性であり、(
b)は750[lx]のバックライトを当てた場合の普
通の櫛形電極TFTのI−V特性である。
FIG. 4(a) shows the IV characteristics of the comb-shaped electrode TFT of the present invention when illuminated with a backlight of 750 [lx];
b) is the IV characteristic of a normal comb-shaped electrode TFT when illuminated with a backlight of 750 [lx].

【符号の説明】[Explanation of symbols]

1    ガラス基板 2    ゲート電極層 3    ゲート絶縁膜 4    チャネル層 5    オーミックコンタクト層 1 Glass substrate 2 Gate electrode layer 3 Gate insulating film 4 Channel layer 5 Ohmic contact layer

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】  非晶質シリコンからなる半導体層、該
半導体層表面とオーミック層をはさんで接続される一対
のソース・ドレイン電極層、該半導体層表面に接して形
成されるゲート絶縁層、および該ゲート絶縁層の半導体
層と接する面と反対側の面に接して形成され該ゲート絶
縁層により半導体層との絶縁性を保たれたゲート電極層
を、絶縁基板上に積層した構造を有する絶縁ゲート型電
界効果薄膜トランジスタにおいて、前記一対のソース・
ドレイン電極層のそれぞれが複数本の歯を有する櫛形構
造であり、この前記一対のソース・ドレイン電極層の櫛
歯が前記半導体上で互いに非接触の状態で組み合わされ
、かつその櫛歯がゲート電極と直交するように配置し、
かつその歯の先端がゲート電極層上の半導体層上にある
ことを特徴とする薄膜トランジスタ。
1. A semiconductor layer made of amorphous silicon, a pair of source/drain electrode layers connected to the surface of the semiconductor layer across an ohmic layer, a gate insulating layer formed in contact with the surface of the semiconductor layer, and a gate electrode layer formed in contact with the surface of the gate insulating layer opposite to the surface in contact with the semiconductor layer and maintained insulated from the semiconductor layer by the gate insulating layer, which is stacked on an insulating substrate. In the insulated gate field effect thin film transistor, the pair of sources and
Each of the drain electrode layers has a comb-shaped structure having a plurality of teeth, and the comb teeth of the pair of source/drain electrode layers are combined on the semiconductor in a non-contact state, and the comb teeth are connected to the gate electrode. placed perpendicular to
A thin film transistor characterized in that the tips of the teeth are located on a semiconductor layer above a gate electrode layer.
JP3163612A 1991-06-07 1991-06-07 Thin film transistor Withdrawn JPH04360583A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3163612A JPH04360583A (en) 1991-06-07 1991-06-07 Thin film transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3163612A JPH04360583A (en) 1991-06-07 1991-06-07 Thin film transistor

Publications (1)

Publication Number Publication Date
JPH04360583A true JPH04360583A (en) 1992-12-14

Family

ID=15777237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3163612A Withdrawn JPH04360583A (en) 1991-06-07 1991-06-07 Thin film transistor

Country Status (1)

Country Link
JP (1) JPH04360583A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283695A (en) * 1992-04-03 1993-10-29 Nec Corp Thin film transistor
JPH06273803A (en) * 1993-01-20 1994-09-30 Hitachi Ltd Active matrix liquid crystal display device
JP2002318390A (en) * 1993-01-20 2002-10-31 Hitachi Ltd Active matrix liquid crystal display device
KR100439944B1 (en) * 1998-12-10 2004-11-03 엘지.필립스 엘시디 주식회사 Thin Film Transistor Fluorescent Sensor, Sensor Thin Film Transistor and Manufacturing Method
US6858867B2 (en) 2002-02-22 2005-02-22 Nec Corporation Channel-etch thin film transistor
JP2005223254A (en) * 2004-02-09 2005-08-18 Sharp Corp Thin film transistor
JP2006287245A (en) * 2006-05-11 2006-10-19 Semiconductor Energy Lab Co Ltd Display
JP2008261954A (en) * 2007-04-10 2008-10-30 Matsushita Electric Ind Co Ltd Organic el device and el display
JP2011233882A (en) * 2010-04-07 2011-11-17 Semiconductor Energy Lab Co Ltd Transistor
US8450743B2 (en) 1994-08-19 2013-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having parallel thin film transistors
JP2019216236A (en) * 2019-05-15 2019-12-19 堺ディスプレイプロダクト株式会社 Organic el display device and manufacturing method of the organic el display device
US11335752B2 (en) 2018-03-28 2022-05-17 Sakai Display Products Corporation Organic-EL display device with alternately lined source drain electrodes and manufacturing method thereof

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05283695A (en) * 1992-04-03 1993-10-29 Nec Corp Thin film transistor
JPH06273803A (en) * 1993-01-20 1994-09-30 Hitachi Ltd Active matrix liquid crystal display device
JP2002318390A (en) * 1993-01-20 2002-10-31 Hitachi Ltd Active matrix liquid crystal display device
US8450743B2 (en) 1994-08-19 2013-05-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having parallel thin film transistors
KR100439944B1 (en) * 1998-12-10 2004-11-03 엘지.필립스 엘시디 주식회사 Thin Film Transistor Fluorescent Sensor, Sensor Thin Film Transistor and Manufacturing Method
US6858867B2 (en) 2002-02-22 2005-02-22 Nec Corporation Channel-etch thin film transistor
US7038241B2 (en) 2002-02-22 2006-05-02 Nec Lcd Technologies, Ltd Channel-etch thin film transistor
JP2005223254A (en) * 2004-02-09 2005-08-18 Sharp Corp Thin film transistor
JP2006287245A (en) * 2006-05-11 2006-10-19 Semiconductor Energy Lab Co Ltd Display
JP4481271B2 (en) * 2006-05-11 2010-06-16 株式会社半導体エネルギー研究所 Display device
JP2008261954A (en) * 2007-04-10 2008-10-30 Matsushita Electric Ind Co Ltd Organic el device and el display
JP2011233882A (en) * 2010-04-07 2011-11-17 Semiconductor Energy Lab Co Ltd Transistor
US9401407B2 (en) 2010-04-07 2016-07-26 Semiconductor Energy Laboratory Co., Ltd. Transistor
US11335752B2 (en) 2018-03-28 2022-05-17 Sakai Display Products Corporation Organic-EL display device with alternately lined source drain electrodes and manufacturing method thereof
US11812643B2 (en) 2018-03-28 2023-11-07 Sakai Display Products Corporation Organic-EL display apparatus with zig-zag source drain electrodes and manufacturing method thereof
JP2019216236A (en) * 2019-05-15 2019-12-19 堺ディスプレイプロダクト株式会社 Organic el display device and manufacturing method of the organic el display device

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