JP2006287245A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor having a high breakdown voltage and capable of handling a high current. <P>SOLUTION: A common active layer is shown at 804 and a channel forming region is formed in the active layer. A common gate electrode and its interconnect line are shown at 801. A common source electrode and its interconnect line are shown at 805. A common drain electrode and its interconnect line are shown at 806. A contact part of source/drain electrodes and source/drain regions is shown at 802. When a plurality of thin film transistors are connected in parallel, a thin film transistor having a high breakdown voltage and capable of handling a high current can be attained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  In recent years, a technique for forming a transistor (referred to as a thin film transistor) using a thin film semiconductor over a glass or quartz substrate has been studied. In particular, a technique using amorphous silicon (amorphous silicon) as a thin film semiconductor has been put into practical use and is used in an active matrix liquid crystal display device and the like.

  However, a thin film transistor using amorphous silicon has a problem that its characteristics are low. For example, when a higher function is required as a display function of an active matrix liquid crystal display device, the characteristics of a thin film transistor using an amorphous silicon film are too low.

  A technique for forming a thin film transistor using a crystalline silicon film obtained by crystallizing an amorphous silicon film is also known. This technique transforms an amorphous silicon film into a crystalline silicon film by performing heat treatment or laser light irradiation after the formation of the amorphous silicon film. A crystalline silicon film obtained by crystallizing an amorphous silicon film generally has a polycrystalline structure or a microcrystalline structure.

When a thin film transistor is formed using a crystalline silicon film, much higher characteristics can be obtained than when an amorphous silicon film is used. For example, in terms of mobility, which is one index for evaluating characteristics of a thin film transistor, a thin film transistor using an amorphous silicon film has a mobility of 1 cm ² / Vs or less, but a thin film transistor using a crystalline silicon film Then, it can be set to about 100 cm ² / Vs.

  However, the crystalline silicon film obtained by crystallizing the amorphous silicon film has a polycrystalline structure, and has a number of problems due to crystal grain boundaries. For example, there is a problem that the breakdown voltage of the thin film transistor is greatly limited because there are carriers that move via the crystal grain boundaries. In addition, there is a problem that characteristic changes and deterioration are likely to occur when performing high-speed operation. There is also a problem that leakage current (leakage current) is increased when the thin film transistor is OFF because there are carriers that move through the crystal grain boundary.

  In addition, when an active matrix liquid crystal display device is to be configured in a more integrated form, it is desired that not only the pixel region but also a peripheral circuit be formed on a single glass substrate. In such a case, in order to drive hundreds of thousands of pixel transistors arranged in a matrix, the thin film transistors arranged in the peripheral circuit are required to handle a large current.

  In order to obtain a thin film transistor capable of handling a large current, it is necessary to adopt a structure with a large channel width. However, a thin film transistor using a polycrystalline silicon thin film or a microcrystalline silicon thin film has a problem that even if the channel width is widened, it cannot be put into practical use due to the problem of breakdown voltage. There is also a problem that the fluctuation of the threshold value is large and is not practical.

An object of the invention disclosed in this specification is to provide a thin film transistor which is not affected by a grain boundary.
Another object of the invention disclosed in this specification is to provide a thin film transistor which has a high withstand voltage and can handle a large current.
Another object of the invention disclosed in this specification is to provide a thin film transistor which has no deterioration or fluctuation in characteristics.

One of the inventions disclosed in this specification is:
A semiconductor device using a thin film silicon semiconductor formed on a substrate having an insulating surface,
The thin-film silicon semiconductor has a region that can be substantially regarded as a single crystal, and the region constitutes at least a part of an active layer,
In the region, carbon and nitrogen atoms have a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and oxygen atoms have a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ^{−. The} hydrogen atom neutralizing the dangling bonds of silicon at a concentration of ³ is contained at a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ .

  In the above structure, a region that can be regarded as substantially a single crystal refers to a region of a thin film silicon semiconductor having a crystal structure that is recognized as being equivalent to the crystallinity of a single crystal silicon wafer. Specifically, compared with the Raman spectrum of single crystal silicon, the intensity ratio of the Raman spectrum is 0.8 or more, the ratio of the half-value width (relative value) of the Raman spectrum is 2 or less, and at the same time A region where no crystal grain boundary substantially exists is defined as a region which can be regarded as a single crystal.

  The region which can be regarded as substantially single crystal as described above can be obtained by heating or laser light irradiation using an amorphous silicon film as a starting film. In particular, by introducing a metal element that promotes the crystallinity of silicon, a region that can be regarded as a single crystal over a large area can be obtained relatively easily.

  As a metal element that promotes crystallization of silicon, one or more elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu, Zn, Ag, and Au are used. Can do. These elements have an intrusion type property with respect to silicon, and are diffused into the silicon film by heat treatment or laser light irradiation. Among these elements, Ni (nickel) is an element that can obtain a particularly remarkable effect.

It is important that the concentration of the metal element is contained in the final silicon film after crystallization at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁹ cm ⁻³ . When the concentration of the metal element is 1 × 10 ¹⁶ cm ⁻³ or less, the effect of promoting crystallization cannot be obtained, and when the concentration is 5 × 10 ¹⁹ cm ⁻³ or more, the properties as a semiconductor are obtained. Will be damaged.

  In order to form the above-mentioned region that can be regarded as a single crystal in the silicon thin film, there is a method as described below. First, an amorphous silicon film is formed on a glass substrate or a quartz substrate, and then a film containing nickel is formed on the surface of the amorphous silicon film. The nickel-containing film may be formed by forming a very thin nickel thin film by sputtering or the like, or by applying a nickel-containing solution on the surface of the amorphous silicon film, the nickel element is converted into amorphous silicon. A method of placing the film in contact with the surface of the film may be employed.

  When nickel element is introduced into the amorphous silicon film, the amorphous silicon film is crystallized by heat treatment. This heat treatment can be performed at a temperature of 600 ° C. or lower by the action of nickel element. When a glass substrate is used as the substrate, it is preferable that the temperature of the heat treatment be as low as possible. However, considering the efficiency of the crystallization step, the temperature is 500 ° C. or higher, preferably 550 ° C. or higher. It is useful. When a quartz substrate is used as the substrate, this heat treatment can be performed at a temperature of 800 ° C. or higher, and a crystalline silicon film can be obtained in a single time. The crystalline silicon film obtained in this step has a polycrystalline or microcrystalline state, and crystal grain boundaries exist in the film.

  Therefore, the crystallinity is locally promoted by irradiating the sample with laser light at a temperature of 450 ° C. or higher. By this step, a region that can be regarded as a single crystal can be formed. It is important to heat the sample or the irradiated surface at a temperature of 450 ° C. or higher when performing this laser light irradiation. This heating temperature is preferably 450 ° C. to 750 ° C., particularly 450 ° C. to 600 ° C. when a glass substrate is used as the substrate.

  As another method for forming a region that can be regarded as a single crystal, an amorphous silicon film is formed and a metal element that promotes crystallization is introduced. And a method for forming a region that can be regarded as a region. Also in this case, it is important to heat the sample at a temperature of 450 ° C. to 750 ° C., particularly when a glass substrate is used as the substrate at the time of laser light irradiation.

  The significance of heating the sample during the laser light irradiation will be described below. FIG. 4 shows that an underlying silicon oxide film is formed on a glass substrate, an amorphous silicon film is formed thereon, and a nickel element is further introduced into the surface of the amorphous silicon film. The Raman spectrum intensity when irradiated with laser light is shown. Each plot point indicates the heating temperature of the sample when irradiated with laser light.

The Raman intensity in FIG. 4 is a relative value indicated by the ratio (I / I ₀ ) between the Raman spectrum intensity I ₀ of the single crystal silicon wafer and the Raman spectrum intensity I with respect to the sample. The intensity of the Raman spectrum is defined by the maximum value of the intensity of the Raman spectrum as shown in FIG. Since there is generally no crystal structure exceeding the single crystal silicon wafer, the maximum value of the Raman intensity indicated by the vertical axis in FIG. It can be understood that the closer the Raman intensity value is to 1, the closer the structure is to a single crystal.

FIG. 5 shows a plot of the relationship between the half-value width of the Raman spectrum and the irradiation energy density of the laser beam for each difference in the heating temperature of the sample. The half width of the vertical axis shown in FIG. 5 indicates the spectral width W _{0 at} the position where the intensity of the Raman spectrum of the single crystal silicon wafer is half and the width of the spectrum at the position where the intensity of the Raman spectrum of the actually obtained sample is half. This is a parameter indicated by the ratio to W (W / W ₀ ). These W and W ₀ are defined as spectrum widths at places where the Raman spectrum intensity is ½ as shown in FIG. In general, the narrower and sharper the Raman spectrum, the better the crystallinity. Therefore, generally, the width of the Raman spectrum of single crystal silicon is the narrowest and sharpest. The sample used is the same as that obtained from the data shown in FIG.

  Therefore, the full width at half maximum shown in FIG. 5 is generally a value of 1 or more. It can be understood that the closer the value is to 1, the closer the structure is to a single crystal. As is apparent from FIG. 5, crystallinity close to that of a single crystal can be obtained by increasing the heating temperature of the sample at the time of laser light irradiation. It is understood that the effect of heating the sample is saturated at about 500 ° C. From FIG. 5, it is concluded that heating at 400 ° C. is not reliable in order to obtain crystallinity close to a single crystal stably, and it is preferable to set the temperature to 450 ° C. or more with a margin.

  According to the knowledge of the present inventors, the Raman intensity shown in FIG. 4 is 0.8 or more, the half width of the Raman spectrum shown in FIG. 5 is 2.0 or less, and the grain boundary is substantially within the region. When it does not exist, the region can be viewed as a region that can be regarded as a single crystal.

The region which can be regarded as a single crystal starts from a silicon film formed by plasma CVD or low pressure thermal CVD, and carbon and nitrogen are contained in the film at 1 × 10 ^{16 to} 5 × 10 ¹⁸ cm. ⁻³ and oxygen are contained at a concentration of 1 × 10 ^{17 to} 5 × 10 ¹⁹ cm ⁻³ . In principle, since lattice defects exist, hydrogen is contained at a concentration of 1 × 10 ^{17 to} 5 × 10 ²⁰ cm ⁻³ in order to neutralize dangling bonds of silicon. That is, the region that can be regarded as a single crystal has a point defect but does not have a line defect or a plane defect. The concentration of these contained elements is defined as the lowest value measured by SIMS (secondary ion analysis).

  The region which can be regarded as the single crystal is different from a general single crystal wafer. This is because the thin film semiconductor is formed by CVD and has a thickness of about 200 to 2000 mm.

Other aspects of the invention are:
A semiconductor device using a thin film silicon semiconductor formed on a substrate having an insulating surface,
The thin film silicon semiconductor has a region that can be substantially regarded as a single crystal,
The region comprises at least part of the active layer;
In the region, carbon and nitrogen atoms have a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and oxygen atoms have a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ^−. It is contained at a concentration of ³ .

Other aspects of the invention are:
A semiconductor device using a thin film silicon semiconductor formed on a substrate having an insulating surface,
The thin-film silicon semiconductor has a region that can be substantially regarded as a single crystal, and the region constitutes at least a part of an active layer,
The semiconductor contains hydrogen atoms neutralizing dangling bonds of silicon in a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3. apparatus.

Other aspects of the invention are:
A semiconductor device using a thin film silicon semiconductor formed on a substrate having an insulating surface,
The thin-film silicon semiconductor has a region that can be substantially regarded as a single crystal, and the region constitutes at least a part of an active layer,
In the region, carbon and nitrogen atoms have a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and oxygen atoms have a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ¹⁹ cm ^{−. 3} and hydrogen atoms neutralizing dangling bonds of silicon are contained at a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ⁻³ ,
The thin film silicon semiconductor has an average thickness of 200 to 2000 mm.

Other aspects of the invention are:
A semiconductor device using a thin film silicon semiconductor formed on a substrate having an insulating surface,
A region having a crystal structure that can be regarded as a substantially single crystal of the thin film silicon semiconductor constitutes at least a channel formation region,
In the channel formation region, carbon and nitrogen atoms have a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and oxygen atoms have a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ^19. It is characterized by containing hydrogen atoms at a concentration of cm ⁻³ and neutralizing dangling bonds of silicon at a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3. To do.

Other aspects of the invention are:
Irradiating a silicon thin film formed on a substrate having an insulating surface with a laser beam to form a region that can be regarded as a single crystal;
The laser beam irradiation is performed in a state where the sample is heated to a temperature of 450 ° C. to 750 ° C.

Other aspects of the invention are:
A plurality of thin film transistors connected in parallel;
Each of the plurality of thin film transistors has a structure in which at least a crystal grain boundary does not exist in a channel formation region,
It is characterized by.

Other aspects of the invention are:
A plurality of thin film transistors connected in parallel;
Each of the plurality of thin film transistors has a structure in which at least a crystal grain boundary does not exist in a channel formation region,
In the channel formation region, carbon and nitrogen atoms have a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and oxygen atoms have a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ^19. It is characterized by containing hydrogen atoms at a concentration of cm ⁻³ and neutralizing dangling bonds of silicon at a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3. To do.

Other aspects of the invention are:
A plurality of thin film transistors connected in parallel;
Each of the plurality of thin film transistors has a structure in which at least a crystal grain boundary does not exist in a channel formation region,
The channel forming region has a thickness of 200 to 2000 mm,
In the channel formation region, carbon and nitrogen atoms have a concentration of 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁸ cm ⁻³ and oxygen atoms have a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ^19. It is characterized by containing hydrogen atoms at a concentration of cm ⁻³ and neutralizing dangling bonds of silicon at a concentration of 1 × 10 ¹⁷ cm ^{−3 to} 5 × 10 ²⁰ cm ^−3. To do.

Other aspects of the invention are:
A plurality of thin film transistors connected in parallel;
Each of the plurality of thin film transistors is formed of a thin film silicon semiconductor in which at least a channel formation region can be substantially regarded as a single crystal.

  By forming a thin film transistor by using a region that can be regarded as a single crystal of a thin film silicon semiconductor as an active layer, a thin film transistor with high withstand voltage and having no characteristic variation or deterioration can be obtained.

  In addition, by adopting a configuration in which a plurality of thin film transistors each configured by using a region that can be regarded as a single crystal of a thin film silicon semiconductor as an active layer are connected in parallel, a configuration capable of flowing a large current can be obtained. Such a configuration can achieve the same effect as substantially increasing the channel width. When this structure is employed, characteristics equivalent to those of a transistor formed using a semiconductor that can be regarded as a single crystal can be obtained, and high mobility, large breakdown voltage, and stable characteristics can be obtained.

  By utilizing the invention disclosed in this specification, a thin film transistor which is not affected by a grain boundary can be obtained. In addition, a thin film transistor that has a high breakdown voltage, does not vary in characteristics, and can handle a large current can be obtained. In addition, since the operation of the thin film transistor can be made free from the influence of crystal grain boundaries, the characteristics of a small OFF current can be obtained.

  In this example, a glass substrate (Corning 7059) is used as a substrate, and a thin film transistor is manufactured at a temperature lower than the strain point temperature of the glass substrate. The strain point of Corning 7059 glass substrate is 593 ° C., and heat treatment at a temperature higher than this temperature is not preferable because it causes shrinkage or deformation of the glass substrate. In particular, when a glass substrate having a large area is used for use in a large liquid crystal display device, the influence of shrinkage or deformation of the glass substrate becomes significant.

  Therefore, the thin film transistor described in this embodiment is characterized in that the influence of heat on the substrate is greatly reduced by setting the maximum temperature in the heat treatment step to 600 ° C. or lower, preferably 550 ° C. or lower.

  FIG. 1 shows a manufacturing process of the thin film transistor shown in this embodiment. First, a silicon oxide film 102 is formed as a base film on a quartz substrate 101 to a thickness of 3000 mm by sputtering. Next, an amorphous silicon film 103 is formed to a thickness of 500 mm by plasma CVD or low pressure thermal CVD. (Fig. 1 (A))

  After the amorphous silicon film 103 is formed, heat treatment is performed at a temperature of 600 ° C. to crystallize the amorphous silicon film 103. Then, laser light is irradiated, and crystal growth is performed around the region indicated by 104 to obtain a crystal region 106 that can be regarded as a single crystal. This laser light irradiation is performed while heating the sample or the irradiated surface to a temperature of 600 ° C. This laser light irradiation is performed on the region indicated by 104 in FIG. 1, and at that time, crystal growth proceeds from the region indicated by 104 to the periphery. (Fig. 1 (A))

  In the above process, it is effective to introduce a metal element that promotes crystallization into the amorphous silicon film. In this way, a region that can be regarded as a single crystal over a larger area can be formed.

  When a region 106 that can be regarded as a single crystal is obtained, an active layer of the thin film transistor is formed by patterning using this region. Most preferably, the active layer is formed in a region which can be regarded as a single crystal as a whole. However, depending on the size of the active layer, the obtained single crystal region is relatively small, and it may be difficult to form the entire active layer. In this case, by setting at least the channel formation region as a region that can be regarded as a single crystal, a state in which no crystal grain boundary exists in the channel formation region can be obtained.

  After forming the active layer, a silicon oxide film 107 is formed as a gate insulating film to a thickness of 1000 mm by plasma CVD. Then, a film mainly composed of aluminum containing 0.2% scandium is formed to a thickness of 6000 mm. Next, the gate electrode 108 is obtained by patterning the film containing aluminum as a main component.

  Then, an oxide layer 109 is formed by performing anodization in an ethylene glycol solution containing 10% tartaric acid with the gate electrode 108 as an anode. The thickness of the oxide layer 109 is about 2000 mm. The presence of this oxide layer makes it possible to form an offset gate region in a subsequent impurity ion implantation step.

  Next, phosphorus ions are implanted into the active layer as impurity ions for N-channel type thin film transistors and boron ions are implanted as impurity ions for P-channel type thin film transistors. In this step, the gate electrode 108 and the surrounding oxide layer 109 serve as a mask, and impurity ions are implanted into the regions indicated by 110 and 114. The region 110 into which impurity ions are implanted is formed as a source region, and the region 114 is formed as a drain region. The oxide layer 109 around the gate electrode 108 serves as a mask, and the offset gate regions 111 and 113 are formed simultaneously. The channel formation region 112 is also formed in a self-aligned manner. (Figure 1 (C))

  After completion of the impurity ion implantation step, laser light is irradiated to anneal the active layer damaged by the impurity ion implantation and activate the implanted impurities. This step may be performed by irradiating strong light such as infrared light.

  Further, a silicon oxide film 115 is formed as an interlayer insulating film to a thickness of 7000 mm by plasma CVD. Further, a source electrode 116 and a drain electrode 117 are formed through a drilling process. Further, the thin film transistor is completed by performing heat treatment in a hydrogen atmosphere at 350 ° C. (Figure 1 (D))

  The thin film transistor shown in this embodiment is formed of a region having a structure in which the active layer can be regarded as a single crystal. Therefore, the problem of low breakdown voltage due to crystal grain boundaries and a problem of large leakage current are solved. Can do.

  This embodiment shows an example in which a crystalline region that can be regarded as a single crystal is formed by introducing a metal element that promotes crystallization into an amorphous silicon film, and a thin film transistor is configured using the crystalline region. .

  FIG. 2 shows a manufacturing process of this embodiment. First, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 3000 mm by sputtering. Then, an amorphous silicon film 103 is formed to a thickness of 1000 mm by plasma CVD or low pressure thermal CVD. Then, an extremely thin oxide film (not shown) is formed on the surface of the amorphous silicon film by UV oxidation. This oxide film is for improving the wettability of the solution in the subsequent solution coating step. The UV oxidation step performed here forms an extremely thin oxide film on the surface of the irradiated surface by irradiating UV light in an oxidizing atmosphere.

  Next, a nickel acetate solution is coated on the surface of the amorphous silicon film 103 on which an ultrathin oxide film is formed by a spin coating method to form a coating film 100 containing nickel. Due to the presence of the coating 100, the nickel element is placed in contact with the amorphous silicon film through an extremely thin oxide film.

  In this state, a heat treatment is performed at 550 ° C. for 4 hours to transform the amorphous silicon film 103 into a crystalline silicon film. Here, since nickel which is a metal element for promoting crystallization is introduced, a crystalline silicon film can be obtained by heat treatment at 550 ° C. for about 4 hours.

  When the silicon film 103 transformed into a crystalline silicon film by heat treatment is obtained, crystal growth is performed from the region indicated by 104 in FIG. 2 by irradiating with laser light. In the case of this example, since nickel, which is a metal element that promotes crystallization, is introduced, a region that can be regarded as a single crystal as indicated by 106 can be easily obtained.

  When a region 106 that can be regarded as a single crystal as shown in FIG. 2B is thus obtained, an active layer of the thin film transistor is formed using the region 106. The nickel-containing film is removed before or after the active layer is formed.

  After the formation of the active layer, the gate insulating film 107 is formed of a silicon oxide film, and a gate electrode 108 mainly composed of aluminum and an oxide layer 109 therearound are formed. These manufacturing steps are the same as those shown in the first embodiment.

  When the state shown in FIG. 2C is thus obtained, impurity ions are implanted, and the source region 110 and the drain region 114 are formed. In this step, the offset gate regions 111 and 113 and the channel formation region 112 are formed in a self-aligned manner.

  Further, laser light irradiation is performed to activate damage of the impurity ions and the implanted impurity ions.

  Then, a silicon oxide film 115 is formed as an interlayer insulating film by a plasma CVD method, and a source electrode 116 and a drain electrode 117 are formed through a drilling process. Finally, heat treatment is performed in a hydrogen atmosphere at 350 ° C. for 1 hour, whereby the thin film transistor illustrated in FIG. 2D is completed.

  This embodiment relates to a structure using the invention disclosed in this specification for a thin film transistor which needs to handle a large current. For example, the peripheral circuit of an active matrix liquid crystal display device requires a buffer amplifier (power conversion circuit with low output impedance) that can pass a large current to drive hundreds of thousands of pixel transistors. It is said. When it is intended to integrate not only the display area but also the peripheral circuit area on a single substrate, this buffer amplifier also needs to be formed of a thin film transistor.

  In order to form a thin film transistor that can be used in such a buffer amplifier, the width of the channel formation region of the thin film transistor needs to be several tens of μm or more. However, when a crystalline silicon thin film having a general polycrystalline or microcrystalline structure is used, there is a problem that the withstand voltage is low and it is difficult to construct a necessary buffer amplifier. In addition, when high-speed operation is performed, there is a problem that characteristic variation and drift are likely to occur. This is because the threshold value fluctuates in each transistor and the characteristics are likely to deteriorate. There is also a problem of heat generation, and there is also a problem that characteristics deteriorate due to the effect of heat generation. These problems are mainly caused by the presence of crystal grain boundaries in the active layer (particularly the channel formation region).

  Therefore, in this embodiment, a plurality of thin film transistors each of which forms a channel formation region are connected in parallel using a region that can be regarded as a single crystal, and a large current equivalent to that of a thin film transistor having an equivalently large channel width is obtained. A configuration that can be handled is provided.

  FIG. 3 shows a structure of the thin film transistor shown in this embodiment. In the structure shown in this embodiment, a structure in which three thin film transistors are connected in parallel is shown. In the configuration shown in FIG. 3, the channel formation region of each thin film transistor and the active layer that forms the periphery thereof are formed of a silicon semiconductor thin film that can be regarded as a single crystal.

  In FIG. 3, a region 301 is a region that can be regarded as a single crystal. A region which can be regarded as a single crystal indicated by 106 includes a channel formation region and a part of the source / drain region. Accordingly, not only the channel formation region but also the interface between the source region and the channel formation region and the vicinity thereof, and the interface between the drain region and the channel formation region and the vicinity thereof can be regarded as a single crystal.

  When such a configuration is adopted, problems caused by the presence of crystal grain boundaries can be solved. That is, it is possible to solve the problem of low withstand voltage, the problem of deterioration of characteristics, and the problem that the threshold value fluctuates. In addition, since carriers moving between the source / drain via the crystal grain boundary can be reduced, the OFF current can be reduced.

  A cross section taken along line A-A ′ of the structure shown in FIG. 3 corresponds to FIG. That is, the structure shown in FIG. 3 has a structure in which three thin film transistors shown in FIG. 1D are connected in parallel. Each transistor has a common gate electrode, and the source electrode and the drain electrode are wired in common by contacts 305 and 306.

  When the configuration shown in this embodiment is adopted, even if the channel width of each thin film transistor is 20 μm, an operation equivalent to that of a thin film transistor having a channel width of 60 μm is obtained by connecting three thin film transistors in parallel. Can be done.

  In this embodiment, an example in which three thin film transistors are connected in parallel is shown. However, the required number of thin film transistors connected in parallel can be selected.

  By adopting the structure shown in this embodiment, a thin film transistor having characteristics equivalent to those of a thin film transistor using a semiconductor that can be regarded as a single crystal and capable of handling a large current can be obtained. Therefore, a high-speed operation can be performed, and a configuration without deterioration or change in characteristics can be realized.

  The configuration shown in this embodiment can be said to be optimal for a circuit that needs to pass a large current, for example, a buffer circuit arranged in a peripheral circuit of an active matrix liquid crystal display device.

  An example of constructing a more advanced active matrix type liquid crystal display system using the invention disclosed in this specification is shown in FIG. The example of FIG. 6 is miniaturized by fixing a semiconductor chip attached to a main board of a normal computer on at least one substrate of a liquid crystal display having a configuration in which a liquid crystal is sandwiched between a pair of substrates. This is an example of reducing the weight and thickness.

  Hereinafter, FIG. 6 will be described. The substrate 15 is also a substrate for a liquid crystal display, on which an active matrix circuit 14 in which a large number of pixels each having a TFT 11, a pixel electrode 12, and an auxiliary capacitor 13 are formed, and an X decoder / driver for driving it, Y A decoder / driver and an XY branch circuit are formed by TFTs. In order to drive the active matrix circuit, it is necessary to arrange a buffer circuit having a low output impedance in the peripheral circuit. However, it is useful to configure this buffer circuit by applying a circuit as shown in FIG. .

  Then, another chip is attached on the substrate 15. These chips are connected to a circuit on the substrate 15 by means such as a wire bonding method or a COG (chip on glass) method. In FIG. 6, a correction memory, a memory, a CPU, and an input port are chips attached in this way, and various other chips may be attached.

  In FIG. 6, an input port is a circuit that reads an externally input signal and converts it into an image signal. The correction memory is a memory unique to the panel for correcting an input signal or the like in accordance with the characteristics of the active matrix panel. In particular, this correction memory has information specific to each pixel as a non-volatile memory, and is used for individual correction. That is, if a pixel of the electro-optical device has a point defect, a signal corrected accordingly is sent to the pixels around the point to cover the point defect and make the defect inconspicuous. Alternatively, when the pixel is darker than the surrounding pixels, a larger signal is sent to the pixel so that the brightness is the same as that of the surrounding pixels. Since the pixel defect information varies from panel to panel, the information stored in the correction memory varies from panel to panel.

  The CPU and the memory have the same functions as those of a normal computer. In particular, the memory has an image memory corresponding to each pixel as a RAM. These chips are all of the CMOS type.

Further, at least a part of the required integrated circuit may be constituted by the invention disclosed in this specification to further increase the thin film of the system.
As described above, even a CPU and a memory are formed on a liquid crystal display substrate, and configuring a simple electronic device such as a personal computer with a single substrate reduces the size of the liquid crystal display system and widens its application range. Is very useful for.

  As shown in this embodiment, a thin film transistor manufactured using the invention disclosed in this specification can be used for a circuit required for a systemized liquid crystal display. In particular, it is extremely useful to use a thin film transistor manufactured using a region that can be regarded as a single crystal for an analog buffer circuit and other necessary circuits.

  This embodiment relates to a configuration in which three thin film transistors are connected in parallel as shown in FIG. In FIG. 8, a common active layer is indicated by 804, and a region indicated by 803 is a region that can be regarded as a single crystal formed in the active layer. FIG. 8 shows three regions that can be regarded as single crystals, and channel forming regions of the respective thin film transistors are formed in the regions that can be regarded as three single crystals.

  Reference numeral 801 denotes a common gate electrode and gate wiring. Reference numeral 805 denotes a common source electrode and source wiring. Reference numeral 806 denotes a common drain electrode and drain wiring. Reference numeral 802 denotes a contact portion between the source / drain electrode and the source / drain region.

The manufacturing process of the thin-film transistor of an Example is shown. The manufacturing process of the thin-film transistor of an Example is shown. The structure of the thin film transistor of an Example is shown. The relationship between the irradiation energy density of the laser beam and the Raman intensity when the heating temperature of the sample is changed is shown. The relationship between the irradiation energy density of the laser beam and the half width of the Raman spectrum when the heating temperature of the sample is changed is shown. An example of a liquid crystal electro-optical device integrated on a single substrate is shown. An example of a Raman spectrum is shown. The structure of the thin film transistor of an Example is shown.

Explanation of symbols

101 glass substrate 102 base film (silicon oxide film)
DESCRIPTION OF SYMBOLS 103 Silicon film 104 Area | region irradiated with laser light 105 Area | region which remain | survives as an amorphous silicon film 106 Area | region which can be regarded as a single crystal 107 Gate insulating film (silicon oxide film)
108 Gate electrode 109 Anodic oxide layer 110 Source region 111, 113 Offset gate region 114 Drain region 115 Interlayer insulating film 116 Source electrode 117 Drain electrode 100 Nickel-containing film 305, 306 Contact region

Claims (11)

A display device having a plurality of thin film transistors formed on a substrate,
The plurality of thin film transistors includes:
A plurality of channel formation regions formed in a common active layer;
With common gate wiring,
A common source line electrically connected to the common active layer;
A common drain wiring electrically connected to the common active layer;
Have
The display device, wherein the plurality of thin film transistors are connected in parallel by the common gate wiring, the common source wiring, and the common drain wiring. A display device having first, second and third thin film transistors formed on a substrate,
The first, second and third thin film transistors are:
First, second and third channel forming regions formed in a common active layer;
With common gate wiring,
A common source line electrically connected to the common active layer;
A common drain wiring electrically connected to the common active layer;
Have
The display device, wherein the first, second, and third thin film transistors are connected in parallel by the common gate wiring, the common source wiring, and the common drain wiring. A common active layer formed on the substrate and having a first channel formation region and a second channel formation region;
With common gate wiring,
A common source line electrically connected to the common active layer in the first contact portion and the third contact portion;
A common drain wiring electrically connected to the common active layer in a second contact portion;
Have
The first channel formation region is disposed between the first contact portion and the second contact portion;
The display device, wherein the second channel formation region is disposed between the second contact portion and the third contact portion. A common active layer formed on the substrate and having a first channel formation region, a second channel formation region, and a third channel formation region;
With common gate wiring,
A common source line electrically connected to the common active layer in the first contact portion and the third contact portion;
A common drain wiring electrically connected to the common active layer in the second contact portion and the fourth contact portion;
Have
The first channel formation region is disposed between the first contact portion and the second contact portion;
The second channel formation region is disposed between the second contact portion and the third contact portion;
The display device, wherein the third channel formation region is disposed between the third contact portion and the fourth contact portion. The display device according to claim 1, wherein the substrate is a glass substrate. 6. The display device according to claim 1, wherein the common gate wiring is formed on the common active layer. 7. The display device according to claim 1, wherein each channel formation region is formed using a region that can be regarded as a single crystal. The display device according to claim 1, wherein the common active layer includes a source region and a drain region. The display device according to claim 1, wherein a part of the common active layer includes phosphorus. 9. The display device according to claim 1, wherein a part of the common active layer includes boron. The display device according to claim 1, wherein the display device is a liquid crystal display device.

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