JPH0570156B2 - - Google Patents
Info
- Publication number
- JPH0570156B2 JPH0570156B2 JP59173849A JP17384984A JPH0570156B2 JP H0570156 B2 JPH0570156 B2 JP H0570156B2 JP 59173849 A JP59173849 A JP 59173849A JP 17384984 A JP17384984 A JP 17384984A JP H0570156 B2 JPH0570156 B2 JP H0570156B2
- Authority
- JP
- Japan
- Prior art keywords
- drain electrode
- electrode
- thin film
- semiconductor thin
- pixel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 25
- 239000010409 thin film Substances 0.000 claims description 19
- 239000004065 semiconductor Substances 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 9
- 239000011159 matrix material Substances 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910006404 SnO 2 Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910001188 F alloy Inorganic materials 0.000 description 1
- 229910000878 H alloy Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 206010034972 Photosensitivity reaction Diseases 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000036211 photosensitivity Effects 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクテイブ・マトリクス液晶表示装
置における薄膜トランジスタ基板に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor substrate in an active matrix liquid crystal display device.
非晶質シリコン（ａ−Si）や多結晶Si（ｐ−Si）
等の半導体薄膜を用いた薄膜トランジスタ
（TFT）は、広く応用されつつある。その１つに
液晶表示装置に代表されるアクテイブマトリクス
表示装置がある。その単位画素は、第２図と第３
図に示す様な構造を有していた。ａ−Si TFTを
例にとつて説明する。第２図は、ガラスや石英の
如き透明絶縁基板１上に、ゲート電極２を配し、
それを被覆するゲート絶縁膜３，ａ−Si膜４を形
成し、その上にドレイン電極配線５、ソース電極
６を配したものである。さらに、ITOやSnO2等
の透明導電膜からなる画素電極７を設け、ソース
電極６を接続する。第２図の例では、ドレイン電
極配線５とソース電極６、画素電極７をすべて透
明導電膜で形成したものである。第３図の例で
は、ドレイン・ソース電極５，６共に、透明導電
膜以外の金属と低抵抗ａ−Siの２層で形成したも
ので、絶縁膜８のコンタクト開孔部を介してａ−
Si膜３や画素電極７に接続されている。この場
合、低抵抗ａ−Si２５，２６は、例えばリンを添
加したａ−Si：Ｈが用いられ、金属１５，１６は
ＡやMo等が用いられる。アクテイブマトリク
ス表示装置の場合、例えばゲート電極２は行電極
に、ドレイン電極配線５は列電極に用いられ、そ
れぞれ１回のマスク工程により形成され、その高
歩留り性が要求されていた。
Amorphous silicon (a-Si) and polycrystalline silicon (p-Si)
Thin film transistors (TFTs) using semiconductor thin films such as these are becoming widely applied. One of them is an active matrix display device typified by a liquid crystal display device. The unit pixel is shown in Figures 2 and 3.
It had a structure as shown in the figure. This will be explained using a-Si TFT as an example. FIG. 2 shows a gate electrode 2 arranged on a transparent insulating substrate 1 such as glass or quartz,
A gate insulating film 3 and an a-Si film 4 are formed to cover it, and a drain electrode wiring 5 and a source electrode 6 are arranged thereon. Further, a pixel electrode 7 made of a transparent conductive film such as ITO or SnO 2 is provided and connected to the source electrode 6. In the example shown in FIG. 2, the drain electrode wiring 5, the source electrode 6, and the pixel electrode 7 are all formed of transparent conductive films. In the example shown in FIG. 3, both the drain and source electrodes 5 and 6 are formed of two layers of metal other than the transparent conductive film and low resistance a-Si, and the a-
It is connected to the Si film 3 and the pixel electrode 7. In this case, the low-resistance a-Si 25 and 26 are made of, for example, a-Si:H added with phosphorus, and the metals 15 and 16 are made of A, Mo, or the like. In the case of an active matrix display device, for example, the gate electrode 2 is used as a row electrode, and the drain electrode wiring 5 is used as a column electrode, each of which is formed by one mask process, and high yield is required.
ａ−SiTFTの場合には第２図と第３図の例の
他に、さらに上下からの遮光膜を形成したり、電
荷保持用の容量を形成したものがあるが、説明は
省略する。ｐ−SiTFTの場合は、特に遮光は必
要ないがほぼ同様な構造を有している。 In the case of a-Si TFTs, in addition to the examples shown in FIGS. 2 and 3, there are also those in which light-shielding films are formed from above and below, and capacitors for charge retention are formed, but their explanation will be omitted. In the case of p-SiTFT, light shielding is not particularly necessary, but it has almost the same structure.
第２図と第３図の従来例から明らかな様に、ド
レイン電極配線５は、長くかつ細いにもかかわら
ず、１回のマスク工程で形成する必要があつた。
そのため、本工程は製造歩留りに直接影響を与
え、歩留り低下の原因にもなつていた。また、第
３図の構造例の場合には、ソース電極６と画素電
極７を接続するため画素電極７とのコンタクト不
良やソース電極６の段切れ等の断線が画素欠陥と
して生じやすかつた。
As is clear from the conventional example shown in FIGS. 2 and 3, the drain electrode wiring 5 had to be formed in one mask process, although it was long and thin.
Therefore, this process had a direct impact on the manufacturing yield and was a cause of a decrease in the yield. Further, in the case of the structural example shown in FIG. 3, since the source electrode 6 and the pixel electrode 7 are connected, poor contact with the pixel electrode 7 and breakage such as a break in the source electrode 6 are likely to occur as pixel defects.
本発明は、上述の問題点を解決するもので、高
歩留りのアクテイブマトリクス表示装置のための
単位画素構造を提供するものである。その結果、
低コストの表示装置の提供を可能ならしめるもの
である。 The present invention solves the above-mentioned problems and provides a unit pixel structure for a high-yield active matrix display device. the result,
This makes it possible to provide a low-cost display device.
本発明では、ドレイン電極配線を２つ以上の導
電膜を、２回以上のマスク工程で形成し、冗長配
線を行なつて、高歩留り化するものである。さら
に具体的には、画素電極用透明導電膜をその１つ
として用い付加ドレイン電極配線となし、さらに
他の導電膜によるドレイン電極配線を設ける。同
様な冗長性は、ソース電極にも適用され、さらに
歩留りを向上できる。また、付加ドレイン電極配
線とドレイン電極配線が半導体薄膜の上または下
で平面的に重なる部分をもたせることにより、両
配線間の抵抗を少なくし、例え一方が断線しても
電気的に影響を少なくするものである。さらに、
従来通りTFT特性をきめる一要因であるチヤン
ネル長は本来のドレイン電極とソース電極間距離
できまる様、付加ドレイン電極と画素電極間距離
の方を長くする様、配慮している。
In the present invention, the drain electrode wiring is formed using two or more conductive films in two or more mask steps, and redundant wiring is provided to achieve a high yield. More specifically, a transparent conductive film for a pixel electrode is used as an additional drain electrode wiring, and a drain electrode wiring is provided using another conductive film. Similar redundancy can be applied to the source electrodes to further improve yield. In addition, by creating a planar overlap between the additional drain electrode wiring and the drain electrode wiring above or below the semiconductor thin film, the resistance between the two wirings is reduced, and even if one of the wirings is disconnected, the electrical effect is reduced. It is something to do. moreover,
As before, we have taken care to ensure that the channel length, which is one of the factors that determines TFT characteristics, is determined by the distance between the original drain electrode and source electrode, and to make the distance between the additional drain electrode and pixel electrode longer.
本発明を図面を用いて以下に詳述する。第１図
は、本発明による単位画素の断面構造例である。
ガラス、石英、サフアイヤ等の透明絶縁基板１の
上に、行電極としてのゲート電極２が形成されて
いる。ゲート電極２はＡ，Mo，Cr，Ta，Ｗ
等の金属やその硅化物場合によつてはｐ−Si等が
用いられる。ゲート電極２上には、ゲート絶縁膜
３が形成され、主にCVDやプラズマCVD等で堆
積される窒化膜（SiNx）、酸化膜（SiOx）や、
場合によつてはゲート電極２材料の酸化物が用い
られる。ゲート絶縁膜３上には、ａ−Si：Ｈ合
金、ａ−Si：Ｆ合金、ｐ−Si等の半導体薄膜４が
堆積されるが、本例ではその前に画素電極７と付
加ドレイン電極配線３５がITOやSnO2の如き透
明導電膜で形成されている。必要に応じ酸化膜等
のフイールド絶縁膜８を堆積、選択開孔後、ドレ
イン電極配線５、ソース電極６、必要によつては
ゲート配線（図示せず）が設けられている。ドレ
イン及びソース電極５，６は、下からn+半導体
薄膜２５，２６，Ａ等の金属膜１５，１６から
成つている。列電極は、ドレイン電極配線５と付
加ドレイン電極配線３５とで冗長配線されている
が、特に工程増にはなつていない。画素電極７
は、半導体薄膜４と直接接しているので、画素欠
陥を発生しにくい。付加ドレイン電極配線３５及
び画素電極７は、必ずしもゲート絶縁膜３を介し
てゲート電極２と平面的に重なる必要はないが、
ドレイン電極配線５及びソース電極６にも冗長性
をもたせる意味で重なつた方が望ましい。しか
し、良好なオーミツク接触を得るには、ドレイン
及びソース電極５及び６を半導体薄膜４の上部に
設けた方が望ましく、TFTのチヤンネル長は、
この両電極５，６の間隔できめている。付加ドレ
イン電極配線３５と画素電極７の間隔は、チヤン
ネル長以上にした方が望ましい。
The present invention will be explained in detail below using the drawings. FIG. 1 is an example of a cross-sectional structure of a unit pixel according to the present invention.
A gate electrode 2 as a row electrode is formed on a transparent insulating substrate 1 made of glass, quartz, sapphire, or the like. Gate electrode 2 is made of A, Mo, Cr, Ta, W
metals such as metals and their silicides, and in some cases p-Si etc. are used. A gate insulating film 3 is formed on the gate electrode 2, and includes a nitride film (SiNx), an oxide film (SiOx) deposited mainly by CVD, plasma CVD, etc.
In some cases, an oxide of the material of the gate electrode 2 is used. A semiconductor thin film 4 of a-Si:H alloy, a-Si:F alloy, p-Si, etc. is deposited on the gate insulating film 3, but in this example, the pixel electrode 7 and the additional drain electrode wiring are deposited before that. 35 is formed of a transparent conductive film such as ITO or SnO 2 . After depositing a field insulating film 8 such as an oxide film if necessary and selectively opening holes, a drain electrode wiring 5, a source electrode 6, and if necessary a gate wiring (not shown) are provided. The drain and source electrodes 5 and 6 are composed of n + semiconductor thin films 25 and 26, and metal films 15 and 16 such as A from the bottom. Although the column electrodes are redundantly wired with the drain electrode wire 5 and the additional drain electrode wire 35, this does not result in a particular increase in the number of steps. Pixel electrode 7
Since it is in direct contact with the semiconductor thin film 4, pixel defects are less likely to occur. The additional drain electrode wiring 35 and the pixel electrode 7 do not necessarily need to overlap the gate electrode 2 in plan with the gate insulating film 3 interposed therebetween;
It is preferable that the drain electrode wiring 5 and the source electrode 6 also overlap in order to provide redundancy. However, in order to obtain good ohmic contact, it is preferable to provide the drain and source electrodes 5 and 6 on the top of the semiconductor thin film 4, and the channel length of the TFT is
The distance between the two electrodes 5 and 6 is defined. It is preferable that the distance between the additional drain electrode wiring 35 and the pixel electrode 7 is equal to or larger than the channel length.
半導体薄膜４の電導率の光感度が高いとき、例
えばａ−Siや単結晶Siを用いた場合には、TFT
を遮光する必要がある。それには、従来の技術を
適用できるので、特に説明はしない。 When the photosensitivity of the conductivity of the semiconductor thin film 4 is high, for example when a-Si or single crystal Si is used, TFT
need to be shielded from light. Since conventional techniques can be applied to this, no particular explanation will be provided.
第４図には、本発明による他の実施例が示され
ている。付加ドレイン電極配線３５を半導体薄膜
４の上に設けたものである。この場合、金属１
５，n+薄膜２５から成るドレイン電極配線５は
付加ドレイン電極配線３５と一部重なり、かつ半
導体薄膜４上に直接コンタクトしている。 FIG. 4 shows another embodiment according to the invention. An additional drain electrode wiring 35 is provided on the semiconductor thin film 4. In this case, metal 1
The drain electrode wiring 5 made of the 5,n + thin film 25 partially overlaps the additional drain electrode wiring 35 and is in direct contact with the semiconductor thin film 4 .
上述の如く、本発明によれば、列電極はドレイ
ン電極配線と付加ドレイン電極配線とで冗長度を
もたせて形成されるもので、たとえ一方が断線し
ても他の配線で救済することができる。また、例
えばドレイン電極と半導体薄膜間のコンタクトに
不良が生じても、付加ドレインによるコンタクト
で多少のコンタクト抵抗があつても致命的な欠陥
になることはない。同様なことは、ソース電極と
画素電極についてもいえ、画素欠陥救済効果を有
する。必要によつては、半導体薄膜と重ならない
画素電極上でもソース電極と接触させれば、その
効果はより大きい。
As described above, according to the present invention, the column electrode is formed with redundancy between the drain electrode wiring and the additional drain electrode wiring, so that even if one is broken, it can be repaired with the other wiring. . Further, even if a defect occurs in the contact between the drain electrode and the semiconductor thin film, for example, even if there is some contact resistance due to the contact made by the additional drain, it will not become a fatal defect. The same thing can be said about the source electrode and the pixel electrode, which has the effect of relieving pixel defects. If necessary, the effect will be even greater if the pixel electrode that does not overlap the semiconductor thin film is brought into contact with the source electrode.
また、既述の如く、工程を特に増加させずに冗
長配線ができるので、高歩留りで表示装置用基板
が製造できる。その結果として、低コスト、高品
質のアクテイブマトリクス表示装置の提供が可能
となる。また、高歩留りであることから大面積大
容量表示装置の製造も容易となり、応用範囲がさ
らに拡がる。 Furthermore, as described above, since redundant wiring can be provided without increasing the number of steps, display device substrates can be manufactured with high yield. As a result, it becomes possible to provide a low-cost, high-quality active matrix display device. Furthermore, since the yield is high, it becomes easy to manufacture large-area, large-capacity display devices, further expanding the range of applications.
第１図は本発明による単位画素の構造断面図、
第２図及び第３図はそれぞれ従来の単位画素の構
造断面図、第４図は本発明による単位画素の他の
構造断面図である。
１……基板、２……ゲート電極、３……ゲート
絶縁膜、４……半導体薄膜、５……ドレイン電極
配線、６……ソース電極、７……画素電極、８…
…絶縁膜、３５……付加ドレイン電極配線。
FIG. 1 is a structural cross-sectional view of a unit pixel according to the present invention;
2 and 3 are structural cross-sectional views of a conventional unit pixel, respectively, and FIG. 4 is a structural cross-sectional view of another unit pixel according to the present invention. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Gate electrode, 3...Gate insulating film, 4...Semiconductor thin film, 5...Drain electrode wiring, 6...Source electrode, 7...Pixel electrode, 8...
...Insulating film, 35...Additional drain electrode wiring.
Claims (1)
覆するゲート絶縁膜と、該絶縁膜上の半導体薄膜
と、前記半導体薄膜上に形成されたソース電極と
ドレイン電極配線とから成る薄膜トランジスタ
と、前記ソース電極に接続された透明導電膜より
成る画素電極を少なく共有する単位画素から成る
アクテイブマトリクス表示装置用基板において、
前記ドレイン電極配線と前記半導体薄膜上または
下で平面的に重なる部分を有する付加ドレイン電
極配線を設け、付加ドレイン電極配線の少なく共
一部を前記透明導電膜で前記画素電極より離間し
て形成したことを特徴とするアクテイブ・マトリ
クス表示装置用基板。 ２ 前記ソース電極と画素電極が前記半導体薄膜
上または下で平面的に重なる部分を有することを
特徴とする特許請求の範囲第１項記載のアクテイ
ブ・マトリクス表示装置用基板。 ３ 前記付加ドレイン電極配線と前記画素電極と
の離間距離が、前記ソース及びドレイン電極配線
の離間距離よりきまる実質的チヤンネル長以上に
長いことを特徴とする特許請求の範囲第１項また
は第２項記載のアクテイブ・マトリクス表示装置
用基板。[Scope of Claims] 1. A gate electrode on a transparent insulating substrate, a gate insulating film covering the electrode, a semiconductor thin film on the insulating film, and a source electrode and drain electrode wiring formed on the semiconductor thin film. and a unit pixel that shares a small number of pixel electrodes made of a transparent conductive film connected to the source electrode,
An additional drain electrode wiring having a portion that overlaps with the drain electrode wiring in a planar manner on or below the semiconductor thin film is provided, and at least a common portion of the additional drain electrode wiring is formed with the transparent conductive film spaced apart from the pixel electrode. A substrate for an active matrix display device characterized by: 2. The substrate for an active matrix display device according to claim 1, wherein the source electrode and the pixel electrode have a planar overlapping portion on or below the semiconductor thin film. 3. Claim 1 or 2, wherein the distance between the additional drain electrode wiring and the pixel electrode is longer than the substantial channel length determined by the distance between the source and drain electrode wiring. The active matrix display device substrate described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59173849A JPS6151188A (en) | 1984-08-21 | 1984-08-21 | Substrate for active matrix display unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59173849A JPS6151188A (en) | 1984-08-21 | 1984-08-21 | Substrate for active matrix display unit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6151188A JPS6151188A (en) | 1986-03-13 |
| JPH0570156B2 true JPH0570156B2 (en) | 1993-10-04 |
Family
ID=15968292
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59173849A Granted JPS6151188A (en) | 1984-08-21 | 1984-08-21 | Substrate for active matrix display unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6151188A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8222098B2 (en) | 2005-10-14 | 2012-07-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having first and second source and drain electrodes sandwiched between an island-shaped semiconductor film |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63216091A (en) * | 1987-03-04 | 1988-09-08 | 三菱電機株式会社 | Matrix type display device |
| JPH01219825A (en) * | 1988-02-29 | 1989-09-01 | Seikosha Co Ltd | Amorphous silicon thin film transistor |
| JP2550692B2 (en) * | 1989-02-11 | 1996-11-06 | 日本電気株式会社 | Method of manufacturing thin film transistor array |
| JPH07113729B2 (en) * | 1989-08-25 | 1995-12-06 | 日本電気株式会社 | Thin film transistor |
| JP3104356B2 (en) * | 1991-12-13 | 2000-10-30 | カシオ計算機株式会社 | Thin film transistor panel and method of manufacturing the same |
| JP5427340B2 (en) * | 2005-10-14 | 2014-02-26 | 株式会社半導体エネルギー研究所 | Semiconductor device |
| US20100224880A1 (en) * | 2009-03-05 | 2010-09-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
| JP6103854B2 (en) * | 2012-08-10 | 2017-03-29 | 三菱電機株式会社 | Thin film transistor substrate |
| CN105161544A (en) * | 2015-10-16 | 2015-12-16 | 深圳市华星光电技术有限公司 | Thin-film field effect transistor, manufacturing method thereof, and LCD |
-
1984
- 1984-08-21 JP JP59173849A patent/JPS6151188A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8222098B2 (en) | 2005-10-14 | 2012-07-17 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having first and second source and drain electrodes sandwiched between an island-shaped semiconductor film |
| US9312393B2 (en) | 2005-10-14 | 2016-04-12 | Semiconductor Energy Laboratory Co., Ltd. | Transistor having tapered gate electrode |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6151188A (en) | 1986-03-13 |
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