JPH0431376B2 - - Google Patents
Info
- Publication number
- JPH0431376B2 JPH0431376B2 JP15255684A JP15255684A JPH0431376B2 JP H0431376 B2 JPH0431376 B2 JP H0431376B2 JP 15255684 A JP15255684 A JP 15255684A JP 15255684 A JP15255684 A JP 15255684A JP H0431376 B2 JPH0431376 B2 JP H0431376B2
- Authority
- JP
- Japan
- Prior art keywords
- gate
- wiring
- electrode
- gate wiring
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 33
- 239000003990 capacitor Substances 0.000 claims description 9
- 239000010409 thin film Substances 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 8
- 239000011159 matrix material Substances 0.000 claims description 7
- 230000014759 maintenance of location Effects 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1335—Structural association of cells with optical devices, e.g. polarisers or reflectors
- G02F1/133509—Filters, e.g. light shielding masks
- G02F1/133512—Light shielding layers, e.g. black matrix
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
- G02F1/13629—Multilayer wirings
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Liquid Crystal (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、アクテイブマトリクス液晶表示装置
における薄膜トランジスタ基板に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film transistor substrate in an active matrix liquid crystal display device.
非晶質シリコンａ−Siや多結晶シリコンＰ−Si
等の半導体薄膜を用いた薄膜トランジスタ
（TFT）の１つの応用に、アクテイブマトリクス
液晶表示装置がある。その単位画素の例を第２図
に示す。第２図ａ及びｂは、単位画素構造例のそ
れぞれ平面図及びＡ−Ｂ，Ｂ−Ｃに沿つた断面図
である。半導体薄膜としてａ−Siを用いた例で説
明する。ガラス等の透明絶縁基板１上には、ITO
による共通電極８が設けられ、画素に書き込まれ
た電荷の保持容量の一方の電極として働く。保持
容量は、共通電極８とITO画素電極７とSiOxや
SiNx等絶縁膜９とで形成されている。絶縁膜９
上にはゲート電極配線２が設けられ、行電極とし
て延在している。他行のゲート電極配線２′も図
示している。ゲート電極配線２，２′上にはゲー
ト絶縁膜３，ａ−Si膜４が設けられ、ａ−Si膜４
上に列電極としてのドレイン電極配線５，５′、
ソース電極６，６′が配されている。この例では、
両電極５，６共金属層１５，１６とn+ａ−Si膜２
５，２６から成る。ソース電極６は、画素電極７
と接続されている。さらに、図示してないが遮光
膜やパツシベーシヨン膜等も形成される場合があ
る。第２図ａ及びｂの構造例では、導電膜の層数
や絶縁膜の層数が多いので製造工数が多く、従つ
て製造歩留りを向上するのに困難がある。
Amorphous silicon a-Si and polycrystalline silicon P-Si
An active matrix liquid crystal display device is one application of thin film transistors (TFTs) using semiconductor thin films such as the above. An example of the unit pixel is shown in FIG. FIGS. 2a and 2b are a plan view and a cross-sectional view taken along AB and BC, respectively, of an example of a unit pixel structure. An example using a-Si as the semiconductor thin film will be explained. ITO is placed on the transparent insulating substrate 1 made of glass etc.
A common electrode 8 is provided, and serves as one electrode of a storage capacitor for charges written in pixels. The storage capacitance is the common electrode 8, ITO pixel electrode 7, SiOx,
It is formed with an insulating film 9 such as SiNx. Insulating film 9
A gate electrode wiring 2 is provided above and extends as a row electrode. Gate electrode wiring lines 2' in other rows are also shown. A gate insulating film 3 and an a-Si film 4 are provided on the gate electrode wirings 2 and 2'.
drain electrode wirings 5, 5' as column electrodes on top;
Source electrodes 6, 6' are arranged. In this example,
Both electrodes 5, 6, metal layers 15, 16 and n + a-Si film 2
It consists of 5.26. The source electrode 6 is the pixel electrode 7
is connected to. Furthermore, although not shown, a light shielding film, a passivation film, etc. may also be formed. In the structural examples shown in FIGS. 2a and 2b, the number of conductive film layers and the number of insulating film layers are large, so the number of manufacturing steps is large, and it is therefore difficult to improve the manufacturing yield.
一方、第２図ｃに示した断面構造例では、電荷
保持容量を他行のゲート電極配線２′と画素電極
７及びゲート絶縁膜３で形成したものを示す。こ
の例では、製造工数が減少するが他行のゲート電
極配線２′で保持容量を形成するため、表示とし
て有効な画素面積即ち開孔率が減少してしまう欠
点を有す。 On the other hand, in the cross-sectional structure example shown in FIG. 2c, the charge storage capacitor is formed by the gate electrode wiring 2' of the other row, the pixel electrode 7, and the gate insulating film 3. In this example, the number of manufacturing steps is reduced, but since the storage capacitance is formed with the gate electrode wiring 2' of the other row, it has the disadvantage that the pixel area effective for display, that is, the aperture ratio is reduced.
第２図ａ，ｂ及びｃの例からわかる様に、従来
はゲート電極配線２，２′は、１回のマスク工程
及びエツチング工程で形成していた。そのため、
そのマスク・エツチ工程に不具合が１ケ所でもあ
ると、ゲート電極配線断線が生じ結果的に不良品
を生じてしまう。画素数を増やしたり、大面積表
示しようとする場合には、結局高い歩留りが得ら
れなくなり、低コストを実現しにくくなる。ま
た、第２図ａ，ｂの例では開孔率が高いが、層
数、工数が多く高歩留り・低コストが得にくい欠
点がある。第２図ｃの例では、開孔率が大きくで
きない欠点を有していた。
As can be seen from the examples shown in FIGS. 2a, b and c, conventionally the gate electrode wirings 2, 2' were formed by one masking process and one etching process. Therefore,
If there is even one defect in the mask/etch process, the gate electrode wiring may be disconnected, resulting in a defective product. When increasing the number of pixels or attempting to display a large area, it becomes impossible to obtain a high yield and it becomes difficult to achieve low costs. Furthermore, although the examples shown in FIGS. 2a and 2b have a high porosity, they have the disadvantage that the number of layers and man-hours are large, making it difficult to achieve high yield and low cost. The example shown in FIG. 2c had the disadvantage that the porosity could not be increased.
本発明は、層数及び工数を特に増加せずに高歩
留り、低コストの表示装置用基板を提供するもの
であり、かつ表示性能の１つである開孔率を特に
落とさずにそれを実現可能とするものである。 The present invention provides a high-yield, low-cost display device substrate without particularly increasing the number of layers or man-hours, and achieves this without particularly reducing the aperture ratio, which is one of display performance. It is possible.
本発明では、ゲート電極配線を少なく共遮光性
を有する導電膜の第１ゲート配線と透明導電膜の
第２ゲート配線の２層を用い、それが少なく共部
分的に接触させることにより行配線の断線確率を
極度に減少する。また、前記透明導電膜を電荷保
持容量の一方の電極に用いることによつて開孔率
の減少を防止するものである。
In the present invention, the gate electrode wiring is made up of two layers: a first gate wiring made of a conductive film having a co-shielding property and a second gate wiring made of a transparent conductive film. Extremely reduces the probability of disconnection. Further, by using the transparent conductive film as one electrode of the charge storage capacitor, a reduction in the porosity is prevented.
第１図ａ及びｂには、本発明の単位画素の構造
例を示す。第１図ｂは、第１図ａの平面図のＡ−
Ｂ，Ｂ−Ｃに沿つた断面図である。ゲート電極配
線２は、Al，Cr，Mo，Ｗ等金属やその硅化物な
どによる不透明導電膜を用いた第１ゲート配線１
２と、ITOやSnO2等透明導電膜を用いた第２ゲ
ート配線２２から成つている。第１及び第２ゲー
ト配線共に、直接重なる部分を有し、電気的には
ほぼ同電位になる。一方、他行の第２ゲート配線
２２′は、画素電極７の下に延在し、ゲート絶縁
膜３とで電荷保持容量を形成している。この例で
は、TFTのゲート電極としては第１ゲート配線
１２のみを配している。TFTは、第１ゲート配
線に、ゲート絶縁膜３、半導体薄膜４、ドレイン
電極配線５、ソース電極６から成つている。さら
に、遮光膜や表面保護膜が必要な場合もあるが、
本発明に直接関係ないので省略する。また図示し
てないがゲート電極配線の外部とり出し部のコン
タクトも２種以上の導電膜を用いているので、よ
り容易にできる利点も合わせもつ。
FIGS. 1a and 1b show an example of the structure of a unit pixel according to the present invention. Figure 1b shows the plan view A- of Figure 1a.
It is a sectional view along B, BC. The gate electrode wiring 2 is a first gate wiring 1 using an opaque conductive film made of metal such as Al, Cr, Mo, W, or its silicide.
2 and a second gate wiring 22 using a transparent conductive film such as ITO or SnO 2 . Both the first and second gate wirings have portions that directly overlap and are electrically at approximately the same potential. On the other hand, the second gate wiring 22' in the other row extends below the pixel electrode 7, and forms a charge storage capacitor with the gate insulating film 3. In this example, only the first gate wiring 12 is provided as the gate electrode of the TFT. The TFT includes a first gate wiring, a gate insulating film 3, a semiconductor thin film 4, a drain electrode wiring 5, and a source electrode 6. In addition, a light-shielding film or surface protection film may be necessary.
Since it is not directly related to the present invention, it will be omitted. Further, although not shown in the drawings, the contact at the externally extending portion of the gate electrode wiring also uses two or more types of conductive films, so it also has the advantage that it can be made more easily.
第３図は、本発明の他の断面構造例である。ゲ
ート電極配線２，２′は、第１ゲート配線１２，
１２′と第２ゲート配線２２，２２′から成つてい
るが、この例では、第２ゲート配線２２もTFT
のゲート電極として働く。また、第１ゲート配線
１２，１２′は第２ゲート配線２２，２２′の上で
かつ幅狭く形成されている。しかしTFT下の第
１ゲート配線１２の幅はTFTを充分遮光する値
に選ばれている。またTFTのドレイン・ソース
電極５，６は画素電極７と同じ透明導電膜で形成
された例を示した。必要により表面は絶縁膜１９
（例えばSiOx）で被われている。 FIG. 3 shows another example of the cross-sectional structure of the present invention. The gate electrode wirings 2, 2' are connected to the first gate wirings 12, 2'.
12' and second gate wiring 22, 22', but in this example, the second gate wiring 22 is also TFT.
acts as a gate electrode. Further, the first gate wirings 12, 12' are formed narrowly above the second gate wirings 22, 22'. However, the width of the first gate wiring 12 under the TFT is selected to a value that sufficiently shields the TFT from light. Further, an example is shown in which the drain and source electrodes 5 and 6 of the TFT are formed of the same transparent conductive film as the pixel electrode 7. If necessary, the surface is covered with an insulating film 19.
(e.g. SiOx).
第４図は、本発明の他の実施例に基いた断面構
造例である。この例では、TFT下のゲート電極
配線２は、幅広い第１ゲート配線１２とその下で
第１ゲート配線１２に被われる第２ゲート配線２
２で成り、それ以外の部分には第１、第２ゲート
配線１２，２２が重ならない（第４図の他行の第
１ゲート配線１２′、第２ゲート配線２２′を参
照）。この様にすれば、基板の損傷等による段差
があつても、断線の危険性はより減少する。ま
た、本例では電荷保持容量はゲート絶縁膜３とフ
イールド絶縁膜１９を介して他行の第２ゲート配
線２２′と画素電極７で設けている。さらに、列
電極であるドレイン電極配線５には画素電極７と
同時の形成できる付加電極配線３５を付加し欠長
配線を行なつている例を示した。ソース電極６も
同様である。 FIG. 4 is an example of a cross-sectional structure based on another embodiment of the present invention. In this example, the gate electrode wiring 2 under the TFT includes a wide first gate wiring 12 and a second gate wiring 2 covering the first gate wiring 12 below.
2, and the first and second gate wirings 12 and 22 do not overlap in other parts (see the first gate wiring 12' and the second gate wiring 22' in the other row in FIG. 4). In this way, even if there is a step due to damage to the board, the risk of wire breakage is further reduced. Further, in this example, the charge storage capacitor is provided between the second gate wiring 22' and the pixel electrode 7 in the other row via the gate insulating film 3 and the field insulating film 19. Furthermore, an example has been shown in which an additional electrode wiring 35 that can be formed at the same time as the pixel electrode 7 is added to the drain electrode wiring 5, which is a column electrode, to form a missing length wiring. The same applies to the source electrode 6.
第５図は、本発明の他の具体例の断面図であ
る。ゲート電極配線２を下に第１ゲート配線は上
に第２ゲート配線２２によつて構成した例であ
る。この例のTFTもやはりドレインソース電極
５，６共に画素電極７と同時に形成した付加電極
３５，３６を有した例を示した。 FIG. 5 is a cross-sectional view of another embodiment of the invention. This is an example in which the gate electrode wiring 2 is arranged below and the first gate wiring is formed by the second gate wiring 22 above. The TFT in this example also has additional electrodes 35 and 36 formed at the same time as the drain and source electrodes 5 and 6 as well as the pixel electrode 7.
以上の電極例において、第１及び第２ゲート配
線の上下の関係は、第１ゲート配線に用いる材質
によつて適宜選ばれる。例えば、酸化しやすい
Crを第１ゲート配線に用いた場合には、第１ゲ
ート配線は上の方が下の第２ゲート配線例えば
ITOとコンタクトをとりやすい。酸化しにくい、
または酸化物を容易に除去できる導電膜を第１ゲ
ート配線に用いるときには、その限りでなく第５
図の例も適用できる。 In the above electrode examples, the vertical relationship between the first and second gate wirings is appropriately selected depending on the material used for the first gate wirings. For example, easy to oxidize
When Cr is used for the first gate wiring, the upper part of the first gate wiring is connected to the lower second gate wiring, for example.
Easy to contact ITO. hard to oxidize,
Alternatively, when a conductive film from which oxide can be easily removed is used for the first gate wiring, the fifth
The illustrated example is also applicable.
上述の如く、従来の１マスク工程で形成される
ゲート電極配線に対して、本発明による第１及び
第２ゲート配線はそれぞれのマスク・エツチ工程
によつて形成されるので、仮に、どちらか一方の
ゲート配線が断線したとしても、他方のゲート配
線とが行電極方向に面接触して電気的に接続して
いるために、同一のゲート電極配線の断線の確率
は従来の確率の自乗に低下する。例えば、１回の
マスク工程で0.1％の割合で断線が生ずるものと
すれば、本発明によれば100万本に１本切れるこ
とになり、不良率が極度に減少する。また、第２
ゲート配線に透明導電膜を使用するので、電荷保
持容量を形成しても開孔率を低下させることはな
い。
As mentioned above, unlike the conventional gate electrode wiring which is formed by one mask process, the first and second gate wirings according to the present invention are formed by respective mask etching processes. Even if one gate wiring is disconnected, the probability of disconnection of the same gate electrode wiring decreases to the square of the conventional probability because the other gate wiring is electrically connected by making surface contact in the row electrode direction. do. For example, if wire breakage occurs at a rate of 0.1% in one mask process, according to the present invention, one out of every one million wires will break, and the defective rate will be extremely reduced. Also, the second
Since a transparent conductive film is used for the gate wiring, the porosity does not decrease even if a charge storage capacitor is formed.
以上によつて、基本的に多数の単位画素を行列
状に配置するアクテイブマトリクス表示装置の製
造歩留りを向上することができ、結果的に低コス
トで市場に提供できる。また、第２ゲート配線形
成工程の分工程増となるが、コストは歩留り向上
で充分カバーできる。さらに欠陥が少ないことと
共に開孔率が低下しないので明るい良質の表示を
得ることができる。
As described above, it is possible to improve the manufacturing yield of an active matrix display device in which a large number of unit pixels are basically arranged in a matrix, and as a result, it can be provided on the market at low cost. Further, although the second gate wiring forming step increases the number of steps, the cost can be sufficiently covered by the improved yield. Furthermore, since there are fewer defects and the aperture ratio does not decrease, a bright, high-quality display can be obtained.
以上、ａ−Si膜を用いたTFTを例に述べてき
たが、ｐ−Si場合によればビームアニール等で形
成した単結晶Si薄膜や他の半導体材料による
TFTを用いたアクテイブマトリクス表示装置用
基板に本発明は適用でき、その工業的価値は高
い。 Above, we have described TFT using an a-Si film as an example, but in the case of p-Si, it is possible to use a single-crystal Si thin film formed by beam annealing or other semiconductor materials.
The present invention can be applied to a substrate for an active matrix display device using TFT, and its industrial value is high.
第１図ａ及びｂは本発明による単位画素構造例
であり、第１図ｂは第１図ａの平面図のＡ−Ｂ，
Ｂ−Ｃに沿つた断面図である。第２図ａ及びｂ
は、従来の構造例の平面図及び断面図であり、第
２図ｃは従来構造の断面例である。第３図乃至第
５図は、本発明による実施例のそれぞれの断面図
である。
１……基板、２，２′……ゲート電極配線、３
……ゲート絶縁膜、４……半導体薄膜、５……ド
レイン電極、６……ソース電極、７……画素電
極、８……共通電極、１２，１２′……第１ゲー
ト配線、２２，２２′……第２ゲート配線。
FIGS. 1a and 1b are examples of unit pixel structures according to the present invention, and FIG. 1b is a plan view of FIG.
It is a sectional view along BC. Figure 2 a and b
2 are a plan view and a cross-sectional view of a conventional structure, and FIG. 2c is a cross-sectional view of the conventional structure. 3 to 5 are respective cross-sectional views of embodiments according to the present invention. 1...Substrate, 2, 2'...Gate electrode wiring, 3
... Gate insulating film, 4 ... Semiconductor thin film, 5 ... Drain electrode, 6 ... Source electrode, 7 ... Pixel electrode, 8 ... Common electrode, 12, 12' ... First gate wiring, 22, 22 '...Second gate wiring.
Claims (1)
の透明導電膜からなる画素電極と、電荷保持容量
とを少なくとも具備する単位画素を有するアクテ
イブマトリクス表示装置用基板において、 前記薄膜トランジスタのゲート電極配線が行配
線として延在し、 該行配線は、遮光性を有する導電膜である第１
ゲート配線と透明導電膜から成る第２ゲート配線
とが積層配設された少なくとも２つのゲート配線
からなり、該積層配設された第１ゲート配線と第
２ゲート配線の少なくとも複数の単位画素部分は
面接触して電気的に導通して積層配設されてお
り、 前記電荷保持容量が画素電極と隣接する他行の
第２ゲート配線の一部と、ゲート絶縁膜を一部に
含む絶縁膜とによつて構成されたことを特徴とす
るアクテイブマトリクス表示装置用基板。[Claims] 1. A thin film transistor on a transparent insulating substrate;
In a substrate for an active matrix display device having a unit pixel including at least a pixel electrode made of a transparent conductive film and a charge storage capacitor, the gate electrode wiring of the thin film transistor extends as a row wiring, and the row wiring is light-shielded. The first conductive film has
It consists of at least two gate wirings in which a gate wiring and a second gate wiring made of a transparent conductive film are arranged in a stacked manner, and at least a plurality of unit pixel portions of the first gate wiring and the second gate wiring arranged in a stacked manner are The charge storage capacitor is arranged in a stacked manner in surface contact and electrically conductive, and the charge retention capacitor is connected to a part of the second gate wiring in the other row adjacent to the pixel electrode and an insulating film partially including the gate insulating film. A substrate for an active matrix display device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15255684A JPS6129820A (en) | 1984-07-23 | 1984-07-23 | Substrate for active matrix display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15255684A JPS6129820A (en) | 1984-07-23 | 1984-07-23 | Substrate for active matrix display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6129820A JPS6129820A (en) | 1986-02-10 |
| JPH0431376B2 true JPH0431376B2 (en) | 1992-05-26 |
Family
ID=15543050
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15255684A Granted JPS6129820A (en) | 1984-07-23 | 1984-07-23 | Substrate for active matrix display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6129820A (en) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0685440B2 (en) * | 1986-04-10 | 1994-10-26 | アルプス電気株式会社 | Thin film transistor |
| JPS639977A (en) * | 1986-07-01 | 1988-01-16 | Citizen Watch Co Ltd | Thin-film transistor |
| JP2620240B2 (en) * | 1987-06-10 | 1997-06-11 | 株式会社日立製作所 | Liquid crystal display |
| JP2620241B2 (en) * | 1987-06-10 | 1997-06-11 | 株式会社日立製作所 | Liquid crystal display |
| JP2668935B2 (en) * | 1988-05-10 | 1997-10-27 | 松下電器産業株式会社 | Semiconductor device for matrix image display device and manufacturing method thereof |
| JPH0833554B2 (en) * | 1988-05-10 | 1996-03-29 | 松下電器産業株式会社 | Semiconductor for image display device and manufacturing method thereof |
| JPH02250038A (en) * | 1989-03-23 | 1990-10-05 | Seiko Instr Inc | Thin film transistor array |
| JPH0820641B2 (en) * | 1989-06-30 | 1996-03-04 | シャープ株式会社 | Liquid crystal display manufacturing method |
| US5162901A (en) * | 1989-05-26 | 1992-11-10 | Sharp Kabushiki Kaisha | Active-matrix display device with added capacitance electrode wire and secondary wire connected thereto |
| JP2711015B2 (en) * | 1990-07-25 | 1998-02-10 | 三菱電機株式会社 | Matrix type display device |
| JP3258768B2 (en) * | 1993-06-22 | 2002-02-18 | 三菱電機株式会社 | Matrix display device |
| JP2002055360A (en) | 2000-08-11 | 2002-02-20 | Nec Corp | Liquid crystal display device and method of manufacture thereof |
| US8836879B2 (en) * | 2010-06-10 | 2014-09-16 | Apple Inc. | Displays with minimized curtain mura |
| JP5955920B2 (en) * | 2014-10-28 | 2016-07-20 | 株式会社半導体エネルギー研究所 | Semiconductor device |
-
1984
- 1984-07-23 JP JP15255684A patent/JPS6129820A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6129820A (en) | 1986-02-10 |
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| EXPY | Cancellation because of completion of term |