JP3104356B2 - Thin film transistor panel and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor panel (hereinafter, referred to as a TFT panel) used for an active matrix liquid crystal display device and a method of manufacturing the same.

[0002]

2. Description of the Related Art A thin film transistor panel used for an active matrix liquid crystal display device has the following structure.

FIG. 7 is a sectional view of a part of a conventional TFT panel. This TFT panel has a pixel electrode 2 and a thin film transistor (TFT) 3 as an active element formed on a transparent substrate 1 made of glass or the like.

The thin film transistor 3 generally has an inverted stagger structure. The thin film transistor 3 having the inverted stagger structure includes a gate electrode G formed on the substrate 1, a gate insulating film 4 covering the gate electrode G, an i-type semiconductor layer 5 formed on the gate insulating film 4, A source electrode S and a drain electrode D are formed on the i-type semiconductor layer 5 via an n-type semiconductor layer 6 and a contact layer 7.

The i-type semiconductor layer 5 is formed of a-Si (amorphous silicon), the n-type semiconductor layer 6 is formed of a-Si doped with an n-type impurity, and a contact layer 7 is formed.
Is C having good ohmic contact with the n-type semiconductor layer 6
The n-type semiconductor layer 6 and the contact layer 7 are formed of a metal such as r (chromium), and correspond to a channel region (a region between the source electrode S and the drain electrode D) of the i-type semiconductor layer 5. Are separated and separated.

The gate electrode G of the thin film transistor 3 is connected to a gate line (not shown) formed on the substrate 1.
The gate insulating film 4 is formed over substantially the entire surface of the substrate 1 so as to cover the gate electrode G and the gate line. The gate insulating film 4 is formed of SiN (silicon nitride) or the like, and a data line (not shown) connected to the drain electrode D is formed on the gate insulating film 4. The gate electrode G and the gate line and the drain electrode D and the data line are
It is formed of Al (aluminum) or an Al alloy.

On the channel region of the i-type semiconductor layer 4, a blocking layer 8 made of SiN or the like is formed. The blocking layer 8 is used to separate the channel region corresponding to the channel region of the n-type semiconductor layer 6 formed on the i-type semiconductor layer 5 by etching when the thin film transistor 3 is manufactured. It is formed to prevent it from being etched.

On the other hand, the pixel electrode 2 is formed on the gate insulating film (transparent film) 4, and its end is connected to the source electrode S of the thin film transistor 3. The pixel electrode 2 is formed of a transparent conductive film made of ITO or the like.
Between the source-side contact layer 7 and the source electrode S.

In FIG. 7, reference numeral 9 denotes a protective insulating film (transparent film) covering the surface of the TFT panel. This protective insulating film 9 is formed of SiN or the like. The terminal portion of the line is exposed by forming an opening in the protective insulating film 9 thereon, and the terminal portion of the gate line is formed by forming an opening in the gate insulating film 4 and the protective insulating film 9 thereon. Is exposed.

The above-mentioned TFT panel is manufactured by the following steps.

[Step 1] A metal film for a gate is formed on the substrate 1, and the metal film is patterned by photolithography to form a gate electrode G and a gate line.

[Step 2] A gate insulating film 4 is formed on the substrate 1 so as to cover the gate electrode G and the gate line.
An i-type semiconductor layer 5 and a blocking layer 8 are sequentially formed.

[Step 3] The blocking layer 8 is patterned by photolithography so as to cover the channel region of the i-type semiconductor layer 5.

[Step 4] An n-type semiconductor layer 6 and a contact layer 7 are sequentially formed.

[Step 5] The contact layer 7, the n-type semiconductor layer 6, and the i-type semiconductor layer 5 are patterned by photolithography so as to have an outer shape of a transistor element region.

[Step 6] A transparent conductive film is formed.

[Step 7] The transparent conductive film is patterned by photolithography to form a pixel electrode 2 whose end overlaps the source electrode formation region.

[Step 8] A source and drain metal film is formed.

[Step 9] The source and drain metal films are patterned by photolithography to form source and drain electrodes S and D and data lines, and the contact layer 7 is formed with the source and drain electrodes S and D Patterning in the same shape (however, pixel electrode 2
Of the n-type semiconductor layer 6 while leaving the metal film and the resist mask used for patterning the contact layer 7 remaining. The portion between D is etched to separate and separate the n-type semiconductor layer 6.

In this case, since the n-type semiconductor layer 6 is separated on the blocking layer 8 formed on the i-type semiconductor layer 4, when the n-type semiconductor layer 6 is etched, The channel region of layer 5 is not etched and damaged. However, since the n-type semiconductor layer 6 removes not only the portion between the source and drain electrodes S and D, but also the portions protruding outside the ends of the source and drain electrodes S and D and the pixel electrode, this portion is removed. In this case, the i-type semiconductor layer 5 is also etched, but since this portion does not affect the characteristics of the thin film transistor 3, even if the surface of the i-type semiconductor layer 5 is etched in this portion,
Alternatively, there is no particular problem even if the i-type semiconductor layer 5 is removed.

[Step 10] Thereafter, a protective insulating film 9 is formed, and openings are formed by photolithography in portions of the protective insulating film 9 on the data line terminal portion and the gate line terminal portion. At the same time, an opening is formed in a portion of the gate insulating film 4 above the gate line terminal to expose the data line terminal and the gate line terminal,
Complete the TFT panel.

[0022]

However, in the above-described conventional TFT panel, a blocking layer 8 made of an insulating material (such as SiN) similar to the gate insulating film 4 is provided on the channel region of the i-type semiconductor layer 5. Therefore, when the blocking layer 8 is patterned in the manufacturing process of the TFT panel, a defect such as a pinhole may be generated in the gate insulating film 4 below the i-type semiconductor layer 5 in some cases.

This is because a pinhole may be formed in the i-type semiconductor layer 5. Even if a pinhole is formed in the i-type semiconductor layer 5, the semiconductor characteristics do not change so much. If the layer 5 has a pinhole, when the blocking layer 8 formed on the i-type semiconductor layer 5 is patterned, the etching solution reaches the gate insulating film 4 through the pinhole of the i-type semiconductor layer 5. . And Si N
Since the patterning of the blocking layer 8 is performed using a hydrofluoric acid-based etchant such as BHF, when the etchant reaches the gate insulating film 4, the gate insulating film 4 is also etched to remove defects such as pinholes. Occurs.

If there is no defect in the i-type semiconductor layer 5,
Although the gate insulating film 4 is not etched during the patterning of the blocking layer 8, it is desirable to reduce the thickness of the i-type semiconductor layer 5 as much as possible in order to improve the characteristics of the thin film transistor. It is difficult to form the semiconductor layer 5.

Since the n-type semiconductor layer 6 and the source and drain electrodes S and D are formed after the blocking layer 8 is patterned as described above, the above-described pinholes are generated in the gate insulating film 4. In this case, an interlayer short circuit occurs between the gate electrode G and the source and drain electrodes S and D. This interlayer short-circuit also occurs at the intersection of the gate line and the data line.

For this reason, in the above-mentioned conventional TFT panel, interlayer short-circuits often occur during the manufacturing process, and the manufacturing yield is high.
However, there was a problem that the manufacturing process was poor .

An object of the present invention is to reduce the number of manufacturing steps.
Thin film transistor structure and resist mask
An object of the present invention is to provide a method for manufacturing a thin film transistor in which the number of forming steps is reduced .

[0028]

A TFT panel according to the present invention comprises a gate electrode, a gate insulating film and an i-type semiconductor on a substrate.
Layer, n-type semiconductor layer, contact layer, source and drain electrodes.
And a thin-film transistor
Pixel electrode consisting of a transparent conductive film connected to the source electrode of the
The thin film transistor panel forming the electrode, wherein
The pixel electrode is interposed between the n-type semiconductor layer and the source-side contact layer.
Having an end portion laminated on the i-type semiconductor layer,
The source electrode is formed to cover an end of the pixel electrode, and
The rain electrode is formed between the n-type semiconductor layer on the i-type semiconductor layer and the drain.
Between the contact side contact layer and the conductive film made of the transparent conductive film.
A source side and a drain formed on a stacked structure
Each contact layer on the side of the pixel electrode is connected to the end of the pixel electrode and
And the conductive film is formed in the same shape as the conductive film .

The method for producing a TFT panel of the present invention, group
A gate electrode, a gate insulating film, an i-type semiconductor layer, and n
Type semiconductor layer, contact layer, source and drain electrodes
Thin film transistor, and the thin film transistor
And a pixel electrode made of a transparent conductive film connected to the source electrode.
In the method of manufacturing the formed thin film transistor panel,
A first step of forming a gate metal film on a substrate and patterning the metal film to form a gate electrode; and contacting a gate insulating film, an i-type semiconductor layer, and an n-type semiconductor layer on the substrate. A second step of sequentially forming layers, a third step of patterning the contact layer, the n-type semiconductor layer, and the i-type semiconductor layer to the outer shape of the transistor element region;
A fourth step of forming a transparent conductive film over the gate insulating film by covering these layers; and a step of patterning the transparent conductive film to form a pixel electrode and a drain electrode formation region whose ends overlap the source electrode formation region. A fifth step of patterning the contact layer into the same shape as the end portion of the pixel electrode and the conductive layer, and a sixth step of forming a source / drain metal film. a step, a seventh step of patterning the source and drain metal film source, the shape of the drain electrode, the n-type semiconductor
Electrical separation between the source and drain electrodes of the layer
And an eighth step .

[0030]

In other words, the TFT panel of the present invention is one in which the n-type semiconductor layer of the thin-film transistor is electrically separated into a source side and a drain side by using a portion between the source and drain electrodes as an oxide insulating layer. Yes, this TFT
Since the panel does not separate the n-type semiconductor layer by etching, the channel region of the i-type semiconductor layer is not damaged even if the blocking layer is not provided on the i-type semiconductor layer. . Moreover, this TFT
In the panel, a conductive layer made of the same transparent conductive film as a pixel electrode formed with an end portion interposed between the source electrode and the source-side contact layer thereunder is formed by forming the drain electrode and the drain-side contact layer thereunder. Also provided between
Since the source-side and drain-side contact layers are formed in the same shape as the end portion of the pixel electrode and the conductive layer, respectively, the pixel electrode and the contact layer are patterned in the same step in manufacturing the same. Can be.

Further, the manufacturing method of the present invention is to manufacture a TFT panel by the above-described steps. In particular, the transparent conductive film is patterned to form a pixel electrode and a drain electrode whose ends overlap the source electrode formation region. When forming the conductive layer provided in the formation region, the contact layer is patterned into the same shape as the end of the pixel electrode and the conductive layer, and the resist mask used for patterning the source and drain metal films is used. Since the n-type semiconductor layer is oxidized while leaving it, and the portion between the source and drain electrodes of the n-type semiconductor layer is used as an oxide insulating layer, the TFT panel can be manufactured with a small number of resist mask formations.

[0032]

An embodiment of the present invention will be described below with reference to the drawings.

First, the structure of the TFT panel will be described. FIG. 4 is a plan view of a part of the TFT panel, and FIGS. 1, 2 and 3 are enlarged sectional views taken along lines II, II-II and III-III in FIG.

This TFT panel has a pixel electrode 12a and a thin film transistor (TFT) 13 as an active element formed on a transparent substrate 10 made of glass or the like.

As shown in FIGS. 1 and 4, the thin film transistor 13 has a gate electrode G formed on a substrate 10.
And a gate insulating film 14 covering the gate electrode G, and an i-type semiconductor layer 15 formed on the gate insulating film 14.
And a source electrode S and a drain electrode D formed on the i-type semiconductor layer 15 via the n-type semiconductor layer 16 and the contact layer 17.

The i-type semiconductor layer 15 is made of a-Si, and the n-type semiconductor layer 16 is made of a-type doped with n-type impurities.
The contact layer 17 is formed of a metal such as Cr.

The gate electrode G of the thin film transistor 13 is formed integrally with a gate line GL formed on the substrate 10, and the gate insulating film 14 is
And over substantially the entire surface of the substrate 10 covering the gate line GL. The gate insulating film 14 is formed of SiN or the like, and a data line DL connected to the drain electrode D is formed on the gate insulating film 14. The gate electrode G and the gate line GL are formed of a gate metal film 11 such as Al or Al alloy. The source and drain electrodes S and D and the data line DL are formed of a source and drain metal such as Al or Al alloy. The film 18 is formed.

On the other hand, the pixel electrode 12a is provided on the gate insulating film (transparent film) 14. The pixel electrode 12a is formed of a transparent conductive film 12 made of ITO or the like. The pixel electrode 12a is formed with its end portion interposed between the source side contact layer 17 of the thin film transistor 13 and the source electrode S. By doing so, it is connected to the source electrode S. Note that this pixel electrode 12a
Is formed in an area smaller than the source electrode S, and the source electrode S is in direct contact with the n-type semiconductor layer 16 in a portion where the pixel electrode end is not interposed.

A conductive layer 12b made of the same transparent conductive film (ITO film or the like) 12 as the pixel electrode 12a is provided between the drain electrode D of the thin film transistor 13 and the drain contact layer 17 thereunder. The source-side and drain-side contact layers 17 are formed in the same shape as the end of the pixel electrode 12a and the conductive layer 12b, respectively. The conductive layer 12b
And the drain-side contact layer 17 has a drain electrode D
The drain electrode D is formed in a smaller area and is entirely covered with the drain electrode D. The drain electrode D is in direct contact with the n-type semiconductor layer 16 in a portion where the conductive layer 12b is not interposed.

Further, the n-type semiconductor layer 16 of the thin-film transistor 13 is formed over the entire area of the i-type semiconductor layer 15, and the portion between the source and drain electrodes S and D of the n-type semiconductor layer 16 is This portion is oxidized over the entire thickness to form an oxide insulating layer 16a. That is, the n-type semiconductor layer 16 has its source,
By providing a portion between the drain electrodes S and D as an oxide insulating layer 16a, the source and drain sides are electrically separated.

In the TFT panel of this embodiment, a protective insulating film (transparent film) 19 made of SiN or the like is provided on the surface, and the terminal portion DLa of the data line DL is
As shown in FIGS. 2 and 4, the protective insulating film 19 thereon is formed.
Is formed by forming an opening 19a.

Also, the terminal portion GLa of the gate line GL
Has a two-layer structure as shown in FIGS. 3 and 4, the lower layer film of which is formed of the gate metal film 11,
The upper layer film is formed of the source / drain metal film 18. The upper film (metal film for source and drain) 18 is filled in the opening 14 a provided in the gate insulating film 14 and is laminated on the lower film (metal film for gate) 11. Then, this gate line terminal portion GLa
Are exposed by forming an opening 19b in the protective insulating film 19 thereon.

That is, in the TFT panel, the n-type semiconductor layer 16 of the thin film transistor 13 is electrically connected to the source side and the drain side by using the oxide insulating layer 16a between the source and drain electrodes S and D. Since the TFT panel is not separated by etching and separating the n-type semiconductor layer unlike the conventional TFT panel, a blocking layer is provided on the channel region of the i-type semiconductor layer 15. Even if it does not, the channel region of the i-type semiconductor layer 15 is not damaged when the n-type semiconductor layer 16 is separated.

In the TFT panel, since it is not necessary to provide a blocking layer on the i-type semiconductor layer 15 of the thin film transistor 13, a pin is formed on the gate insulating film 14 at the time of patterning the blocking layer as in the conventional TFT panel. No defects such as holes are generated. Therefore, an interlayer short-circuit between the gate electrode G and the source / drain electrodes S and D and an interlayer short-circuit at the intersection between the gate line GL and the data line DL are generated. To prevent
The production yield can be improved.

Further, in the above-mentioned TFT panel, the conductive layer 12b made of the same transparent conductive film as the pixel electrode 12a formed with an end portion interposed between the source electrode S and the source side contact layer 17 thereunder is formed. The drain electrode D
And the drain-side contact layer 17 thereunder, so that the source-side and drain-side contact layers 17 are connected to the end of the pixel electrode 12a and the conductive layer 1 at the drain electrode D portion.
2b, the pixel electrode 12a and the contact layer 17 can be patterned in the same step at the time of manufacture.

Next, a method of manufacturing the TFT panel will be described.

FIG. 5 and FIG. 6 are manufacturing process diagrams of the TFT panel. 5 (a) to 5 (d) and FIG. 6 (e)
(H) respectively show the cross section of the thin film transistor portion, the data line terminal portion, and the data line terminal portion of the TFT panel.

[Step 1] First, as shown in FIG. 5A, a gate electrode G is formed on a transparent substrate 10 made of glass or the like.
And a gate line GL (see FIG. 4). The gate electrode G and the gate line GL are formed by forming a gate metal film 11 on the substrate 10 and patterning the metal film 11 by photolithography. The metal film 11 shown at the right end in FIG.
Is a lower layer film of the gate line terminal portion GLa.

[Step 2] Next, as shown in FIG. 5A, a gate insulating film 14 and an i-type semiconductor layer are formed on the substrate 10 so as to cover the gate electrode G and the gate line GL. 15, n-type semiconductor layer 16, and contact layer 17
Are sequentially formed.

[Step 3] Next, as shown in FIG. 5B, the contact layer 17, the n-type semiconductor layer 16 and the i-type semiconductor layer 15 are formed by photolithography on the outer shape of the transistor element region. Perform patterning.

[Step 4] Next, as shown in FIG. 5C, a transparent conductive film 1 such as an ITO film is formed on the gate insulating film 14 so as to cover the patterned layers 17, 16 and 15.
2 is formed.

[Step 5] Next, as shown in FIG. 5D, the transparent conductive film 12 is patterned by the photolithography method, and the pixel electrode 12a and the drain electrode formation region whose ends overlap the source electrode formation region. Conductive layer 1 provided on
2b, and the contact layer 17 is patterned into the same shape as the end of the pixel electrode 12a and the conductive layer 12b. The pixel electrode 12a
And the source side contact layer 17 thereunder are patterned into an area smaller than the source electrode formation region, and the conductive layer 12b and the drain side contact layer 1 therebelow are patterned.
7 is patterned to have an area smaller than the drain electrode forming region and completely within the region.

[Step 6] Next, as shown in FIG. 5D, a gate line terminal portion GL is formed on the gate insulating film 14.
opening 1 for exposing lower layer film (metal film for gate) 11
4a is formed by photolithography.

[Step 7] Next, as shown in FIG. 6E, a source / drain metal film 18 is formed on the gate insulating film 14 so as to cover the patterned transparent conductive film 12 and the like. At this time, the source and drain metal films 18 are
The opening 14a formed in the gate insulating film 14 is also filled.

[Step 8] Next, as shown in FIG. 6F, the source and drain metal films 18 are patterned by photolithography to form source and drain electrodes S and D and data lines DL (FIG. 4) and an upper layer film of the gate line terminal portion GLa. Note that the source and drain electrodes S and D are formed in an area covering the end of the pixel electrode 12a and the conductive layer 12b. In FIG. 6F, DLa is a terminal portion of the data line DL, and the data line terminal portion DLa is formed only of the source / drain metal film 18.

[Step 9] Next, as shown in FIG. 6F, the oxidation of the n-type semiconductor layer 16 is performed while the resist mask 20 used for patterning the source and drain metal films 18 is left. A portion between the source and drain electrodes S and D is subjected to a treatment to form an oxide insulating layer 16a oxidized over the entire thickness, and the oxide insulating layer 16a causes the n-type semiconductor layer 16 to be electrically connected to the source side and the drain side. Then, the thin film transistor 13 is completed.

The oxidation of the n-type semiconductor layer 15 is performed, for example, by anodic oxidation.
Is immersed in the electrolytic solution so that the n-type semiconductor layer 16 faces the counter electrode (platinum electrode) in the electrolytic solution.
6 is used as an anode, and a counter electrode is used as a cathode, and a voltage is applied between the two electrodes. As described above, when a voltage is applied between the n-type semiconductor layer 16 and the counter electrode in the electrolytic solution, a region (a region in contact with the electrolytic solution) of the n-type semiconductor layer 16 which is an anode, which is not covered with the resist mask 20, is formed. An anodization is caused by a chemical reaction, and the oxidized region of the n-type semiconductor layer 16 becomes an oxide insulating layer 16a.

In this case, the n-type semiconductor layer 16 is oxidized from its surface side, but the oxidation depth is mainly determined by the applied voltage. By setting the voltage, the oxidized region of the n-type semiconductor layer 16 can be oxidized over its entire thickness.

The current supply to the n-type semiconductor layer 16 in the anodic oxidation can be performed through the data line DL through the drain electrode D using the data line DL as a current path. The n-type semiconductor layers 16 of all the formed thin film transistors 13 can be uniformly anodized.

In this case, since the side surfaces of the drain electrode D and the data line DL are not covered with the resist mask 20, the side surfaces of the drain electrode D and the data line DL are also anodized. DL only has an oxide insulating layer on its side,
The central part is not oxidized.

The conductive layer 12b under the drain electrode D
Is exposed outside the drain electrode D, a current flows between the exposed portion of the conductive layer 12b and the counter electrode (the conductive layer 12b is an oxide such as ITO and does not cause a chemical reaction. Therefore, the current continues to flow between the exposed portion of the conductive layer 12b and the counter electrode), and almost no current flows through the n-type semiconductor layer 16, so that the n-type semiconductor layer 16
However, as described above, if the drain electrode D is formed in an area covering the conductive layer 12b, a current flows between the n-type semiconductor layer 16 and the counter electrode, and n The type semiconductor layer 16 can be anodized.

The resistivity of the i-type semiconductor layer 15 (resistivity when no gate voltage is applied to the gate electrode G) is three orders of magnitude greater than the resistivity of the n-type semiconductor layer 16. When anodizing the n-type semiconductor layer 16, the i-type semiconductor layer 15 thereunder is not oxidized.

[Step 10] Next, the resist mask 2
Then, the protective insulating film 19 is formed as shown in FIG.

[Step 11] Next, as shown in FIG. 6H, the protective insulating film 18 is patterned by photolithography to form openings 19 a on the data line terminal portion DLa and the gate line terminal portion GLa. , 19b, and exposing these terminal portions DLa, GLa to form a TFT.
Complete the panel.

According to the above-described method for manufacturing a TFT panel, when the transparent conductive film 12 is patterned to form the pixel electrode 12a whose end overlaps the source electrode formation region and the conductive layer 12b provided in the drain electrode formation region, Contact layer 1
7 is an end of the pixel electrode 12a and the conductive layer 12b.
The n-type semiconductor layer 16 is oxidized while leaving the resist mask 20 used for patterning the source / drain metal film 18 to form the source / drain of the n-type semiconductor layer 16. Electrodes S, D
Since the portion between them is the oxide insulating layer 16a, the TFT panel can be manufactured with a small number of times of forming the resist mask.

That is, the number of times of forming a resist mask when a TFT panel is manufactured by the above manufacturing method is as follows: (1) When patterning the gate metal film 11 (2) The contact layer 17, the n-type semiconductor layer 16 and the i-type semiconductor (3) When patterning the transparent conductive film 12 and the contact layer 16 thereunder (4) When forming the opening 14a in the gate insulating film 14 (5) Metal for source and drain At the time of patterning of the film 18 and the anodic oxidation of the n-type semiconductor layer 16 (6) The number of times of forming the openings 19a and 19b in the protective insulating film 19 may be six times in total.

Therefore, according to the above manufacturing method, the TFT panel can be manufactured with high efficiency and low cost with a small number of times of forming a resist mask.

In the above embodiment, the gate line GL
The terminal portion GLa of the gate metal film 11 as a lower layer film,
Although the source / drain metal film 18 has a two-layer structure in which the upper film is used, the terminal portion GLa of the gate line GL may be formed only by the gate metal film 11. In that case,
The opening 14a provided in the gate insulating film 14 is
Since the openings 19a and 19b can be formed at the same time as the formation of the openings 19a and 19b, [Step 6] in the above embodiment becomes unnecessary, so that the number of times of forming the resist mask can be further reduced by one.

In the above embodiment, the n-type semiconductor layer 16
The portion between the source and drain electrodes S and D of the n-type semiconductor layer 16 is oxidized by an oxidation treatment that causes a chemical reaction in the electrolytic solution. Plasma oxidation.

[0070]

According to the TFT panel of the present invention, the n-type semiconductor layer of the thin film transistor is electrically separated into a source side and a drain side by using a portion between the source and drain electrodes as an oxide insulating layer. Since this TFT panel does not separate the n-type semiconductor layer by etching, the channel region of the i-type semiconductor layer may be damaged without providing a blocking layer on the i-type semiconductor layer. I will not give. In addition, in this TFT panel, a conductive layer made of the same transparent conductive film as a pixel electrode formed with an end portion interposed between the source electrode and the source-side contact layer therebelow is provided between the drain electrode and the underlying layer. Also provided between the drain-side contact layer, the source-side and drain-side contact layers are formed in the same shape as the end of the pixel electrode and the conductive layer, respectively. The electrode and the contact layer can be patterned in the same step.

Further, in the manufacturing method of the present invention, when the transparent conductive film is patterned to form a pixel electrode whose end overlaps with the source electrode formation region and a conductive layer provided in the drain electrode formation region, the contact layer is formed as described above. This n-type semiconductor layer is patterned by patterning it into the same shape as the end portion of the pixel electrode and the conductive layer, and oxidizing the n-type semiconductor layer while leaving the resist mask used for patterning the source and drain metal films. Since the portion between the source and drain electrodes of the layer is an oxide insulating layer, the TFT panel can be manufactured with a small number of times of forming a resist mask.

[Brief description of the drawings]

FIG. 1 is an enlarged sectional view taken along line II of FIG.

FIG. 2 is an enlarged sectional view taken along line II-II of FIG.

FIG. 3 is an enlarged sectional view taken along the line III-III of FIG. 4;

FIG. 4 is a plan view of a part of a TFT panel showing one embodiment of the present invention.

FIG. 5 is a first-half manufacturing process diagram showing a method for manufacturing a TFT panel.

FIG. 6 is a manufacturing process diagram of the latter half showing a method of manufacturing a TFT panel.

FIG. 7 is a cross-sectional view of a part of a conventional TFT panel.

[Explanation of symbols]

10: substrate, 11: metal film for gate, G: gate electrode,
GL: gate line, GLa: terminal portion, 12: transparent conductive film, 12a: pixel electrode, 12b: conductive layer, 13: thin film transistor, 14: gate insulating film, 15: i-type semiconductor layer, 16: n-type semiconductor layer, 16a: oxide insulating layer, 17:
Contact layer, 18 ... metal film for source and drain, S ...
Source electrode, D: drain electrode, DL: data line,
DLa: terminal portion, 19: protective insulating film, 20: resist mask.

Continuation of the front page (56) References JP-A-61-51188 (JP, A) JP-A-1-265233 (JP, A) JP-A-2-27771 (JP, A) JP-A-1-219722 (JP) JP-A-64-49272 (JP, A) JP-A-2-21663 (JP, A) JP-A-2-224254 (JP, A) JP-A-63-168460 (JP-A-2-89433) (JP, U) (58) Field of investigation (Int. Cl. ⁷ , DB name) G02F 1/136 G02F 1/1343

Claims (2)

(57) [Claims] A gate electrode, a gate insulating film and an i.
A thin film transistor including a semiconductor layer, an n-type semiconductor layer, a contact layer, and source and drain electrodes; and a transparent conductive film connected to a source electrode of the thin film transistor.
In the thin film transistor panel formed with a pixel electrode, the pixel electrode includes an n-type semiconductor layer and a source-side contact layer.
And an end portion stacked on the i-type semiconductor layer via the first electrode layer, and the source electrode is formed to cover an end portion of the pixel electrode.
And the drain electrode is connected to an n-type semiconductor layer on the i-type semiconductor layer.
Conductivity comprising the drain-side contact layer and the transparent conductive film
The contact layer on the source side and the drain side is formed on a laminated structure with a film.
Each having the same shape as the end portion of the pixel electrode and the conductive film.
A thin film transistor panel characterized by being formed . A gate electrode, a gate insulating film and an i.
A thin film transistor including a semiconductor layer, an n-type semiconductor layer, a contact layer, and source and drain electrodes; and a transparent conductive film connected to a source electrode of the thin film transistor.
That the method of manufacturing a thin film transistor panel forming the pixel electrode, forming a gate metal film on a substrate, a first step of forming a gate electrode by patterning this metal film, on the substrate, the gate A second step of sequentially forming an insulating film, an i-type semiconductor layer, an n-type semiconductor layer, and a contact layer; and forming the contact layer, the n-type semiconductor layer, and the i-type semiconductor layer,
A third step of patterning the outer shape of the transistor element region, a fourth step of forming a transparent conductive film on the gate insulating film covering these layers, and an end portion of the transparent conductive film by patterning the transparent conductive film. Forming a pixel electrode overlapping the source electrode formation region and a conductive layer provided in the drain electrode formation region, and patterning the contact layer into the same shape as the end portion of the pixel electrode and the conductive layer; A sixth step of forming a source / drain metal film; a seventh step of patterning the source / drain metal film into the shape of a source / drain electrode; and a source / drain electrode of the n-type semiconductor layer. The part between
8. A method for manufacturing a thin film transistor panel, comprising: an eighth step of gaseous separation .