JPH0990406A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device lowered in source resistance and drain resistance without increasing photolithography stages. SOLUTION: Gate electrodes 2, gate insulating films 3, semiconductor layers 4 and semiconductor protective layers 5 are formed on a glass substrate 1. An n<+> Type low resistance semiconductor layers 6a, 6b consisting of amorphous silicon heavily doped with phosphorus are formed on both sides of the semiconductor protective layers 5. Molybdenum layers 7, ITO layers 8 and molybdenum layers 9 are laminated and formed. Display pixel electrodes 8c connected to the source electrodes 10a of the ITO layers 8 are formed and drain electrodes 10b are formed. A protective film 12 is formed on the surface, by which a matrix array substrate 13 is formed. The matrix array substrate 13 and a counter substrate 24 are stuck and liquid crystals 35 are sealed and held therebetween. Even if oxidized films are formed on the molybdenum layers 9 at the time of forming the ITO layers 8 on the molybdenum layers 9, the molybdenum layers have electrical conductivity and, therefore, the characteristics of the TRs do not degrade.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device having reduced source resistance and drain resistance.

[0002]

2. Description of the Related Art As a conventional liquid crystal display device, a structure described in, for example, Japanese Patent Laid-Open No. 6-43487 is known. The configuration disclosed in Japanese Patent Laid-Open No. 6-43487 is as follows.
A gate electrode of the first conductive film is formed on the insulating substrate,
A gate insulating film is formed so as to cover the gate electrode,
A low resistance semiconductor layer is formed on the gate insulating film, and a titanium (Ti) layer and ITO are formed on the low resistance semiconductor layer.
A metal film is formed via a transparent oxide conductive film of (Indium Tin Oxide) to form a source electrode and a drain electrode.

[0003]

However, since the titanium layer is interposed between the low resistance semiconductor layer and the transparent oxide conductive film, the transparent oxide conductive film is formed on the titanium layer by the sputtering method. When forming a film, since a mixed gas of an inert gas and oxygen (O ₂ ) is used as a sputtering gas, the titanium layer is oxidized. Further, since the oxide of titanium is an insulator, the source and drain resistances increase in the titanium layer, and the characteristics of the thin film transistor deteriorate.

Then, ITO which is a transparent oxide conductive film
The oxidation of the titanium layer during the film formation is more remarkable as the amount of O ₂ introduced during the film formation is larger, and is more remarkable as the film formation temperature is higher. Therefore, in order to suppress the oxidation of the titanium layer, it is necessary to reduce the amount of O ₂ introduced during the film formation of ITO, which is the translucent oxide conductive film, or to lower the film formation temperature.

However, if the amount of O ₂ introduced is reduced,
Due to the lack of O atoms in ITO, which is a translucent oxide conductive film, the light transmittance is reduced and the O ₂ concentration in the target is also reduced, so that the life of the target is shortened. Furthermore, when the film of ITO, which is a translucent oxide conductive film, is formed at a low temperature, the film quality deteriorates.
Compared with the case of film formation at 00 ° C., the resistance value at room temperature film formation is about 5 times higher, and there is a problem in etching that the etching rate becomes faster and the uniformity becomes worse.

The present invention has been made in view of the above problems, and an object thereof is to provide a liquid crystal display device in which the source resistance and the drain resistance are reduced without increasing the photolithography process.

[0007]

According to the present invention, a gate electrode of a first conductive film formed on an insulating substrate, a gate insulating film covering the gate electrode, and a gate insulating film formed on the gate insulating film are formed. A semiconductor layer, a second conductive film which is conductive even if at least a part thereof is oxidized and is formed above the semiconductor layer, and a drain which is connected to the second conductive film and includes a transparent oxide conductive film. An array substrate having a thin film transistor having an electrode and a source electrode integrally formed with a display pixel electrode, a counter substrate provided so as to face the array substrate, and a liquid crystal disposed between the array substrate and the counter substrate. And the second conductive film interposed between the semiconductor layer and the transparent oxide conductive film is formed of a material having conductivity even when oxidized, and therefore, the transparent oxide conductive film is formed. Second when the film is formed It prevents the conductive film insulating layer on the second conductive film between the semiconductor layer and the conductive transparent oxide film be oxidized to form the source resistance and the drain resistance is lowered.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the liquid crystal display device of the present invention will be described below with reference to the drawings.

As shown in FIG. 1, molybdenum / tantalum (Mo) is formed on one main surface of a glass substrate 1 as an insulating substrate.
A gate electrode 2 which is a first conductive film of -Ta) is formed, and the gate electrode 2 is formed integrally with a gate wiring (not shown), and a gate line lead portion for connection with an external circuit is formed on the gate wiring. Are formed.

A gate insulating film 3 of amorphous silicon oxide is formed on the glass substrate 1 so as to cover the gate electrode 2, and a semiconductor such as amorphous silicon is formed on the gate insulating film 3 near the gate electrode 2. Layer 4 has been formed. Further, the semiconductor layer 4 above the gate electrode 2
A semiconductor protective layer 5 of amorphous silicon nitride is formed on the top.

On both sides of the semiconductor protective layer 5 of the semiconductor layer 4, an n ⁺ type low resistance semiconductor layer 6 made of amorphous silicon or the like heavily doped with phosphorus (P) atoms and the like, and a second conductive film are formed. Molybdenum (Mo) molybdenum layer 7, ITO (Indium) as a transparent oxide conductive film
A tin oxide (ITO) layer 8 and a molybdenum layer 9 as a third conductive film are laminated. Also, n ⁺
-Type low resistance semiconductor layer 6a forms a source contact region, n ⁺ -type low resistance semiconductor layer 6b forms a drain contact region, and molybdenum layer 7 on one end side of semiconductor protective layer 5 is formed.
Source electrode 1 with a, ITO layer 8a and molybdenum layer 9a
0a is formed, the drain electrode 10b is formed by the molybdenum layer 7b, the ITO layer 8b, and the molybdenum layer 9b on the other end side of the semiconductor protective layer 5, and the thin film transistor is formed in a matrix.
11 are formed. A signal line (not shown) is integrally formed with the drain electrode 10b.

A display pixel electrode 8c is formed continuously with the source electrode 10a of the ITO layer 8. The display pixel electrode 8c is arranged in a matrix corresponding to the thin film transistor 11.

Further, a protective film 12 of silicon nitride or the like is formed on these surfaces, and a matrix array substrate 13 is formed.

On the other hand, on a glass substrate 21 as an insulating substrate, a color filter 22 on which a black matrix (not shown) is formed and a counter electrode 23 of ITO are laminated, and a counter substrate 24 is formed.

Polyimide films 31 and 32 are formed on the surfaces of the matrix array substrate 13 and the counter substrate 24, which face each other.
Is provided, and polarizing plates 33 and 34 are attached to the opposite surface.

Further, the matrix array substrate 13 and the counter substrate 24 are adhered to each other, and these matrix array substrate 13
A liquid crystal 35 is enclosed and sandwiched between the counter substrate 24 and the counter substrate 24.

Next, the manufacturing process of the above embodiment will be described.

First, as shown in FIG. 2, a first conductive film of molybdenum / tantalum having a thickness of 1000 to 3000 angstrom is formed on one main surface of the glass substrate 1, and a gate electrode 2 and a gate electrode 2 are formed by a photolithography process. A gate wiring (not shown) is formed. Then, a gate insulating film 3 of amorphous silicon oxide having a thickness of 2000 to 4000 angstroms and a thickness of 200 to 200 Å is formed by a plasma CVD method or the like so as to cover the gate electrode 2 and the gate wiring.
A semiconductor layer 4 of amorphous silicon having a thickness of 3000 angstroms and a semiconductor protective film 5 of amorphous silicon nitride having a thickness of 1000 to 3000 angstroms are sequentially formed. Then, the semiconductor protective layer 5 other than on the semiconductor layer 4 serving as a channel above the gate electrode 2 is removed by a photolithography process. Further, an n ⁺ type low resistance semiconductor layer 6 of amorphous silicon which is heavily doped with P atoms or the like having a thickness of 200 to 700 Å is formed.

Further, as shown in FIG. 3, a film thickness of 100 to 1 is formed on the n ⁺ type low resistance semiconductor layer 6 by the sputtering method.
A molybdenum layer 7 of 000 angstrom is formed.

Further, as shown in FIG. 4, the molybdenum layer 7 to the semiconductor layer 4 in the formation region of the thin film transistor 11 are formed in an island shape by a photolithography process, and a gate line lead-out portion for connection with an external circuit is also formed. .

Further, as shown in FIG. 5, an IT having a thickness of 300 to 1500 angstrom is formed by the sputtering method.
The O layer 8 is formed. Here, since the mixed gas of argon (Ar) and oxygen (O ₂ ) is used as the sputtering gas, the molybdenum layer 7 is oxidized from the portion in contact with the ITO layer 8 which is the surface of the molybdenum layer 7. Since the oxide has conductivity, the contact resistance with the ITO layer 8 is low,
Form a good ohmic contact. That is, the contact characteristics between molybdenum (Mo) of the molybdenum layer 7 and n ⁺ -a-Si of the n ⁺ type low resistance semiconductor layer 6 exhibit good ohmic property,
Does not affect the transistor characteristics. Next, IT
A molybdenum layer 9 having a thickness of 2000 to 4000 angstrom is formed on the O layer 8.

Further, as shown in FIG. 6, the ITO layers 8a and 8b and the molybdenum layer 9 are formed by a photolithography process.
a and 9b are formed, the molybdenum layers 7a and 7b are etched by using the ITO layers 8a and 8b and the molybdenum layers 9a and 9b as masks to form the source electrode 10a, the drain electrode 10b and the display pixel electrode 8c, and further by etching. The n ⁺ type low resistance semiconductor layers 6a and 6b are formed separately.

Further, as shown in FIG. 7, the display pixel electrode 8c
The upper molybdenum layer 7 is removed by a photolithography process. The molybdenum layer 7 on the display pixel electrode 8c is removed by forming the protective film 12 shown in FIG.
May be removed as a mask.

Then, as shown in FIG. 1, a protective film 12 is formed to complete a matrix array substrate 13. Polyimide films 31 and 32 are formed on the opposed surfaces of the matrix array substrate 13 and the opposed substrate 24, and polarizing plates 33 and 34 are formed on the opposite surfaces,
The matrix array substrate 13 and the counter substrate 24 are attached to each other, and the liquid crystal is sandwiched between the matrix array substrate 13 and the counter substrate 24.
35 is enclosed and sandwiched to complete the liquid crystal display substrate.

According to the above embodiment, the molybdenum layer 7
Since not only the molybdenum of a and 7b but also the oxide of this molybdenum (MoO _x ) has conductivity, the ITO layers 8a and 8b
When molybdenum is formed on the molybdenum layers 7a and 7b, even if molybdenum is oxidized to form an oxide film, the source resistance and the drain resistance do not increase, and deterioration of transistor characteristics can be prevented. If the resistance value in the direction is 20 kΩ or less, the characteristics are not adversely affected. Even if the oxide film is formed in this way, the ITO film, which is a translucent oxide conductive film, can be formed without increasing the photolithography process as compared with the conventional case.
It is not necessary to change the film forming conditions for the layer 8.

Here, regarding the deterioration of the characteristics of the thin film transistor when the second conductive film such as the molybdenum layers 7a and 7b located between the n ⁺ type low resistance semiconductor layers 6a and 6b and the ITO layers 8a and 8b is oxidized. Will be described with reference to FIG. In addition,
Rx represents the ratio of the resistance of the oxide of the second conductive film to the channel resistance. Then, when judging the deterioration of the characteristics of the thin film transistor based on the decrease of mobility,
When Rx is 2%, 10% and 30%, the mobilities are 4%, 12% and 25%, respectively.

Further, as a result of the simulation, when the mobility is reduced by 5% or more, the influence on the aperture ratio and the driving voltage becomes large, which is not preferable in the device design. Therefore, it is necessary to suppress Rx to about 2%.

[0028] For example, the channel resistance of the n ⁺ -type low-resistance semiconductor layer 6a, 6b of the thin film transistor 11, n ⁺ -type low-resistance semiconductor layer 6a, depending on the size of the mobility or the thin film transistor 11 of 6b itself, typically 1MΩ Therefore, the resistance value in the film thickness direction of molybdenum oxide (MoO _x ) that is the oxide film of the molybdenum layers 7a and 7b that is the second conductive film must be 20 kΩ or less. That is, the resistivity of molybdenum oxide formed by the chemical conversion sputtering method is 1 × 1.
0 ^{−4 to} 2 × 10 ⁻³ Ωcm, and the thickness of the oxide film is 100.
0 angstrom, n ⁺ type low resistance semiconductor layers 6a and 6b to be the source contact region and the drain contact region
Even when the contact area with the oxide film is 5 μm ² , the resistance value of the oxide film is 0.01 Ω, which is a sufficiently low resistance value. Therefore, when titanium (Ti) is used for the second conductive film and titanium oxide is formed as the oxide film as in the prior art, the resistivity is 10 ⁸
Ωcm, when the film thickness is 10 Å and the contact area is 50 μm ² , the resistance value is 400 kΩ, and the characteristics of the thin film transistor 11 are significantly deteriorated. Can be made smaller.

The second conductive film is not limited to molybdenum, but may be tin, zinc, a conductive film containing molybdenum, tin or zinc as a main component, a laminated film of molybdenum and an oxide film of molybdenum, and an oxide of tin and tin. Laminated film of membranes,
Alternatively, a similar effect can be obtained with a laminated film of zinc and a zinc oxide film.

Further, the oxide film may be formed by a method of forming a film by sputtering or a method of partially oxidizing the film in the film thickness direction. Even when a laminated film is formed, etching can be performed as in the case of a single layer. Therefore, the etching process does not become complicated.

Further, the same effect can be obtained by using not only amorphous silicon oxide but also amorphous silicon nitride for the gate insulating film 3.

The same effect can be obtained by using aluminum (Al) instead of the molybdenum layer as the third conductive film.

[0033]

According to the present invention, the second conductive film interposed between the semiconductor layer and the light-transmissive oxide conductive film is formed of a material having conductivity even when oxidized, and therefore, the light-transmitting property is reduced. Even if the second conductive film is oxidized during the formation of the conductive oxide conductive film, an insulating layer is not formed in the second conductive film between the semiconductor layer and the light-transmitting oxide conductive film. In addition, the drain resistance is reduced, which can prevent deterioration of transistor characteristics.

[Brief description of drawings]

FIG. 1 is a sectional view showing one embodiment of a liquid crystal display device of the present invention.

FIG. 2 is a cross-sectional view showing one manufacturing process of the liquid crystal display device.

3 is a cross-sectional view showing the next manufacturing step of FIG. 2 of the above liquid crystal display device.

FIG. 4 is a cross-sectional view showing the next manufacturing step of FIG. 3 of the liquid crystal display device.

5 is a cross-sectional view showing the next manufacturing step of FIG. 4 of the liquid crystal display device.

FIG. 6 is a cross-sectional view showing the next manufacturing step of FIG. 5 for the liquid crystal display device.

FIG. 7 is a cross-sectional view showing the next manufacturing step of FIG. 6 for the liquid crystal display device.

FIG. 8 is a graph showing the relationship between the drain current and the gate voltage for each ratio of the resistance of the oxide of the second conductive film to the channel resistance.

[Explanation of symbols]

1 glass substrate as an insulating substrate 2 gate electrode as a first conductive film 3 gate insulating film 6 n ⁺ type low resistance semiconductor layer 7 molybdenum layer as a second conductive film 8 as a transparent oxide conductive film ITO layer 8c Display pixel electrode 10a Source electrode 10b Drain electrode 13 Matrix array substrate 24 Counter substrate 35 Liquid crystal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasunori Miura 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock Company Toshiba Yokohama Office (72) Inventor Caca de Ramesh 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Stock Company Toshiba Inside the Yokohama office

Claims (6)

[Claims] 1. A gate electrode of a first conductive film formed on an insulating substrate, a gate insulating film covering the gate electrode, a semiconductor layer formed on the gate insulating film, and at least a part thereof. A second conductive film which is conductive even when oxidized and is formed above the semiconductor layer, and a drain electrode and a display pixel electrode which are connected to the second conductive film and include a transparent oxide conductive film. An array substrate having a thin film transistor provided with a source electrode to be formed, a counter substrate provided to face the array substrate, and a liquid crystal disposed between the array substrate and the counter substrate. Liquid crystal display device. 2. The second conductive film has a metal in the center and an oxide on the surface, and the ratio of the resistance of the oxide to the channel resistance is 2% or less. Liquid crystal display device. 3. The liquid crystal display device according to claim 1, wherein the second conductive film has conductivity even if it is oxidized. 4. The liquid crystal display device according to claim 1, wherein the second conductive film is a laminated film of a material having conductivity and an oxide of this material. 5. The liquid crystal display device according to claim 1, wherein the second conductive film is composed of at least one of molybdenum, tin and zinc. 6. The liquid crystal display device according to claim 1, wherein the second conductive film contains at least one of molybdenum, tin, and zinc as a main component.