JPH05251705A - Thin-film transistor - Google Patents

Thin-film transistor

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Publication number
JPH05251705A
JPH05251705A JP4081483A JP8148392A JPH05251705A JP H05251705 A JPH05251705 A JP H05251705A JP 4081483 A JP4081483 A JP 4081483A JP 8148392 A JP8148392 A JP 8148392A JP H05251705 A JPH05251705 A JP H05251705A
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Prior art keywords
layer
film
electrode
gate
film transistor
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JP4081483A
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Japanese (ja)
Inventor
Tsutomu Hamada
Hisao Ito
久夫 伊藤
勉 浜田
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Fuji Xerox Co Ltd
富士ゼロックス株式会社
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Priority to JP4081483A priority Critical patent/JPH05251705A/en
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Abstract

PURPOSE:To obtain a thin-film transistor, of which numerical aperture can be increased without being influenced by light, by forming a semiconductor layer with specific carrier concentration into a translucent film. CONSTITUTION:A Cr film to be a gate electrode 2 is attached to and patterned on a substrate 1 by sputtering, a silicon nitride film as a gate insulating layer 3 is attached by a plasma CVD method, an oxygen content in the film is adjusted, and ITO film to be a semiconductor active layer 8 is attached by sputtering. Then, the silicon nitride film as a channel protective layer 5 is attached to and patterned on the semiconductor active layer 8 by the plasma CVD method, and the Cr film to be a source electrode 7 and drain electrode 6 is attached by sputtering and patterned by photolithographic. Therefore, the oxygen content in the ITO film is increased, a carrier concentration is controlled to 10<18>/cm<3> and less to lower electrical conductivity and the ITO film is used as the semiconductor active layer 8 so that element characteristics can be improved without influence of light.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は、光電変換素子及び発光素子を駆動する薄膜トランジスタに係り、特に光に影響されず、素子特性を向上できる薄膜トランジスタに関する。 The present invention relates to relates to a thin film transistor for driving the photoelectric conversion elements and the light emitting element is not particularly affect the light, to a thin film transistor capable of improving the device characteristics.

【0002】 [0002]

【従来の技術】従来の薄膜トランジスタ(TFT)は、 A conventional thin film transistor (TFT) is,
ガラス等の基板上にゲ−ト電極、ゲ−ト絶縁層、水素化アモルファスシリコン(a−Si:H)等の半導体層、 Gate on a substrate of glass or the like - gate electrode, gate - gate insulating layer, a hydrogenated amorphous silicon (a-Si: H) semiconductor layer such as,
ソ−ス及びドレイン電極を積層した逆スタガ構造のものがあり、イメ−ジセンサを始め、大面積デバイスの分野においてアクティブマトリスク型の液晶ディスプレイに代表されるフラットパネルディスプレイ等の駆動素子として用いられている。 Seo - are as scan and the reverse stagger structure in which the drain electrodes are laminated, Ime - Jisensa started, is used as a driving element such as flat panel displays represented by active matrix-type liquid crystal displays in the field of large area devices ing.

【0003】次に、従来の逆スタガ型の薄膜トランジスタの構成について図5を使って説明する。 [0003] Next will be described with reference to FIG. 5 the configuration of a conventional inverted staggered thin film transistor. 図5は、従来の薄膜トランジスタの断面説明図である。 Figure 5 is a cross sectional view showing a conventional thin film transistor. 図5に示すように、逆スタガ型の薄膜トランジスタ(TFT)は、ガラス等の基板20上にゲ−ト電極21としてのクロム(Cr1 )層、ゲ−ト絶縁層22としてのシリコン窒化膜(SiNx )、半導体活性層23としての水素化アモルファスシリコン(a−Si:H)層、ゲ−ト電極21 As shown in FIG. 5, inverted staggered thin film transistor (TFT) is gate on a substrate 20 of glass or the like - chromium as gate electrode 21 (Cr1) layer, gate - silicon nitride film as the gate insulating layer 22 (SiNx ), hydrogenated amorphous silicon as the semiconductor active layer 23 (a-Si: H) layer, gate - gate electrode 21
に対向するよう設けられたチャネル保護層24としてのシリコン窒化膜(SiNx )、オ−ミックコンタクト層25としてのn+ 型水素化アモルファスシリコン(n+ Silicon nitride film (SiNx), as the channel protective layer 24 provided so as to face the o - n + -type hydrogenated amorphous silicon as ohmic contact layer 25 (n +
a−Si:H)層、ソ−ス電極26及びドレイン電極2 a-Si: H) layer, source - scan electrode 26 and the drain electrode 2
7としてのクロム (Cr2 )層、その上に層間絶縁層29としてのポリイミド層、更に、その上に配線層30 Chromium (Cr2) layer as 7, polyimide layers as an interlayer insulating layer 29 thereon, further, the wiring layer 30 thereon
又はチャネル保護層24の上部においてはa−Si:H Or at the top of the channel protection layer 24 is a-Si: H
層の遮光用としてのアルミニウム(Al)の遮光層28 Shielding layer of aluminum as a light-shielding layer (Al) 28
とを順次積層した構造となっている(特開昭63−93 And has a sequentially laminated structure of the door (JP-63-93
58号公報参照)。 See No. 58).

【0004】 [0004]

【発明が解決しようとする課題】しかしながら、上記従来の薄膜トランジスタにおいては、半導体活性層にアモルファスシリコンを用いていることから、半導体活性層に光が当たると導電性を持ってスイッチング素子の特性が劣化するという問題点があった。 [SUMMARY OF THE INVENTION However, the above conventional thin film transistor, since it is an amorphous silicon semiconductor active layer, characteristics of the switching elements with a conductive when light strikes the semiconductor active layer is degraded there was a problem in that is.

【0005】そのために、半導体活性層に光が当たらないように遮光層を設ける方法があり、例えば、遮光層としては金属薄膜が用いられていた。 [0005] Therefore, there is a method of providing a light shielding layer so as not exposed to light in the semiconductor active layer, for example, a metal thin film has been used as a light-shielding layer. しかしながら、遮光層を設けると工程が増えるだけでなく浮遊電位を持つこととなるので、遮光層をグランドレベルにする必要があり、その場合にも、寄生容量が発生するという問題点があった。 However, since the have a floating potential well process increases the provision of the light shielding layer, it is necessary to light-shielding layer to the ground level, even in this case, parasitic capacitance is disadvantageously generated.

【0006】また、薄膜トランジスタを光電変換素子又は発光素子との積層構造にする場合には、図6の光電変換素子の上に薄膜トランジスタを積層した積層型光電変換装置の平面説明図に示すように、従来の積層型のものであれば、ソ−ス電極26及びドレイン電極27が金属電極であり、単位画素内でTFTが占める割合が増大し、当然ながら開口率(単位画素内における光電変換素子の受光エリアが占める割合)の低下を招き、感度が低下するという問題点もあった。 [0006] In the case of the thin film transistors stacked structure of the photoelectric conversion device or a light emitting device, as shown in plan view of a stacked photoelectric conversion device formed by laminating a thin film transistor on the photoelectric conversion element of FIG. 6, as long as the conventional laminated, source - source electrode 26 and drain electrode 27 is a metal electrode, the proportion of the TFT is increased in the unit pixel, of course the photoelectric conversion element in the aperture ratio (unit pixel cause a decrease in percentage) occupied by the light-receiving area, the sensitivity was also a problem of a decrease.

【0007】本発明は上記実情に鑑みて為されたもので、半導体層としてアモルファスシリコンよりバンドギャップの大きい透明材質の半導体を使うことで光に影響されず、更に開口率を増大させることができる薄膜トランジスタを提供することを目的とする。 [0007] The present invention has been made in view of the above circumstances, it is not affected by light using a semiconductor large transparent material bandgap of amorphous silicon as a semiconductor layer, it is possible to further increase the aperture ratio and to provide a thin film transistor.

【0008】 [0008]

【課題を解決するための手段】上記従来例の問題点を解決するための請求項1記載の発明は、ゲ−ト電極とゲート絶縁膜とソ−ス電極とドレイン電極と半導体層とを有する薄膜トランジスタにおいて、前記半導体層の伝導帯と価電子帯とのエネルギバンドギャップが3eV以上で、前記半導体層を透光性膜としたことを特徴としている。 Invention SUMMARY OF THE INVENTION The above prior art according to claim 1 for solving the problem of the gate - and a source electrode and the drain electrode and the semiconductor layer - gate electrode and the gate insulating film and the source in the thin film transistor, the energy band gap between the conduction band and the valence band of the semiconductor layer is at least 3 eV, is characterized in that the said semiconductor layer and the transparent film.

【0009】上記従来例の問題点を解決するための請求項2記載の発明は、ゲ−ト電極とゲート絶縁膜とソ−ス電極とドレイン電極と半導体層とを有する薄膜トランジスタにおいて、前記半導体層のキャリア濃度が10 18個・cm -3以下で、かつ前記半導体層を透光性膜としたことを特徴としている。 [0009] invention of the prior art problems solved according to claim 2 for the of, gate - gate electrode and the gate insulating film and the source - in a thin film transistor having a source electrode and the drain electrode and the semiconductor layer, said semiconductor layer carrier concentration is characterized by at 10 18 · cm -3 or less, and has the semiconductor layer and the transparent film.

【0010】 [0010]

【作用】請求項1記載の発明によれば、半導体層の伝導帯と価電子帯とのエネルギバンドギャップが3eV以上で、半導体層を透光性膜とした薄膜トランジスタとしているので、光が透過した場合でも導電性が変化しにくくなる。 SUMMARY OF According to the first aspect of the invention, the energy band gap between the conduction band and the valence band of the semiconductor layer is at least 3 eV, since the semiconductor layer is a thin film transistor and the transparent film, light is transmitted through conductivity is hardly changed even if the.

【0011】請求項2記載の発明によれば、半導体層のキャリア濃度が10 18個・cm -3以下で、かつ半導体層を透光性膜としているので、抵抗率が高くなり、光が透過した場合でも導電性が変化しにくい薄膜トランジスタとすることができる。 According to the second aspect of the invention, the carrier concentration of the semiconductor layer at 10 18 · cm -3 or less, and since the light transmissive film of the semiconductor layer, the resistivity is increased, light transmittance conductive even when it can be hardly changes TFT.

【0012】 [0012]

【実施例】本発明の一実施例について図面を参照しながら説明する。 It will be described with reference to the accompanying drawings, an embodiment of EXAMPLES The invention. 図1は、本発明の一実施例に係る薄膜トランジスタの断面説明図である。 Figure 1 is a cross-sectional view of a thin film transistor according to an embodiment of the present invention. 尚、本実施例(実施例1)では、例として逆スタガ型の薄膜トランジスタについて説明する。 In the present embodiment (Example 1), the inverted staggered thin film transistor as an example will be described.

【0013】図1に示すように、実施例1の薄膜トランジスタは、ガラス等の透明絶縁性の基板1と、基板1上に形成されたCr等のゲ−ト電極2と、ゲ−ト電極2を覆うように形成された窒化シリコン(SiNx )等のゲ−ト絶縁層3と、ゲ−ト絶縁層3上に酸素濃度を調製して形成された酸化インジィウム・スズ(ITO)等の半導体活性層8とが積層され、更に半導体活性層8上には窒化シリコン等のチャネル保護層5が形成され、Cr等のソ−ス電極7及びドレイン電極6とがチャネル保護層5の一部を覆うよう形成される構成となっている。 [0013] As shown in FIG. 1, the thin film transistor in Example 1, a substrate 1 of transparent insulating glass, the gate of Cr or the like formed on the substrate 1 - the gate electrode 2, gate - gate electrode 2 the formed silicon nitride so as to cover (SiNx) or the like of the gate - DOO and the insulating layer 3, gate - gate insulating layer 3 oxide Injiiumu tin the oxygen concentration is formed by preparing on (ITO) or the like of the semiconductor active It is laminated and the layer 8 is further formed channel protective layer 5 such as a silicon nitride on the semiconductor active layer 8, Cr or the like of the source - and source electrode 7 and the drain electrode 6 covers a portion of the channel protective layer 5 It is configured to be formed as.

【0014】次に、実施例1の薄膜トランジスタの製造方法について図1を使って説明する。 [0014] Next will be described with reference to FIG. 1 a method for manufacturing the thin film transistor in Example 1. まず、基板1上にゲ−ト電極2となるCrを500オングストロ−ム程度スパッタリングにより着膜し、フォトリソエッチングを用いて所定の形状にパタ−ニングする。 First, gate on the substrate 1 - the Cr to be the gate electrode 2 500 Å - to-deposit by an order of sputtering, pattern in a predetermined shape using a photolithographic etching - to training.

【0015】次に、ゲ−ト絶縁層3として窒化シリコンをプラズマCVD法で2500オングストロ−ム程度着膜する。 [0015] Next, gate - a gate insulating layer 3 of silicon nitride with a plasma CVD method 2500 Å - to beam about-deposit. そして、膜中の酸素濃度を調整し、半導体活性層8となるITO膜をスパッタリングにより500オングストロ−ム程度着膜する。 Then, by adjusting the oxygen concentration in the film, by sputtering an ITO film serving as a semiconductor active layer 8 500 Å - to beam about-deposit.

【0016】具体的には、着膜時の酸素ガス濃度を1% [0016] More specifically, 1% oxygen gas concentration of Chakumakuji
以上にしてスパッタリングを行うことで実現することができる。 It can be achieved by performing sputtering in the above. このとき、ITO膜のキャリア濃度が10 18個・cm -3以下となれば、縮退が解け半導体としてのIT At this time, if the carrier concentration of the ITO film 10 18 · cm -3 or less, as a semiconductor degenerated solved
O膜(半導体活性層8)が実現される。 O film (semiconductor active layer 8) is realized.

【0017】そして、半導体活性層8上に、チャネル保護層5として窒化シリコンをプラズマCVD法により2 [0017] Then, on the semiconductor active layer 8, as a channel protective layer 5 a silicon nitride by a plasma CVD method 2
500オングストロ−ム程度着膜し、フォトリソエッチングを用いて所定の形状にパタ−ニングする。 500 Å - to beam about film deposited, pattern in a predetermined shape using a photolithographic etching - to training.

【0018】更に、ソ−ス電極7及びドレイン電極6となるCrを1500オングストロ−ム程度スパッタリングにより着膜し、フォトリソエッチングを用いてパタ− Furthermore, source - source electrode 7 and the drain electrode 6 become Cr 1500 Å - to-deposit by an order of sputtering, patterns using photolithographic etching -
ニングすることにより実施例1の薄膜トランジスタが作製される。 The thin film transistor of Example 1 is prepared by training.

【0019】一般にITOなどの酸化物の透明導電膜は、膜中の酸素量を変化させることにより膜の導電率を変化させることができるものである。 The transparent conductive film of oxide such as general ITO is one that can change the conductivity of the film by changing the amount of oxygen in the film. これは、化学量論的組成からのずれ(酸素欠損)によりキャリアが発生していることによる。 This is because the carriers are generated by the deviation from the stoichiometric composition (oxygen deficiency).

【0020】ITO(Indium Tin Oxide)膜の電気抵抗率のスパッタ時での酸素濃度依存性は、図2に示すような特性をもっているので、Arガスと酸素ガスとを用いた反応性スパッタリングにおいて、酸素ガスの割合(O The oxygen concentration dependence at the time of sputtering the electrical resistivity of ITO (Indium Tin Oxide) film, so has the characteristics as shown in FIG. 2, in a reactive sputtering using Ar gas and oxygen gas, ratio of the oxygen gas (O
2 /Ar+O 2 )を1%以上にすれば、ITO膜における電気抵抗率(ρ[Ω・cm])を増加させることができ、ITO膜の導電性を低下するように制御できるものである。 If 2 / Ar + O 2) of 1% or more, the electrical resistivity at ITO film (ρ [Ω · cm]) can be increased, it is possible to control so as to reduce the conductivity of the ITO film.

【0021】また、光が当っても導電性が変化しないエネルギバンドギャップの大きい半導体を半導体活性層8 Further, the energy band gap even light hitting conductivity does not change a large semiconductor semiconductor active layer 8
として用いる必要があるので、半導体活性層の伝導帯と価電子帯とのエネルギバンドギャップが3eV以上であることが望ましい。 Since it is necessary to use as it is desirable energy band gap between the conduction band and a valence band of a semiconductor active layer is not less than 3 eV. 従来のa−Siの半導体層ではエネルギバンドギャップが1.7〜1.8eV程度であったが、本実施例で製造されるITO膜の半導体層ではエネルギバンドギャップが3eV以上とすることができる。 While the energy band gap in the semiconductor layer of the conventional a-Si was about 1.7~1.8EV, can be energy band gap is greater than or equal to 3eV in the semiconductor layer of the ITO film to be produced in this example .

【0022】実施例1の薄膜トランジスタによれば、従来透明電極として用いられていたITO膜の膜中の酸素量を増加させることにより、膜中のキャリア濃度を10 According to the thin film transistor of Example 1, by increasing the oxygen content in the film of ITO film which has been conventionally used as a transparent electrode, the carrier concentration in the film 10
18個・cm -3以下に制御して導電性を低下させ、半導体活性層8にITO膜を使用することで、光に影響されず、素子特性を向上できる効果がある。 18 · cm -3 controlled to lower the conductivity below, the use of ITO film on the semiconductor active layer 8, without being affected by the light, there is an effect capable of improving the device characteristics.

【0023】次に、別の実施例(実施例2)として図3 Next, FIG. 3 as another example (Example 2)
の断面説明図に示す透明薄膜トランジスタについて簡単に説明すると、実施例2の透明薄膜トランジスタは、実施例1の薄膜トランジスタと略同様の構成となっており、相違点はソ−ス電極11及びドレイン電極10、更にゲ−ト電極9にITO膜を使用している点である。 Briefly the transparent thin film transistor shown in the sectional view, of a transparent thin film transistor in Example 2, has a thin film transistor and substantially the same structure as in Example 1, the differences Seo - scan electrode 11 and the drain electrode 10, in that using the ITO film gate electrode 9 - further gate. この場合のITO膜は、一般的な透明導電膜である。 ITO film in this case is a typical transparent conductive film.

【0024】次に、実施例2の透明薄膜トランジスタの製造方法について図3を使って説明する。 Next, a manufacturing method of the transparent thin film transistor of Example 2 will be described with reference to FIG. 3 for. 尚、実施例2 In Example 2
の透明薄膜トランジスタの製造方法は、実施例1の薄膜トランジスタの製造方法と略同様であるので相違点について説明することにする。 The method of the transparent thin film transistor fabrication is to describe differences are the substantially similar to the manufacturing method of a thin film transistor in Example 1.

【0025】先ず、基板1上にITO膜を500オングストロ−ム程度スパッタリングにより着膜し、ゲ−ト電極9となるようフォトリソエッチングを用いてパタ−ニングする。 [0025] First, an ITO film 500 angstroms on the substrate 1 - to-deposit by an order of sputtering, gate - to be a gate electrode 9 with a photolithographic etching pattern - for training. そして、実施例1の場合と同様の方法により、窒化シリコンから成るゲ−ト絶縁層3、導電性の低いITO膜から成る半導体活性層8、窒化シリコンから成るチャネル保護層5を順次積層して所定形状にパタ− Then, by the same method as in Example 1, a gate made of silicon nitride - gate insulating layer 3, the semiconductor active layer 8 made of low conductivity ITO film are sequentially laminated a channel protective layer 5 made of silicon nitride predetermined shape pattern -
ニングする。 Training to.

【0026】その後、透明電極であるソ−ス電極11及びドレイン電極10として用いられるITO膜を150 [0026] Then, a transparent electrode source - 150 ITO film used as the source electrode 11 and drain electrode 10
0オングストロ−ム程度にスパッタリング法により着膜し、フォトリソエッチングを用いて所定の形状にパタ− 0 Å - to-deposit by sputtering about arm, into a predetermined shape using the photolithographic etching pattern -
ニングし、実施例2の透明薄膜トランジスタが作製される。 And training, transparent thin-film transistor of Example 2 is produced.

【0027】実施例2の透明薄膜トランジスタによれば、ソ−ス電極11及びドレイン電極10は透明電極であるので、図3に示す透明薄膜トランジスタを光電変換素子又は発光素子上部に一体的に形成するようにすれば、光電変換素子への入射光量を増大させ又は発光素子からの発光量を増大させ、開口率を上げることができる効果がある。 According to the transparent thin film transistor of Example 2, source - so the source electrode 11 and drain electrode 10 is a transparent electrode, so as to integrally form a transparent thin film transistor shown in FIG. 3 in the photoelectric conversion device or the light emitting device top if the increase the amount of light emitted from the increased allowed or the light emitting device to the amount of light incident on the photoelectric conversion element, there is an effect that can increase the aperture ratio.

【0028】次に、実施例3として透明薄膜トランジスタを光電変換素子上部に一体的に積層した積層型光電変換装置について図4を使って説明する。 Next, it will be described with reference to FIG. 4 for the stacked photoelectric conversion device in which stacked integrally on the photoelectric conversion element upper transparent thin film transistor as Example 3. 図4は、積層型光電変換装置の断面説明図である。 Figure 4 is a cross sectional view showing a stacked photoelectric conversion device.

【0029】実施例3の積層型光電変換装置における光電変換素子部分は、ガラス等の透明絶縁性の基板1上に積層されたCr等の共通電極12と、共通電極12上に形成された水素化アモルファスシリコン(a−Si: The photoelectric conversion element portion in the stacked photoelectric conversion device of the third embodiment, the common electrode 12 of Cr or the like which is laminated on the substrate 1 of the transparent insulating such as glass, which is formed on the common electrode 12 hydrogen amorphous silicon (a-Si:
H)等の光電変換層13と、光電変換層13上部に形成されたITO等の上部透明電極14とが順次積層され、 A photoelectric conversion layer 13 of H) or the like, and the upper transparent electrode 14 of ITO or the like formed on the photoelectric conversion layer 13 upper are sequentially laminated,
更に、上部透明電極14上部には、ポリイミド等の層間絶縁膜15が全体を覆うよう形成され、ドレイン電極1 Further, the upper transparent electrode 14 top, is formed as the interlayer insulating film 15 such as polyimide covers the entire drain electrode 1
1が接続するためのコンタクトホ−ルが設けられている。 A contact hole for 1 connects - le are provided.

【0030】そして、実施例3の積層型光電変換装置における透明薄膜トランジスタ(TFT)部分は、ITO [0030] Then, a transparent thin film transistor (TFT) portion in the stacked photoelectric conversion device of Example 3, ITO
等の透明電極であるドレイン電極10及びソ−ス電極1 A transparent electrode of an equal drain electrode 10 and the source - the source electrode 1
1が層間絶縁膜15上部に形成されており、ドレイン電極10は上記コンタクトホ−ルを介して上部透明電極1 1 is formed in the interlayer insulating film 15 upper drain electrode 10 is the contact hole - the top via the Le transparent electrode 1
4に接続するようになっている。 It is adapted to be connected to 4. そして、ドレイン電極10及びソ−ス電極11上部にはTFT部分の半導体活性層8となるITO膜が形成され、更にゲ−ト絶縁層3 The drain electrode 10 and the source - ITO film serving as a semiconductor active layer 8 of the TFT portion to the scan electrode 11 upper is formed, further gate - gate insulating layer 3
が半導体活性層8を覆い、ゲ−ト絶縁層3上にITO等の透明電極であるゲ−ト電極9が所定の形状で形成されている。 There cover the semiconductor active layer 8, gate - a transparent electrode of ITO or the like over the gate insulating layer 3 gate - gate electrode 9 is formed in a predetermined shape. 尚、実施例3の積層型光電変換装置では、光はTFT部分のゲ−ト電極9側から入射するようになっている。 In the stacked photoelectric conversion device Example 3, the light gate of the TFT portion - is incident from the gate electrode 9 side.

【0031】次に、実施例3の積層型光電変換装置の製造方法について図4を使って説明する。 Next, a manufacturing method of a stacked photoelectric conversion device of Example 3 will be described with reference to FIG. 4. ガラス基板1上に光電変換素子の共通電極12として、Crを1500 As a common electrode 12 of the photoelectric conversion element on the glass substrate 1, a Cr 1500
オングストロ−ム程度スパッタリングにより着膜し、フォトリソエッチングを用いてパタ−ニングする。 Å - to-deposit by an order of sputtering, patterns using photolithographic etching - to training. 次に、 next,
光電変換層13として、a−Si:HをプラズマCVD As the photoelectric conversion layer 13, a-Si: Plasma CVD of H
で1.3μm着膜する。 In the 1.3μm film deposition. そして、上部透明電極14としてITO膜をスパッタリングにより、600オングストロ−ム程度着膜し、上部透明電極14と光電変換層13 Then, by sputtering an ITO film as the upper transparent electrode 14, 600 Å - to beam about-deposit, the upper transparent electrode 14 and the photoelectric conversion layer 13
をパタ−ニングして光電変換素子部分を作成する。 The pattern - training to create a photoelectric conversion element portion.

【0032】そして、ポリイミドを層間絶縁膜15として所定の形状に形成し、フォトリソエッチングによりコンタクトホ−ルを開ける。 [0032] Then, polyimide is formed into a predetermined shape as an interlayer insulating film 15, a contact hole by a photolithographic etching - open Le. そして、ITO膜を1500 Then, 1500 an ITO film
オングストロ−ム程度スパッタリングにより着膜し、フォトリソエッチングを用いて所定の形状にパタ−ニングして透明電極であるドレイン電極10及びソ−ス電極1 Å - to-deposit by an order of sputtering, pattern in a predetermined shape using a photolithographic etching - training to a transparent electrode a drain electrode 10 and the source - the source electrode 1
1を作成する。 To create a 1.

【0033】更に、半導体活性層8となるITO膜中の酸素濃度を実施例1で説明したように調整し、スパッタリングにより500オングストロ−ム程度着膜する。 Furthermore, the oxygen concentration of the ITO film to be the semiconductor active layer 8 was adjusted as described in Example 1, 500 angstroms by sputtering - to beam about-deposit.

【0034】次に、ゲ−ト絶縁層3となる窒化シリコンをプラズマCVD法で2500オングストロ−ム程度着膜する。 Next, gate - silicon nitride as the gate insulating layer 3 by plasma CVD 2500 Å - to beam about-deposit. 透明電極であるゲ−ト電極9となるITO膜を1500オングストロ−ム程度スパッタリングにより着膜し、フォトリソエッチングを用いてパタ−ニングすることで実施例3の積層型光電変換装置が作製される。 A transparent electrode gate - 1500 the ITO film to be a gate electrode 9 Å - to-deposit by an order of sputtering, patterns using photolithographic etching - stacked photoelectric conversion device of Example 3 by training is fabricated.

【0035】実施例3の積層型光電変換装置によれば、 [0035] According to the stacked photoelectric conversion device of Example 3,
ゲ−ト電極9とソ−ス電極11及びドレイン電極10が従来の金属電極からTFTの透明電極に代えられており、また半導体活性層8も導電性の低いITO膜で作成されているので、光電変換素子上部にTFTが形成されても光電変換素子の受光領域が制限されることがなく、 Gate - gate electrode 9 and the source - the source electrode 11 and drain electrode 10 are provided instead of the transparent electrode of the TFT from conventional metal electrodes, also because it is created semiconductor active layer 8 at a low ITO film conductivity, without even a TFT is formed on the photoelectric conversion element upper limits are receiving regions of the photoelectric conversion element,
積層型光電変換装置の微細化による開口率の低下を防ぐことができ、入射光を効率よく利用できる効果がある。 It is possible to prevent a reduction in the aperture ratio due to miniaturization of the stacked photoelectric conversion device, there is an effect of utilizing the incident light efficiently.

【0036】 [0036]

【発明の効果】請求項1記載の発明によれば、半導体層の伝導帯と価電子帯とのエネルギバンドギャップが3e According to the invention of claim 1, wherein, according to the present invention, the energy band gap between the conduction band and the valence band of the semiconductor layer 3e
V以上で、半導体層を透光性膜とした薄膜トランジスタとしているので、光が透過した場合でも導電性が変化しにくくなり、素子特性を向上できる効果がある。 Above V, since a thin film transistor and the transparent film of the semiconductor layer, conductive even when the light is transmitted is less likely to change, there is an effect capable of improving the device characteristics.

【0037】請求項2記載の発明によれば、半導体層のキャリア濃度が10 18個・cm -3以下で、かつ半導体層を透光性膜としているので、抵抗率が高くなり、光が透過した場合でも導電性が変化しにくい薄膜トランジスタとすることができ、素子特性を向上できる効果がある。 [0037] According to the second aspect of the invention, the carrier concentration of the semiconductor layer at 10 18 · cm -3 or less, and since the light transmissive film of the semiconductor layer, the resistivity is increased, light transmittance conductive even when it is possible to change difficult TFT, there is an effect capable of improving the device characteristics.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】 本発明の一実施例に係る薄膜トランジスタの断面説明図である。 1 is a cross sectional view showing a thin film transistor according to an embodiment of the present invention.

【図2】 ITO膜の抵抗率のスパッタ時の酸素濃度依存度を示す図である。 2 is a diagram showing the oxygen concentration dependency of the sputtering of the resistivity of the ITO film.

【図3】 別の実施例(実施例2)に係る透明薄膜トランジスタの断面説明図である。 It is a cross sectional view of a transparent thin film transistor according to Figure 3 another embodiment (Example 2).

【図4】 別の実施例(実施例3)に係る積層型光電変換装置の断面説明図である。 It is a cross sectional view of a stacked photoelectric conversion device according to Figure 4 another embodiment (Example 3).

【図5】 従来の薄膜トランジスタの断面説明図である。 5 is a cross sectional view showing a conventional thin film transistor.

【図6】 従来の積層型光電変換装置の平面説明図である。 6 is an explanatory plan view of a conventional stacked photoelectric conversion device.

【符号の説明】 DESCRIPTION OF SYMBOLS

1,20…基板、 2,21…ゲ−ト電極、 3,22 1,20 ... substrate, 2, 21 ... gate - gate electrode, 3, 22
…ゲ−ト絶縁層、 5,24…チャネル保護層、 6, ... gate - gate insulating layer, 5, 24 ... channel protective layer, 6,
27…ドレイン電極、 7,26…ソ−ス電極、 8… 27 ... drain electrode, 7,26 ... source - the source electrode, 8 ...
半導体活性層(ITO)、 9…ゲ−ト電極(IT Semiconductor active layer (ITO), 9 ... gate - gate electrode (IT
O)、 10…ドレイン電極(ITO)、 11…ソ− O), 10 ... drain electrode (ITO), 11 ... Seo -
ス電極(ITO)、 12…共通電極、 13…光電変換層、 14…上部透明電極、 15…層間絶縁膜、 Scan electrodes (ITO), 12 ... common electrode 13 ... photoelectric conversion layer, 14 ... upper transparent electrode, 15 ... interlayer insulation film,
23…半導体活性層(a−Si)、 25…オ−ミックコンタクト層、 28…遮光層、 29…層間絶縁層、 23 ... semiconductor active layer (a-Si), 25 ... O - ohmic contact layer, 28 ... light shielding layer, 29 ... interlayer dielectric layer,
30…配線層 30 ... wiring layer

Claims (2)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】 ゲ−ト電極とゲート絶縁膜とソ−ス電極とドレイン電極と半導体層とを有する薄膜トランジスタにおいて、前記半導体層の伝導帯と価電子帯とのエネルギバンドギャップが3eV以上で、前記半導体層を透光性膜としたことを特徴とする薄膜トランジスタ。 1. A gate - gate electrode and the gate insulating film and the source - in a thin film transistor having a source electrode and the drain electrode and the semiconductor layer, the energy band gap between the conduction band and the valence band of the semiconductor layer is at least 3 eV, a thin film transistor, characterized in that the semiconductor layer was transparent film.
  2. 【請求項2】 ゲ−ト電極とゲート絶縁膜とソ−ス電極とドレイン電極と半導体層とを有する薄膜トランジスタにおいて、前記半導体層のキャリア濃度が10 18個・c 2. A gate - gate electrode and the gate insulating film and the source - in a thin film transistor having a source electrode and the drain electrode and the semiconductor layer, the carrier concentration of the semiconductor layer is 10 18 · c
    -3以下で、かつ前記半導体層を透光性膜としたことを特徴とする薄膜トランジスタ。 m -3 or less, and a thin film transistor, characterized in that the semiconductor layer was transparent film.
JP4081483A 1992-03-04 1992-03-04 Thin-film transistor Pending JPH05251705A (en)

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