JP2010165922A - Field effect transistor, method for manufacturing field effect transistor and method for manufacturing semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field effect transistor with high cut-off frequency. <P>SOLUTION: The field effect transistor includes a semiconductor layer 13 containing an oxide, and a protective layer 16 of the semiconductor layer. An etching rate of the semiconductor layer to the following A or B is 1/2 of an etching rate of a silicon dioxide or below. A is a wet etching liquid containing a hydrofluoric acid of 10 mass%, and B is a wet etching liquid containing an ammonium fluoride of 15 mass%. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a field effect transistor, a method for manufacturing a semiconductor element, and a method for manufacturing a field effect transistor.

  Field effect transistors are widely used as unit electronic elements, high frequency signal amplifying elements, liquid crystal driving elements and the like of semiconductor memory integrated circuits, and are the most widely used electronic devices at present.

  Among them, with the remarkable development of display devices in recent years, not only liquid crystal display devices (LCD) but also various display devices such as electroluminescence display devices (EL) and field emission displays (FED) are used as display elements. Thin film transistors (TFTs) are frequently used as switching elements that drive a display device by applying a driving voltage.

  As a material for TFT, a silicon semiconductor compound is most widely used. In general, a silicon single crystal is used for a high-frequency amplifier element, an integrated circuit element, and the like that require high-speed operation, and amorphous silicon is used for a liquid crystal driving element and the like because of a demand for a large area.

However, a crystalline silicon-based thin film requires a high temperature of, for example, 800 ° C. or higher when crystallization is performed, so that it is difficult to construct on a glass substrate or an organic substrate. For this reason, it could be formed only on an expensive substrate having high heat resistance such as a silicon wafer or quartz. In addition, there is a problem that a great deal of energy and the number of processes are required for the production.
In addition, a crystalline silicon-based thin film is usually difficult to reduce costs by reducing the number of masks and the like because the element configuration of the TFT is limited to a top gate configuration.

  On the other hand, amorphous silicon semiconductors (amorphous silicon) that can be formed at a relatively low temperature have a lower switching speed than crystalline ones. Therefore, when used as a switching element for driving a display device, a high-speed moving image The display may not be followed.

  Currently, as a switching element for driving a display device, an element using a silicon-based semiconductor film occupies the mainstream, but it has a high switching speed in addition to the stability and workability of a silicon thin film. This is because various performances are good. Such silicon-based thin films are generally manufactured by a chemical vapor deposition (CVD) method.

  A conventional TFT has a reverse structure in which a gate electrode, a gate insulating layer, a semiconductor layer such as hydrogenated amorphous silicon (a-Si: H), a source and a drain electrode are laminated on a substrate such as glass. There is a staggered structure. The TFT is used as a driving element for a flat panel display represented by an active matrix type liquid crystal display in the field of large area devices including image sensors. In these applications, there has been a demand for high-speed operation due to high definition, high frequency, and large screen of peripheral circuits such as driver circuits.

Under such circumstances, in recent years, a transparent semiconductor thin film made of a metal oxide has been attracting attention as being more stable than a silicon-based semiconductor thin film. In general, the electron mobility of an oxide crystal increases as the s orbital overlap of metal ions increases, and a Zn, In, Sn oxide crystal having a large atomic number has a large electron of 0.1 to 200 cm ² / Vs. Has mobility. In addition, in an oxide, since oxygen and metal ions are ionically bonded, there is no direction of chemical bonding, and even in an amorphous state where the bonding direction is not uniform, electron mobility close to the mobility of the crystalline state It is possible to have a degree. Therefore, unlike a Si-based semiconductor, a transistor with high field-effect mobility can be formed even if the metal oxide is amorphous.
Because of the above advantages, various semiconductor devices using crystalline / amorphous metal oxides containing Zn, In, and Sn, circuits using the same, and the like have been studied.

As a semiconductor device using a metal oxide, for example, a TFT using zinc oxide (ZnO) has been studied. However, the semiconductor layer made of zinc oxide has a field effect mobility as low as about 1 cm ² / V · sec and a small on-off ratio. Also, since leakage current is likely to occur, it has been difficult to put it to practical use industrially.

Many studies have been made on TFTs using an oxide semiconductor film containing a crystalline zinc oxide. However, when a semiconductor film is formed by a sputtering method commonly used in industry, the mobility is low, the on-off ratio is low, the leakage current is large, the pinch-off is unclear, and normally on As a result, there is a risk that the performance of the TFT may be lowered.
In addition, since chemical resistance is inferior, there are limitations on the manufacturing process and use environment, such as difficulty in wet etching.
In order to improve performance, it is necessary to form a semiconductor film at a high pressure. Therefore, there have been problems in industrialization, such as a slow film formation rate and the necessity of high-temperature treatment at 700 ° C. or higher.
Further, in the case of a bottom gate type TFT, performance such as electrolytic mobility was low. In order to improve the performance, it is necessary to use a top gate type TFT, and the thickness of the semiconductor layer needs to be 50 nm or more. Therefore, the configuration of the TFT is also limited.

In addition to a zinc oxide semiconductor film, an amorphous oxide semiconductor film made of indium oxide and zinc oxide, or a composite oxide (IGZO) film containing indium, zinc and gallium elements can be applied to a TFT. It is being considered.
However, when a TFT using an oxide semiconductor was examined, there was a case in which variation in transistor characteristics (Id-Vg characteristics) of the TFT occurred depending on the composition of the film and the manufacturing conditions. The variation in characteristics, for example, causes variations in the operation of an organic EL, liquid crystal, or the like to be driven when used in a pixel circuit of a display and the like, which ultimately causes a reduction in image quality of the display. The variation in characteristics is thought to be due to variations in parasitic capacitance between the TFTs because the formation position and dimensional accuracy of each member constituting the TFT are not sufficient.
In addition, there is a problem that the operating frequency is low when a peripheral circuit such as a driver or a circuit such as a ring oscillator (RO) is configured. This seems to be due to the fact that the cut-off frequency is reduced due to the large parasitic capacitance.

  In order to solve the above-described problems, the manufacture of a transistor in which a gate electrode and a source / drain electrode are self-aligned has been studied (Patent Document 1). In this manufacturing method, the nature of the source / drain region of the amorphous oxide semiconductor is made different from that of the channel region by ion implantation. However, when ion implantation is used, the implanted ions become a source of scattering, the mobility is lowered, defects are generated in the gate insulating film, the leakage current is increased, traps are generated at the interface, and the threshold voltage is increased. There is a problem that the transistor performance is greatly deteriorated, for example, the characteristics change due to the ions moving due to stress during driving. In addition, the ion implantation equipment has a problem that it is difficult to increase the size and the manufacturing cost is high.

In addition, the manufacture of a transistor in which a gate electrode and a source / drain electrode are self-aligned using an amorphous oxide semiconductor by a lift-off process has been studied (Patent Document 2). However, the lift-off process is industrially problematic and difficult to put into practical use. That is, there are problems such as low yield, low processing accuracy, large variation, and difficulty in miniaturization (the TFT portion becomes large and the aperture ratio becomes small).
In particular, there is a problem that it is difficult to miniaturize the TFT in the lift-off process. Since the obtained TFT becomes relatively large and as a result, the cutoff frequency of the TFT becomes low, there is a limit to the operating frequency (oscillation frequency, etc.) when the circuit is configured (Non-patent Document 1).
JP 2007-259883 A JP 2006-165527 A IEEE ELECTRON DEVICE LETTERS, vol. 28, no. 4, (2007) 273

An object of the present invention is to provide a field effect transistor having a high cutoff frequency.
Another object of the present invention is to provide a circuit with a high operating frequency and a TFT substrate with small variations by using a field effect transistor having a high cutoff frequency.

The present inventors considered that by forming the protective layer of the gate electrode and the semiconductor layer (channel layer) so as to be self-aligned, variation in transistor characteristics can be reduced and the cutoff frequency of the transistor is increased.
As described above, a TFT in which a gate electrode and a source / drain electrode are self-aligned has been studied. On the other hand, little consideration has been given to self-alignment of the gate electrode and the protective layer. This is because the manufacturing method is limited by the difference in the deposition method of each layer and the chemical and physical properties of the oxide semiconductor layer and the protective layer.

Specifically, silicon oxide (SiOx) or the like is usually used as the protective layer of the channel layer, and patterning of the protective layer is performed by lift-off, dry etching, or wet etching. However, lift-off has low yield and processing accuracy, and has a large variation. Moreover, there existed problems, such as difficult refinement | miniaturization, and industrialization was difficult.
In addition, since dry etching has a very low etching rate, there is a problem that the etching time becomes long when the protective layer is thick, which is also difficult to industrialize.

On the other hand, oxide semiconductors (crystalline ZnO, amorphous IGZO, indium zinc oxide, etc.) that have been extensively studied as semiconductor layers are not sufficiently resistant to hydrofluoric acid-based etching solutions. was there. For this reason, when SiOx on these oxide semiconductors is wet-etched with a hydrofluoric acid-based etchant, the oxide semiconductor is dissolved, so that it is difficult to form a semiconductor layer.
For the above reasons, it has been difficult to manufacture a field effect transistor using an oxide semiconductor in which a gate electrode and a protective layer are self-aligned using wet etching.

  Therefore, the present inventors have studied various oxide semiconductor materials and composition ratios that are difficult to dissolve in a hydrofluoric acid-based etching solution and can be a good field effect transistor. As a result, it has been found that the gate electrode and the protective layer can be self-aligned, and the transistor characteristics of the field effect transistor can be improved.

According to the present invention, the following field effect transistors and the like are provided.
1. A field effect transistor having a semiconductor layer containing an oxide and a protective layer for the semiconductor layer, wherein an etching rate of the semiconductor layer with respect to A or B below is half or less of an etching rate of silicon oxide .
A: Wet etching solution containing 10% by mass of hydrofluoric acid B: Wet etching solution containing 15% by mass of ammonium fluoride 2. The field effect transistor according to 1, wherein the semiconductor layer is made of an oxide containing at least one element selected from In, Zn, Sn, and Ga.
3. 3. The field effect transistor according to 1 or 2, wherein the semiconductor layer includes an oxide in a crystalline state.
4). 4. The field effect transistor according to any one of 1 to 3, wherein the semiconductor layer contains an In element and an oxide having a rare earth oxide C-type crystal structure.
5). The field effect transistor according to any one of 1 to 4, wherein the semiconductor layer is an oxide containing an In element and at least one kind of positive divalent element or at least one kind of positive trivalent element.
6). The field effect transistor according to any one of 1 to 5, wherein the cutoff frequency is 1 MHz or more.
7). A semiconductor element in which a semiconductor protective layer is formed using a gate electrode as a pattern.
8). 8. The semiconductor element according to 7, wherein the semiconductor protective layer is formed by selective etching by wet etching.
9. 9. The semiconductor device according to 8, wherein a wet etching solution containing hydrofluoric acid or ammonium fluoride is used for the wet etching.
10. The semiconductor element according to claim 9, which is a field effect transistor.
11. Forming an oxide film containing at least one element selected from In, Zn, Sn and Ga, and forming a protective layer on the oxide film using a gate electrode as a mask, A method for manufacturing a field effect transistor, which uses a wet etching solution containing hydrofluoric acid or ammonium fluoride in an etching process for forming a protective layer.
12 The method for manufacturing a field effect transistor according to claim 11, wherein an etching rate of the oxide film with respect to A or B below is half or less of an etching rate of silicon oxide.
A: Wet etching solution containing 10% by mass of hydrofluoric acid B: Wet etching solution containing 15% by mass of ammonium fluoride 13. 13. The method for producing a field effect transistor according to 11 or 12, wherein the oxide film is a crystalline oxide.
14 A display substrate comprising a driver circuit comprising the field effect transistors according to 1 to 6 above.
15. The laminated body which has a 1st conductor layer, a 1st insulator layer, a semiconductor layer containing an oxide, a 2nd insulator layer, and a 2nd conductor layer in this order.
16. 16. A field effect transistor comprising the laminate according to 15.
17. The first insulator layer is an oxide, the semiconductor layer containing the oxide is a polycrystalline oxide containing In and containing a rare earth oxide C-type crystal structure, and the second insulator layer is an oxide. The field effect transistor according to 16, wherein
18. 18. The field effect transistor according to 16 or 17, wherein the gate electrode and the protective layer of the semiconductor layer are self-aligned.

According to the present invention, a field effect transistor having a high cutoff frequency can be obtained. In addition, with the field effect transistor of the present invention, a circuit with a high operating frequency and a TFT substrate with small variations in characteristics can be manufactured.
In addition, a field effect transistor in which the gate electrode and the protective layer of the channel layer are self-aligned can be manufactured.

The field effect transistor of the present invention includes a semiconductor layer containing an oxide and a protective layer for the semiconductor layer.
FIG. 1 is a schematic cross-sectional view of a field effect transistor according to an embodiment of the present invention.
In this field effect transistor, gate electrodes 11 are formed in stripes on a substrate 10. A gate insulating film 12 is provided so as to cover the gate electrode 11, and an oxide semiconductor layer 13 (channel layer) is formed on the gate insulating film 12 and on the gate electrode 12.
A source electrode 14 is connected to one end side of the semiconductor layer 13 in a direction orthogonal to the gate electrode 11. A drain electrode 15 is connected to the other end side of the semiconductor layer 13.
A protective layer (etching stopper) 16 is formed at an intermediate position between the semiconductor layer 13, the source electrode 14 and the drain electrode 15.

The field effect transistor of the present invention is characterized in that the etching rate of the oxide semiconductor layer 13 with respect to the following A or B is half or less of the etching rate of silicon oxide.
A: Wet etching solution containing 10% by mass of hydrofluoric acid B: Wet etching solution containing 15% by mass of ammonium fluoride

  When the etching rate of the semiconductor layer 13 is half or less of silicon oxide (SiOx), the protective layer 16 can be patterned by back exposure wet etching using the gate electrode 11 as a mask. Thereby, a field effect transistor in which the gate electrode 11 and the protective layer 16 are self-aligned is obtained.

Here, the self-alignment means that there is substantially no overlap between the gate electrode 11 and the protective layer 16. That is, it means that both ends of the gate electrode 11 and both ends of the protective layer 16 are substantially at the positions of the lines X and Y shown in FIG.
In the self-alignment of the present invention, the overlap between the gate electrode 11 and the protective layer 16 is usually 3.0 μm or less, preferably 2.0 μm or less, more preferably 1.0 μm or less, further preferably 0.5 μm or less, particularly preferably. 0.2 μm or less.

The overlapping portion of the gate electrode 11 and the source electrode 14 and drain electrode 15 may function as a parasitic capacitance. This parasitic capacitance prevents high-speed operation of the transistor. In addition, if the overlapping portion varies between the transistors, the transistor characteristics of the transistors vary.
In the present invention, since the protective layer 16 can be formed in self-alignment with the gate electrode 11, the overlapping portion can be made uniform among the transistors. Therefore, the parasitic capacitance of the transistor can be made uniform. As a result, a transistor with high driving ability and excellent uniformity can be manufactured.

  The field effect transistor of the present invention preferably includes a portion where the semiconductor layer 13, the protective layer 16, the source electrode 14, and the drain electrode 15 are stacked in this order. Even if there is an overlapping portion of the gate electrode 11 and the source electrode 14 or the drain electrode 15, the parasitic capacitance can be reduced by providing the protective layer 16 between these electrodes, and a field effect transistor having a high cutoff frequency can be obtained.

In the present invention, the source electrode 14 or the drain electrode 15 is preferably in contact with the protective layer 16. More preferably, the source electrode 14 or the drain electrode 15 is in contact with the protective layer 16 that is self-aligned with the gate electrode 11. When the source electrode 14 or the drain electrode 15 is in contact with the protective layer 16 that is self-aligned with the gate electrode 11, the capacitance generated between the source electrode 14, the drain electrode 15, and the gate electrode 11 becomes constant. Thereby, it is possible to reduce variations among field effect transistors formed in the same substrate.
Note that the gate electrode 11 and the protective layer 16 need only be self-aligned, and the gate electrode 11, the source electrode 14, and the drain electrode 15 do not necessarily have to be self-aligned.

In the present invention, the field effect transistor is preferably a bottom gate type. The bottom gate type can reduce the number of masks during manufacturing. In addition, there is an advantage that metal ions such as a glass substrate are less likely to move to the semiconductor layer. Further, the transistor characteristics are also good, and the gate electrode 11 and the protective layer 16 are easily self-aligned.
Hereinafter, examples of members constituting the field effect transistor of the present invention will be described.

1. Substrate There is no particular limitation, and those known in this technical field can be used. For example, glass substrates such as alkali silicate glass, non-alkali glass and quartz glass, silicon substrates, resin substrates such as acrylic, polycarbonate and polyethylene naphthalate (PEN), polymer film bases such as polyethylene terephthalate (PET) and polyamide Materials can be used. As for the thickness of a board | substrate or a base material, 0.1-10 mm is common, and 0.3-5 mm is preferable. In the case of a glass substrate, those chemically or thermally reinforced are preferred. When transparency and smoothness are required, a glass substrate and a resin substrate are preferable, and a glass substrate is particularly preferable. When weight reduction is required, a resin substrate or a polymer material is preferable.

2. Semiconductor layer The semiconductor layer has the etching characteristics described above. When the etching rate is slower than that of silicon oxide (SiOx), the protective layer (SiOx) stacked on the semiconductor layer can be selectively etched by wet etching. The selectivity (silicon oxide etching rate / semiconductor layer etching rate) is more preferably 5 or more, and even more preferably 10 or more.
Examples of the semiconductor layer used in the present invention include a layer made of an oxide containing at least one element selected from In, Zn, Sn, and Ga. Preferred are oxides containing In and Zn, In and Ga, Zn and Sn, In and Zn and Sn, In and Zn and Ga, and Zn, Sn and Ga. By using these oxides, the characteristics of the obtained field effect transistor are improved. In particular, those containing In and Zn, In and Ga, Zn and Sn, and In and Zn and Sn are preferred, and most preferred are those containing In and Zn, In and Ga, and In, Zn and Sn.

  The semiconductor layer preferably contains an oxide in a crystalline state. The crystalline state can be confirmed by X-ray diffraction. A crystal refers to a crystal exhibiting a specific diffraction line with X-rays. Including those in which microcrystals can be confirmed in the amorphous by TEM observation. In addition, an amorphous thing means that a halo pattern is observed by X-ray diffraction and does not show a specific diffraction line.

  As the crystalline oxide of the semiconductor layer, an oxide containing at least indium element (In) is preferable. When indium element is included, the content of indium element in all atoms excluding oxygen is preferably 85 atomic percent or more and 100 atomic percent or less, more preferably 87 atomic percent or more and 100 atomic percent or less, and further preferably 90 atoms. % Or more and 100 atom% or less. When the indium element content is 85 atomic% or more, the semiconductor layer can be crystallized at a low temperature.

The semiconductor layer preferably contains In and contains an oxide exhibiting a rare earth oxide C-type crystal structure. An oxide having a rare earth oxide C-type crystal structure is preferable because of its high resistance to a hydrofluoric acid-based etching solution.
Here, the rare earth oxide C-type crystal structure refers to a cubic system having a space group of (T _h ⁷ , I _a3 ), and is also referred to as an Mn ₂ O ₃ (I) -type oxide crystal structure. In X-ray diffraction, JCPDS card no. 6-0416 pattern is shown. Sc ₂ O ₃ , Y ₂ O ₃ , Tl ₂ O ₃ , Pu ₂ O ₃ , Am ₂ O ₃ , Cm ₂ O ₃ , In ₂ O ₃ , ITO (In ₂ O ₃ doped with Sn of about 10 wt% or less Shows the above crystal structure.
In the present application, as a result of evaluating the semiconductor layer by X-ray diffraction, JCPDS card No. When the pattern 6-0416 is confirmed, it is determined that the crystal structure of the rare earth oxide C type is obtained. The JCPDS card No. If the pattern of 6-0416 is shown, the peak position may be shifted due to a change in interstitial distance, film stress, or the like (generally, the peak position shifts to the wide angle side as the interstitial distance becomes narrow).
The rare earth oxide C-type crystal structure is obtained by X-ray diffraction according to JCPDS Card No. If the pattern of 6-0416 is shown, the stoichiometric ratio may be deviated from M ₂ X ₃ . That is, it may be M ₂ O _3-d . Here, the oxygen deficiency d is preferably in the range of 3 × 10 ^{−5 to} 3 × 10 ⁻¹ . The oxygen deficiency d is a value obtained by subtracting the number of oxygen ions contained in one mole of oxide crystal from the number of stoichiometric oxygen ions. The oxygen deficiency d can be adjusted by film forming conditions, post-treatment after film formation, and the like.
The number of oxygen ions contained in the oxide crystal can be calculated, for example, by measuring the amount of carbon dioxide produced by heating the oxide in carbon powder using an infrared absorption spectrum. The number of stoichiometric oxygen ions can be calculated from the mass of the oxide crystal.

The crystal structure of the rare earth oxide C type has a stoichiometric ratio of M ₂ X ₃ (M: cation, X: anion). This fluorite-type crystal structure which is one of the crystal structure of the compound represented by MX _2, a structure in which the anion is missing one. The anion (usually oxygen in the case of an oxide) is 6-coordinated to the cation, and the remaining two anion sites are empty (the empty anion sites are quasi-ion sites) Also called). A rare earth oxide C-type crystal structure in which oxygen (anion) is coordinated to 6 positive ions (cations) has an oxygen octahedral ridge sharing structure. When the oxygen octahedral ridge sharing structure is used, the ns orbitals of the p metal that is a cation overlap each other to form an electron conduction path, and the effective mass is reduced, so that high electron mobility is exhibited.

  In order to obtain a rare earth oxide C-type crystal structure, the semiconductor layer includes Ga, Zn, Sn, Mg, Al, B, Sc, Y, lanthanoids (La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), Zr, Hf, Ge, Si, Ti, Mn, W, Mo, V, Cu, Ni, Co, Fe, Cr And two or more elements selected from Nb.

  The semiconductor layer of the present invention preferably has a rare earth oxide C-type crystal structure as a main component. The main component means that the maximum intensity of a peak attributed to a rare earth oxide C-type crystal structure in X-ray diffraction is at least twice the maximum intensity of a peak attributed to another crystal type. means. The maximum intensity of the peak attributed to the crystal structure of the rare earth oxide C type by X-ray diffraction is preferably 5 times or more, more preferably 10 times or more, more preferably 20 times the maximum intensity of the peak attributed to other crystal types. The above is particularly preferable.

In the X-ray diffraction measurement of the semiconductor layer, it is preferable that the β-Ga ₂ O ₃ structure (JCPDS card No. 43-1012) or β-GaInO ₃ structure (JCPDS card No. 21-0334) cannot be confirmed. In particular, the β-Ga ₂ O ₃ structure is preferably not confirmed by X-ray diffraction. If the β-Ga ₂ O ₃ structure exists, the mobility may be lowered.

  When the crystalline indium oxide thin film is used as the semiconductor layer, the lattice constant of the crystalline indium oxide thin film is preferably smaller than the lattice constant of the thin film made of indium oxide alone. Reduction of the crystal lattice means that the distance between metal elements is reduced, which increases the speed of movement of electrons moving on the orbit of the metal element and increases the mobility of the resulting transistor. There is.

In the present invention, the semiconductor layer is preferably an oxide containing an In element and one or more elements selected from a positive divalent element and a positive trivalent element.
A positive divalent metal element is an element that can take a positive divalence as a valence in an ionic state. By including indium, which is a positive trivalent element, and a positive divalent metal element, electrons generated by oxygen deficiency can be controlled when the semiconductor layer is crystallized, so that the carrier density can be kept low.
As the positive divalent metal element, Zn, Be, Mg, Ca, Sr, Ba, Ti, V, Cr, Mn, Fe, Co, Ni, Pd, Pt, Cu, Ag, Cd, Hg, Sm, Eu, Yb etc. are mentioned. From the viewpoint of efficiently controlling the carrier concentration, Zn, Mg, Mn, Co, Ni, Cu or Ca is preferable. From the viewpoint of the carrier control effect by addition, Cu and Ni are more preferable. Further, Zn and Mg are more preferable from the viewpoint of transmittance and wide band gap.
Two or more kinds of positive divalent metal elements may be contained.

  The atomic ratio [X / (X + In)] of the positive divalent metal element X is preferably 0.0001 to 0.13. When the atomic ratio [X / (X + In)] is less than 0.0001, the content of the positive divalent metal element is small, and the number of carriers may not be controlled. On the other hand, when the atomic ratio [X / (X + In)] exceeds 0.13, the interface between the crystalline layer and the amorphous layer or the surface of the crystalline layer is easily changed and becomes unstable. There is a possibility that the crystallization becomes difficult and the carrier concentration becomes high, the hole mobility decreases, the threshold voltage fluctuates when the transistor is driven, or the driving becomes unstable.

  The positive trivalent metal element is an element that can take positive trivalence as a valence in an ionic state. Examples of the positive trivalent element include Ga, Al, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, and Lu. Two or more kinds of positive trivalent metal elements may be contained. The content of the positive trivalent metal element is preferably 20 atomic% or less.

Furthermore, a positive tetravalent metal element may be included. A positive tetravalent metal element is an element that can take a positive tetravalence as a valence in an ionic state. Examples of the positive tetravalent element include Sn, Ge, Si, Zr, Ti, Hf, and V. Two or more kinds of positive tetravalent metal elements may be contained.
The content of the positive tetravalent metal element is preferably 0.01 atomic% to 10 atomic% of the positive trivalent metal element contained in the semiconductor layer.

  In addition, it is preferable to include a combination of two or more of positive divalent elements, positive trivalent elements, and positive tetravalent elements.

  The semiconductor layer can be produced, for example, by forming a thin film using an oxide target (semiconductor layer target).

The electron carrier concentration of the semiconductor layer is preferably 10 ¹³ to 10 ¹⁸ / cm ³ , and particularly preferably 10 ¹⁴ to 10 ¹⁷ / cm ³ . When the electron carrier concentration is in the above range, it is easy to become a non-degenerate semiconductor, and when used as a transistor, the balance between mobility and on / off ratio is good, which is preferable. The band gap is preferably 2.0 to 6.0 eV, and more preferably 2.8 to 5.0 eV. If the band gap is smaller than 2.0 eV, visible light is absorbed and the field effect transistor may malfunction. On the other hand, if it is larger than 6.0 eV, it is difficult to supply carriers and the field effect transistor may not function.

  The semiconductor layer is preferably a non-degenerate semiconductor exhibiting a thermal activation type. In the case of a degenerate semiconductor, there are too many carriers to increase the off-current / gate leakage current, and the threshold value may become negative and normally on. Whether the semiconductor layer is a non-degenerate semiconductor can be determined by measuring temperature changes in mobility and carrier density using the Hall effect. In addition, the semiconductor layer can be made a non-degenerate semiconductor by adjusting the oxygen partial pressure during film formation, post-processing, etc., and controlling the amount of oxygen defects to optimize the carrier density.

  The surface roughness (RMS) of the semiconductor layer is preferably 1 nm or less, more preferably 0.6 nm or less, and particularly preferably 0.3 nm or less. If it is larger than 1 nm, the mobility may decrease.

  The film thickness of the semiconductor layer is usually 0.5 to 500 nm, preferably 1 to 150 nm, more preferably 3 to 80 nm, and particularly preferably 10 to 60 nm. If it is thinner than 0.5 nm, it is difficult to form a uniform film industrially. On the other hand, if it is thicker than 500 nm, the film formation time becomes long and cannot be adopted industrially. Moreover, when it exists in the range of 3-80 nm, TFT characteristics, such as a mobility and an on / off ratio, are especially favorable.

3. Protective layer of semiconductor layer The field effect transistor of the present invention has a protective layer of a semiconductor. Without the protective layer, oxygen in the vicinity of the surface of the semiconductor layer is desorbed and a current flows in a vacuum or under a low pressure, so that the off-current increases and the threshold voltage may become negative. Further, since it is affected by ambient conditions such as humidity even in the atmosphere, there is a risk that variations in transistor characteristics such as threshold voltage will increase.

The thickness of the protective layer is preferably 100 to 1000 nm, more preferably 200 to 800 nm, and further preferably 250 to 700 nm. When the protective layer is 100 nm or more, the influence on the parasitic capacitance of the source / drain electrodes is reduced.
The protective layer is preferably thicker than the semiconductor layer. As for the thickness of a protective layer, it is more preferable that it is 2 times or more of the thickness of a semiconductor layer, and it is more preferable that it is 3 times or more. Thereby, the variation of the parasitic capacitance is reduced, and the parasitic capacitance itself is also reduced.

The material for forming the semiconductor protective layer is not particularly limited as long as the etching rate for the above-described wet etching solution (A or B) is equal to or higher than that of silicon oxide. What is generally used can be arbitrarily selected as long as the effects of the present invention are not lost.
For _{example, SiOx (SiO 2), SiNx} , Al 2 O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O ₃ , Y ₂ O ₃ , Hf ₂ O ₃ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTiO ₃ , AlN, or the like can be used. Among _{these, SiO 2, SiNx, Al 2} O 3, Y 2 O 3, Hf 2 O 3, it is preferable to use CaHfO _3, more preferably _{SiO 2, SiNx, Y 2 O} 3, Hf 2 O 3 , CaHfO ₃ , and oxides such as SiOx, Y ₂ O ₃ , Hf ₂ O ₃ , and CaHfO ₃ are particularly preferable. The number of oxygen in these oxides does not necessarily match the stoichiometric ratio (for example, it may be SiO ₂ or SiO x). SiNx may contain a hydrogen element (SiNx: H may be used).
SiOx is particularly preferred. Accordingly, it is possible to prevent carriers from being generated due to release of oxygen from a semiconductor containing an oxide during the formation of the protective layer.

The protective layer may have a structure in which two or more different insulating films are stacked.
The protective layer may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that is easy to produce industrially. However, it is particularly preferred that the protective layer is amorphous. If it is not an amorphous film, the smoothness of the interface is poor and the mobility is lowered, and the threshold voltage and S value may be too large.

  The protective layer of the semiconductor layer is preferably an amorphous oxide or an amorphous nitride, and particularly preferably an amorphous oxide. Further, if the protective layer is not an oxide, oxygen in the semiconductor moves to the protective layer side, and there is a possibility that the off current becomes high or the threshold voltage becomes negative and normally off.

4). Gate insulating film There is no particular limitation on the material for forming the gate insulating film. What is generally used can be arbitrarily selected as long as the effects of the present invention are not lost. For _{example, SiO 2, SiNx, Al 2} O 3, Ta 2 O 5, TiO 2, MgO, ZrO 2, CeO 2, K 2 O, Li 2 O, Na 2 O, Rb 2 O, Sc 2 O 3, Y ₂ O ₃ , Hf ₂ O ₃ , CaHfO ₃ , PbTi ₃ , BaTa ₂ O ₆ , SrTiO ₃ , AlN, or the like can be used. Among _{these, SiO 2, SiNx, Al 2} O 3, Y 2 O 3, Hf 2 O 3, it is preferable to use CaHfO _3, more preferably _{SiO 2, SiNx, Y 2 O} 3, Hf 2 O 3 , CaHfO ₃ . The number of oxygen in these oxides does not necessarily match the stoichiometric ratio (for example, it may be SiO ₂ or SiO x). SiNx may contain a hydrogen element.
Moreover, the thing with a high light transmittance of an exposure wavelength is more preferable since exposure becomes easy.

  The gate insulating film may have a structure in which two or more different insulating films are stacked. The gate insulating film may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that is easy to manufacture industrially.

  The gate insulating film is preferably SiOx or SiNx, and particularly preferably SiOx. SiOx and SiNx have an industrial track record and can be stably formed at low cost.

5). Electrode There are no particular limitations on the material for forming each of the gate electrode, the source electrode, and the drain electrode, and any material that is generally used can be selected as long as the effects of the present invention are not lost. For example, transparent electrodes such as indium tin oxide (ITO), indium zinc oxide, ZnO, SnO ₂ , metal electrodes such as Al, Ag, Cr, Ni, Mo, Au, Ti, Ta, Cu, or these An alloy metal electrode can be used.
In addition, when using a gate electrode as a mask, the material which interrupts | blocks light is used.
Two or more layers may be stacked. Thereby, it is preferable to reduce contact resistance or improve interface strength.
In order to reduce the contact resistance of the source electrode and the drain electrode, the resistance of the interface with the semiconductor electrode may be adjusted by plasma treatment, ozone treatment or the like.

  It is preferable that the semiconductor layer of the source / drain electrode is homojunction. When homojunction is achieved, the contact resistance is lowered, and the movement of the substance between the source / drain electrodes and the semiconductor layer hardly occurs, and the stability is improved. Homojunction refers to the joining of the same main components and structures.

  In the field effect transistor of the present invention, the ratio W / L of the channel width W to the channel length L is usually 0.1 to 100, preferably 0.5 to 20, and particularly preferably 1 to 8. If W / L exceeds 100, the leakage current may increase or the on-off ratio may decrease. If it is less than 0.1, the field effect mobility may be lowered, or pinch-off may be unclear. The channel length L is usually 0.1 to 1000 μm, preferably 1 to 100 μm, and more preferably 2 to 10 μm. If the thickness is 0.1 μm or less, it is difficult to produce industrially and the leakage current may increase.

  In the field effect transistor of the present invention, a contact layer may be provided between the semiconductor layer and the source / drain electrodes. The contact layer preferably has a lower resistance than the semiconductor layer. As a material for forming the contact layer, a composite oxide having the same composition as that of the semiconductor layer described above can be used.

  There are no particular restrictions on the method for forming the contact layer, but a contact layer having the same composition ratio as the semiconductor layer can be formed by changing the film formation conditions, a layer having a composition ratio different from that of the semiconductor layer can be formed, or a semiconductor electrode The contact portion may be formed by increasing the resistance by plasma treatment or ozone treatment, or a layer having a higher resistance may be formed by film formation conditions such as oxygen partial pressure when forming the semiconductor layer.

  In the field effect transistor of the present invention, an oxide resistance layer having a higher resistance than the semiconductor layer is provided between the semiconductor layer and the gate insulating film and / or between the semiconductor layer and the protective layer. Also good. The presence of the oxide resistance layer can reduce the off-current, the threshold voltage becomes positive, and the transistor is likely to be normally off, so that the possibility that the semiconductor layer is altered and the characteristics are deteriorated during a post-treatment process such as protective film formation or etching can be reduced.

  Regarding the characteristics of the field effect transistor of the present invention, the cutoff frequency is preferably 1 MHz or more, more preferably 10 MHz or more, further preferably 100 MHz or more, and particularly preferably 1 GHz or more. When the cut-off frequency is 1 MHz or more, the operating frequency of the circuit can be increased when the peripheral circuit is configured. In order to increase the cutoff frequency, it is effective to reduce the parasitic capacitance of the transistor, shorten the channel length, and increase the mobility. In order to reduce the parasitic capacitance of the transistor in order to increase the cutoff frequency, it is effective to self-align the gate electrode and the protective film.

The cut-off frequency is a frequency at which the current amplification factor (cut-off frequency / use frequency) becomes 1. The current amplification factor increases as the element is operated at a frequency lower than the cutoff frequency. That is, the higher the cutoff frequency, the more advantageous in terms of high-speed operation and power consumption.
The cut-off frequency (f _T ) can be obtained from the gate capacitance (C _G ) and the mutual conductance (g _m ) according to the following equation: f _T = g _m / 2πC _G

Mobility is preferably not less than ^{3 cm} 2 / Vs, more preferably at least ^{8 cm} 2 / Vs, more preferably at least 12cm ² / Vs, and particularly preferably equal to or greater than 16cm ² / Vs. If it is greater than 1 cm ² / Vs, the switching speed becomes faster and it can be used for a large-screen high-definition display.

The on / off ratio is preferably 10 ⁶ or more, more preferably 10 ⁷ or more, and particularly preferably 10 ⁸ or more.

  The off current is preferably 2 pA or less, and more preferably 1 pA or less. If the off-current is larger than 2 pA, the contrast may be deteriorated when used as a TFT of a display, and the uniformity of the screen may be deteriorated.

  The gate leakage current is preferably 1 pA or less. If it is less than 1 pA, the risk of poor contrast when used as a TFT of a display is reduced.

  The threshold voltage is usually −5 to 10V, preferably −2 to 4V, more preferably −1 to 3V, and particularly preferably 0 to 2V. If it is larger than -5V, the voltage at the off time can be reduced and the power consumption can be reduced. If it is less than 10V, the drive voltage can be reduced and the power consumption can be suppressed.

The S value is preferably 0.8 V / dec or less, more preferably 0.3 V / dec or less, further preferably 0.25 V / dec or less, and particularly preferably 0.2 V / dec or less. If it is less than 0.8 V / dec, the drive voltage can be reduced and the power consumption can be reduced. In particular, when used in an organic EL display, it is preferable to set the S value to 0.3 V / dec or less because of direct current drive because power consumption can be greatly reduced. The S value (Swing Factor) is a value indicating the steepness of the drain current that rises sharply from the off state to the on state when the gate voltage is increased from the off state. As defined by the following equation, an increment of the gate voltage when the drain current increases by one digit (10 times) is defined as an S value.
S value = dVg / dlog (Ids)
The smaller the S value, the sharper the rise ("All about Thin Film Transistor Technology", Ikuhiro Ukai, 2007, Industrial Research Committee). If the S value can be reduced, it is not necessary to apply a high gate voltage when switching from on to off, and power consumption can be reduced.

  Further, the shift amount of the threshold voltage before and after being applied for 100 hours at a DC voltage of 10 μA at 50 ° C. is preferably 1.0 V or less, more preferably 0.5 V or less. If it is greater than 1V, the image quality may change when used as a transistor in an organic EL display.

  Further, it is preferable that the hysteresis is small when the gate voltage is raised or lowered on the transfer curve.

Then, the manufacturing method of the semiconductor element of this invention is demonstrated.
The manufacturing method of the present invention includes a step of selectively etching an insulator on a semiconductor containing an oxide by wet etching. When the insulator is wet-etched, the processing time can be shortened and the cost can be reduced as compared with dry etching.

  The selectivity between the semiconductor containing an oxide and the insulator thereover (the etching rate of the insulator / the etching rate of the semiconductor containing the oxide) is preferably 2 or more, more preferably 5 or more, and even more preferably 10 or more 20 or more is particularly preferable. The higher the selectivity, the less the damage on the semiconductor side and the more the insulator can be etched. Further, the etching time margin (allowable range) is widened.

  The wet etching solution used for wet etching is preferably hydrofluoric acid. As hydrofluoric acid-based wet etching solutions, hydrofluoric acid / water system, hydrofluoric acid / ammonium fluoride / water system (also referred to as BHF, which will be described later), hydrofluoric acid / hydrogen peroxide solution / water system, and the like are common. When such a wet etching solution containing hydrofluoric acid is used, an oxide film such as silicon oxide (SiOx) or a nitride film such as SiNx (including SiNx: H) can be etched. Further, since the etching rate is high, it is suitable for wet etching of an oxide film, particularly silicon oxide (SiOx), which is difficult to etch with other wet etching solutions.

  Hydrofluoric acid is usually marketed as an aqueous solution of about 47 wt%. It is preferable to dilute and use at 0.1 to 10 wt%, more preferably 0.5 to 7.5 wt%, and particularly preferably 1 to 5 wt%. If it is 10 wt% or less, the glass melting rate becomes slow, so that a glass substrate can be used. Further, hydrofluoric acid may be used in a buffer solution (BHF: Buffered HF) with ammonium fluoride. BHF is preferable because the pH is kept constant and the reproducibility of conditions is improved.

  The buffer solution preferably contains 8 to 35% by weight of ammonium fluoride and 0.1 to 10% by weight of hydrofluoric acid. Within this range, there are advantages that the etching rate is high and that etching is possible even when the temperature of the etching solution is low.

  The wet etching solution preferably has an etching rate of 50 to 450 nm with respect to SiO x at 30 ° C., more preferably 70 to 300 nm. Within this range, etching can be performed at an etching rate suitable for tact time.

  It is preferable to add a surfactant to the wet etching solution containing hydrofluoric acid. The inclusion of a surfactant is preferable because it improves the etching uniformity.

  The etching temperature is preferably 5 to 50 ° C, more preferably 10 to 35 ° C, and particularly preferably 15 to 30 ° C. In the above temperature range, it is easy to control to an appropriate etching rate, and temperature control is possible with simple equipment.

The manufacturing method of the present invention can be applied to the manufacture of semiconductor elements such as field effect transistors, sensors such as gas sensors and ultraviolet sensors, memories such as resistance change memories, and solar cells.
The semiconductor element preferably includes a structure in which semiconductor / insulator / conductor or semiconductor / insulator / semiconductor are stacked in this order. With the above structure, fine processing is possible by wet etching the insulator.
Hereinafter, an example applied to the manufacture of a field effect transistor will be described.

2a to 2c are process diagrams for explaining an embodiment of a method for producing a semiconductor element (field effect transistor) according to the present invention.
A gate electrode 11, a gate insulating film 12, and an oxide film 13a are sequentially formed on the substrate 10 (FIGS. 2a (a) to (c)). The oxide film 13a is patterned to form the semiconductor layer 13 (FIG. 2a (d)). An insulating layer 16a serving as a protective layer for the semiconductor layer is formed on the semiconductor layer 13 and the gate insulating film 12 (FIG. 2a (e)), and a photoresist 21 is formed thereon (FIG. 2a (f)).
In the present embodiment, the semiconductor layer 13 corresponds to “a semiconductor including an oxide”, and the insulating layer 16a corresponds to “an insulator on a semiconductor”.

The photoresist 21 is exposed (FIG. 2b (g)). In this embodiment, the photoresist 21 is patterned by irradiating light from the substrate 10 side. Since the gate electrode 11 does not transmit light, the photoresist 21 on the back surface thereof is not exposed (FIG. 2b (h), non-exposed portion 21a). That is, the gate electrode 11 is used as a mask. On the other hand, by using a member that transmits light except for the gate electrode 11, the photoresist 21 is exposed except for the non-exposed portion 21a (exposed portion 21b).
The non-exposed portion 21 a is the shape of the protective layer 16. Therefore, the protective layer 16 is self-aligned with the gate electrode 11.

  By making self-alignment, the positional relationship between the gate electrode 11 and the protective layer 16 can be automatically determined. That is, steps such as mask alignment that are likely to cause errors are not necessary. In addition, since it is not necessary to consider an error caused by mask alignment, the size of the transistor can be reduced.

After the exposure, the exposed portion 21b of the photoresist is removed by washing or the like to form a photoresist pattern (FIG. 2b (i)).
Thereafter, the insulating layer 16a is etched by wet etching, the photoresist is removed, and the protective layer 16 is formed (FIGS. 2c (j) (k)).

Subsequently, a metal layer 14a to be a source electrode and a drain electrode is formed on the protective layer 16 and the like, and patterned by a known method, thereby forming the source electrode 14 and the drain electrode 15. Thus, a field effect transistor can be manufactured.
Note that a second protective layer 17 may be further formed after the formation of the source electrode 14 and the drain electrode 15 (FIG. 2c (n)). In this case, a contact hole 18 for connecting the source electrode 14 and the drain electrode 15 to the external electrode may be formed.
When the protective layer 16 is an oxide film such as SiOx, the second protective layer 17 is preferably a nitride film such as SiNx. When the nitride film is formed, the moisture resistance is improved. The second protective layer 17 may be laminated on one side of the protective layer 16.

In the method for producing a field effect transistor of the present invention, it is particularly preferable to have the following steps.
Step 1: Step of forming an oxide film containing at least one element selected from In, Zn, Sn, and Ga Step 2: Step of forming a protective layer on the oxide film using the gate electrode as a mask

In Step 1, an oxide film containing at least one element selected from In, Zn, Sn, and Ga is formed as the oxide film 13a (FIG. 2a (d)). Specific examples of the material of the oxide film are the same as those of the semiconductor layer of the transistor of the present invention described above. Although an oxide film can be formed by sputtering, the formed film may be an amorphous film, but can be crystallized by a subsequent heat treatment or the like. In the present invention, it is preferable to etch the oxide film in an amorphous state and then crystallize the amorphous film. Etching is easy when etched in an amorphous state. Further, when an amorphous film is formed and then crystallized, it is easier to form a uniform and high mobility film than directly forming a crystalline film.
The amorphous film is preferably a degenerate semiconductor having a carrier density of 10 ¹⁸ cm ⁻³ or more, and the crystal film formed by crystallizing the amorphous film is preferably a non-degenerate semiconductor having a carrier density of less than 10 ¹⁸ cm ^−3. .

  In step 2, an etching process for forming the protective layer uses a wet etching solution containing hydrofluoric acid or ammonium fluoride.

Each constituent member (layer) of the above-described field effect transistor can be formed by a method known in this technical field.
Specifically, as a film formation method, a chemical film formation method such as a spray method, a dip method, or a CVD method, or a physical film formation method such as a sputtering method, a vacuum evaporation method, an ion plating method, or a pulse laser deposition method. The method can be used. Since the carrier density is easily controlled and the film quality can be easily improved, a physical film formation method is preferably used, and a sputtering method is more preferably used because of high productivity.

In sputtering, a method using a sintered complex oxide target, a method using co-sputtering using a plurality of sintered targets, a method using reactive sputtering using an alloy target, and the like can be used. However, in the method using co-sputtering using a plurality of sintered targets or the method using reactive sputtering using an alloy target, the uniformity and reproducibility are deteriorated, or the energy width of delocalized levels (E ₀ ) May increase, resulting in a decrease in transistor characteristics such as a decrease in mobility and an increase in threshold voltage. Preferably, a composite oxide sintered target is used.

The formed film can be patterned by various etching methods.
In the present invention, the semiconductor layer is preferably formed by DC or AC sputtering. By using DC or AC sputtering, damage during film formation can be reduced as compared with RF sputtering. For this reason, in the field effect transistor, effects such as a reduction in threshold voltage shift, an improvement in mobility, a reduction in threshold voltage, and a reduction in S value can be expected.

  Moreover, in this invention, after forming a semiconductor layer and a semiconductor protective layer, it is preferable to heat-process at 70-450 degreeC. When the temperature is higher than 70 ° C., the thermal stability and heat resistance of the obtained transistor are decreased, the mobility is decreased, the S value is increased, and the threshold voltage is increased. On the other hand, when the temperature is higher than 450 ° C., there is a possibility that the equipment cost for heat treatment cannot be used because the substrate without heat resistance cannot be used.

  The heat treatment temperature is preferably 80 to 350 ° C, more preferably 90 to 280 ° C, and further preferably 100 to 180 ° C. In particular, a heat treatment temperature of 180 ° C. or lower is preferable because a resin substrate having low heat resistance such as PEN can be used as the substrate.

  The heat treatment time is usually preferably 1 second to 24 hours, but is preferably adjusted by the treatment temperature. For example, at 70 to 180 ° C., 10 minutes to 24 hours are more preferable, 20 minutes to 6 hours are more preferable, and 30 minutes to 3 hours are particularly preferable. In 180-260 degreeC, 6 minutes to 4 hours are more preferable, and 15 minutes to 2 hours are still more preferable. At 260 to 300 ° C., 30 seconds to 4 hours is more preferable, and 1 minute to 2 hours is particularly preferable. At 300 to 350 ° C., 1 second to 1 hour is more preferable, and 2 seconds to 30 minutes is particularly preferable.

The heat treatment is preferably performed in an inert gas in an environment where the oxygen partial pressure is 10 ⁻³ Pa or less, or after the semiconductor layer is covered with a protective layer. Reproducibility is improved under the above conditions.

Then, the laminated body of this invention is demonstrated.
The laminate of the present invention has a first conductor layer, a first insulator layer, a semiconductor layer containing an oxide, a second insulator layer, and a second conductor layer in this order.
FIG. 3 is a schematic cross-sectional view showing an embodiment of the laminate of the present invention. This figure shows the same field effect transistor as in FIG. This transistor includes the laminate of the present invention. The gate electrode 11 is a first conductor layer, the gate insulating film 12 is a first insulator layer, the oxide semiconductor layer 13 is a semiconductor layer containing an oxide, and the protective layer 16 is a second insulator layer. The drain electrode 15 corresponds to the second conductor layer.
By using this stack structure for an element such as a field effect transistor, the parasitic capacitance generated between the conductors is reduced, and the capacitance of the elements varies even when the overlapping portions of the conductors and conductors vary. Can be reduced.

The first or second conductor layer is made of a transparent electrode such as indium tin oxide (ITO), indium zinc oxide, ZnO, SnO ₂ , Al, Ag, Cr, Ni, Mo, Au, Ti, Ta, Cu. Etc., or a metal electrode of an alloy containing these can be used. Two or more of these may be laminated.

  The first or second insulating layer is preferably an oxide or nitride, more preferably an oxide, and silicon oxide (SiOx) is particularly preferable because of its low dielectric constant and low electric capacity. Nitride may reduce a semiconductor layer containing an oxide during stacking to be a conductor.

  As the semiconductor containing an oxide, a polycrystalline oxide semiconductor having a rare earth oxide C-type crystal structure containing indium element is preferable.

The first insulator is an oxide, the semiconductor layer including the oxide is a polycrystalline oxide including In and containing a rare earth oxide C-type crystal structure, and the second insulator layer is an oxide. Is preferred.
The insulator made of oxide is preferably SiO ₂ , SiOx, Al ₂ O ₃ , Y ₂ O ₃ , Hf ₂ O ₃ , TiO ₂ , or CaHfO _{3. In} particular, SiOx has a low dielectric constant and a parasitic capacitance. It is preferable because it is small.

  In the field-effect transistor having a stacked structure, the gate electrode and the protective layer of the semiconductor layer are preferably self-aligned.

Example 1 [Fabrication of Field Effect Transistor]
(1) Production of Sputtering Target As a raw material, powders of indium oxide and gallium oxide have an atomic ratio [In / (In + Ga)] of 0.95 and an atomic ratio [Ga / (In + Ga)] of 0.05. Mixed. This was supplied to a wet ball mill, mixed and pulverized to obtain a raw material fine powder.

  After granulating the obtained raw material fine powder, it was press-molded into dimensions of 10 cm in diameter and 5 mm in thickness, put in a firing furnace and fired at 1400 ° C. for 12 hours to obtain a sintered body (target). .

  The target had a bulk resistance of 12 mΩ and a theoretical relative density of 0.99. The theoretical relative density was obtained by calculating the ratio of the density calculated from the specific gravity of each oxide and the amount ratio thereof to the density measured by the Archimedes method.

(2) Fabrication of Transistor The field effect transistor illustrated in FIG. 1 was fabricated in the steps illustrated in FIGS.
After depositing 200 nm of molybdenum metal on the glass substrate 10 by RF sputtering at room temperature, patterning was performed by wet etching to produce the gate electrode 11 (FIG. 2 a (a)).
Next, SiNx was formed at a temperature of 300 ° C. (thickness: 200 nm) on the substrate on which the gate electrode 11 was produced by a plasma enhanced chemical vapor deposition apparatus (PECVD) to form the gate insulating film 12 (FIG. 2a (b)). ).
Next, the target manufactured in (1) above is mounted on a DC magnetron sputtering film forming apparatus, an oxide film is formed on the gate insulating film 12, and then patterned by a photolithography process to form a semiconductor layer (channel Part) 13 (film thickness 50 nm) was formed (FIGS. 2a (c) to (d)).

The sputtering conditions were as follows: substrate temperature: 25 ° C., ultimate pressure: 1 × 10 ⁻⁶ Pa, atmospheric gas: Ar 99% and oxygen 1%, sputtering pressure (total pressure): 4 × 10 ⁻¹ Pa, input power 100 W, The ST distance was 80 mm.
When the semiconductor layer 13 was confirmed by X-ray diffraction, it was an amorphous film. This amorphous film was not resistant to a hydrofluoric acid-based etching solution. In addition, the carrier density of the semiconductor layer 13 was 1 × 10 ²⁰ cm ⁻³ and was a degenerate semiconductor.

The carrier density was measured with a Hall measuring device under the following measurement conditions.
・ Hall measuring device manufactured by Toyo Technica: Resi Test 8310
・ Measurement conditions Measurement temperature: Room temperature (25 ℃)
Measurement magnetic field: 0.5T
Measurement current: 10 ⁻¹² to 10 ⁻⁴ A
Measurement mode: AC magnetic field Hall measurement Further, non-degenerate semiconductors and degenerate semiconductors were judged by temperature dependence of mobility.
FIG. 4 shows an example of temperature dependence of mobility. The activation energy can be calculated from the slope of the straight line. In the figure, (1) corresponds to a degenerate semiconductor and (2) corresponds to a non-degenerate semiconductor.

Next, an SiO ₂ film 16a serving as the protective layer 16 (etching stopper) was formed to a thickness of 300 nm by PECVD (FIG. 2a (e)). Next, the substrate was heat-treated at a temperature of 300 ° C. for 1 hour.
As a result of confirmation by X-ray diffraction, the semiconductor layer 13 was crystallized (slightly shifted to the outer angle side). Further, the carrier density of the crystallized semiconductor layer 13 was a non-degenerate semiconductor of 1 × 10 ¹⁶ cm ⁻³ . Further, the crystallized semiconductor layer 13 was resistant to a hydrofluoric acid etching solution.

Thereafter, a positive type photoresist 21 was formed (FIG. 2a (f)), and exposure was performed from the back surface using the gate electrode 11 as a mask (FIG. 2b (g)). After removing the photoresist exposed portion 21b (FIG. 2b (i)), the SiO ₂ film 16a is formed into a hydrofluoric acid etching solution (BHF: HF (hydrofluoric acid) 2 wt%, NH ₄ F (ammonium fluoride)). 15 wt%) to form a protective layer 16 that is self-aligned with the gate electrode 11 (FIG. 2c (k)).
Subsequently, a molybdenum metal layer 14a (thickness: 200 nm) was formed and patterned by a photolithography process to form a source electrode 14 and a drain electrode 15.
Through the above steps, an etching stopper type field effect transistor having a bottom gate structure was manufactured (FIG. 1, the gap (L) between the source and drain electrodes was 20 μm, and the width (W) was 20 μm).

  Note that, in the vicinity of the end portion of the protective layer 16 of the manufactured field effect transistor, a first conductor, a first insulator, a semiconductor containing an oxide, a second insulator, and a second conductor are stacked in this order. It is a laminated body. The protective layer 16 is a second insulator.

(3) Transistor evaluation (A) Field effect mobility (μ), on / off ratio, off current, S value, threshold voltage (Vth) and cut-off frequency It was measured.
(B) Hysteresis Using a semiconductor parameter analyzer, the transfer curve at the time of rising voltage (IV characteristic) and the transfer curve at the time of falling voltage (IV characteristic) are measured, and the difference in voltage at the time of raising and lowering is taken as ΔVg. The case where the maximum value of ΔVg is 0.5 V or less is “less”, the case where 0.5 to 3 V is “Yes”, and the case where it is 3 V or more is “large”.
(C) Resistance of hydrofluoric acid-based etching solution of semiconductor layer The etching rate with a hydrofluoric acid-based etching solution (hydrofluoric acid 10 wt%) was measured, and the selectivity was calculated by the following formula.
Selectivity = (SiOx etching rate) / (Semiconductor film etching rate)
Those having a selection ratio of less than 2 were not resistant to hydrofluoric acid-based etching solutions, and those having a selectivity of 2 or more (etching rate of 1/2 or less of SiOx) were considered to have resistance to hydrofluoric acid-based etching solutions.
The SiOx etching rate used in the calculation of the selectivity was that of a thermal oxide film.

(4) Evaluation of TFT substrate (A) Variation 1000 TFTs fabricated in the same substrate were evaluated, and the variation coefficient of the cut-off frequency was calculated.
Coefficient of variation = 3σ (standard deviation) / average value × 100 (%)
The coefficient of variation was evaluated according to the following criteria.
○: Less than 1%, △: 1% or more and less than 10%, ×: 10% or more (B) Yield Evaluate 1000 TFTs on the same substrate, and any of field effect mobility, S value and cutoff frequency is Yield was calculated by assuming that the product deviated from 3σ was defective.
Yield was evaluated according to the following criteria.
○: 99.5% or more, Δ: 99% or more and less than 99.5%, ×: less than 99%

(5) Evaluation by Ring Oscillator Fabrication In Example 1, except that W / L = 60/10 μm, an 11-stage ring oscillator was fabricated for a field-effect transistor fabricated in the same manner, and the delay time per stage was evaluated. In the examples and comparative examples described later, W / L was 60/10 μm.
The evaluation results are shown in Table 1.

-Absorption coefficient of semiconductor layer The absorption coefficient of the semiconductor layer (after heat processing) of Example 1 and the amorphous silicon layer formed similarly to the semiconductor layer of Example 1 were compared. FIG. 5 shows the relationship between the absorption coefficient and the wavelength. For light with a short wavelength of 500 nm or less, the absorption coefficient of the semiconductor layer (crystal film) of Example 1 was 1/10 or less of that of the amorphous silicon layer. For this reason, when the irradiation light passes through the semiconductor layer to expose the back layer, the loss of the irradiation light is small, and characteristic changes due to partial heat generation, non-uniform crystal growth, and the like can be prevented. In Example 1, the photoresist could be exposed without any problem using the gate electrode as a mask. In addition, it was possible to raise processing precision using the light of a short wavelength.

Example 2
A field effect transistor was manufactured in the same manner as in Example 1 except that the second protective layer 17 was formed (FIG. 2c (o)). The results are shown in Table 1.
The second protective layer was made of SiNx by PECVD (thickness 100 nm). Since SiNx was laminated, the moisture resistance was improved.

Example 3
The field effect transistor shown in FIG. 6 was manufactured.
Specifically, the semiconductor layer 13, the source electrode 14, and the drain electrode 15 were collectively formed by dry etching, and the same procedure as in Example 1 was performed except that the second protective film and the contact hole were not provided. The results are shown in Table 1.

Examples 4-25
A field effect transistor was fabricated and evaluated in the same manner as in Example 1 except that the composition of the semiconductor layer was changed as shown in Tables 1 to 3. The results are shown in Tables 1-3.

Example 26
Using the same materials and methods as in Example 1, a field effect transistor was manufactured and evaluated in the manufacturing process of FIG.
Specifically, the gate electrode 903 is formed over the support substrate 901 (FIG. 7A), the gate insulating film 905 is formed so as to cover the gate electrode 903, and the non-coated over the formed gate insulating film 905. A crystalline oxide film 907 was formed (FIG. 7B). The amorphous oxide film 907 was crystallized by heat treatment to form a semiconductor layer 907 ′ (FIG. 7C). Subsequently, a first protective film 911 was formed (FIG. 7D). A resist 915 was stacked on the first protective film 911 ((FIG. 7E)).
The laminated body was exposed from the support substrate 901 side using the gate electrode 903 as a mask and the resist was removed (part numbered 915b), and the resist was patterned ((FIGS. 7 (f) and (g)), numbered 915a. ). After patterning the resist, the first protective film 911 was etched, the first protective film 911 was patterned, and the resist 915a was removed (FIG. 7H). The first protective film was etched by wet etching using a hydrofluoric acid-based etchant.
A part of the semiconductor layer 907 ′ was reduced in resistance, and a channel portion 909 and source / drain portions 907a and 907b were formed in the semiconductor layer. Further, a second protective film 917 was formed (FIG. 7 (i)). Next, a source / drain electrode 919 is formed through the contact hole to form a field effect transistor (FIG. 7J).
Note that SiOx was formed by PECVD as the first protective film, and SiNx: H was formed by PECVD as the second protective film. At that time, the resistance of the semiconductor layer was lowered simultaneously with SiNx: H by PECVD to form a source part and a drain part.
The results are shown in Table 1.

  In the above embodiment, the moisture resistance of Examples 2 and 26 was improved compared to Example 1. This is considered to be an effect of stacking SiNx: H as the second protective film.

In Example 5, the SiO ₂ film 16a was formed and the substrate was heat-treated at a temperature of 300 ° C. for 1 hour (FIG. 2a (e)), and then the X-ray diffraction of the semiconductor layer 13 was measured. The results are shown in FIG. In FIG. 8, A is an X-ray diffraction chart, and B is a JCPDS card no. The pattern of 06-0416 is shown. The range of the measurement angle (2θ) is 10 to 42 °.
The amorphous film of the semiconductor layer was crystallized to be a crystalline film having a rare earth oxide C-type crystal structure (JCPDS card No. 06-0416). The β-Ga ₂ O ₃ structure (JCPDS card No. 43-1012) and β-GaInO ₃ structure (JCPDS card No. 21-0334) were not confirmed.

Comparative Examples 1-4
A field effect transistor was fabricated and evaluated in the same manner as in Example 1 except that the composition of the semiconductor layer was changed as shown in Table 4 and the protective layer 16 was formed by lift-off. The results are shown in Table 4. The semiconductor layer was not resistant to hydrofluoric acid etching solution.

Comparative Example 5
A field effect transistor was manufactured by the process shown in FIG.
First, an IGZO film that is the channel layer 11 is formed on the substrate 10 by patterning. Next, a gate insulating layer 12 is deposited. Further, the gate electrode 11 is formed by patterning. Further, as a hydrogen addition step, hydrogen is added by hydrogen plasma treatment using a plasma treatment apparatus. The hydrogen plasma treatment can be performed using a parallel plate type plasma CVD apparatus or an RIE type plasma etching apparatus. By implanting into the hydrogen oxide thin film using the gate electrode 11 as a mask (FIG. 9A), a source region 14 ′ and a drain region 15 ′ are formed (FIG. 9B). Thereafter, annealing treatment was performed in order to homogenize the amount of hydrogen.
Thereafter, an insulating layer 17 ′, a source electrode 14, and a drain electrode 15 were formed to produce a field effect transistor (FIG. 9C). The results are shown in Table 4.
This is probably because the TFT characteristics were low overall, and hydrogen diffused into the oxide semiconductor.

Comparative Example 6
A field effect transistor was manufactured by the process shown in FIG.
First, the drain electrode 14 and the source electrode 15 are formed on the glass substrate 10 (FIG. 10A).
After forming the gate insulating layer 12, an IGZO film and a Y ₂ O ₃ film 13 to be a gate insulating film are formed (FIG. 10B).

  A positive resist 21 is applied thereon, and then the positive resist 21 is exposed with light having a wavelength of 436 nm through a pattern of a source / drain electrode made of a gold film from the back side of the substrate (FIG. 10C).

  After the post-baking, development is performed to remove the resist where the gate electrode 11 is to be formed (FIG. 10D).

Next, Ni film 11 'is vapor-deposited as 80 nm as the gate electrode 11 (FIG.10 (e)).
Thereafter, the resist film is removed by a lift-off process to obtain a gate electrode having a position and shape aligned with the ends of the previously formed source / drain electrodes (FIG. 10 (f)).
From the cross-sectional observation of the completed field effect transistor, the overlapping width L of the source electrode 14, the drain electrode 15 and the gate electrode 11 was 0.5 μm.

Comparative Example 7
The composition of the semiconductor layer is such that the atomic ratio [In / (In + Ga + Zn)] is 0.4, the atomic ratio [Ga / (In + Ga + Zn)] is 0.4, and the atomic ratio [Zn / (In + Ga + Zn)] is 0.2. Tried producing a field effect transistor in the same manner as in Example 1.
As a result, unlike Example 1, the semiconductor layer 13 (amorphous film) remained an amorphous film even after heat treatment at a temperature of 300 ° C. for 1 hour (confirmed by X-ray diffraction). This amorphous film had an etching rate with respect to a hydrofluoric acid etching solution higher than that of silicon oxide (SiOx). For this reason, when the protective layer is formed by wet etching after the back exposure, even the semiconductor layer has melted. Therefore, a field effect transistor could not be manufactured.

Comparative Example 8
The composition of the semiconductor layer is such that the atomic ratio [In / (In + Ga + Zn)] is 0.34, the atomic ratio [Ga / (In + Ga + Zn)] is 0.33, and the atomic ratio [Zn / (In + Ga + Zn)] is 0.33. Tried producing a field effect transistor in the same manner as in Example 1.
As a result, a field effect transistor could not be produced for the same reason as in Comparative Example 7.

Comparative Example 9
A field effect transistor was fabricated in the same manner as in Example 1 except that zinc oxide (ZnO) was used for the semiconductor layer.
As a result, unlike Example 1, the semiconductor layer was a polycrystalline film from the time of film formation, and remained a polycrystalline film even after heat treatment at 300 ° C. for 1 hour. This polycrystalline film had an etching rate with respect to a hydrofluoric acid etching solution higher than that of silicon oxide (SiOx). For this reason, when the protective layer is formed by wet etching after the back exposure, even the semiconductor layer has melted. Therefore, a field effect transistor could not be manufactured.

  The field effect transistor of the present invention is suitable for a display substrate including a driver circuit. It is particularly suitable for gate driver circuits such as shift registers.

It is a schematic sectional drawing of one Embodiment of the field effect transistor of this invention. It is process drawing for demonstrating one Embodiment of the manufacturing method of the semiconductor element of this invention. It is process drawing for demonstrating one Embodiment of the manufacturing method of the semiconductor element of this invention. It is process drawing for demonstrating one Embodiment of the manufacturing method of the semiconductor element of this invention. It is a schematic sectional drawing of one Embodiment of the laminated body of this invention. FIG. It is a figure which shows the relationship between temperature and mobility of an oxide semiconductor. It is a figure which shows the relationship between the absorption coefficient of a semiconductor layer and an amorphous silicon layer of Example 1, and a wavelength. 6 is a schematic cross-sectional view of a field effect transistor produced in Example 3. FIG. FIG. 26 shows a manufacturing process for the field-effect transistor fabricated in Example 26. FIG. 26 shows a manufacturing process for the field-effect transistor fabricated in Example 26. 6 is an X-ray diffraction chart of a semiconductor layer manufactured in Example 5. FIG. 10 is a diagram showing a manufacturing process of a field-effect transistor of Comparative Example 5. FIG. 10 is a diagram illustrating a manufacturing process of the field effect transistor of Comparative Example 6. FIG.

DESCRIPTION OF SYMBOLS 10 Substrate 11 Gate electrode 12 Gate insulating film 13 Semiconductor layer 14 Source electrode 15 Drain electrode 16 First protective layer 17 Second protective layer 18 Contact hole 30 Laminate

Claims (18)

A semiconductor layer containing an oxide, and a protective layer for the semiconductor layer;
A field effect transistor in which an etching rate of the semiconductor layer with respect to A or B below is half or less of an etching rate of silicon oxide.
A: Wet etching solution containing 10% by mass of hydrofluoric acid B: Wet etching solution containing 15% by mass of ammonium fluoride   The field effect transistor according to claim 1, wherein the semiconductor layer is made of an oxide containing at least one element selected from In, Zn, Sn, and Ga.   The field effect transistor according to claim 1, wherein the semiconductor layer includes an oxide in a crystalline state.   The field effect transistor according to claim 1, wherein the semiconductor layer includes an oxide containing an In element and having a rare earth oxide C-type crystal structure.   The field effect transistor according to any one of claims 1 to 4, wherein the semiconductor layer is an oxide containing an In element and at least one kind of positive divalent element or at least one kind of positive trivalent element.   The field effect transistor according to any one of claims 1 to 5, wherein a cutoff frequency is 1 MHz or more.   A semiconductor element in which a semiconductor protective layer is formed using a gate electrode as a pattern.   The semiconductor element according to claim 7, wherein the semiconductor protective layer is formed by selective etching by wet etching.   9. The semiconductor device according to claim 8, wherein a wet etching solution containing hydrofluoric acid or ammonium fluoride is used for the wet etching.   The semiconductor element according to claim 9, which is a field effect transistor. Forming an oxide film containing at least one element selected from In, Zn, Sn and Ga;
Forming a protective layer on the oxide film using a gate electrode as a mask;
A method for manufacturing a field effect transistor, wherein a wet etching solution containing hydrofluoric acid or ammonium fluoride is used in an etching process for forming the protective layer. The method for manufacturing a field effect transistor according to claim 11, wherein an etching rate of the oxide film with respect to A or B below is half or less of an etching rate of silicon oxide.
A: Wet etching solution containing 10% by mass of hydrofluoric acid B: Wet etching solution containing 15% by mass of ammonium fluoride   The method of manufacturing a field effect transistor according to claim 11, wherein the oxide film is an oxide in a crystalline state.   A display substrate comprising a driver circuit having the field effect transistor according to claim 1.   The laminated body which has a 1st conductor layer, a 1st insulator layer, a semiconductor layer containing an oxide, a 2nd insulator layer, and a 2nd conductor layer in this order.   A field effect transistor comprising the laminate according to claim 15.   The first insulator layer is an oxide, the semiconductor layer containing the oxide is a polycrystalline oxide containing In and containing a rare earth oxide C-type crystal structure, and the second insulator layer is an oxide. The field effect transistor according to claim 16.   18. The field effect transistor according to claim 16, wherein the gate electrode and the protective layer of the semiconductor layer are self-aligned.

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