JPH0876144A - Production of thin film transistor - Google Patents
Production of thin film transistorInfo
- Publication number
- JPH0876144A JPH0876144A JP23228794A JP23228794A JPH0876144A JP H0876144 A JPH0876144 A JP H0876144A JP 23228794 A JP23228794 A JP 23228794A JP 23228794 A JP23228794 A JP 23228794A JP H0876144 A JPH0876144 A JP H0876144A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- electrode
- semiconductor layer
- pixel electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、薄膜トランジスタの製
造方法に関し、特にアクティブマトリクス型の液晶ディ
スプレイに用いられる薄膜トランジスタの製造方法に関
するものである。The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a method of manufacturing a thin film transistor used for an active matrix type liquid crystal display.
【０００２】[0002]
【従来の技術】薄膜トランジスタをスイッチング素子と
するアクティブマトリクス型の液晶ディスプレイは、階
調表示が可能で、高コントラスト比、高精細な表示を容
易に実現できることからＣＲＴに対抗しうるディスプレ
イ手段として盛んに開発が行われている。しかし、薄膜
トランジスタを用いたアクティブマトリクス型液晶ディ
スプレイは製造工程が複雑なことから価格的に高価にな
るという欠点がある。2. Description of the Related Art An active matrix type liquid crystal display using a thin film transistor as a switching element is capable of displaying gray scales, and can easily realize a high contrast ratio and a high definition display. Development is underway. However, an active matrix type liquid crystal display using a thin film transistor has a disadvantage that the manufacturing process is complicated and the price is expensive.
【０００３】図３は、従来の一般的に採用されている製
造方法（以下、これを第１の従来例という）を示す工程
順断面図である。まず、透明ガラス基板１上に、Ｃｒ、
Ａｌなどのゲート用金属膜を成膜し、フォトレジストを
塗付し、第１のマスクを用いて露光し現像した後、フォ
トレジストをマスクとしてゲート用金属膜をエッチング
してゲート電極４を形成する〔図３（ａ）〕。FIG. 3 is a sectional view in the order of steps showing a conventional and generally employed manufacturing method (hereinafter referred to as a first conventional example). First, on the transparent glass substrate 1, Cr,
A gate metal film such as Al is formed, a photoresist is applied, exposed and developed using a first mask, and then the gate metal film is etched using the photoresist as a mask to form a gate electrode 4. [FIG. 3 (a)].
【０００４】次に、シリコン窒化膜などからなるゲート
絶縁膜６、トランジスタの活性層となるノンドープのア
モルファスシリコン（以下、ａ−Ｓｉと記す）膜７およ
びこのａ−Ｓｉ膜７と金属配線のオーミックコンタクト
をとるためのｎ+ 型ａ−Ｓｉ膜８を、プラズマＣＶＤ法
により順次連続的に成膜する。次に、第２のマスクを用
いてフォトレジストパターンを形成し、ＲＩＥ（Reacti
ve Ion Etching）法などにより、ａ−Ｓｉ膜７、８をエ
ッチングしてゲート電極部上にのみ残るようにパターニ
ングする。続いて、第３のマスクを用いたフォトリソグ
ラフィ法により、周辺部配線の導通をとるために、選択
的にゲート絶縁膜６を除去する〔図３（ｂ）〕。Next, a gate insulating film 6 made of a silicon nitride film or the like, a non-doped amorphous silicon (hereinafter referred to as a-Si) film 7 serving as an active layer of a transistor, and an ohmic contact between the a-Si film 7 and a metal wiring. An n + -type a-Si film 8 for making a contact is formed sequentially and continuously by a plasma CVD method. Next, a photoresist pattern is formed by using a second mask, and RIE (Reacti
ve Ion Etching) method or the like, and the a-Si films 7 and 8 are etched and patterned so as to remain only on the gate electrode portion. Subsequently, the gate insulating film 6 is selectively removed by the photolithography method using the third mask to electrically connect the peripheral wiring [FIG. 3 (b)].
【０００５】次に、Ａｌなどの金属膜をスパッタ法など
により堆積し、これを第４のマスクを用いたフォトリソ
グラフィ工程によりパターニングしてソース電極９、ド
レイン電極１０を形成する〔図３（ｃ）〕。さらに、Ｉ
ＴＯなどからなる透明導電膜をスパッタ法などにより成
膜し、これを第５のマスクを用いたフォトリソグラフィ
法によりパターニングして画素電極５を形成する〔図３
（ｄ）〕。Next, a metal film such as Al is deposited by a sputtering method or the like, and is patterned by a photolithography process using a fourth mask to form a source electrode 9 and a drain electrode 10 (FIG. 3C). )]. Furthermore, I
A transparent conductive film made of TO or the like is formed by a sputtering method or the like and patterned by a photolithography method using a fifth mask to form the pixel electrode 5 [FIG.
(D)].
【０００６】次に、シリコン酸化膜などからなるパッシ
ベーション膜１１をプラズマＣＶＤ法あるいはスパッタ
法を用いて成膜し、第６のマスクを用いるフォトリソグ
ラフィ法により、画素電極上などの不要なパッシベーシ
ョン膜を除去して、従来法によるアクティブマトリクス
液晶ディスプレイ用の薄膜トランジスタの形成が完了す
る〔図５（ｅ）〕。Next, a passivation film 11 made of a silicon oxide film or the like is formed by a plasma CVD method or a sputtering method, and an unnecessary passivation film on a pixel electrode or the like is formed by a photolithography method using a sixth mask. After the removal, the formation of the thin film transistor for the active matrix liquid crystal display by the conventional method is completed [FIG. 5 (e)].
【０００７】以上のように、従来法による製造方法で
は、必要となるフォトマスクの枚数は６であり、またエ
ッチング工程数はチャネルエッチングを含めると７であ
る。このように従来法では、工程数が多くそのため製品
のコストアップを招いていた。そこで、この問題点を解
決すべくフォトリソグラフィ工程数を削減できる製造方
法がいくつか提案されている。As described above, in the conventional manufacturing method, the number of photomasks required is 6, and the number of etching steps is 7 when channel etching is included. As described above, in the conventional method, the number of steps is large, and thus the cost of the product is increased. In order to solve this problem, several manufacturing methods have been proposed that can reduce the number of photolithography steps.
【０００８】図４（ａ）〜（ｅ）は、特開平１−１３２
１６５号公報にて提案された製造方法（以下、これを第
２の従来例という）を説明するための工程順断面図であ
る。透明ガラス基板１上に、ＩＴＯ、ＳｎＯ2 などから
なる透明導電膜２およびＣｒ、Ａｌなどからなる金属膜
３をそれぞれスパッタ法などにより連続して成膜する。
次に、第１のマスクを用いたフォトリソグラフィ法によ
りこの２層膜をパターニングしてゲート電極４と画素電
極５を形成する〔図４（ａ）〕。FIGS. 4 (a) to 4 (e) show JP-A-1-132.
FIG. 16 is a cross-sectional view in order of the processes, for explaining the manufacturing method proposed in Japanese Patent No. 165 (hereinafter, referred to as second conventional example). On a transparent glass substrate 1, a transparent conductive film 2 made of ITO, SnO 2 or the like and a metal film 3 made of Cr, Al or the like are continuously formed by a sputtering method or the like.
Next, the gate electrode 4 and the pixel electrode 5 are formed by patterning this two-layer film by a photolithography method using a first mask (FIG. 4A).
【０００９】その後、プラズマＣＶＤ法により、シリコ
ン窒化膜からなるゲート絶縁膜６、ａ−Ｓｉ膜７および
ゲート絶縁膜と同じくシリコン窒化膜からなる保護絶縁
膜１２を連続的に成膜し、第２のマスクを用いたフォト
リソグラフィ法により、保護絶縁膜１２およびａ−Ｓｉ
膜７をパターニングして、ゲート電極４上にアイランド
状に残す〔図４（ｂ）〕。After that, a gate insulating film 6 made of a silicon nitride film, an a-Si film 7 and a protective insulating film 12 made of a silicon nitride film like the gate insulating film are successively formed by a plasma CVD method. Protective insulating film 12 and a-Si
The film 7 is patterned and left in an island shape on the gate electrode 4 (FIG. 4B).
【００１０】次に、第３のマスクを用いたフォトリソグ
ラフィ法により、ゲート絶縁膜６および保護絶縁膜１２
をパターニングして、画素電極上のゲート絶縁膜６を除
去するとともに、保護絶縁膜１２にａ−Ｓｉ膜７へのコ
ンタクトホールを形成する〔図４（ｃ）〕。その後、光
透過型の液晶表示を可能ならしめるために、画素電極部
の金属膜をエッチング除去する工程を追加し、透明な表
示電極を得る〔図４（ｄ）〕。Next, the gate insulating film 6 and the protective insulating film 12 are formed by photolithography using a third mask.
Is patterned to remove the gate insulating film 6 on the pixel electrode and to form a contact hole to the a-Si film 7 in the protective insulating film 12 (FIG. 4C). Then, in order to enable the light-transmissive liquid crystal display, a step of etching away the metal film of the pixel electrode portion is added to obtain a transparent display electrode [FIG. 4 (d)].
【００１１】続いて、ｎ+ 型ａ−Ｓｉ膜８およびＡｌな
どからなる金属膜を連続的に成膜する。これらの２層
を、第４のマスクを用いたフォトリソグラフィ工程によ
りパターニングして、一端がそれぞれａ−Ｓｉ膜７と接
続されたソース電極９と、ドレイン電極１０とを形成す
る。ソース電極９の他端は画素電極５に接続される〔図
４（ｅ）〕。以上のように、この第２の従来例によれ
ば、４回のフォトリソグラフィ工程により薄膜トランジ
スタを形成することができる。Subsequently, an n + type a-Si film 8 and a metal film made of Al or the like are continuously formed. These two layers are patterned by a photolithography process using a fourth mask to form a source electrode 9 and a drain electrode 10 each having one end connected to the a-Si film 7. The other end of the source electrode 9 is connected to the pixel electrode 5 (FIG. 4E). As described above, according to this second conventional example, a thin film transistor can be formed by four photolithography steps.
【００１２】また、特開昭６４−３１４５７号公報に
は、３回乃至４回のフォトリソグラフィ工程により薄膜
トランジスタを形成する方法（以下、これを第３の従来
例という）が開示されている。以下、その工程順断面図
である図５（ａ）〜（ｅ）を参照してこの第３の従来例
について説明する。透明ガラス基板１上に、ＩＴＯ、Ｓ
ｎＯ2 などからなる透明導電膜２およびＣｒ、Ａｌなど
からなる金属膜３をそれぞれスパッタ法などにより連続
して成膜する。次に、第１のマスクを用いたフォトリソ
グラフィ法によりこの２層膜をパターニングしてゲート
電極４と画素電極５を形成する〔図５（ａ）〕。Further, Japanese Patent Application Laid-Open No. 64-31457 discloses a method of forming a thin film transistor by a photolithography process three to four times (hereinafter referred to as a third conventional example). Hereinafter, the third conventional example will be described with reference to FIGS. ITO, S on transparent glass substrate 1
A transparent conductive film 2 made of nO 2 or the like and a metal film 3 made of Cr, Al or the like are continuously formed by a sputtering method or the like. Next, the gate electrode 4 and the pixel electrode 5 are formed by patterning the two-layer film by a photolithography method using a first mask (FIG. 5A).
【００１３】その後、プラズマＣＶＤ法などにより、シ
リコン窒化膜からなるゲート絶縁膜６、ａ−Ｓｉ膜７お
よびｎ+ 型ａ−Ｓｉ膜８を順次成膜する〔図５
（ｂ）〕。次に、第２のマスクを用いたフォトリソグラ
フィ法およびＲＩＥ法により、ａ−Ｓｉ膜７、８および
ゲート絶縁膜６を同時にパターニングしてゲート電極４
上にアイランド状の半導体層を形成する。この際、画素
電極５の表面も露出される〔図５（ｃ）〕。Thereafter, a gate insulating film 6 made of a silicon nitride film, an a-Si film 7 and an n + -type a-Si film 8 are sequentially formed by a plasma CVD method or the like (FIG. 5).
(B)]. Next, the a-Si films 7 and 8 and the gate insulating film 6 are simultaneously patterned by the photolithography method and the RIE method using the second mask to form the gate electrode 4.
An island-shaped semiconductor layer is formed thereon. At this time, the surface of the pixel electrode 5 is also exposed [FIG. 5 (c)].
【００１４】その後、Ａｌなどからなる金属膜を蒸着法
などにより成膜し、第３のマスクを用いたフォトリソグ
ラフィ法によりパターニングしてソース電極９とドレイ
ン電極１０を形成する。さらに、画素電極５の金属膜３
を除去し、続いて、ａ−Ｓｉ膜７上の露出しているｎ+
型ａ−Ｓｉ膜８を除去する〔図５（ｄ）〕。Thereafter, a metal film made of Al or the like is formed by a vapor deposition method or the like, and is patterned by a photolithography method using a third mask to form a source electrode 9 and a drain electrode 10. Further, the metal film 3 of the pixel electrode 5
Is removed, and then the exposed n + on the a-Si film 7 is removed.
The mold a-Si film 8 is removed (FIG. 5D).
【００１５】以上の工程により、薄膜トランジスタは形
成できたことになるが、信頼性上の問題および液晶ディ
スプレイに応用する場合、光遮蔽を行う必要があること
からパッシベーション膜１１と光遮蔽膜１３を成膜し、
第４のマスクを用いたフォトリソグラフィ法により光遮
蔽膜をパターニングして、第３の従来例による製造は完
了する〔図４（ｅ）〕。Although the thin film transistor can be formed by the above steps, the passivation film 11 and the light shielding film 13 are formed because light shielding is required in the case of reliability and application to a liquid crystal display. Membrane
The light shielding film is patterned by the photolithography method using the fourth mask, and the manufacturing according to the third conventional example is completed (FIG. 4E).
【００１６】[0016]
【発明が解決しようとする課題】上述の一般的に採用さ
れている第１の従来例では、６回ものフォトリソグラフ
ィ工程が必要となり、製造工程が複雑でコスト低減が困
難であるという問題点があった。また、第２の従来例で
は、フォトリソグラフィ工程は４回と少なくなっている
が、透明な表示電極を得るために画素電極部の金属膜の
エッチング工程を追加する必要があり、製造工程が複雑
になる問題点があった。この点については、第３の従来
例も同様である。The above-mentioned generally adopted first conventional example has a problem that the photolithography process is required six times, the manufacturing process is complicated, and cost reduction is difficult. there were. Further, in the second conventional example, the number of photolithography steps is reduced to four times, but it is necessary to add an etching step of a metal film of a pixel electrode portion to obtain a transparent display electrode, which complicates the manufacturing process. There was a problem. This is the same in the third conventional example.
【００１７】また、第３の従来例では、トランジスタの
活性層であるａ−Ｓｉ膜の大きさがゲート絶縁膜の大き
さと等しいため、必然的にａ−Ｓｉ膜の大きさがゲート
電極より広くなりゲート電極による遮光効果が減殺さ
れ、さらにａ−Ｓｉ膜が必要以上に広くなるためリーク
電流が増大して表示品質が低下するという問題があっ
た。また、このようなａ−Ｓｉ膜がゲート電極を覆う構
造では、ａ−Ｓｉ膜が画素電極など他の領域との短絡し
やすく高歩留りで製造することが困難である。Further, in the third conventional example, since the size of the a-Si film which is the active layer of the transistor is equal to the size of the gate insulating film, the size of the a-Si film is necessarily wider than that of the gate electrode. Therefore, there is a problem that the light shielding effect by the gate electrode is diminished, and the a-Si film becomes wider than necessary, so that the leak current increases and the display quality deteriorates. In such a structure in which the a-Si film covers the gate electrode, the a-Si film is easily short-circuited to another region such as a pixel electrode, and it is difficult to manufacture the a-Si film at a high yield.
【００１８】本発明は、このような状況に鑑みてなされ
たものであって、その目的は、液晶ディスプレイの表示
品質を犠牲にすることなく真に製造工程数を削減してコ
ストダウンと歩留りの向上を図ることのできる薄膜トラ
ンジスタの製造方法を提供することである。SUMMARY OF THE INVENTION The present invention has been made in view of such circumstances, and has as its object to reduce the number of manufacturing steps without sacrificing the display quality of a liquid crystal display, thereby reducing costs and yield. An object of the present invention is to provide a method for manufacturing a thin film transistor which can be improved.
【００１９】[0019]
【課題を解決するための手段】上記目的を達成するた
め、本発明によれば、（１）透明基板上に透明導電膜お
よび第１の金属膜を堆積する工程と、（２）前記第１の
金属膜および透明導電膜をパターニングしてゲート電極
および第１の金属膜に被覆された画素電極を形成する工
程〔図１（ａ）〕と、（３）全面にゲート絶縁膜、高比
抵抗半導体層および低比抵抗半導体層を順次堆積する工
程と、（４）高比抵抗半導体層および低比抵抗半導体層
をパターニングして前記ゲート電極上に島状の半導体層
を形成する工程〔図１（ｂ）〕と、（５）前記画素電極
上の前記ゲート絶縁膜をエッチング除去する工程〔図１
（ｃ）〕と、（６）全面に第２の金属膜を堆積する工程
と、（７）前記第２の金属膜をパターニングしてソース
電極およびドレイン電極を形成するとともに前記画素電
極上の第１の金属膜を除去する工程〔図１（ｄ）〕と、
を有する薄膜トランジスタの製造方法、が提供される。In order to achieve the above object, according to the present invention, (1) a step of depositing a transparent conductive film and a first metal film on a transparent substrate, and (2) the first step. Patterning the metal film and the transparent conductive film to form a gate electrode and a pixel electrode covered with the first metal film [FIG. 1 (a)], and (3) a gate insulating film and a high specific resistance over the entire surface. A step of sequentially depositing a semiconductor layer and a low-resistivity semiconductor layer; and (4) a step of patterning the high-resistivity semiconductor layer and the low-resistivity semiconductor layer to form an island-shaped semiconductor layer on the gate electrode [FIG. (B)] and (5) a step of etching away the gate insulating film on the pixel electrode [FIG.
(C)], (6) depositing a second metal film on the entire surface, and (7) patterning the second metal film to form a source electrode and a drain electrode, and a second electrode on the pixel electrode. A step of removing the metal film of No. 1 [FIG. 1 (d)],
A method of manufacturing a thin film transistor having:
【００２０】[0020]
【実施例】次に、本発明の実施例について図面を参照し
て説明する。 ［第１の実施例］図１を参照して本発明の第１の実施例
について説明する。なお、図１は、第１の実施例の製造
工程を順に示した工程断面図である。まず、透明ガラス
基板１上にスパッタ法などによりＩＴＯなどの透明導電
膜２を１００〜５００Åの厚さに、Ｃｒ、Ａｌなどから
なる金属膜３を１０００〜３０００Åの厚さに連続的に
堆積する。次いで、第１のマスクを用いたフォトリソグ
ラフィ法により、この２層膜のパターニングを行ない、
ゲート電極４と金属膜３に被覆された画素電極５とを同
時に形成する〔図１（ａ）〕。Embodiments of the present invention will now be described with reference to the drawings. [First Embodiment] A first embodiment of the present invention will be described with reference to FIG. 1A to 1C are process cross-sectional views sequentially showing the manufacturing process of the first embodiment. First, a transparent conductive film 2 of ITO or the like and a metal film 3 of Cr, Al or the like are continuously deposited on the transparent glass substrate 1 by sputtering or the like to a thickness of 100 to 500 ° and a thickness of 1000 to 3000 °. . Next, this two-layer film is patterned by a photolithography method using a first mask,
The gate electrode 4 and the pixel electrode 5 covered with the metal film 3 are simultaneously formed [FIG. 1 (a)].
【００２１】次に、プラズマＣＶＤ法などにより、シリ
コン窒化膜などからなるゲート絶縁膜６を２０００〜４
０００Åの厚さに、ノンドープのａ−Ｓｉ膜７を２００
〜１０００Åの厚さに、ｎ+ 型ａ−Ｓｉ膜８を３０〜１
５０Åの厚さに連続的に成膜する。続いて、第２のマス
クを用いたフォトリソグラフィ法により、ｎ+ 型ａ−Ｓ
ｉ膜８およびａ−Ｓｉ膜７をパターニングしてゲート電
極４上にアイランド状に残す〔図１（ｂ）〕。Next, a gate insulating film 6 made of a silicon nitride film or the like is formed by a plasma CVD method or the like.
A non-doped a-Si film 7 having a thickness of
The n + type a-Si film 8 to a thickness of about 1000 Å 30 to 1
The film is continuously formed to a thickness of 50Å. Subsequently, the n + -type aS
The i film 8 and the a-Si film 7 are patterned and left on the gate electrode 4 in an island shape [FIG. 1 (b)].
【００２２】次に、第３のマスクを用いたフォトリソグ
ラフィ法により、ゲート絶縁膜６を選択的にエッチング
して、画素電極５上の金属膜を露出させる開口を形成す
る〔図１（ｃ）〕。その後、Ｃｒ、Ａｌなどの、金属膜
３と同一材料からなる金属膜を１０００〜３０００Åの
膜厚に堆積し、これを第４のマスクを用いたフォトリソ
グラフィ法によりパターニングして、ソース電極９とド
レイン電極１０を形成する。このとき、同時にゲート絶
縁膜の開口部に露出している金属膜３もエッチング除去
して透明な表示電極を得る〔図１（ｄ）〕。Next, the gate insulating film 6 is selectively etched by photolithography using a third mask to form an opening exposing the metal film on the pixel electrode 5 (FIG. 1C). ]. After that, a metal film made of the same material as the metal film 3 such as Cr or Al is deposited to a thickness of 1000 to 3000 °, and this is patterned by a photolithography method using a fourth mask, so that the source electrode 9 The drain electrode 10 is formed. At this time, the metal film 3 exposed at the opening of the gate insulating film is also removed by etching to obtain a transparent display electrode [FIG. 1 (d)].
【００２３】次に、チャネルエッチングを行って、露出
しているｎ+ 型ａ−Ｓｉ膜８を除去する。次いで、薄膜
トランジスタ特性の安定化処理として４００Ｐａ程度の
圧力にした真空チャンバー内に基板を装着し、Ｈ2 ガス
を充満させ、０．０２Ｗ／ｃｍ2 程度の放電を２０秒程
度行い、剥きだしになったバックチャネル部を処理す
る。その後、さらに２００℃で１時間程度のアニールを
行う。Next, the exposed n + -type a-Si film 8 is removed by channel etching. Next, as a process for stabilizing the characteristics of the thin film transistor, the substrate was mounted in a vacuum chamber at a pressure of about 400 Pa, filled with H 2 gas, and discharged at about 0.02 W / cm 2 for about 20 seconds, thereby exfoliating. Process the back channel part. Thereafter, annealing is further performed at 200 ° C. for about 1 hour.
【００２４】以上により本実施例による製造工程が完了
するが、本実施例では、必要なフォトリソグラフィ工程
の回数は４となっており、そしてソース・ドレイン電極
のパターニング工程が画素電極上の金属膜の除去工程を
かねているため、工程が簡素化されている。また、アイ
ランド状のａ−Ｓｉ膜をゲート電極４よりも十分に小さ
く形成することができるため、ゲート電極による遮光効
果を十分に享受することができる。The manufacturing process according to this embodiment is completed as described above. In this embodiment, the required number of photolithography processes is four, and the patterning process of the source / drain electrodes is performed by the metal film on the pixel electrode. , The process is simplified. Further, since the island-shaped a-Si film can be formed sufficiently smaller than the gate electrode 4, the light shielding effect of the gate electrode can be fully enjoyed.
【００２５】［第２の実施例］次に、本発明の第２の実
施例について説明する。本実施例では、図１（ｃ）に示
す状態に加工した後、金属膜を被着し、この金属膜のパ
ターニングと画素電極上の金属膜の除去とを同時に行う
（ここまでの工程は第１の実施例の場合と同様であ
る）。[Second Embodiment] Next, a second embodiment of the present invention will be described. In the present embodiment, after processing to the state shown in FIG. 1C, a metal film is applied, and patterning of this metal film and removal of the metal film on the pixel electrode are performed simultaneously (the steps up to this point are This is the same as in the first embodiment).
【００２６】続いて、基板をバッファードフッ酸に３０
秒程度浸漬する。その後、チャネルエッチングを行い、
さらに、２００℃で１時間程度のアニールを行う。以上
のフッ酸処理およびアニールは薄膜トランジスタ特性の
安定化のために行うものである。Subsequently, the substrate was placed in buffered hydrofluoric acid for 30 minutes.
Soak for about a second. After that, channel etching is performed,
Further, annealing is performed at 200 ° C. for about 1 hour. The above hydrofluoric acid treatment and annealing are performed for stabilizing the thin film transistor characteristics.
【００２７】［第３の実施例］次に、本発明の第３の実
施例について説明する。本実施例では、図１（ｄ）に示
す状態までは、第１の実施例と同様の工程を行い、その
後、図２に示されるように、プラズマＣＶＤ法等によ
り、シリコン窒化膜、シリコン酸化膜などからなるパッ
シベーション膜１１を１０００〜３０００Åの膜厚に堆
積し、第５のマスクを用いたフォトリソグラフィ法を適
用して画素電極部の窓開けを行う。本実施例では、フォ
トリソグラフィ工程は１回増えて５回となるが、製品の
耐久性をより向上させることができる。Third Embodiment Next, a third embodiment of the present invention will be described. In this embodiment, steps similar to those in the first embodiment are performed until the state shown in FIG. 1D, and thereafter, as shown in FIG. 2, a silicon nitride film and a silicon oxide film are formed by a plasma CVD method or the like. A passivation film 11 made of a film or the like is deposited to a film thickness of 1000 to 3000Å, and a window of the pixel electrode portion is opened by applying a photolithography method using a fifth mask. In this embodiment, the number of photolithography steps is increased by one to five, but the durability of the product can be further improved.
【００２８】[0028]
【発明の効果】以上説明したように、本発明による薄膜
トランジスタの製造方法は、ゲート電極と金属膜によっ
て被覆された画素電極とを同時に形成しておき、ソース
・ドレイン電極形成時に画素電極上に形成された金属膜
を同時に除去するものであるので、パッシベーション膜
を形成しないのであれば、４回のフォトリソグラフィ工
程と、より少ないエッチング工程により薄膜トランジス
タを形成することができるため、製造工程の簡素化を実
現することができ、それにともない製造歩留りの向上と
コストの削減を図ることができる。As described above, in the method of manufacturing a thin film transistor according to the present invention, a gate electrode and a pixel electrode covered with a metal film are simultaneously formed, and the gate electrode and the pixel electrode are formed on the pixel electrode when forming the source / drain electrodes. If the passivation film is not formed, the thin film transistor can be formed by four photolithography steps and a smaller number of etching steps, so that the manufacturing process can be simplified. Accordingly, the production yield can be improved and the cost can be reduced.
【００２９】また、薄膜トランジスタの活性層であるａ
−Ｓｉ膜をゲート電極上にこれより狭く形成することが
できるため、ａ−Ｓｉ膜と画素電極などとの短絡を防止
することができる。さらに、ゲート電極によって活性層
の遮光を行うことができるため、リーク電流を抑制して
高い表示品質の画像を得ることができる。Further, a which is the active layer of the thin film transistor
Since the -Si film can be formed narrower than the gate electrode, a short circuit between the a-Si film and the pixel electrode can be prevented. Further, since the active layer can be shielded by the gate electrode, leak current can be suppressed and an image with high display quality can be obtained.
【図１】 本発明の第１の実施例の製造方法を説明する
ための工程順断面図。FIG. 1 is a cross-sectional view in a process order for describing a manufacturing method according to a first embodiment of the present invention.
【図２】 本発明の第３の実施例の製造方法を説明する
ための断面図。FIG. 2 is a cross-sectional view for explaining a manufacturing method according to a third embodiment of the present invention.
【図３】 第１の従来例の製造方法を説明するための工
程順断面図。3A to 3C are cross-sectional views in order of the processes, for illustrating a manufacturing method of a first conventional example.
【図４】 第２の従来例の製造方法を説明するための工
程順断面図。FIG. 4 is a process order sectional view for explaining a manufacturing method of a second conventional example.
【図５】 第３の従来例の製造方法を説明するための工
程順断面図。5A to 5C are cross-sectional views in order of the processes, for illustrating a manufacturing method of a third conventional example.
１ 透明ガラス基板 ２ 透明導電膜 ３ 金属膜 ４ ゲート電極 ５ 画素電極 ６ ゲート絶縁膜 ７ ａ−Ｓｉ膜 ８ ｎ+ 型ａ−Ｓｉ膜 ９ ソース電極 １０ ドレイン電極 １１ パッシベーション膜 １２ 保護絶縁膜 １３ 光遮蔽膜DESCRIPTION OF SYMBOLS 1 Transparent glass substrate 2 Transparent conductive film 3 Metal film 4 Gate electrode 5 Pixel electrode 6 Gate insulating film 7 a-Si film 8 n + type a-Si film 9 Source electrode 10 Drain electrode 11 Passivation film 12 Protective insulating film 13 Light shielding film
Claims (4)
１の金属膜を堆積する工程と、 （２）前記第１の金属膜および透明導電膜をパターニン
グしてゲート電極および第１の金属膜に被覆された画素
電極を形成する工程と、 （３）全面にゲート絶縁膜、高比抵抗半導体層および低
比抵抗半導体層を順次堆積する工程と、 （４）低比抵抗半導体層および高比抵抗半導体層をパタ
ーニングして前記ゲート電極上に島状の半導体層を形成
する工程と、 （５）前記画素電極上の前記ゲート絶縁膜をエッチング
除去する工程と、 （６）全面に第２の金属膜を堆積する工程と、 （７）前記第２の金属膜をパターニングしてソース電極
およびドレイン電極を形成するとともに前記画素電極上
の第１の金属膜を除去する工程と、を有することを特徴
とする薄膜トランジスタの製造方法。1. A step of depositing a transparent conductive film and a first metal film on a transparent substrate, and (2) patterning the first metal film and the transparent conductive film to form a gate electrode and a first metal film. A step of forming a pixel electrode covered with a metal film, (3) a step of sequentially depositing a gate insulating film, a high specific resistance semiconductor layer and a low specific resistance semiconductor layer on the entire surface, and (4) a low specific resistance semiconductor layer and Patterning the high-resistivity semiconductor layer to form an island-shaped semiconductor layer on the gate electrode; (5) etching the gate insulating film on the pixel electrode; And (7) patterning the second metal film to form source and drain electrodes and removing the first metal film on the pixel electrode. Characterized by thin Manufacturing method of membrane transistor.
膜を同一の金属材料により形成することをことを特徴と
する請求項１記載の薄膜トランジスタの製造方法。2. The method of manufacturing a thin film transistor according to claim 1, wherein the first metal film and the second metal film are formed of the same metal material.
る低比抵抗半導体層をエッチング除去し、続いて、水素
プラズマ中で処理を行うことを特徴とする請求項１記載
の薄膜トランジスタの製造方法。3. The thin film transistor according to claim 1, wherein after the step (7), the exposed low-resistivity semiconductor layer is removed by etching, followed by treatment in hydrogen plasma. Manufacturing method.
ドフッ酸にて処理し、続いて露出している低比抵抗半導
体層をエッチング除去することを特徴とする請求項１記
載の薄膜トランジスタの製造方法。4. The thin film transistor according to claim 1, wherein after the step (7), a treatment with buffered hydrofluoric acid is performed, and subsequently, the exposed low resistivity semiconductor layer is removed by etching. Manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23228794A JP2639356B2 (en) | 1994-09-01 | 1994-09-01 | Method for manufacturing thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23228794A JP2639356B2 (en) | 1994-09-01 | 1994-09-01 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0876144A true JPH0876144A (en) | 1996-03-22 |
| JP2639356B2 JP2639356B2 (en) | 1997-08-13 |
Family
ID=16936861
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23228794A Expired - Lifetime JP2639356B2 (en) | 1994-09-01 | 1994-09-01 | Method for manufacturing thin film transistor |
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| Country | Link |
|---|---|
| JP (1) | JP2639356B2 (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1174537A (en) * | 1997-08-26 | 1999-03-16 | Lg Electron Inc | Thin-film transistor and its production |
| KR20000039794A (en) * | 1998-12-16 | 2000-07-05 | 김영환 | Method for manufacturing liquid crystal display device with high aperture rate and high transparency |
| JP2004153171A (en) * | 2002-10-31 | 2004-05-27 | Sony Corp | Method for patterning transparent conductive film |
| JP2005252293A (en) * | 1996-06-26 | 2005-09-15 | Siemens Ag | Semiconductor light emitting element |
| KR100601171B1 (en) * | 1999-07-08 | 2006-07-13 | 삼성전자주식회사 | Thin film transistor substrate for liquid crystal display and manufacturing method thereof |
| KR100696264B1 (en) * | 2000-04-27 | 2007-03-16 | 엘지.필립스 엘시디 주식회사 | Method of Fabricating Thin Film Transistor |
| CN100359397C (en) * | 2004-08-09 | 2008-01-02 | 广辉电子股份有限公司 | Pixel structure of thin film transistor LCD and manufacturing method thereof |
| CN100386689C (en) * | 2004-07-12 | 2008-05-07 | 友达光电股份有限公司 | Liquid crystal display picture element structure and manufacturing method thereof and liquid crystal display panel |
| JP2008129314A (en) * | 2006-11-21 | 2008-06-05 | Hitachi Displays Ltd | Image display device and manufacturing method thereof |
| CN100397225C (en) * | 2004-06-05 | 2008-06-25 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN100407035C (en) * | 2004-06-05 | 2008-07-30 | 乐金显示有限公司 | Liquid crystal display device and fabricating method thereof |
| GB2451151A (en) * | 2007-07-20 | 2009-01-21 | Lg Philiph Lcd Co Ltd | LCD array substrate with semiconductor layer lying within gate electrode boundary |
| JP2009071289A (en) * | 2007-08-17 | 2009-04-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device, and manufacturing method thereof |
| JP2009231824A (en) * | 2008-02-29 | 2009-10-08 | Semiconductor Energy Lab Co Ltd | Thin-film transistor and display device |
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|---|---|---|---|---|
| JP2005252293A (en) * | 1996-06-26 | 2005-09-15 | Siemens Ag | Semiconductor light emitting element |
| JPH1174537A (en) * | 1997-08-26 | 1999-03-16 | Lg Electron Inc | Thin-film transistor and its production |
| KR20000039794A (en) * | 1998-12-16 | 2000-07-05 | 김영환 | Method for manufacturing liquid crystal display device with high aperture rate and high transparency |
| KR100601171B1 (en) * | 1999-07-08 | 2006-07-13 | 삼성전자주식회사 | Thin film transistor substrate for liquid crystal display and manufacturing method thereof |
| KR100696264B1 (en) * | 2000-04-27 | 2007-03-16 | 엘지.필립스 엘시디 주식회사 | Method of Fabricating Thin Film Transistor |
| JP2004153171A (en) * | 2002-10-31 | 2004-05-27 | Sony Corp | Method for patterning transparent conductive film |
| KR100938886B1 (en) * | 2003-06-30 | 2010-01-27 | 엘지디스플레이 주식회사 | Method of fabricating array substrate for Liquid Crystal Display Device with driving circuit |
| CN100397225C (en) * | 2004-06-05 | 2008-06-25 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN100407035C (en) * | 2004-06-05 | 2008-07-30 | 乐金显示有限公司 | Liquid crystal display device and fabricating method thereof |
| CN100386689C (en) * | 2004-07-12 | 2008-05-07 | 友达光电股份有限公司 | Liquid crystal display picture element structure and manufacturing method thereof and liquid crystal display panel |
| CN100359397C (en) * | 2004-08-09 | 2008-01-02 | 广辉电子股份有限公司 | Pixel structure of thin film transistor LCD and manufacturing method thereof |
| JP2008129314A (en) * | 2006-11-21 | 2008-06-05 | Hitachi Displays Ltd | Image display device and manufacturing method thereof |
| GB2451151A (en) * | 2007-07-20 | 2009-01-21 | Lg Philiph Lcd Co Ltd | LCD array substrate with semiconductor layer lying within gate electrode boundary |
| GB2451151B (en) * | 2007-07-20 | 2011-02-09 | Lg Philips Lcd Co Ltd | Array substrate for liquid crystal display device and method of fabricating the same |
| US8045078B2 (en) | 2007-07-20 | 2011-10-25 | Lg Display Co., Ltd. | Array substrate for liquid crystal display device and method of fabricating the same |
| JP2009071289A (en) * | 2007-08-17 | 2009-04-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device, and manufacturing method thereof |
| JP2009231824A (en) * | 2008-02-29 | 2009-10-08 | Semiconductor Energy Lab Co Ltd | Thin-film transistor and display device |
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