JPS6284563A - Manufacture of thin-film field-effect transistor array - Google Patents

Abstract

PURPOSE:To prevent plasma damage at the time of formation through a plasma CVD method by covering an ITO film for a display electrode with a metallic film during the time when a thin-film field-effect transistor is shaped. CONSTITUTION:An indium-tin oxide film (an ITO film) 2 is formed onto a glass substrate 1 as a display electrode. A chromium film 3 is shaped onto the ITO film as a gate electrode. The superposed ITO and chromium two layer films are processed to the predetermined shapes of the gate electrode 4 and the display electrode 5 through photolithographic-etching. An silicon nitride film 6 as a gate insulating layer, an amorphous silicon film 7 as a semiconductor layer and a phorus-doped N<+> amorphous silicon film 8 as an ohmic contact layer are formed continuously by using a three-chamber in-line type plasma CVD device. Lastly, a chromium film for the gate electrode coated onto a display electrode 13, a chromium film for drain-source electrode and an silicon nitride film as a protective film are removed through photolithographic-etching.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a thin film field effect transistor layer.

[Conventional technology]

Since an amorphous silicon film can be formed on a glass substrate at a relatively low temperature by the plasma CVD method, thin-wall field effect transistor arrays using this film are being developed and put into practical use for active matrix liquid crystal displays. This thin film field effect transistor array is
Gate pass lines and drain pass lines are formed in a matrix, and a thin film field effect transistor is provided at the intersection of these lines.The structure of this transistor is an inverted staggered structure in which the gate electrode is on the bottom layer and the drain and source electrodes are on the top layer. A staggered structure in which the gate insulating layer is the upper layer and the drain/source electrodes are the lower layer has been proposed. A display electrode pad is connected to the source electrode of both transistor structures.

A plated Injem tin film formed by sputtering is used for the display electrode, and the thickness of this film is approximately 0.1 μm in view of both transparency and film resistance requirements.

[Problems to be solved by the invention] The conventional method for manufacturing a U film field effect transistor play is as follows:
A manufacturing method in which a display electrode is formed into a pattern after forming a thin film field effect transistor, and a manufacturing method in which a film is formed into a pattern before formation of a four-layer field effect transistor are included.

The problem with the former manufacturing method is that there are restrictions on the conditions for forming the injem tin oxide (ITO) film in order to avoid damaging the characteristics of the thin film field effect transistor. The substrate temperature during film formation must be kept low, and the sputtering power must also be kept low. This restriction not only adversely affects the transparency and film resistance of the canopy, but also causes deterioration of ITO during the assembly process of the active matrix liquid crystal panel and during the life of the panel. In addition, since the ITO layer is as thin as 0.1 μm, there is a problem in that the thin film field effect transistor is prone to breakage due to uneven steps.

On the other hand, a problem with the latter manufacturing method is that the ITO [
However, when an amorphous silicon film and a gate insulating film are formed by plasma CVD, defects such as reduction and devitrification due to H2 gas are likely to occur. Normally, to avoid this problem, the power during film formation is lowered or the substrate temperature is lowered, but this has a negative effect on the characteristics of the thin film field effect transistor. In particular, a decrease in 1 mobility and an increase in the amount of drift of the threshold voltage vT occur.

An object of the present invention is to provide a method for manufacturing a thin film field effect transistor array that solves problems such as devitrification, decreased mobility, increased drift, etc., using the same number of flanges as the conventional method or a simpler process. There is a thing called LC.

[Means for solving problems]

A method for manufacturing a thin film field effect transistor array according to the first invention of the present application includes a step of forming a conductive film for a display electrode on a glass substrate, a step of forming a metal film for a gate electrode on the conductive film, and a step of forming a metal film for a gate electrode on the conductive film. a step of selectively etching the metal film to form a gate electrode and a display electrode; a step of depositing a gate insulating layer and a semiconductor layer; and a step of etching the gate insulating layer and the semiconductor layer to form a gate insulating m and a source in a predetermined shape.・A step of forming a drain region, a step of forming a metal layer for the drain and source electrodes, a step of etching the drain and source electrodes and a channel portion into a predetermined shape, and a step of etching the gate covered on the display electrode. The method is purchased including the step of removing the metal used for the electrode.

The method for manufacturing a thin film field effect transistor array according to the second invention of the present application includes the steps of forming a conductive film for a display electrode on a glass substrate, a step of forming a metal film for drain/source electrodes, and a semiconductor film for ohmic contact. a step of etching the display electrode conductive film, the drain/source electrode metal film, and the ohmic contact semi-integrated layer into a predetermined shape of the drain electrode, source electrode 1 and display electrode; Semiconductor layer for drain and source.

A process of sequentially depositing a gate insulating film, a process of forming a metal film for the gate electrode, and etching to form the gate electrode, source electrode, source region, and drain electrode.

The metal film for the drain and source electrodes forms the drain region 9 display electrode and is on the display electrode.

The process includes a step of removing a semiconductor layer for an ohmic contact, a semiconductor layer for a drain/source, a gate insulating film, and a metal film for a gate electrode.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) to 1) are cross-sectional views of an inversely staggered thin film field effect transistor shown in the order of manufacturing steps to illustrate the first embodiment of the invention of wooden tablet 1.

First, as shown in FIG. 1(a), indium oxide (ITO) was coated on a glass substrate l for display electrodes.
2 is formed with a film thickness of about 0.1 μm by sputtering.

Next, as shown in Figure 1 (tb), a chromium film 3 for a gate electrode is deposited on the ITOg to a thickness of about 0.15 μm by sputtering.
Formed to a film thickness of .

Next, ITO was superimposed as shown in FIG. 1 (Te).

A predetermined gate electrode 4. is formed by photolithography and etching the two-layer film of chromium. It is processed into the shape of the display electrode 5. Display Ti! ! 5 is covered with a chromium film 3.

Next, as shown in Fig. 1+d), a three-chamber in-line plasma CVD apparatus was used to deposit silicon nitride A6 as a gate insulating layer, an amorphous silicon film 7 as a semiconductor layer, and a phosphorus-doped n amorphous silicon film as an ohmic contact layer. 8 and 0.3 μm each
, A film is continuously formed to a thickness of 0.3 μm and 0.05 μm.

Next, as shown in FIG. 1, the three-layer film formed by plasma CVD is processed into a predetermined shape by photolithography and etching.

Next, as shown in Fig. 1(f), a chromium film lO was sputtered to a thickness of υ 0.15μ as the drain and source electrodes.
Form into m.

Next, as shown in FIG. 1(g), it is processed into a predetermined shape by photolithography and etching to form a drain/source electrode and a channel part 1).

Next, as shown in Fig. 1 (h) K, the channel part 1)
is exposed, so a silicon nitride pattern 12 is used as a protective layer.
is formed using a plasma CVD apparatus.

Finally, as shown in FIG. 1(i), the chromium film for the gate electrode, the chromium film for the drain/source electrodes, and the silicon nitride film as a protective layer are coated on the display electrode 13. Remove by etching. In the manufacturing method described above, the ITO film is covered with a chromium film in the second step, and the chromium film is removed in the last step after transistor formation, so when forming by the plasma CVD method, the ITOdg surface is exposed to a plasma atmosphere. It is not exposed inside.

FIGS. 2(a) to 2(i) are cross-sectional views of an inverted staggered Hakuzo thin electrophoresis effect transistor shown in the order of manufacturing steps to explain a second embodiment of the invention of wooden tablet 1.

The steps up to 1a), (b), and tc) in FIG. 2 are manufactured in exactly the same steps as in the first embodiment.

Next, as shown in Figure 2 (d), a silicon nitride pattern 6. An amorphous silicon film 7 as a semiconductor layer and a silicon nitride film 12 as a protective layer are each successively formed to a thickness of 0.3 μm.

Next, as shown in FIG. 2(e), the pattern 31- formed by the plasma CVD method is processed into a predetermined shape by photolithography and etching.

As shown in Figure 2), the silicon nitride film 12 of the protective layer on the drain and source electrodes is removed by etching using etching.

The channel portion is covered with a silicon nitride film 12 as a protective layer.

Next, as shown in FIG. 2(g), n-amorphous silicon rA8t plasma CVD for drain and source electrodes was performed.
The chromium film 10 was formed with a sputtering method to a film thickness of Q, 05
am, formed at 0.15 ttm.

Next, as shown in FIG. 2(h), photolithography φ
The drain/source electrode 16 is processed into a predetermined shape by etching. In this step, the chromium for the gate electrode, the n+ amorphous silicon film for the ohmic contact, and the chromium film for the drain and source electrodes on the display electrode are removed.

Finally, as shown in FIG. 2(i), polyimide [18] is coated and baked by the Svener method to form a protective layer for the entire substrate.

In the manufacturing method described above, ITO is used in the second step.
Since ll&2 is covered with a chromium film 3 and the chromium film is removed after the transistor is formed, the ITO pattern is not exposed to the plasma atmosphere during formation by plasma CVD.

FIGS. 3(a) to 3(h) are cross-sectional views of a hard staggered Hakuzo thin film field effect transistor shown in the order of steps for explaining one embodiment of the invention of wooden tablet 2.

First, as shown in No. 31ffi(a), the glass substrate l
Then, an ITO film 2 is formed to a thickness of 40.1 μm (by sputtering).

Next, as shown in FIG. 3(b), a chromium film 3 with a thickness of 0.15 μm was sputtered as the drain/source electrode.
Form into m.

Next, as shown in FIG. 3(C), a total amorphous silicon film 8 is formed by plasma CVD for ohmic contact.
The gJio layer is formed to a thickness of 05 μm by the method.

Next, as shown in FIG. 3 (td), the three-layered film is processed into a predetermined shape of a drain electrode 19 and a source electrode 9 by photolithography etching.

Next, as shown in FIG. 3 (16), using a two-chamber in-line plasma CVI) device, amorphous silicon G7 and a silicon nitride film 6 as a gate insulating layer are each continuously formed to a thickness of 0.3 μm (Q film thickness). do.

Next, as shown in FIG. 3(f)K, chromium [3] is formed to a thickness of 0.15 μm by sputtering for the gate electrode.

Next, as shown in Figure 3(g), photolithography
Gate electrode 22. Source electrode 21. f
Process the i-indicator electrode 13. In this process, the drain and source electrode material on the display electrode is chrome-plated.

The n+ amorphous silicon film, amorphous silicon film, silicon nitride film, and gate electrode chromium film are removed.

Finally, as shown in Figure 3(h), protect the entire board 1.
- A polyimide pattern 18 is coated and fired by the speech method.

In this embodiment as well, similarly to the first and second embodiments of the first invention described above, ITO for the display electrode is made of plasma carbon.
During formation by the VD method, since it is covered with a chromium film, it is not exposed to a plasma atmosphere.

〔Effect of the invention〕

As explained above, one aspect of the present invention is that during the formation of a thin film field effect transistor, the ITO film for the display electrode is covered with a metal film, so that it does not suffer plasma damage during formation using the plasma CVD method. There is an effect.

In addition, in conventional manufacturing methods, the display electrode and the gate electrode, or the drain and source electrodes, were patterned separately, but in the present invention, the display electrode and the gate electrode (or drain and source electrode) are patterned in the same process. ,
Furthermore, since the metal film on the display electrode is removed when patterning the drain/source electrode (or gate electrode), the number of photolithography steps is reduced by one compared to the conventional manufacturing method.

[Brief explanation of drawings]

Fig. 1 (t8) to (i) are cross-sectional views of an inverted stagger structure thin film field effect transistor shown in the order of steps for explaining the first embodiment of the first invention, and Fig. 2 (a) to (i) is the first
Inverted staggered structure shown in the order of steps for explaining the second embodiment of the invention of 1) g. FIG. 1) is a 1)'r side view of a staggered structure thin film field effect transistor shown in the order of steps that will not be explained. 1...Glass substrate, 2...ITOd,
3...Chromium film, 4...Gate electrode,
5...Display electrode, 6...Silicon nitride film, 7...Amorphous silicon 7m% 8...
...n+ amorphous silicon l1g, 10-...
...Chromium film, 1)...Pa...channel part, 12.
-... Silicon nitride film, 13... ITO display electrode, 16... Source/drain electrode, 18
...Polyimide, 19...Drain electrode, 21...Source electrode, 22...Gate electrode. Bud 1 Tsuko 2I! 1 /q\L-in1 rainbow screw 3 $3 Figure

Claims (2)

[Claims] (1) A step of forming a conductive film for a display electrode on a glass substrate, a step of forming a metal film for a gate electrode on the conductive film, and selectively etching the conductive film and the metal film to form a gate electrode and a display electrode. a step of depositing a gate insulating layer and a semiconductor layer; a step of etching the gate insulating layer and the semiconductor layer to form a gate insulating film and a source/drain region of a predetermined shape; and a step of forming a drain/source electrode. a step of etching the drain/source electrode and the channel portion into a predetermined shape; and a step of removing the metal film for the gate electrode coated on the display electrode. A method for manufacturing a thin film field effect transistor array characterized by: (2) a step of forming a conductive film for display electrodes on a glass substrate; a step of forming a metal film for drain/source electrodes;
a step of forming a semiconductor layer for ohmic contacts, and etching the conductive film for display electrodes, the metal film for drain/source electrodes, and the semiconductor layer for ohmic contacts into predetermined shapes of drain electrodes, source electrodes, and display electrodes. A step of sequentially depositing a semiconductor layer for drain/source and a gate insulating film, a step of forming a metal film for a gate electrode, and etching to form a gate electrode, a source electrode, a source region, a drain electrode, a drain region, and a display. In addition to forming electrodes, the metal film for drain/source electrodes, the semiconductor layer for ohmic contact, the drain/source electrode on the display electrode, etc.
A method for manufacturing a thin film field effect transistor array, comprising the step of removing a semiconductor layer for a source, a gate insulating film, and a metal film for a gate electrode.