JPS61225869A - Thin film transistor device and manufacture thereof - Google Patents
Thin film transistor device and manufacture thereofInfo
- Publication number
- JPS61225869A JPS61225869A JP6816985A JP6816985A JPS61225869A JP S61225869 A JPS61225869 A JP S61225869A JP 6816985 A JP6816985 A JP 6816985A JP 6816985 A JP6816985 A JP 6816985A JP S61225869 A JPS61225869 A JP S61225869A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- thin film
- semiconductor thin
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 title claims description 14
- 239000010408 film Substances 0.000 claims abstract description 130
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 12
- 238000000151 deposition Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 abstract description 6
- 238000000576 coating method Methods 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 5
- 239000012212 insulator Substances 0.000 abstract 3
- 238000009413 insulation Methods 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 230000008021 deposition Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 238000000605 extraction Methods 0.000 description 2
- 230000000873 masking effect Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78636—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with supplementary region or layer for improving the flatness of the device
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、非晶質シリコン（ａ−８Ｌ）や多結晶シリコ
ン（ｐ−８Ｌ）等の半導体薄膜を用いた薄膜トランジス
タ（ＴＰＴ ）装置と、その簡単な製造方法に関する。[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a thin film transistor (TPT) device using a semiconductor thin film such as amorphous silicon (a-8L) or polycrystalline silicon (p-8L); Regarding its simple manufacturing method.
〈発明の概要〉
絶縁基板上に順次ゲート電極配線、ゲート絶縁膜、半導
体薄膜が同一形状に島状領域に形成され、島状領域の少
なく共側面は塗布絶縁膜によって被覆され、半導体薄膜
上に接するソース電極、とドレイン電極が魔布絶縁禮上
に延在するＴＩＦＴ構造である。絶縁基板上に第１導電
膜、ゲート絶縁膜、半導体薄膜を順次堆積後、これらの
膜を島状領域として残す。塗布絶縁膜をコートした後、
島状領域上を裏面露光等を利用して開孔し、第２導電膜
を堆積、選択エッチしてソース・ドレイン電極を製作す
る。第１４電膜は、ゲート電極配線となる。<Summary of the Invention> A gate electrode wiring, a gate insulating film, and a semiconductor thin film are sequentially formed on an insulating substrate in an island-like region having the same shape, and the few coplanar surfaces of the island-like region are covered with a coated insulating film. It has a TIFT structure in which the source and drain electrodes that are in contact with each other extend on the magic cloth insulation. After sequentially depositing a first conductive film, a gate insulating film, and a semiconductor thin film on an insulating substrate, these films are left as island-like regions. After coating the coating insulation film,
A hole is formed on the island-like region using backside exposure or the like, and a second conductive film is deposited and selectively etched to produce source/drain electrodes. The fourteenth electrical film becomes a gate electrode wiring.
以上、少なく共２回のマスク工程で製造可能なＴＩＦＴ
装置でわる。As described above, TIFT can be manufactured with at least two mask processes.
It depends on the device.
く従来の技術〉
ＴＰＴは低温で製作可能なため面積の大きな装置例えば
液晶表示装置等に用いられている。第２図には、アクテ
ィブマトリクス液晶表示装置用ＴＰＴ装置の単位画素断
面例を示す。ガラス等の絶縁基板１の上にＴＦ’Ｔは形
成され、ゲート電極配線（行電極）２、ゲート絶縁膜３
−半導体薄膜４、ドレイン電極（列電極）５．ソース電
極（画素電極）６から成る。ドレイン・ソース電極５゜
６は、半導体薄膜４に対し低抵抗半導体薄膜を含む第３
導電膜１５，１６ｆ介し接触することもある。従来の構
造特にゲート電極２が下にある逆スタガー構造では、ゲ
ート絶縁＃３がゲート電極２の端部も被覆していた。そ
のためゲート絶縁膜３のステップカバー性が充分でない
と、ゲート・ソース、ゲート・ドレイン間の耐圧が充分
でなく、欠陥を発生しやすい問題があった。また一方、
製造工程も４〜６回の多いマスク工程数を必要とし。Prior Art Since TPT can be manufactured at low temperatures, it is used in devices with large areas, such as liquid crystal display devices. FIG. 2 shows an example of a unit pixel cross section of a TPT device for an active matrix liquid crystal display device. A TF'T is formed on an insulating substrate 1 made of glass or the like, and includes gate electrode wiring (row electrodes) 2 and a gate insulating film 3.
- Semiconductor thin film 4, drain electrode (column electrode) 5. It consists of a source electrode (pixel electrode) 6. The drain/source electrode 5°6 is a third electrode including a low resistance semiconductor thin film with respect to the semiconductor thin film 4.
Contact may occur via the conductive films 15 and 16f. In the conventional structure, particularly the inverted staggered structure with the gate electrode 2 at the bottom, the gate insulation #3 also covered the ends of the gate electrode 2. Therefore, if the step coverage of the gate insulating film 3 is not sufficient, the breakdown voltage between the gate and the source and between the gate and the drain will not be sufficient, resulting in the problem that defects are likely to occur. On the other hand,
The manufacturing process also requires a large number of mask processes, 4 to 6 times.
歩留り、コスト等の点で問題があった。There were problems in terms of yield, cost, etc.
〈発明が解決しようとする問題点〉 本発明は叙上の従来技術を改醤丁べくなされ。<Problem that the invention seeks to solve> The present invention has been made to improve the prior art described above.
（１） ゲート絶縁膜がゲート電極配線端部を覆う会
費がなく、（１１） 製造工程が簡単なＴＰＴ構造と
その製造方法を提供することを目的とする。(1) There is no membership fee for the gate insulating film to cover the end of the gate electrode wiring, and (11) the purpose of the present invention is to provide a TPT structure and a manufacturing method thereof that have a simple manufacturing process.
く問題点を解決するための手段〉
本発明によるＴＰＴは、絶縁基板上に連続堆積した第１
導電膜、ゲート絶縁膜、半導体薄膜を同一形状の島状領
域として残し、段差被覆性の良い塗布絶縁膜をフィール
ド絶縁膜に用い島状領域上部を開孔した後、第２導電Ｂ
Ｉｌを堆積、選択エッチした構造をもち、第１導電膜を
ゲート電極配線、第２導電膜をドレイン電極、ソース電
極とするものである。半導体薄膜の上に低抵抗半導体薄
膜を含む第３導電膜を連続堆積し、同一の島状領域とし
、第２導電膜の選択エッチに続き露出した第３導電膜を
除去することもできる。フィールド絶縁膜の島状領域上
面部の開孔は、基板裏面露光等自己整合的に行なう。以
上により、基本的に２回のマスク工程で製造できるもの
である。Means for Solving Problems〉 The TPT according to the present invention consists of a first layer continuously deposited on an insulating substrate.
The conductive film, the gate insulating film, and the semiconductor thin film are left as island-like regions of the same shape, and a coated insulating film with good step coverage is used as the field insulating film. After opening a hole in the upper part of the island-like region, a second conductive B is formed.
It has a structure in which Il is deposited and selectively etched, and the first conductive film is used as a gate electrode wiring, and the second conductive film is used as a drain electrode and a source electrode. It is also possible to continuously deposit a third conductive film including a low-resistance semiconductor thin film on the semiconductor thin film to form the same island-like region, and then remove the exposed third conductive film following selective etching of the second conductive film. The opening in the upper surface of the island-like region of the field insulating film is performed in a self-aligned manner, such as by exposing the back surface of the substrate. As described above, it can basically be manufactured in two mask steps.
く作用〉
上述の様に一本発明によるＴＰＴは、連続堆積した後ゲ
ート電極配線がパターニングされるので、ゲート絶縁膜
はゲート電極配線の上面とのみ平面的に接触している。Effects> As described above, in the TPT according to the present invention, the gate electrode wiring is patterned after continuous deposition, so that the gate insulating film is in planar contact only with the upper surface of the gate electrode wiring.
ゲート電極配線の側面端部はフィールド絶縁膜で覆われ
るので、ゲート絶縁膜の段差被覆性は影響しない。ゲー
ト電極配線端部と半導体薄膜間の距離はゲート絶縁膜の
厚み程度であるが、ゲート絶縁膜の幅よシゲート電極配
線の幅を狭くすることによりこの距離を長くできて耐圧
はさらに改善される。半導体薄膜はＴＦ’Ｔの動作部だ
けでなくゲート電極配線上に延在する構造であるが、半
導体薄膜の高抵抗性と１寸法（長さ、１ｌｉｉ、厚み）
等でその悪影響をなくすことが可能である。Since the side edges of the gate electrode wiring are covered with the field insulating film, the step coverage of the gate insulating film has no effect. The distance between the end of the gate electrode wiring and the semiconductor thin film is approximately the thickness of the gate insulating film, but by making the width of the gate electrode wiring narrower than the width of the gate insulating film, this distance can be increased and the breakdown voltage can be further improved. . The semiconductor thin film has a structure that extends not only over the operating part of the TF'T but also over the gate electrode wiring, but the semiconductor thin film has a high resistance and one dimension (length, 1lii, thickness).
It is possible to eliminate its negative effects.
〈実施例〉 液晶表示装置用ＴＰＴ基板を例に説明する。<Example> A TPT substrate for a liquid crystal display device will be explained as an example.
ａ 実施例１．単位画素構造（第１図）第１図（ａ）に
平面図、第１図（１，）に第１図（ａ）のＡ−Ａ′線に
沿った断面口を示す。ガラス等の絶縁基板１上にゲート
電極配線２．ゲート絶縁膜５．半導体薄膜４がゲート電
極配線として必要な形状でほぼ同一端部を有する島状領
域１０として形成されている。フィールド絶縁膜７は段
差被覆性の良いものが用いられ、島状領域１０の側面を
カバーしている。ドレイン電極５は半導体薄膜４に接し
、フィールド絶縁膜７上に延在し、この例では列電極と
なっている。ソース電極６はやはυ半導体薄膜４に接し
フィールド絶縁膜７上に延在し、画素電極を形成してい
る。半導体薄膜４とソース・ドレイン電極６．５の重な
る部分には、必要に応じ低抵抗半導体薄膜またはこの膜
と金属膜等から収る第６導電膜１６．ｉ５が挿入されて
いる。行電極として働くゲート電極配線２は、ドレイン
電極５に対し上面はゲート絶縁ｐ１１３（半導体薄膜４
、第３導電膜を介して）で、側面はフィールド絶縁膜７
で絶縁され交差している。a Example 1. Unit pixel structure (FIG. 1) FIG. 1(a) is a plan view, and FIG. 1(1,) is a cross-sectional view taken along line AA' in FIG. 1(a). Gate electrode wiring 2 on an insulating substrate 1 made of glass or the like. Gate insulating film 5. A semiconductor thin film 4 is formed as an island region 10 having a shape necessary for a gate electrode wiring and having substantially the same end portions. The field insulating film 7 is made of a film having good step coverage and covers the side surfaces of the island region 10. The drain electrode 5 is in contact with the semiconductor thin film 4, extends over the field insulating film 7, and serves as a column electrode in this example. The source electrode 6 is in contact with the υ semiconductor thin film 4 and extends over the field insulating film 7, forming a pixel electrode. A sixth conductive film 16.5 made of a low-resistance semiconductor thin film or this film and a metal film is placed in the overlapping portion of the semiconductor thin film 4 and the source/drain electrodes 6.5, if necessary. i5 is inserted. The gate electrode wiring 2 functioning as a row electrode has a gate insulating p113 (semiconductor thin film 4) on the upper surface with respect to the drain electrode 5.
, via a third conductive film), and the side surface is a field insulating film 7.
are insulated and crossed.
本構造において、ゲート電極配線２の幅はゲート絶縁膜
３の幅より狭く、ドレイン・ソース電極５．６間距離（
チャンネル長）より広い値を選択できる。こめ例では、
信号電荷保持容ｉｌヲ設けてないが、必要に応じ他の行
のゲート電極配線とソース電極６の間でゲート絶縁膜３
．半導体膜ｇ＋、（第３導電膜）を介して容量を形成で
きる。In this structure, the width of the gate electrode wiring 2 is narrower than the width of the gate insulating film 3, and the distance between the drain and source electrodes 5.6 (
channel length) allows you to select a wider value. In the example,
Although a signal charge holding capacity is not provided, a gate insulating film 3 may be formed between the gate electrode wiring of another row and the source electrode 6 if necessary.
．． A capacitor can be formed via the semiconductor film g+ (third conductive film).
ｂ 実施例Ｚ ＴＦＴ部 （第５図）第３図を用いて
本発明によるＴＦ’Ｉ’の製造工程例を説明する。第３
図（ａ）は、ガラス、石英等の絶縁基板１上に連続して
第１導電膜２０．ゲート絶縁膜３、半導体薄膜４、第３
導電膜５０を堆積した状態である。この例では第３導電
膜３０は低抵抗半導体薄膜３１と金属膜５２から取るが
、第５導電膜３０は必ずしも必要ない。第１導電膜２０
には、Ｏｒ、Ｍｏ、’Ｗ、Ｔａ、Ａｎ、等の金属膜や硅
素化物、ＩＴＯ等透明導電膜、ｎ”ｐ−８Ｌやｎ”ａ−
８１等の低抵抗半導体膜やこれらの多層膜が用いられる
。ゲート絶縁Ｉｇ！３は５ＬＯＸや８１ＮＸ等が用いら
れ、プラズマＯＶ Ｄ、光ＯＶＤ、減圧ＯＶＤ、スパッ
タ等で堆積される。半導体薄膜４にはａ−８ＬＬＨ，ａ
−８ＬＬＦ等のａ−８１や、高抵抗ｐ−ｓｔが用いられ
、ゲート絶縁膜３と同様な堆積ができる。これらの膜は
、大気に触れることなく連続的に堆積することが工程簡
略化、品質の安定化にとって望ましい。各膜厚に任意の
値が選べるが、典を的には、第１導電膜２０は５００〜
５ｏｏｏＸ、ゲート絶縁膜３は５００〜４０００Ａ％半
導体薄ＢｊＸ４は２００〜５０００ Ａ、低抵抗半導体
膜ｌｌｌ３１４ｄ１００〜１０ Ｇ ＯＡ、金属膜３２
は５００〜２０００Ａが選ばれる。b Example Z TFT section (Fig. 5) An example of the manufacturing process of TF'I' according to the present invention will be explained using Fig. 3. Third
Figure (a) shows a first conductive film 20 continuously formed on an insulating substrate 1 made of glass, quartz, etc. Gate insulating film 3, semiconductor thin film 4, third
This is a state in which a conductive film 50 has been deposited. In this example, the third conductive film 30 is made of the low resistance semiconductor thin film 31 and the metal film 52, but the fifth conductive film 30 is not necessarily required. First conductive film 20
Metal films such as Or, Mo, 'W, Ta, An, etc., transparent conductive films such as silicides, ITO, n"p-8L and n"a-
A low resistance semiconductor film such as 81 or a multilayer film thereof is used. Gate insulation Ig! 3 uses 5LOX, 81NX, etc., and is deposited by plasma OVD, optical OVD, reduced pressure OVD, sputtering, or the like. The semiconductor thin film 4 has a-8LLH, a
A-81 such as -8LLF or high resistance p-st is used, and the same deposition as the gate insulating film 3 can be performed. It is desirable for these films to be deposited continuously without being exposed to the atmosphere in order to simplify the process and stabilize quality. Although any value can be selected for each film thickness, typically, the first conductive film 20 has a thickness of 500 to 500.
5oooX, gate insulating film 3 is 500-4000A% semiconductor thin Bj
is selected from 500 to 2000A.
第５図（１＋）は、１回のマスク工程で第３導電膜３０
、半導体薄膜４．ゲート絶縁膜５、第１導電膜２０を連
続選択エッチし、島状領域１０を形成した断面である。FIG. 5 (1+) shows that the third conductive film 30 is removed by one mask process.
, semiconductor thin film 4. This is a cross section where the gate insulating film 5 and the first conductive film 20 are sequentially and selectively etched to form an island region 10.
この例では、第１導電７１３２０をオーバーエッチして
ゲート電極配線２とすると共にゲート絶縁膜３をオーバ
ーハング状にしている。In this example, the first conductive layer 71320 is overetched to form the gate electrode wiring 2, and the gate insulating film 3 is formed into an overhang shape.
オーバーハング量は例えば０〜５μｍである。島状領域
１０の形状は基本的にゲート電極配線２の形状できまる
。The amount of overhang is, for example, 0 to 5 μm. The shape of the island region 10 is basically determined by the shape of the gate electrode wiring 2.
第５図（０）は、°フィールド絶縁膜７を堆積し、島状
領域１０の上面全開孔した状態を示す。フィールド絶縁
膜７の堆積はステップカバー性の良いことが必要で、ス
ピンオングラスやＰＩＱ等の塗布絶縁膜が望ましい、勿
論、塗布絶縁膜とＯＶＤ絶縁膜の２層でもよい。フィー
ルド絶Ｍ）１１７は島状領域１０の側面特にゲート絶縁
膜３のオーバーノ−ングを埋めることが必要である。フ
ィールド絶縁膜７の島状領域１０の上面の開孔は後述の
様に裏面露光等を利用して行なえる。FIG. 5(0) shows a state in which the ° field insulating film 7 is deposited and the upper surface of the island region 10 is completely opened. The field insulating film 7 needs to have good step coverage, and is preferably a coated insulating film such as spin-on glass or PIQ.Of course, it may also be a two-layer film of a coated insulating film and an OVD insulating film. The field insulation M) 117 is required to fill the side surface of the island region 10, especially the overhang of the gate insulating film 3. The openings in the upper surface of the island-like regions 10 of the field insulating film 7 can be made using backside exposure or the like, as will be described later.
第３図（ｄ）は、第２導電膜４０を堆積後、選択エッチ
してドレイン電極５．ソース電極６を形成して完成した
状態を示す。この例では、第２導電膜４０の選択エッチ
後露出する第３導電膜３０も除去し、各電極５．６の半
導体薄膜４への接触を低抵抗半導体薄膜６１、金属膜５
２から成る第５導電膜１５．１６を介して行なわしめて
いる。第２導電膜４０には、例えば透過型表示装置のと
きはＩＴＯ等の透明導電膜が、反射型のときは反射しや
すい金属が用いられる。島状領域１０の端部の不要な第
３導電膜３０を完全に除去するため、第２導電膜４０の
選択エッチ後フィールド絶＊＠７を一部除去して行なう
ことが望ましい。FIG. 3(d) shows that after depositing the second conductive film 40, selective etching is performed to remove the drain electrode 5. A completed state after forming the source electrode 6 is shown. In this example, the third conductive film 30 exposed after the selective etching of the second conductive film 40 is also removed, and the contact of each electrode 5.6 to the semiconductor thin film 4 is reduced by the low resistance semiconductor thin film 61, the metal film 5, and the like.
This is done through the fifth conductive films 15 and 16 made of 2. For the second conductive film 40, for example, a transparent conductive film such as ITO is used in the case of a transmissive display device, and a metal that is easily reflective is used in the case of a reflective display device. In order to completely remove the unnecessary third conductive film 30 at the end of the island region 10, it is preferable to selectively etch the second conductive film 40 and then partially remove the field isolation *@7.
ゲート電極配線の外部取り出し部について説明すると、
従来通りマスク工程を用いても良いが、第５図（ａ）の
少なく共ゲート絶縁膜５、半導体薄膜４の堆積時に外部
取り出し部をマスクすることが工程簡単化の上で望まし
い。To explain the external extraction part of the gate electrode wiring,
Although a conventional masking process may be used, it is desirable to mask the external extraction portion during the deposition of the common gate insulating film 5 and the semiconductor thin film 4 as shown in FIG. 5(a) in order to simplify the process.
Ｃ実施例３ フィールド絶縁膜の開孔方法（第４図）
第４図（ａ）には、透明絶縁基板１上に形成した島状領
域１０（この例ではゲート電極線２、ゲート絶ａ膜５．
半導体薄膜４から成る）ｆフィールド絶縁膜７で被覆し
た状態を示す。さらにネガレジスト８ｆｔコートし、基
板裏側から光を照射し現像すると、島状領域１０がマス
クとして働き島状領域１０の上面のレジスト８を除去で
きる。その後、フィールド絶縁膜７を選択エッチし、レ
ジストを除去すれば第４図（ｂ）の状態になる。島状領
域１゜の最上層に不透明な膜をもつ第３導電膜を用いれ
ば、マスク効果は完全となる。C Example 3 Method of opening holes in field insulating film (FIG. 4) FIG. 5.
The state is shown covered with an f-field insulating film 7 (consisting of a semiconductor thin film 4). Furthermore, when 8 ft of negative resist is coated and developed by irradiating light from the back side of the substrate, the island-like region 10 acts as a mask and the resist 8 on the upper surface of the island-like region 10 can be removed. Thereafter, the field insulating film 7 is selectively etched and the resist is removed, resulting in the state shown in FIG. 4(b). If a third conductive film having an opaque film is used as the top layer of the 1° island-like region, the mask effect will be complete.
フィールド絶縁膜７に感光性Ｐ工Ｑ等のネガ型塗布絶縁
膜を用いれば、レジストなしにそのまま裏面露光現像で
島状領域１０上面の開孔ができる。If a negative coated insulating film such as photosensitive P-type Q is used as the field insulating film 7, openings can be formed on the upper surface of the island region 10 by exposing and developing the back side without using a resist.
また、塗布絶ｌＩｋ膜７は島状領域１ｏの上面が最も薄
くなるので、全面エッチ、にょっても目的が達せられる
。Further, since the coating-free lIk film 7 is thinnest on the upper surface of the island-like region 1o, the purpose can be achieved even if the entire surface is etched.
ｄ 実施例４ ＴＦ’Ｔ部製造工程例 （第５図）第
５図を用い他の製造工程例を説明する。第５図（ａ）は
、透明絶縁基板１上にゲート電極配線２、ゲート絶縁膜
３、半導体薄膜、５ｔｏｘ等絶縁膜１７′ｆ連続堆積し
、島状領域１０を形成したものテする。この際、ゲート
電極配線２はオーバーエッチされ、さらにポジレジスト
８？コートしてゲート電極配線３をマスクに裏面露光し
、絶縁膜１７上にレジスト８ｆ残している。この裏面露
光は半導体薄膜４ｆ通して行なわれる。第５図（１１）
は。d Example 4 TF'T part manufacturing process example (FIG. 5) Another manufacturing process example will be explained using FIG. 5. In FIG. 5(a), a gate electrode wiring 2, a gate insulating film 3, a semiconductor thin film, and an insulating film 17'f such as 5tox are successively deposited on a transparent insulating substrate 1 to form an island region 10. At this time, the gate electrode wiring 2 is over-etched, and the positive resist 8? After coating, the back side is exposed using the gate electrode wiring 3 as a mask, leaving a resist 8f on the insulating film 17. This backside exposure is performed through the semiconductor thin film 4f. Figure 5 (11)
teeth.
フィールド絶縁［７？堆積し島状領域１ｏ上面を開孔し
た状態である。この開孔は、半導体膜＠４をマスクにし
た適正な裏面露光、全面エッチ等で行なえる。第５図（
ｃ）は第３導電膜３ｏ堆積後レジスト１８をマスクに選
択エッチした状態である。Field insulation [7? This is a state in which a hole is formed in the upper surface of the island-like region 1o. This hole can be formed by proper backside exposure using the semiconductor film @4 as a mask, whole surface etching, etc. Figure 5 (
c) shows a state where the third conductive film 3o is deposited and then selectively etched using the resist 18 as a mask.
第３導電膜５０が充分光を透過すれば、半導体薄膜４ｆ
マスクにした裏面露光が利用できる。第５図（ｄ）は第
２導電瞑４０堆積後選択エッチし、続いて第３導電膜３
０も選択除去して、ドレイン・ソース電極５．６を形成
し完成した断面図を示す。If the third conductive film 50 transmits enough light, the semiconductor thin film 4f
Backside exposure using a mask can be used. FIG. 5(d) shows selective etching after deposition of the second conductive film 40, followed by third conductive film 3.
0 is also selectively removed to form drain/source electrodes 5.6, and a completed cross-sectional view is shown.
この例では基本的なマスク工程は２回であシ、その他は
車面露光等の自己整合技術が使える。In this example, the basic masking process is performed twice, and self-alignment techniques such as surface exposure can be used for the rest.
〈発明の効果〉
以上の様に本発明によるＴＩＦＴは、製造工程が簡単な
上に、ゲート・ドレイン、ゲート・ソース間耐圧が改善
されている。そのため良質の表示装置が、高歩留り、低
コストに得られる。また、各膜が膜が連続的に堆積でき
るので、工程時間が短縮できると共に、コンタクト抵抗
も低減°でき、性能的にもコスト的にもさらに改善され
る。主に、液晶表示装置用ＴＩＦＴ基板を例に挙げてき
たが、他のＴＩＦＴ装置にも本発明は適用される。主に
ａ−８Ｌを用いた例で説明したが、ｐ−８１、他の半導
体薄膜を用いたＴＵＦＴ装置についても本発明は適用で
き、その効果は大きい。<Effects of the Invention> As described above, the TIFT according to the present invention not only has a simple manufacturing process but also has improved gate-drain and gate-source breakdown voltages. Therefore, high quality display devices can be obtained at high yield and low cost. Furthermore, since each film can be deposited continuously, process time can be shortened and contact resistance can also be reduced, further improving both performance and cost. Although the TIFT substrate for a liquid crystal display device has been mainly taken as an example, the present invention is also applicable to other TIFT devices. Although the description has been given mainly of an example using A-8L, the present invention can also be applied to TUFT devices using P-81 and other semiconductor thin films, and the effects thereof are significant.
第１図（、）は本発明による’ｒＦＴ’ｉ用いた単位画
素の平面図、第１図（１））は第１図（ａ）のＡ−Ａ’
線に沿ったその断面Ｕである；・第２図は従来のＴＰＴ
を用いた単位画素断面図、第５図（ａ）〜（、ｉ）は本
発明によるＴＦ’Ｔの製造工程順の断面図、第４図（ａ
）と（ｂ）は製造工程一部の詳細説明図、第５図（ａ）
〜（ｄ）は他の製造工程順断面図である。
１・・・基板 ２・・・ゲート電極配線３・
・・ゲート絶縁［４・・・半導体薄膜５・・・ドレイン
電極 ６・・・ソース電極７・・・フィールド絶縁膜
８．１８・・・レジスト １０・・・島状領域１５、ｉ
６，３０・・・第３導電膜
２０・・・第１導電［４０・・・第２導電膜以上Figure 1 (,) is a plan view of a unit pixel using 'rFT'i according to the present invention, and Figure 1 (1)) is AA' in Figure 1 (a).
Its cross section U along the line; Figure 2 shows the conventional TPT
5(a) to 5(i) are cross-sectional views of a unit pixel using TF'T according to the present invention, and FIG.
) and (b) are detailed explanatory diagrams of part of the manufacturing process, and Figure 5 (a)
-(d) are sequential cross-sectional views of other manufacturing steps. 1...Substrate 2...Gate electrode wiring 3.
...Gate insulation [4...Semiconductor thin film 5...Drain electrode 6...Source electrode 7...Field insulating film 8.18...Resist 10...Island region 15, i
6, 30...Third conductive film 20...First conductive [40...Second conductive film or higher
Claims (6)
ート絶縁膜、半導体薄膜と、該薄膜の表面に互いに離間
して設けられたソース電極、ドレイン電極とから少なく
共成る薄膜トランジスタにおいて、 少なく共ゲート電極配線、ゲート絶縁膜、半導体薄膜は
ほぼ同一形状の島状領域として設けられ、ゲート電極配
線の側面端部はゲート絶縁膜によつて被覆されずに少な
く共前記島状領域の側面を被覆するフィールド絶縁膜に
よつて覆われ、ゲート電極配線の幅は前記ゲート絶縁膜
の幅以下に形成され、 前記ソース電極及びドレイン電極の延在部は前記フィー
ルド絶縁膜上に形成されていることを特徴とする薄膜ト
ランジスタ装置。(1) A thin film transistor consisting of a gate electrode wiring, a gate insulating film, and a semiconductor thin film sequentially formed on an insulating substrate, and a source electrode and a drain electrode provided on the surface of the thin film at a distance from each other. The gate electrode wiring, the gate insulating film, and the semiconductor thin film are provided as island-like regions having almost the same shape, and the side edges of the gate electrode wiring are not covered with the gate insulating film, but the side surfaces of the island-like regions are covered at least. The width of the gate electrode wiring is formed to be less than the width of the gate insulating film, and the extending portions of the source electrode and the drain electrode are formed on the field insulating film. Characteristic thin film transistor device.
膜であることを特徴とする特許請求の範囲第１項記載の
薄膜トランジスタ装置。(2) The thin film transistor device according to claim 1, wherein at least a common portion of the field insulating film is a coated insulating film.
薄膜に対して少なく共低抵抗半導体薄膜を介して接して
いることを特徴とする特許請求の範囲第１項または第２
項記載の薄膜トランジスタ装置。(3) The source electrode and the drain electrode are in contact with the semiconductor thin film through at least a low resistance semiconductor thin film.
The thin film transistor device described in .
半導体薄膜を順次堆積する第１工程 （ｂ）半導体薄膜、ゲート絶縁膜、第１導電膜をゲート
電極配線の形状に島状領域として残し第１導電膜をゲー
ト電極配線とする第２工程（ｃ）フィールド絶縁膜を堆
積する第３工程（ｄ）少なく共前記島状領域上のフィー
ルド絶縁膜を選択的に除去する第４工程 （ｅ）第２導電膜を堆積し選択エッチして前記半導体薄
膜上に接し、フィールド絶縁膜上に延在するソース電極
とドレイン電極を形成する第５工程とから成る薄膜トラ
ンジスタ装置の製造方法。(4) (a) A first conductive film, a gate insulating film on an insulating substrate,
First step (b) of sequentially depositing semiconductor thin films; Second step (c) of leaving the semiconductor thin film, gate insulating film, and first conductive film as an island-like region in the shape of the gate electrode wiring and using the first conductive film as the gate electrode wiring; ) a third step of depositing a field insulating film; (d) a fourth step of selectively removing at least the field insulating film on the island region; and (e) depositing and selectively etching a second conductive film to remove the semiconductor thin film. A method for manufacturing a thin film transistor device comprising a fifth step of forming a source electrode and a drain electrode that are in contact with the field insulating film and extend over the field insulating film.
膜であり、第４工程が前記島状領域をマスクとして用い
た前記基板裏面からの光照射露光を利用した選択エッチ
であることを特徴とする特許請求の範囲第４項記載の薄
膜トランジスタ装置の製造方法。(5) The field insulating film deposited in the third step is a coated insulating film, and the fourth step is selective etching using light irradiation exposure from the back surface of the substrate using the island-like region as a mask. A method for manufacturing a thin film transistor device according to claim 4.
導体薄膜を含む第３導電膜を堆積し、前記第２工程で第
３導電膜も前記島状領域と同一形状に選択的に残し、前
記第５工程で第２導電膜の選択エッチに続き露出した第
３導電膜を除去することを特徴とする特許請求の範囲第
４項または第５項記載の薄膜トランジスタ装置の製造方
法。(6) depositing a third conductive film including a low-resistance semiconductor thin film following the semiconductor thin film in the first step, and selectively leaving the third conductive film in the same shape as the island region in the second step; 6. The method of manufacturing a thin film transistor device according to claim 4, wherein the exposed third conductive film is removed following selective etching of the second conductive film in the fifth step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6816985A JPS61225869A (en) | 1985-03-29 | 1985-03-29 | Thin film transistor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6816985A JPS61225869A (en) | 1985-03-29 | 1985-03-29 | Thin film transistor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61225869A true JPS61225869A (en) | 1986-10-07 |
Family
ID=13365994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6816985A Pending JPS61225869A (en) | 1985-03-29 | 1985-03-29 | Thin film transistor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61225869A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63182862A (en) * | 1987-01-23 | 1988-07-28 | Nec Corp | Manufacture of thin film field-effect transistor |
| JPS63221680A (en) * | 1987-03-10 | 1988-09-14 | Nec Corp | Manufacture of thin-film transistor |
| JPS6484669A (en) * | 1987-09-26 | 1989-03-29 | Casio Computer Co Ltd | Thin film transistor |
| US6018181A (en) * | 1990-10-12 | 2000-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| JPWO2007097068A1 (en) * | 2006-02-24 | 2009-07-09 | シャープ株式会社 | Active matrix substrate, display device, television receiver |
| JP2009158941A (en) * | 2007-12-03 | 2009-07-16 | Semiconductor Energy Lab Co Ltd | Manufacturing method of thin film transistor and manufacturing method of display device |
| JP2009230128A (en) * | 2008-02-27 | 2009-10-08 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and manufacturing method thereof, and electronic apparatus |
| JP2009231828A (en) * | 2008-02-26 | 2009-10-08 | Semiconductor Energy Lab Co Ltd | Method for manufacturing display device |
| JP2009246352A (en) * | 2008-03-11 | 2009-10-22 | Semiconductor Energy Lab Co Ltd | Method for manufacturing thin film transistor, and method for manufacturing display device |
| JP2010028103A (en) * | 2008-06-17 | 2010-02-04 | Semiconductor Energy Lab Co Ltd | Thin film transistor, method of manufacturing the same, display device, and method of manufacturing the device |
| JP2010212677A (en) * | 2009-02-16 | 2010-09-24 | Semiconductor Energy Lab Co Ltd | Method of manufacturing thin-film transistor and method of manufacturing display device |
| JP2010230950A (en) * | 2009-03-27 | 2010-10-14 | Semiconductor Energy Lab Co Ltd | Method for manufacturing display device |
| JP2011228560A (en) * | 2010-04-22 | 2011-11-10 | Hitachi Displays Ltd | Image display device and manufacturing method of the same |
| US8168980B2 (en) | 2006-02-24 | 2012-05-01 | Sharp Kabushiki Kaisha | Active matrix substrate, display device, television receiver, manufacturing method of active matrix substrate, forming method of gate insulating film |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59225569A (en) * | 1983-06-06 | 1984-12-18 | Fujitsu Ltd | Manufacture of self-aligning thin film transistor |
| JPS61185783A (en) * | 1985-02-13 | 1986-08-19 | シャープ株式会社 | Manufacture of thin film transistor |
-
1985
- 1985-03-29 JP JP6816985A patent/JPS61225869A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59225569A (en) * | 1983-06-06 | 1984-12-18 | Fujitsu Ltd | Manufacture of self-aligning thin film transistor |
| JPS61185783A (en) * | 1985-02-13 | 1986-08-19 | シャープ株式会社 | Manufacture of thin film transistor |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63182862A (en) * | 1987-01-23 | 1988-07-28 | Nec Corp | Manufacture of thin film field-effect transistor |
| JPS63221680A (en) * | 1987-03-10 | 1988-09-14 | Nec Corp | Manufacture of thin-film transistor |
| JPS6484669A (en) * | 1987-09-26 | 1989-03-29 | Casio Computer Co Ltd | Thin film transistor |
| US6018181A (en) * | 1990-10-12 | 2000-01-25 | Mitsubishi Denki Kabushiki Kaisha | Thin film transistor and manufacturing method thereof |
| JP4588785B2 (en) * | 2006-02-24 | 2010-12-01 | シャープ株式会社 | Active matrix substrate, display device, television receiver |
| JPWO2007097068A1 (en) * | 2006-02-24 | 2009-07-09 | シャープ株式会社 | Active matrix substrate, display device, television receiver |
| US7868960B2 (en) | 2006-02-24 | 2011-01-11 | Sharp Kabushiki Kaisha | Active matrix substrate, display device, and television receiver |
| US8168980B2 (en) | 2006-02-24 | 2012-05-01 | Sharp Kabushiki Kaisha | Active matrix substrate, display device, television receiver, manufacturing method of active matrix substrate, forming method of gate insulating film |
| JP2009158941A (en) * | 2007-12-03 | 2009-07-16 | Semiconductor Energy Lab Co Ltd | Manufacturing method of thin film transistor and manufacturing method of display device |
| JP2009231828A (en) * | 2008-02-26 | 2009-10-08 | Semiconductor Energy Lab Co Ltd | Method for manufacturing display device |
| US8901561B2 (en) | 2008-02-26 | 2014-12-02 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device |
| JP2014160849A (en) * | 2008-02-27 | 2014-09-04 | Semiconductor Energy Lab Co Ltd | Thin film transistor |
| JP2009230128A (en) * | 2008-02-27 | 2009-10-08 | Semiconductor Energy Lab Co Ltd | Liquid crystal display device and manufacturing method thereof, and electronic apparatus |
| JP2009246352A (en) * | 2008-03-11 | 2009-10-22 | Semiconductor Energy Lab Co Ltd | Method for manufacturing thin film transistor, and method for manufacturing display device |
| JP2010028103A (en) * | 2008-06-17 | 2010-02-04 | Semiconductor Energy Lab Co Ltd | Thin film transistor, method of manufacturing the same, display device, and method of manufacturing the device |
| JP2010212677A (en) * | 2009-02-16 | 2010-09-24 | Semiconductor Energy Lab Co Ltd | Method of manufacturing thin-film transistor and method of manufacturing display device |
| US8709836B2 (en) | 2009-02-16 | 2014-04-29 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing thin film transistor and method for manufacturing display device |
| JP2010230950A (en) * | 2009-03-27 | 2010-10-14 | Semiconductor Energy Lab Co Ltd | Method for manufacturing display device |
| JP2011228560A (en) * | 2010-04-22 | 2011-11-10 | Hitachi Displays Ltd | Image display device and manufacturing method of the same |
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