JP3153938B2 - Active matrix substrate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix type liquid crystal display device, and more particularly to a structure of an active matrix substrate on which pixel electrodes, thin film transistors (TFTs), auxiliary capacitors and the like are formed. More particularly, the present invention relates to a thin film transistor having a trench structure and an electrode shape of an auxiliary capacitor.

[0002]

2. Description of the Related Art A conventional liquid crystal display device comprises a pair of substrates opposed to each other with a predetermined gap therebetween, and a liquid crystal layer filled and sealed in the gap. In particular, in an active matrix liquid crystal display device, pixel electrodes arranged in a matrix on one substrate inner surface, thin film transistors (TFTs) connected to the pixel electrodes, and auxiliary capacitors for holding electric charges via the thin film transistors Are formed. A substrate having such a configuration is hereinafter referred to as an active matrix substrate. After the thin film transistor is selected and the image signal is written to the pixel electrode, the non-selected state is held and the written image signal is held. An image is displayed by a so-called sampling hold. The storage capacitor is connected in parallel with the pixel to suppress the attenuation of the image signal during the non-selection period.

[0005] The pixel electrode becomes an effective display area, and the thin film transistor and the storage capacitor constitute an ineffective display area. As the pixels become finer and higher definition, the ratio of the effective display area to the entire display area, that is, the aperture ratio is sacrificed, and the contrast is reduced. As a countermeasure, a thin film transistor and an auxiliary capacitor having a trench structure have been conventionally proposed, which is disclosed in, for example, Japanese Patent Application Laid-Open No. 64-82262.

[0004]

FIG. 17 shows a conventional storage capacitor trench structure. The auxiliary capacitance is provided using a groove or trench 101 formed in the main surface of the active matrix substrate by etching. A first electrode having a continuous pattern is formed along the main surface of the substrate and the inner wall of the trench. This first electrode is made of, for example, a polysilicon thin film. Since the area utilization efficiency can be improved by using the substrate three-dimensionally in this manner, there is an advantage that the size of the auxiliary capacitance can be reduced accordingly. The first electrode 102 is processed into a predetermined pattern by etching after depositing a polysilicon thin film on the entire surface of the substrate. Although not shown, an auxiliary capacitance can be formed by depositing a dielectric film and a second electrode on the first electrode 102.

Conventionally, there has been a problem or problem that an unnecessary polysilicon thin film 103 remains on the bottom surface of the trench 101 even after the etching process. Such an unetched residue causes a variation of each auxiliary capacitance, and causes a variation. The etching is performed using, for example, a positive photoresist. After the photoresist is coated on the polysilicon thin film, exposure processing is performed using a stepper to remove the exposed portion, and the resist is patterned.
Thereafter, the polysilicon thin film is selectively etched using the photoresist as a mask to form a pattern of the first electrode 102. However, when the depth of the trench 101 is 1
Since the thickness ranges from μm to 10 μm, the thickness of the resist is increased only in the trench portion, and a sufficient exposure amount cannot be absorbed. For this reason, the resist on the bottom portion and the lower portion of the side wall of the trench 101 is not exposed, and the resist in this portion cannot be peeled off. Therefore, an etching residue of the polysilicon thin film occurs. Further, even when a one-to-one projection type exposure apparatus or a projection type exposure apparatus is used in place of the stepper, the amount of exposure to the bottom portion of the trench 101 becomes insufficient, so that etching residue occurs.

FIG. 18 shows a trench structure of a conventional thin film transistor. In the illustrated example, two thin film transistors are provided in a common groove or trench 104 formed in the surface of the active matrix substrate. The polysilicon thin film 105A serving as a semiconductor region of one thin film transistor is continuously formed in a predetermined pattern along the main surface of the substrate and the inner wall of the trench 104. The polysilicon thin film 105B of the other transistor is similarly formed at a predetermined interval. Trench 104
By embedding a common gate electrode 106 after embedding a gate insulating film (not shown), a pair of thin film transistors can be formed. As in the case of FIG. 17, an etching residue 107 of the polysilicon thin film is formed on the bottom of the trench 104. This etching residue 107 is not preferable because it causes capacitive coupling and parasitic capacitance of the thin film transistor.

[0007]

SUMMARY OF THE INVENTION In view of the above-mentioned problems in the prior art, the present invention improves the pattern shape of a trench type thin film element to reduce variation in auxiliary capacitance, capacitive coupling of a thin film transistor, or parasitic capacitance. The purpose is to control. In order to achieve such an object, the means shown in FIG. 1 was taken. As shown in (A), the active matrix substrate according to the present invention has, as basic components, pixel electrodes 1 arranged in a matrix, a thin film transistor (TFT) 2 connected to the pixel electrodes, and a TFT 2
And an auxiliary capacitor 3 for holding an electric charge through the capacitor. The active matrix substrate 4 having such a configuration and the other substrate (not shown) having the counter electrode are overlapped with a predetermined gap therebetween to hold a liquid crystal layer (not shown), thereby obtaining a liquid crystal display device.

Each storage capacitor 3 has a trench structure,
It is formed using a groove or trench 5 formed on the main surface of the substrate 4. Auxiliary capacitor 3 has a laminated structure, and has a first electrode layer, for example, a first polysilicon layer 6 formed continuously along the inner wall of trench 5 and on the main surface of substrate 4.
And a dielectric film 7 formed on the first polysilicon layer 6.
And a second electrode layer, for example, a second polysilicon layer 8 formed on the dielectric film 7.

On the other hand, the TFT 2 is also formed utilizing another trench 9. In the trench 9, a semiconductor region made of the first polysilicon layer 6 described above is formed. This semiconductor region is continuously formed in a predetermined pattern along the main surface of the substrate 4 and the inner wall of the trench 9. A gate insulating film 10 is deposited on the semiconductor region. The film 10 is made of the same material as the dielectric layer 7 as described above
You . Further, a gate electrode made of the second polysilicon layer 8 is formed on the gate insulating film 10 so as to overlap with each other, thereby forming the trench type TFT 2. A metal wiring 12 made of aluminum or the like is electrically connected to the drain region D of the TFT 2 via a first interlayer insulating film, for example, a first PSG film 11. The above-mentioned pixel electrode 1 is provided in the source region of the TFT 2.
Are electrically connected via the first PSG film 11. Further, the metal wiring 12 is covered with a second interlayer insulating film, for example, a second PSG film 13. In this example, the auxiliary capacitance 3
Both the TFT and the TFT 2 have a trench structure, but the present invention is not limited to this, and includes an active matrix substrate in which at least one has a trench structure.

FIG. 1B schematically shows the first characteristic feature of the present invention. The first polysilicon layer 6 constituting the auxiliary capacitance 3 includes two pattern regions. That is, the internal pattern region 14 completely covers the inner wall and the bottom of the trench 5 and the surface pattern region 16 formed on the main surface 15 of the substrate. The surface pattern region 16 is continuous with the internal pattern region 14 and is included so as to surround the opening 17 of the trench 5. Here, the surface pattern region 16 corresponds to the opening 1.
7 extend from the end to the periphery by 0.5 μm or more. That is, the width of the surface pattern region 16 having a frame shape is 0.5 μm or more.

FIG. 2C schematically shows a second characteristic feature of the present invention. A first polysilicon layer 6 having a predetermined patterning shape is formed to cross the trench 9 and
Is configured. The first polysilicon layer 6 has a strip pattern shape in plan view, and at least one side 18 of the pattern formed on the bottom surface of the trench 9 is located inside the bottom edge 19 of the trench 9. I do. Similarly, at least one side 20 of the pattern of the first polysilicon layer 6 located on the main surface of the substrate is also inside the opening end 21 of the trench. In this example, the pattern shape shown in (C) is applied to the TFT 2, but the present invention is not limited to this.
The pattern shape (C), the is applied to the auxiliary capacitor 3 in place of the pattern shape shown in (B).

[0012]

According to the first aspect of the present invention, as shown in FIG. 1B, the inner wall and the bottom surface of the trench are completely covered with the first polysilicon layer and surround the trench opening. In this manner, the first polysilicon layer on the main surface of the substrate is patterned. In other words, in the structure shown in FIG.
After depositing the first polysilicon layer over the entire surface of the substrate, only the portion on the main surface needs to be etched, and there is no need to etch the first polysilicon layer deposited on the bottom of the trench. Therefore, it is possible to suppress the variation of the trench-type storage capacitor without fear of remaining etching as in the related art.

As shown in FIG. 1C, the second embodiment of the present invention
According to the feature of the first aspect, the first polysilicon layer 6 is patterned in a strip shape when viewed in plan, and at least one side 18 of the first polysilicon layer 6 is formed at the bottom of the trench 9.
A certain space is provided between the trench 9 and the inner wall end 19 of the trench 9. In other words, unlike the conventional case, the shape of the pattern is such that there is no residual etching, and the trench type TFT is used.
Capacitive coupling and parasitic capacitance can be suppressed. Note that the pattern shape shown in (C) is applied to an auxiliary capacitor instead of the pattern shape shown in (B). In this case, since the surface area of the trench-type auxiliary capacitor can be reduced, higher-density integration becomes possible, and the pixel aperture ratio can be improved.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 2 is a schematic plan view showing one embodiment of the trench type storage capacitor according to the present invention. In this embodiment, ten trenches 31 are formed in a stripe shape. A first polysilicon film 32 is formed by patterning so as to cover all the trenches 31, and one end of the first polysilicon film 32 is connected to a pad 33 for taking out an electrode. The first polysilicon film 32 completely covers the inner wall and the bottom of each trench 31, and the pattern region deposited on the main surface of the substrate has a width including an alignment margin of at least 0.5 μm. Each trench 31 is included. Since the patterning of the first polysilicon film 32 only needs to be performed on the surface region, no etching residue remains on the bottom surface of the trench 31 unlike the related art. Further, after depositing a dielectric film, a second polysilicon film 34 is formed in pattern in alignment with the trench 31. One end of the second polysilicon film 34 is connected to another electrode extraction pad 3.
5 is connected. In this manner, a pair of pads 3
An auxiliary capacitance is obtained between the capacitors 3 and 35.

For comparison, FIG. 3 shows a plan structure of a conventional trench type auxiliary capacitor. The same components as those in the embodiment shown in FIG. 2 are denoted by the same reference numerals to facilitate understanding. In the conventional example shown in FIG.
The pattern width on the main surface of the substrate is
Is set shorter than the total length of the trench 31, and both ends of the bottom surface of the trench 31 are exposed when viewed in a plan view. In this portion, an etching residue 36 of the first polysilicon film 32 is generated, which causes a variation in the auxiliary capacitance.

FIG. 4 is a schematic perspective view of the trench-type auxiliary capacitance shown in FIG. 2, in which the longitudinal dimension of the trench is shown in a reduced size for ease of illustration. The value of the auxiliary capacity is calculated with reference to this figure. The trench 31 has a width dimension W, for example.
Is 1 μm, length L is 100 μm, height H is 3 μm
m. Further, a margin M of 0.5 μm is set in the plane pattern dimension of the first polysilicon film 32 formed on the main surface 37 of the substrate. The margin M needs to be at least 0.5 μm, and is appropriately determined in consideration of the alignment accuracy of the exposure apparatus and the amount of overetching of the first polysilicon film 32.

In the embodiment shown in FIG. 4, the side face, end face and bottom face of the trench 31 are all covered with the first polysilicon film 32, and the total is the electrode area. The area of the pair of side and bottom portions is 100 μm × (3 μm + 1 μm).
m + 3μm) = 700μm ^2, and the area of the pair of end surface portions 1μm × 3μm × ² = 6μm 2, and the total area is calculated as 706μm ^2. In this embodiment, the trench 31 is used.
Are formed in parallel, so that the total electrode area is 706.
[mu] m ² × 10 pieces = 7060μm ² becomes always the value of the design value is obtained. Also, a dielectric film (not shown) is formed of a SiO ₂ film having a thickness of 40 nm and a Si film having a thickness of 15 nm.
Assuming a two-layer structure of an N film, the unit capacity is 7.38 × 10 ^−8.
F / cm ² . Therefore, the value of the trench type auxiliary capacitance shown in FIG. 4 is 7060 × 10 ⁻⁸ × 7.38 × 10 ⁻⁸ = 5.
2102 pF, which is a value as designed.

On the other hand, for comparison, the value of the conventional trench type auxiliary capacitance is calculated with reference to FIG. The structure shown in FIG. 5 is a schematic perspective view of the conventional example shown in FIG. The width dimension W and the height dimension H of the trench 31 are the same as those of the embodiment shown in FIG. 4, but the length dimension is the same as the original design value L and the dimension E at both ends of the portion 36 remaining after etching. Can be Assuming that the dimension E is, for example, 10 μm, the electrode area is calculated. 720 .mu.m ² plus electrode area 20 [mu] m ² of the original electrode area 700 .mu.m ² and etching residue 36
Is the electrode area of each trench. Therefore, the value of the auxiliary capacitance including the ten trenches is 7200 × 10 ⁻⁸ × 7.
It is given by 38 × 10 ⁻⁸ = 5.316 pF. A deviation of about 2% occurs from the original design value of 5.2102 pF. This error increases as the longitudinal dimension E of the etching residue 36 increases. On the other hand, in the present invention, since no etching residue occurs on the bottom surface of the trench, it is possible to stably secure an auxiliary capacitance substantially equal to the design value. By suppressing the variation in the auxiliary capacitance, the voltage holding capability of each pixel becomes uniform, and for example, the bright spot defect on the display screen is reduced.

FIG. 6 is a schematic perspective view showing the structure of a trench type TFT according to the present invention. A first polysilicon film 42 patterned in a strip shape so as to intersect in the width direction of the trench 41 is formed. In the bottom surface of the trench 41, the patterned side of the first polysilicon film 42 is separated inward from the bottom end 50, and the etching residue is completely removed. The gate insulating film 43 is patterned so as to match the first polysilicon film 42 patterned in a strip shape. This gate insulating film 43
Has a three-layer structure of, for example, SiO ₂ / SiN / SiO ₂ and has improved gate breakdown voltage. Further, the trench 41
The second polysilicon film 44 is patterned so as to be aligned with the longitudinal direction of the semiconductor device, thereby forming a gate electrode wiring.
Since the trench pattern matches the gate wiring pattern, the manufacturing process can be simplified. In addition, a source contact hole 45 and a drain contact hole 46 for electrode connection are formed on the surface of the first polysilicon film 42 on both sides of the gate electrode wiring.

FIG. 7 shows the first polysilicon film 4 shown in FIG.
FIG. 4 is an explanatory diagram showing a second patterning method. First, a first polysilicon film (not shown) is deposited on the entire inner wall and bottom of the trench 41. Next, a positive photoresist 47 is coated. Subsequently, the photoresist 47 is irradiated through a photomask 48 using a projection type exposure apparatus, and the exposed portions are removed to form a stripe-shaped resist pattern. By performing etching through this resist pattern, a strip-shaped first polysilicon film 42 is obtained. In particular, a region corresponding to the trench 41 of the mask pattern 49 formed on the photomask 48 is partially cut out, and by sufficiently exposing the bottom surface portion, the etching residue can be completely suppressed. By optimizing the exposure conditions without providing a notch in the mask pattern 49, insufficient exposure of the bottom surface of the trench can be eliminated. For example, when a projection type exposure apparatus is used, the exposure time of about 10 seconds is conventionally extended to about 25 seconds to 30 seconds, so that the trench bottom having a depth of about 3 μm can be sufficiently exposed. You can do it.

FIG. 8 is a schematic perspective view showing another embodiment of the trench type storage capacitor according to the present invention. Basically, it is similar to the structure shown in FIG. 1B, but in particular, by reducing the surface pattern area of the first polysilicon film 51, the area occupied by the trench capacitance is reduced. The aperture ratio is improved. As shown, one side 52 of the surface pattern region is set at a position that does not exceed the open end 54 of the trench 53 to the outside. In the illustrated example, one side 52 of the surface pattern region is located inside the trench opening end 54, but it may be made to match as much as possible. The patterning process of such a shape can be easily performed by, for example, the method shown in FIG. Also on the bottom surface of the trench 53, one side 55 of the first polysilicon film 51 is located inside the bottom end 56 of the trench, so that no etching residue occurs unlike the conventional case.

Referring to FIG. 9, the surface occupied area of the trench type auxiliary capacitance shown in FIG. 8 is calculated. As shown in (A),
In this example, it is assumed that one side 52 of the surface pattern region of the first polysilicon film coincides with the trench opening end 54. By doing so, the first polysilicon film can be entirely deposited on the four side surfaces and the bottom surface of the trench. The area of the trench opening is represented by A × B. On the other hand, the dimension of the surface pattern region of the first polysilicon film is indicated by C × D.

For comparison, FIG. 9B shows the surface occupied area of the trench capacitor shown in FIG. 1B. When the area A × B of the trench opening is set to be the same, the same auxiliary capacitance value can be obtained. Since the surface pattern region of the first polysilicon film surrounds the entire periphery of the trench opening, its area is D × E.
The occupied area is increased as compared with the embodiment shown in FIG. 9A, which is disadvantageous from the viewpoint of improving the aperture ratio.

Finally, a method of manufacturing the active matrix substrate shown in FIG. 1 will be described with reference to FIGS. First, FIG. 10 shows the processing up to the first polysilicon film patterning. In step A, a substrate 61 made of, for example, quartz glass is prepared. Next, in a step B, the main surface of the substrate 61 is etched to form trenches 62 and 63. One trench 62 is for a TFT, and the other trench 63 is for an auxiliary capacitor. This etching is
For example, the wet etching is performed by using a mixed solution of HF: NH ₄ F = 1: 6. In the process C, the substrate 61
A first polysilicon film 64 is deposited over the entire main surface of the semiconductor device. By this process, the inner wall portions and the bottom portions of the trenches 62 and 63 are completely covered. The first polysilicon film 64 is deposited by, for example, the LPCVD method, and is formed to a thickness of 80 nm. Thereafter, silicon or the like is ion-implanted and annealing for solid phase growth is added. Subsequently, in a step D, the first polysilicon film 64 is patterned. For the trench 62 where the TFT is to be formed, for example, a first polysilicon film having a pattern as shown in FIG. 1C is formed, and for the trench 63 for the auxiliary capacitance, for example, A first polysilicon film having a pattern as shown in B) is formed. Instead, a first polysilicon film region having a pattern as shown in FIG. 8 may be formed. In any case, there is no fear that an etching residue is left on the bottom surface of the trench unlike the related art.

Next, a process for forming an insulating film will be described with reference to FIG. First, in step E, the first polysilicon film 64
Is thermally oxidized to form a 10 nm SiO ₂ insulating film 65. The insulating film 65 thus formed is formed in the trench 62
The inside becomes a gate insulating film, and inside the other trench 63 becomes a dielectric film. Next, in step F, ions of arsenic or the like are implanted into the trench 63 while the one trench 62 is masked with the resist 66 to reduce the resistance of the first polysilicon film 64. The first polysilicon film 64 having a reduced resistance is used as a first electrode of an auxiliary capacitance. Subsequently, in step G, an SiO ₂ insulating film is further formed to a thickness of 60 nm by the HTO method.

Referring to FIG. 12, the process up to the second polysilicon film patterning process will be described. In step H, a second polysilicon film 67 is deposited on the entire main surface of the substrate 61 to completely fill the trenches 62 and 63. The second polysilicon film 67 is formed to a thickness of 350 nm by, for example, the LPCVD method. Thereafter, the second polysilicon film 67 is coated with PSG or the like to reduce the resistance, and then the PSG is removed. Next, in step I, the second polysilicon film is patterned to form a gate electrode 68 in the trench 62 and a second electrode 69 of an auxiliary capacitor in the other trench 63. The patterning of the second polysilicon film is performed by, for example, CF ₄
It is performed by plasma etching using a mixed gas of / O ₂ = 95/5.

The impurity ion implantation process will be described with reference to FIG. In step J, the upper portion of the trench 62 is covered with a resist 70 and arsenic is ion-implanted at a relatively low concentration to form a so-called LDD region. Next, in a process K, after covering the upper portion of the trench 62 with a resist 71 having a larger area, arsenic ions are implanted at a relatively high concentration and N
The source / drain regions of the channel TFT are formed. Subsequently, in a process L, the trench 62 in which the N-channel transistor is formed and the trench 6 in which the storage capacitor is formed.
Boron is ion-implanted in a state where 3 is covered with the resist 72 to form a P-channel TFT (not shown).

The patterning of the first PSG film will be described with reference to FIG. First, in step M, a first PSG film 73 is deposited over the entire surface of the substrate 61 by the LPCVD method. Subsequently, in step N, the first PSG film 73 is etched to form a first contact hole 75 communicating with the drain region D of the N-channel TFT 74 formed in the trench 62. The patterning of the first PSG film 73 is performed by, for example, wet etching using a mixed solution of HF / NH ₄ F.

The metal wiring process will be described with reference to FIG. In step O, a metal film 76 of Al / Si is deposited on the surface of the substrate 61 to a thickness of 600 nm by sputtering. At this time, the first contact hole 75 is
6 and the drain region D of the TFT 74
Is conducted. Next, in a step P, the metal film is patterned to form a metal wiring 77. This patterning is performed by wet etching using a phosphoric acid aqueous solution of H ₃ PO ₄ / H ₂ O = 2/10, for example. In step Q, the second PSG is formed on the surface of the substrate 61 by LPCVD or the like.
The film 78 is covered. Thereafter, if necessary, a nitride film or the like may be temporarily deposited, and the first polysilicon film 64 may be hydrogenated.

Finally, the pixel electrode patterning processing will be described with reference to FIG. In the process R, the insulating film 65 and the first PSG film 7 are dry-etched or wet-etched.
Second, a second contact hole 79 communicating with the source region S of the TFT 74 is opened with respect to the stack of the second PSG film 78. Next, in step S, an ITO film 80 is formed on the surface of the substrate 61.
Is deposited. At this time, the second contact hole 79 is completely buried, and electrical conduction to the source region S is established. The thickness of the ITO film 80 is set to, for example, 140 nm, and the film forming temperature is set to 400 ° C. Finally, in step T, the ITO film is patterned into a predetermined shape and the pixel electrode 81 is formed.
Is obtained. The thus-formed TFT substrate 82 and the counter substrate 84 on which the counter electrode 83 is formed are attached to each other.
By filling and enclosing the liquid crystal layer 85 in the gap between them, an active matrix type liquid crystal display device can be obtained.

[0031]

As described above, according to the present invention, the first capacitor formed on the active matrix substrate is formed along the inner wall of the trench and continuously on the surface of the substrate. A first electrode formed on the surface of the substrate, comprising a layer, a dielectric film formed on the first electrode layer, and a second electrode layer formed on the dielectric film. The region of the layer has an area dimension that encompasses the opening of the trench. According to such a configuration, it is not necessary to perform patterning on the first electrode layer deposited on the bottom surface of the trench, and no etching residue occurs. According to another aspect of the present invention, at least one of the storage capacitor and the thin film transistor formed on the active matrix substrate is provided with a first electrode layer formed continuously along the trench and on the substrate surface; An insulating film formed on the first electrode layer and a second electrode layer formed on the insulating film, and at least one of the first electrode layers formed on the bottom surface of the trench. It has a pattern shape in which the side is located inside the bottom end of the trench. Therefore, the etching residue at the bottom of the trench is removed. In this manner, by removing the etching residue of the first electrode from the bottom surface of the trench, there is an effect that a cause of variation of the trench type auxiliary capacitance is removed and an image display without luminance unevenness is obtained. Further, since the parasitic capacitance or capacitive coupling of the trench type thin film transistor can be suppressed, there is an effect that a stable image display can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a basic configuration of an active matrix substrate according to the present invention.

FIG. 2 is a plan view showing an example of a trench type storage capacitor according to the present invention.

FIG. 3 is a plan view showing an example of a conventional trench type storage capacitor.

FIG. 4 is a schematic perspective view of the trench storage capacitor shown in FIG. 2;

FIG. 5 is a schematic perspective view of the conventional trench-type auxiliary capacitance shown in FIG.

FIG. 6 is a schematic perspective view showing an example of a trench thin film transistor according to the present invention.

FIG. 7 is an explanatory view showing a patterning method of the trench type thin film transistor shown in FIG.

FIG. 8 is a perspective view showing another example of the trench type storage capacitor according to the present invention.

9 is a schematic plan view for calculating an area occupied by the trench-type auxiliary capacitance shown in FIG.

FIG. 10 is a process chart showing a method for manufacturing the active matrix substrate shown in FIG.

FIG. 11 is a process drawing showing the same manufacturing method.

FIG. 12 is a process drawing showing the same manufacturing method.

FIG. 13 is a process drawing showing the same manufacturing method.

FIG. 14 is a process drawing showing the same manufacturing method.

FIG. 15 is a process drawing showing the same manufacturing method.

FIG. 16 is a process drawing showing the same manufacturing method.

FIG. 17 is a perspective view of a conventional trench-type storage capacitor.

FIG. 18 is a perspective view showing an example of a conventional trench thin film transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 pixel electrode 2 thin film transistor (TFT) 3 storage capacitor 4 active matrix substrate 5 trench 6 first polysilicon layer 7 dielectric film 8 second polysilicon layer 9 trench 10 gate insulating film

Claims (6)

(57) [Claims] 1. An active matrix substrate comprising: a pixel electrode arranged in a matrix on an insulating substrate; a thin film transistor connected to the pixel electrode; and an auxiliary capacitor for holding a charge via the thin film transistor. A storage capacitor is formed along the inner wall of the groove formed in the main surface of the insulating substrate and is formed on the main surface of the thin film transistor.
A first electrode layer continuously formed up to the conductor layer , and a gate insulating film of the thin film transistor on the first electrode layer
A dielectric film formed of the same material as the over the dielectric layer
A second electrode layer formed of the same material as a gate electrode of the thin film transistor, and a region of the first electrode layer formed on the main surface has an area dimension including an opening of the groove. Yes, and the opening of the groove, said first conductive
An active matrix substrate, wherein the active matrix substrate is arranged at least 0.5 μm inside the region of the pole layer . 2. A substrate having a pixel electrode arranged in a matrix, a thin film transistor connected to the pixel electrode, and an auxiliary capacitor for holding an electric charge through the thin film transistor, and a counter electrode. In a liquid crystal display device comprising: the other substrate opposed to the one substrate; and a liquid crystal layer held between the two substrates, the auxiliary capacitance is formed in a groove formed on a main surface of the one substrate. Of the thin film transistor along the inner wall of and on the main surface
A first electrode layer continuously formed up to the semiconductor layer , and a gate insulating layer of the thin film transistor on the first electrode layer;
A dielectric film formed of the same material as the film, before over this dielectric layer
A second electrode layer formed of the same material as the gate electrode of the thin film transistor, and a region of the first electrode layer formed on the main surface including an opening of the groove; have a, the opening of the groove, the first
A liquid crystal display device, wherein the liquid crystal display device is arranged at least 0.5 μm inside the region of the electrode layer . 3. A semiconductor wherein the thin film transistor is formed along the inner wall of another groove formed on the main surface of one substrate simultaneously with the groove, and is formed of the same material as the first electrode layer. 3. The semiconductor device according to claim 2, comprising a layer, a gate electrode formed of the same material as the second electrode layer, and a gate insulating film interposed between the gate electrode and the semiconductor layer. Liquid crystal display. 4. An active matrix substrate comprising: a pixel electrode arranged in a matrix on an insulating substrate; a thin film transistor connected to the pixel electrode; and an auxiliary capacitor for holding a charge through the thin film transistor. At least one of the storage capacitor and the thin film transistor is, the insulating the storage capacitor is formed continuously until on along and the main surface to the inner wall of the grooves formed on the main surface of the substrate 及
And a first electrode layer common to the thin film transistors, and the auxiliary capacitor and the thin film transistor formed on the first electrode layer.
A common insulating film, and the auxiliary film formed on the insulating film.
An active layer comprising a second electrode layer common to the capacitor and the thin film transistor, and at least one side of the first electrode layer formed on the bottom of the groove is inside the bottom end of the groove. Matrix substrate. 5. The active matrix according to claim 4, wherein at least one side of the first electrode layer formed on the main surface of the insulating substrate does not extend outside the opening end of the groove. substrate. 6. A substrate including a pixel electrode arranged in a matrix, a thin film transistor connected to the pixel electrode, and an auxiliary capacitor for holding an electric charge via the thin film transistor, and a counter electrode. In a liquid crystal display device comprising: the other substrate facing the one substrate; and a liquid crystal layer held between the two substrates, at least one of the auxiliary capacitor and the thin film transistor is provided on a main surface of the insulating substrate. The auxiliary capacitor and the auxiliary capacitor formed continuously along the inner wall of the formed groove and up to the main surface.
And a first electrode layer common to the thin film transistors, and the auxiliary capacitor and the thin film transistor formed on the first electrode layer.
A common insulating film and the auxiliary film formed on the insulating film.
A liquid crystal comprising a capacitor and a second electrode layer common to the thin film transistor , wherein at least one side of the first electrode layer formed on the bottom of the groove is inside the bottom end of the groove. Display device.