JPH0534709A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To obviate the generation of level differences in the liquid crystal display device formed with additive capacitors of a trench type and to avert the generation of the disconnection of picture element electrodes, etc., by forming the front surface of the upper layer electrodes in the trenches to the same flat surface as the surface of dielectric layers. CONSTITUTION:This liquid crystal display device has substrates 1 and 2 facing each other, a liquid crystal layer 3 disposed between the substrates 1 and 2, liquid crystal picture element electrodes 51 arranged in a matrix shape, and thin-film transistors TFTs connected to the picture element electrodes 51. The additive capacitors Cs consisting of the electrodes 21 of the same layers as the semiconductor layers 4 of the TFTs, the dielectric layers 23 of the same layers as gate insulating layers 8, and the electrodes 22 of the same layers as the gate electrodes 9 are formed in the trenches 70 formed on the opposite surface 1a of the substrate 1 on which the TFTs are disposed. The electrodes 22 are formed to the same plane as the surface of the dielectric layers 23. Then, the generation of the disconnection of the steps, etc., is obviated even if interlayer insulating layers 53 and the picture element electrodes 51 are successively formed on the flat surface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art Active matrix liquid crystal display devices are
As shown in FIG. 9, each liquid crystal pixel 62 is driven by the switching elements 61 arranged in a matrix.

In FIG. 9, 63 is the vertical scanning circuit,
Reference numeral 64 represents a video signal sample hold circuit.

In this structure, after the switching elements 61 are sequentially turned on to write a potential in the liquid crystal pixels 62,
Although it is necessary to hold the potential for a predetermined time, the transistor serving as the switching element 61 actually has a leak current even when the transistor is off. Therefore, an additional capacitance C _S for compensating for the leak current is provided for each pixel.

Such an active matrix liquid crystal display device is remarkably popularized because the problem of crosstalk between pixels is improved and a fine image can be displayed.

In a liquid crystal display device of this type, when a transmissive structure is adopted as shown in a sectional view of an essential part of an example of the liquid crystal display device, the inner surface of each of the liquid crystal display devices is transparent, for example, ITO (composite oxide of indium and tin). ), The transparent electrodes 1 and 2 facing each other on which the pixel electrode 51 and the counter electrode 52 for applying a voltage to the liquid crystal are formed, and the liquid crystal layer 3 filled with the liquid crystal is disposed therebetween.

A semiconductor layer 4 made of, for example, a polycrystalline silicon layer is formed on the inner surface of one substrate 1, for example, a quartz substrate or a glass substrate.

In the semiconductor layer 4, source / drain (S / D) regions 5 and 6 which form a thin film transistor TFT which becomes a switching element 61 of each pixel, and a channel forming region 7 are formed between them.

Further, the channel forming region 7 of the semiconductor layer 4 is formed.
The gate insulating layer 8 is formed on the gate insulating layer 8 and the gate electrode 9 is formed on the gate insulating layer 8.
Is configured.

In the illustrated example, the gate insulating layer 8 of the thin film transistor TFT is made of, for example, Si in order to increase the breakdown voltage.
A lower first insulating layer 31 made of O ₂ is formed, and a second insulating layer 32 made of, for example, Si ₃ N ₄ is formed thereon to form a multi-layer structure.

On the other hand, in the other part of the substrate 1, an additional capacitance C _S is formed at the same time as the fabrication of the thin film transistor TFT in the same step.

In the illustrated example, for example, Japanese Patent Laid-Open No. 64-812
As disclosed in Japanese Patent Laid-Open No. 62-62, its additional capacitance C _S
Shows a case where a trench type structure is adopted.

That is, in this case, a long groove 70 is formed in a predetermined portion of the surface 1a of the substrate 1 facing the substrate 2, and the semiconductor layer 4 is formed including the inner surface of the groove 70, whereby the additional capacitance C An insulating layer having the same structure as the gate insulating layer 8 of the thin film transistor TFT is formed as the dielectric layer 23, which is one of the first electrodes 21 constituting _S , and T is formed on the insulating layer.
The second electrode 22 is formed simultaneously with the formation of the gate electrode 9 of the FT transistor, and a trench type additional capacitance C _S is formed between the two electrodes 21 and 22.

In this case, the inside of the groove 70 is mainly the second electrode 2.
2, the second electrode 22 is normally wider than the groove width We of the portion of the groove 70 in which the second electrode 22 is actually buried, that is, the upper insulating layer 32. , Is formed by pattern etching by photolithography on the surface on both sides of the second electrode 22 having the width Ws on the upper surface along the surface 1a of the substrate 1, and therefore, the second side edge portion has A step 71 is created.

Reference numeral 53 is an interlayer insulating layer made of, for example, PSG (phosphosilicate glass) formed so as to cover the thin film transistor TFT, the additional capacitor C _S, etc., and the semiconductor layer 4 is formed through a contact window 53W ₁ formed in the insulating layer 53. Of the thin film transistor TFT, the low resistivity region 11 connected to one of the S / D regions 5, that is, one of the high concentration S / D regions is formed of an Al layer or the like connected to the sample hold circuit 64 shown in FIG. The wiring layer 54 to be the signal line is ohmic-contacted.

Further, an interlayer insulating layer 53 similar to that described above is further formed thereon.

A low resistivity region 10, that is, the other S / D region is formed adjacent to the other S / D region 6 of the semiconductor layer 4 of the thin film transistor TFT, and a contact formed in the interlayer insulating layer 53 in this region 10 is formed. A pixel electrode 5 formed of a transparent conductive layer through the window 53W ₂ and provided for each liquid crystal pixel
1 is formed in ohmic contact and extends over the effective screen of the liquid crystal display.

However, in the case of such a configuration, as described above, the surface of the dielectric layer 23 where the second electrode 22 extends along the surface 1a of the substrate 1 over the insulating layer 32, that is, Since it is formed over the surface of the second insulating layer 32, the step 71 is formed by the side edge thereof. Therefore, there is a problem that the pixel electrode 51 is broken at the step 71, for example. Actually, since the pixel electrode 51, that is, the transparent electrode is formed as a thin film, that is, a thin film having a thickness of about 1400Å, there is a problem that step breakage or disconnection occurs, which causes defective products or lowers reliability.

[0019]

SUMMARY OF THE INVENTION The present invention provides a liquid crystal display device in which the above-mentioned trench type additional capacitance is formed, in which a disconnection of a pixel electrode or the like is generated due to a step due to an edge portion of an upper layer electrode in the trench. A highly reliable liquid crystal display device that effectively avoids the above problem.

[0020]

As shown in FIG. 1 which is a cross-sectional view of a main part of the present invention, the present invention is directed to substrates 1 and 2 facing each other and a liquid crystal layer disposed between the substrates 1 and 2. 3 and
A liquid crystal display device is formed which includes liquid crystal pixel electrodes 51 arranged in a matrix on a surface 1a of one substrate 1 facing the other substrate 2 and thin film transistors TFT connected to the pixel electrodes 51. .

Then, in the groove 70 formed in the facing surface 1a of the substrate 1 on which the thin film transistor TFT is arranged, the first electrode 21 made of the same layer as the semiconductor layer 4 of the thin film transistor TFT and the gate insulating layer 8 of the thin film transistor TFT.
Of the dielectric layer 23, which is at least the same layer as one component layer, and the second electrode 2, which is the same layer as the gate electrode 9 of the thin film transistor TFT
A trench type additional capacitance C _S consisting of 2 and 3 is formed.

In the present invention, the second electrode 22
Is the same plane a as the surface of the dielectric layer 23 along the facing surface 1a of the substrate 1.

Further, according to the present invention, as shown in FIG. 6 which is a sectional view of a main part of the example, a groove 80 for forming a thin film transistor TFT is provided in the substrate 1 on which the liquid crystal pixel electrode 51 is formed, and this groove is formed. A semiconductor layer having a width smaller than the length of the groove 80 is formed along the inside of the groove 80, and the gate insulating layer 8 is formed on the semiconductor layer.
And a gate electrode 9 are provided to form a trench type thin film transistor. 6, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted.

[0024]

According to the present invention described above, the trench type additional capacitance C _S is formed, and the upper surface of the second electrode 22 filling the trench is made flush with the surface of the dielectric layer 23. Therefore, the step 71 described with reference to FIG. 8 is eliminated, and thereby, the step breakage of the pixel electrode 51 and the like formed thereon can be avoided.

Further, by forming the transistor TFT as a switching element in the same trench structure,
The surface of the gate electrode 9 can be made flush with the surface of the gate insulating layer 8, and the overall planarization can be achieved.
Patterning of each pixel electrode, wiring layer, etc., for example, high precision of photolithography can be improved.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the present invention will be described with reference to FIG. 1, parts corresponding to those in FIG. 8 are designated by the same reference numerals. As described above, the present invention has a matrix-like structure on the facing surfaces 1a of the substrates 1 and 2 facing each other, the liquid crystal layer 3 arranged between the substrates 1 and 2, and the one substrate 1 and the other substrate 2. A liquid crystal display device having a liquid crystal pixel electrode 51 arranged in the pixel array and a thin film transistor TFT connected to the pixel electrode 51 is configured.

Then, in the groove 70 formed in the facing surface 1a of the substrate 1 on which the thin film transistor TFT is arranged, the first electrode 21 made of the same layer as the semiconductor layer 4 of the thin film transistor TFT and the gate insulating layer 8 of the thin film transistor TFT are formed. A dielectric layer 23 at least in the same layer as one component layer, and a second electrode 22 in the same layer as the gate electrode 9 of the thin film transistor TFT.
Forming a trench type additional capacitance C _S.

In the present invention, the second electrode 22
Is the same plane a as the surface of the dielectric layer 23 along the facing surface 1a of the substrate 1.

Next, an example of the liquid crystal display device according to the present invention shown in FIG. 1 will be described in detail together with an example of a manufacturing method thereof with reference to FIGS.

First, as shown in FIG. 2A, a transparent substrate constituting one substrate 1 of the finally obtained liquid crystal display device, for example, a substrate of quartz, glass or the like having a thickness of, for example, 800 μm is prepared and finally obtained. On the inner surface of the liquid crystal display device, that is, on one smooth surface side that is the facing surface 1a facing the other substrate 2,
Finally, the groove 70 is formed in the additional capacitance forming portion of each pixel.

The groove 70 can be formed by selectively chemically etching the surface 1a of the substrate 1. The groove 70 is formed with a predetermined length in a direction orthogonal to the paper surface of FIG. 2, and the depth d thereof is selected to be 2 μm and the width W thereof is selected to be 1.0 μm, for example.

As shown in FIG. 2B, a first semiconductor made of, for example, polycrystalline silicon having a thickness of 800 Å is formed along the bottom surface of the groove 70 and the opposite side surfaces by, for example, LP-CVD (Low Pressure Chemical Vapor Deposition). The layer 4 is grown over the entire surface, and Si is ion-implanted over the entire surface. Then, finally, the channel forming region 7 of the thin film transistor TFT is formed.
A first conductivity type impurity such as p-type impurity,
For example, B (boron) is entirely ion-implanted.

Thereafter, the semiconductor layer 4 is selectively photolithographically formed in a desired pattern, that is, an effective display portion for performing liquid crystal display, other portions, for example, leaving a portion for forming the thin film transistor TFT and the additional capacitance C _S. Etching is performed to form a desired pattern.

Then, the surface of the semiconductor layer 4 is thermally oxidized to form a first insulating layer 31 made of SiO ₂ .

As shown in FIG. 3A, a resist 72, for example, a photoresist is applied, exposed, and developed to open a window in a portion where the additional region C _S is finally formed to cover the other portion and to cover the other portion. Ion implantation is performed, for example, at 5 × 10 ¹⁴ cm
The first electrode 21 is formed in a predetermined portion in the groove 70 and around the groove 70, which is formed of a part of the semiconductor layer 4, by implanting at a dose of ^-2 .

As shown in FIG. 3B, the resist 72 is removed, and the second insulating layer 32 made of, for example, SiO ₂ and having a thickness of, for example, 600 Å is entirely formed including the inside of the groove 70 by HTO (High Temparature Oxide). To form.

Thereafter, similarly, by LP-CVD or the like, a second semiconductor layer 73 made of, for example, polycrystalline silicon having a thickness of 3500Å is filled in the groove 70, and the substrate 1 is formed on the second insulating layer 32. It is formed as a flat surface along the surface 1a. In order to form such a flat surface in the second semiconductor layer 73 and prevent inconvenience such as stress from occurring, in practice, the width W of the groove 70 is 1/3 times or more and 10 times or less, preferably The film thickness of the second semiconductor layer 73 is selected to be 7 times or less.

Then, the second semiconductor layer 73 is doped with a second conductivity type impurity such as phosphorus by a well-known technique, for example, deposition or diffusion of phosphorus silicate, to reduce the specific resistance, and then this Phosphorus silicate glass PS
The G is removed by etching.

Next, as shown in FIG. 4A, the second line of FIG. 3B is used.
An etching resist 74 such as a photoresist is applied, exposed, and developed only on a portion where a gate portion of a thin film transistor to be finally formed on the semiconductor layer 73 is formed. In this case, no resist is formed on the groove 70.

In this way, the resist 74 in the gate portion is removed.
In the area where the additional capacitance is formed by etching resist,
The second semiconductor layer 73 is entirely etched. This
Forming the gate electrode 9 under the resist 74
Also, in the region including the other portion forming portion, substantially the entire surface
Etching to form a gate insulating layer in the trench 70
Semiconductor layer in the groove 70 formed in the second insulating layer 32
Only 73 is additional capacity C _SThe second electrode 22 is left. This
In the case of, etching for this second semiconductor layer 73
Is an additional capacitance other than the portion where the gate electrode 9 is formed.
C_SIn the part where the
The second semiconductor layer 73 formed in the groove 70
A second insulation layer in which the surface of the electrode 22 is just parallel to the surface 1a of the substrate 1 is formed.
Etch up to the position where the same flat surface a as the surface of the edge layer 32 is formed.
Ching.

Further, when the gate electrode 9 is further provided,
Using the resist 74 as an ion implantation mask, for example, an n-type impurity As of the second conductivity type is ion-implanted with a dose amount of 1 × 10 ¹³ cm ⁻² , and finally S /
D regions 5 and 6 are formed.

Next, as shown in FIG. 4B, for example, the resist 74 is once removed, and an ion-implanted resist 75 made of, for example, photoresist is formed on both side surfaces of the gate electrode 9 on the source and drain sides with a predetermined width. For example, As of the second conductivity type is ion-implanted at a dose amount of 2 × 10 ¹⁵ cm ⁻² to form a high concentration S / D region, that is, low specific resistance regions 10 and 11.
To form.

As shown in FIG. 5A, the resist 75 is removed and an interlayer insulating layer 53 such as PSG (phosphorus silicate glass) is formed on the entire surface by LP-CVD or the like. Then, a contact window 53W _{1 is formed} on a part of the low resistivity region 11.
It was formed by etching or the like by photolithography, the low resistivity region 1 through the contact window 53W ₁
A conductive layer of Al or the like is formed over the entire surface by vapor deposition sputtering or the like in ohmic contact with 1, and is patterned by photolithography to form a signal line wiring layer 54.
To form.

As shown in FIG. 5B, a similar interlayer insulating layer 53 is further formed on the entire surface, and the low resistivity region 10 is similarly etched by photolithography to form a contact window 53W ₂ . Throughout this, IT
A transparent conductive layer such as O is formed by vapor deposition, sputtering, etc.,
Similarly, this is patterned by photolithography to form the pixel electrode 51.

In this case, since the interlayer insulating layer 53 and the pixel electrode 51 are sequentially formed on the flat surface a as described above, it is possible to form an accurate pattern without causing step breakage or the like. .

Then, although not shown, an alignment layer of polyimide or the like including the pixel electrode 51 is formed. On the other hand, as shown in FIG. 1, the counter electrode 52 made of a transparent electrode is formed on the inner surface of the other substrate 2 as well. Although not shown, an alignment layer made of polyimide or the like is formed on this, and the liquid crystal layer 3 is filled between the two.

In this way, the liquid crystal display device according to the present invention described with reference to FIG. 1 is constructed.

In the above-mentioned example, the liquid crystal display device is constructed by the planar type thin film transistor TFT and the trench type additional capacitance C _S. As shown in FIG. Can have a trench configuration.

Also in this case, the same steps as those shown in FIGS. 2 to 5 can be adopted. In this case, in the step described in FIG. 2A, the groove 70 is formed and the same groove is formed in the thin film transistor TFT formation portion. 80, that is, a trench is formed, and the second semiconductor layer 73 is formed by filling the groove 80 and flattening the surface by taking the same steps as in FIGS.

As shown in FIG. 7B, the entire surface of the second semiconductor layer 73 forms the same flat surface a as the surface of the second gate insulating layer 32 which is parallel to the surface 1a of the substrate 1. So that it is etched. That is, the trench type additional capacitance C
The gate electrode 9 of the thin film transistor TFT is also formed in the groove 80 on the same plane a as the second electrode 22 in _s .

The part of the second semiconductor layer 73 left in the groove 80 in this way constitutes the gate electrode 9 of the thin film transistor TFT to be finally formed, and the first and second insulating layers outside the gate electrode 9 are formed. The gate insulating layer 8 is constituted by 31 and 32.

Next, as shown in FIG. 8A, a resist 74 which is wider than the gate electrode 9 and serves as an ion implantation mask made of, for example, photoresist is formed, and a second conductivity type, for example, n-type impurity As is added, for example. Ions are implanted at a dose of × 10 ¹³ cm ^-2 to form low-concentration S / D regions 5 and 6.

As shown in FIG. 8B, a resist 75, which is wider than the resist 74 and is made of, for example, a photoresist and serves as an ion implantation mask, is formed.
Conductive type, eg, n-type impurity As, for example, 2 × 10 ¹⁵ cm
Ions are implanted at a dose of ^-2 to form high-concentration S / D regions, that is, low resistivity regions 10 and 11.

After that, as described above, as shown in FIG. 6, the formation of the interlayer insulating layer 53 and the contact window 53W ₁
, The wiring layer 54, the interlayer insulating layer 53, the contact window 53W ₂ and the pixel electrode 51 are formed. In FIG. 6, parts corresponding to those in FIG. 1 are designated by the same reference numerals and duplicate description will be omitted.

As described above, when the thin film transistor TFT also adopts the trench type structure, the overall flattening and area can be achieved. Therefore, it is possible to improve reliability in reducing the area of each pixel and reduce the area where each element C _S and TFT is formed, and to increase the effective area of liquid crystal display.

As described above, in the steps of FIGS. 3B and 7B, the film thickness of the second semiconductor layer 73 is set to the grooves 70 and 8.
When it is selected to be 1/3 or more of the width of 0, the surface can be flattened. This means that when the width of the grooves 70 and 80 is 1.2 μm, for example, the total thickness of the first polycrystalline silicon semiconductor layer 4 and the insulating layers 31 and 32 is about 0.
Since it is about 16 μm, both grooves 7 are formed by CVD.
The semiconductor layer 73 grows from each inner surface of the groove
The thickness of the second semiconductor layer 73 required to fill 0,80 is 0.34 μm obtained by subtracting 0.16 μm from 1/2 of 1.0 μm, that is, 0.34 μm / 1.0 μm≈1.
It is understood that it is / 3.

In the above-mentioned example, the TFT transistor has an n-channel type structure. However, as the p-channel type structure, the conductivity type of each part shown in the figure can be selected to be the conductivity type opposite to that shown in the figure.

In the above example, although the description is omitted, in actuality, when a C-MOS structure is adopted in other peripheral driving circuits, a thin film transistor having a conductivity type opposite to that of the thin film transistor TFT is used. The forming step can be introduced within a suitable manufacturing step of the steps described above.

[0059]

As described above, according to the present invention, the train
Chi type additional capacity C_S, And this capacity C _SAnd switching
A trench type transistor TFT is formed as an element.
However, from now on, the second electrode 22 and the gate electrode
The upper surface is used as a peripheral insulating layer, and in the above example, the second insulating layer 32.
Since it is formed as the same flat surface a, it is formed on this
It is possible to avoid step breaks in the pixel electrode 51, etc.
It is possible to obtain a liquid crystal display device having low reliability and high reliability.

Further, in spite of adopting the above-mentioned structure,
There is no particular increase in the number of steps, and in the manufacture thereof, the second electrode 22 made of the second semiconductor layer 73 embedded in the groove 70 of the trench type additional capacitance C _S and the upper surface of the gate electrode 9 are made flat. Since it can be formed by etching the entire surface, strict mask alignment and the like when forming it by pattern etching are eliminated, and the manufacturing is further simplified.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a main part of an example of a liquid crystal display device according to the present invention.

FIG. 2 is a process diagram (1) of a manufacturing method of an example of the device of the present invention.

FIG. 3 is a process diagram (2) of the manufacturing method of the example of the device of the present invention.

FIG. 4 is a process diagram (3) of the manufacturing method of the example of the device of the present invention.

FIG. 5 is a process diagram (4) of the manufacturing method of the example of the device of the present invention.

FIG. 6 is a sectional view of a main part of a liquid crystal display device as another example of the device of the present invention.

FIG. 7 is a manufacturing process diagram (1) of an example thereof.

FIG. 8 is a manufacturing process diagram (2) of the example.

FIG. 9 is a configuration diagram of a liquid crystal display device.

FIG. 10 is a cross-sectional view of a main part of a conventional liquid crystal display device.

[Explanation of symbols]

1 Substrate 2 Substrate 3 Liquid Crystal Layer 70 Groove 80 Groove 4 Semiconductor Layer 73 Second Semiconductor Layer TFT Thin Film Transistor C _S Additional Capacitance

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 29/784 21/336

Claims (2)

[Claims] 1. A substrate facing each other, a liquid crystal layer disposed between the substrates, liquid crystal pixel electrodes arranged in a matrix on a surface of one of the substrates facing the other substrate, and the pixel electrode. A liquid crystal display device comprising a thin film transistor connected to the thin film transistor, wherein a first electrode formed of the same layer as the semiconductor layer of the thin film transistor is provided in a groove formed in the facing surface of the substrate on which the thin film transistor is arranged. A dielectric layer in the same layer as at least one constituent layer of the gate insulating layer of the thin film transistor, and a second layer in the same layer as the gate electrode of the thin film transistor.
A liquid crystal display device, wherein a trench-type additional capacitance including an electrode is formed, and a surface of the second electrode is formed in the same plane as a surface of the dielectric layer along the facing surface of the substrate. 2. A groove for forming a thin film transistor is provided on a substrate on which a liquid crystal pixel electrode is formed, and a groove for forming a thin film transistor is provided on the substrate, and the length of the groove is smaller than the length of the groove along the inside of the groove. The liquid crystal display device according to claim 1, wherein a semiconductor layer having a width is formed, and a gate insulating layer and a gate electrode are provided thereon to form a trench type thin film transistor.