JPH10133233A - Active matrix type display circuit and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure for obtaining auxiliary capacitors of an active matrix type display circuit formed by using thin-film transistors(TFTs). SOLUTION: The interlayer insulator between the gate wirings 4 and data wirings of the active matrix type display circuit formed by using the top gate type TFTs is formed of a multilayered structure composed of thin silicon nitride films 3 and polyimide films 8. The capacitors consisting of dielectric substances 3 for the silicon nitride films are formed between the conductive films which are the upper layers of the data wirings and function as black matrices 11 and active layers 2 which are doped to an N type or P type by etching the polyimide 8 of the parts to be formed with the auxiliary capacitors.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a circuit configuration of a pixel region of an active matrix display device using a top gate thin film transistor. In particular, it relates to the configuration of the auxiliary capacitance.

[0002]

2. Description of the Related Art Recently, a technique for manufacturing a thin film transistor (TFT) on an inexpensive glass substrate has been rapidly developed. The reason is that the demand for the active matrix type liquid crystal display device has increased. The active matrix type liquid crystal display device has a configuration in which tens to millions of pixels arranged in a matrix are each provided with a thin film transistor, and electric charges flowing into and out of each pixel electrode are controlled by a switching function of the thin film transistor. .

A liquid crystal is sandwiched between each pixel electrode and a counter electrode to form a kind of capacitor. Therefore,
By controlling the flow of charges into and out of the capacitor by the thin film transistor, the electro-optical characteristics of the liquid crystal are changed, and light transmitted through the liquid crystal panel can be controlled to display an image. In addition, since the holding voltage of the capacitor having such a configuration gradually decreases due to current leakage, there is a problem that the electro-optical characteristics of the liquid crystal change and the contrast of image display deteriorates.

In order to solve this problem, it is a general practice to provide another capacitor called an auxiliary capacitor in series with the capacitor composed of liquid crystal, and to supply charges lost due to leakage or the like to the capacitor composed of liquid crystal. FIG. 4 shows a circuit diagram of a conventional active matrix type liquid crystal display device. An active matrix display circuit is roughly divided into three parts. That is, a gate driver circuit 62 for driving a gate wiring (scan wiring, scanning wiring) 64,
A data driver circuit 61 for driving data lines (source lines and signal lines) 65 and an active matrix circuit 63 provided with pixels are provided. Among them, the data driver circuit 61 and the gate driver circuit 62 are collectively called peripheral circuits.

In the active matrix circuit 63, a large number of gate wirings 64 and data wirings 65 are provided so as to cross each other, and a pixel electrode 67 is provided at each intersection. In addition, a switching element (thin film transistor) 66 for controlling the charge flowing into and out of the pixel electrode is provided. Further, as described above, the auxiliary capacitance 68 is provided in parallel with the capacitor of the pixel in order to suppress the fluctuation of the voltage of the pixel due to the leak current. (FIG. 4)

Reference numeral 105 denotes a semiconductor layer constituting an active layer of the thin film transistor, 106 denotes a contact portion with a data line, and 107 denotes a contact portion with a pixel electrode. Various methods have been proposed for forming the auxiliary capacitance, but the most typical structure is a structure using an overlap of an active layer (semiconductor layer) of a thin film transistor and a gate wiring. FIG. 3 shows the state of the cross section by explaining a manufacturing process. An intrinsic active layer 42 is formed on a substrate 41 and selectively doped with N-type or P-type impurities to form a conductive region 44. Further, a gate insulating film 43 is formed so as to cover the active layer, and gate wirings 45 and 46 are formed. (FIG. 3 (A))

Generally, gate lines 45 and 46 use lines in different rows. In the pixel shown in FIG.
Function as a gate electrode of the thin film transistor, and the gate wiring 46 functions as an electrode of the storage capacitor 49. if,
If the gate wirings 45 and 46 are formed in the same row, the parasitic capacitance between the drain of the thin film transistor and the gate electrode becomes extremely large, which hinders switching. Although the gate wiring 46 is for the purpose of forming an auxiliary capacitance in the drawing, it is not usually performed to form a separate wiring solely for that purpose in order to increase the aperture ratio.

Next, using the gate electrode as a mask, an impurity of the same conductivity type as that of the conductive region 44 is implanted in a self-aligned manner,
A source 47 and a drain 48 are formed. Thus, an auxiliary capacitance 49 is formed between the gate wiring 46 and the conductive region 44 and the drain 48. (FIG. 3B) Thereafter, a first layer 51 of a silicon nitride layer 50 as a passivation film and a layer 51 of a material suitable for planarization such as polyimide is formed.
Is formed, and this is etched to form a contact hole reaching the source 47.
2 is provided. (FIG. 3 (C))

Since the conductivity of the thin film transistor changes due to light irradiation, a light-shielding coating (black matrix) 54 is overlaid on the thin film transistor in order to prevent the change. Further, the above-mentioned light-shielding film is also formed between pixels in order to prevent mixing of colors and brightness between pixels and to prevent display failure due to disturbance of an electric field at a boundary portion between pixels. For this reason, this light-shielding coating has a matrix shape and is called a black matrix (BM). B
M54 is formed on the second interlayer insulator 53. (FIG. 3 (D))

After that, a third interlayer insulator 55 is formed,
This is etched to form a contact hole reaching the drain 48 (or the conductive region 44), and the pixel electrode 56 is formed by a transparent conductive film. BM
Is formed of an insulating material, the third interlayer insulator 5
5 is unnecessary. (FIG. 3 (E))

[0011] Among the above steps, the main steps are listed as follows. A Process for forming active layer 42 B Selective doping process for forming conductive region 44 C Process for forming gate insulating film 43 D Process for forming gate wires 45 and 46 E Self-forming process for forming source 47 and drain 48 Consistent doping step F Step of forming first interlayer insulators 50 and 51 G Step of forming contact hole H Step of forming data wiring 52 I Step of forming second interlayer insulator 53 J Step of forming black matrix K Step 3 of forming interlayer insulator 55 L Step of forming contact hole M Step of forming pixel electrode 56 Of these, steps A and P involve a photolithography step.
8 steps of B, D, G, H, J, L and M.

[0012]

The active matrix circuit having the above structure has a feature that a large capacity can be obtained because a gate insulating film having a high withstand voltage can be used as an insulator (dielectric) of an auxiliary capacitor. doing. However, it also has the following disadvantages. (1) The doping process is required twice, and a photolithography process for defining the doping region is required to form the conductive region 44. (2) Since the gate wiring 46 also serves as an auxiliary capacitance electrode, the parasitic capacitance of the wiring becomes large, and the operation speed and the signal shape are reduced.

Regarding the above (1), if doping of the source and drain is also performed in the step B, the doping step can be performed once. However, in such a case, the transistor does not become a self-aligned transistor, and the parasitic capacitance is large and may vary from transistor to transistor. Also, in this case, a photolithography step at the time of doping is necessary.

The process of the improved type is as follows. A Step of forming active layer 42 B ′ Selective doping step for forming conductive region 44, source 47 and drain 48 C Step of forming gate insulating film 43 D Step of forming gate wirings 45 and 46 (corresponding to E) F) Step of forming first interlayer insulators 50 and 51 G Step of forming contact holes H Step of forming data wiring 52 I Step of forming second interlayer insulator 53 J Step of forming black matrix 54 K Step 3 of forming interlayer insulator 55 L Step of forming contact hole M Step of forming pixel electrode 56

The photolithography process involves eight processes A, B, D, G, H, J, L and M. Regarding the above (2), there is a method of separately providing the gate wiring and the wiring of the auxiliary capacitance. However, as described above, the area occupied by the wiring increases by that amount, and the aperture ratio decreases. The present invention has been made to solve the above problems (1) and (2).

[0016]

According to the invention disclosed in this specification, a capacitance is formed between a black matrix and an N-type or P-type active layer as an auxiliary capacitance, and a first dielectric is used as a dielectric. 3 is characterized in that a silicon nitride layer (corresponding to the silicon nitride layer 50 in FIG. 3) used as a passivation film of the interlayer insulator is used.

The active matrix type display circuit of the present invention comprises a top gate type thin film transistor, an N-type or P-type active layer, a conductive film which functions as a black matrix and is maintained at a constant potential, a gate wiring and a data wiring. A first interlayer insulator between the gate wiring and the data wiring and having a silicon nitride layer and a polyimide layer (the silicon nitride layer is below the polyimide layer); and a second interlayer insulating material between the data wiring and the conductive coating. And an interlayer insulator.

A first aspect of the present invention is that, in the above structure, an active layer and a conductive film are used as both electrodes in a portion where the polyimide layer of the first interlayer insulator and the second interlayer insulator are etched, An auxiliary capacitor having at least a silicon nitride layer as a first interlayer insulator as a dielectric is formed.

According to a second aspect of the present invention, in the above structure, in the first interlayer insulator, a conductive film is provided on a portion of the first interlayer insulator overlapping with the active layer, the portion being in contact with the silicon nitride layer of the first interlayer insulator. It is characterized by having. In the first or second aspect of the present invention, if the active layer functioning as an auxiliary capacitance electrode has a structure continuous with the source or drain of the thin film transistor, the circuit structure is simple and the occupied area can be reduced. .

The dielectric of the auxiliary capacitance may have a multilayer structure of a gate insulating film and a silicon nitride layer, or may have only a silicon nitride layer. In the former case, the probability of a short circuit is reduced by utilizing the breakdown voltage of the gate insulating film. In the latter case, a larger capacitance can be obtained by using silicon nitride having a thin dielectric and a large dielectric constant. In the first or second aspect of the present invention, the thickness of the silicon nitride layer is 1000 ° or less, preferably 500 ° or less.

The main steps for obtaining the configuration of the present invention are listed below. a Step of forming active layer (No step corresponding to B) c Step of forming gate insulating film d Step of forming gate wiring e Self-aligned doping step for forming source and drain (conductive region) f First Step of forming contact hole h Step of forming data wiring i Step of forming second interlayer insulator x Step of etching auxiliary storage hole j Formation of black matrix Step k Step of forming third interlayer insulator l Step of forming contact hole m Step of forming pixel electrode

The photolithography process involves eight processes a, d, g, h, x, j, l, and m. The total number of steps is 13 steps compared to 13 steps of the conventional example and 12 steps of the improved version thereof. Therefore, although it seems to be inferior to the improved version of the conventional example, in that the thin film transistor is formed in a self-aligned manner,
Because of the superiority, even if the number of steps is increased by one, the superiority of the present invention does not change. The number of photolithography steps is the same as in the conventional example, its improved type, and the present invention. Since the thin film transistor is a self-aligned type, the present invention is equivalent to the conventional example, and the number of the doping step is one.
It can be concluded that the number of times is superior to the conventional example.

As described above, the present invention has an advantage in mass production because the number of doping can be one. In addition, according to the present invention, since the gate wiring does not serve as an electrode of the storage capacitor, there is no problem such as a dull gate signal. However, this does not deny the combination of the present invention with the structure of the conventional example. It is beneficial to combine them to get a larger capacity. Further, adding a further step in addition to the above-mentioned steps to achieve a more sophisticated circuit is not against the gist of the present invention. For example, the number of steps may be increased in order to manufacture a thin film transistor having a more advanced structure. The same applies to the wiring structure.

[0024]

[Embodiment 1] A manufacturing process of this embodiment is shown in FIG. First,
Next, an amorphous silicon film is formed to a thickness of 500 .ANG. On a glass substrate 1 on which a silicon oxide film is formed as a base film to a thickness of 3000 .ANG. By sputtering or plasma CVD.
The film is formed by a method or a low pressure thermal CVD method. Then, a crystalline silicon film is obtained by heating or irradiation with a laser beam. By etching this, the active layer 2 of the thin film transistor is obtained.

Next, a silicon oxide film 3 is formed as a gate insulating film to a thickness of 1000 ° by a plasma CVD method, a low pressure thermal CVD method or a sputtering method. Then, a polycrystalline silicon film containing phosphorus is formed to a thickness of 5000 ° by a low pressure CVD method, and the gate wiring 4 is obtained by etching the film. (Fig. 1 (A))

Next, a source 5 and a drain 6 are formed by implanting ions of phosphorus, which is an impurity imparting N-type, at a dose of 5 × 10 ^{14 to} 5 × 10 ¹⁵ atoms / cm ³ . Both are N-type. After implantation of impurity ions,
By performing heat treatment, laser light irradiation, or intense light irradiation, the region into which the impurity ions have been implanted is activated. (FIG. 1 (B))

Next, the silicon nitride film 7 is
Or silane and N ₂ O, or silane, ammonia and N
_{It is} formed by a plasma CVD method using ₂ O. This silicon nitride film 7 is formed to a thickness of 250 to 1000 °, here 500 °. The method for forming the silicon nitride film may be a method using dichlorosilane and ammonia. Alternatively, a low pressure thermal CVD method or a photo CVD method may be used.

After the formation of the silicon nitride film, at a temperature of 350.degree.
By performing the heat treatment for a long time, the surfaces of the silicon oxide film 3, the source 5, and the drain 6 damaged by the previous impurity ion implantation are annealed. In this step, defects existing on the surfaces of silicon oxide film 3, source 5 and drain region 6 are removed by diffusion of hydrogen from silicon nitride film 7. Further, hydrogen diffuses also into the channel forming region below the gate wiring 4, and the defect is removed.

Subsequently, by a spin coating method,
The polyimide layer 8 is formed to a thickness of at least 8000 ° or more, preferably 1.5 μm. The surface of the polyimide layer is formed flat. Thus, an interlayer insulator composed of the silicon nitride layer 7 and the polyimide layer 8 is formed. Thereafter, the polyimide layer 8, the silicon nitride layer 7, and the silicon oxide film 3 are etched to form a contact hole reaching the source 5. Further, an aluminum film having a thickness of 6000 ° is formed by a sputtering method, and the aluminum film is etched to form the data wiring 9. Data wiring 9 contacts source 5. (Fig. 1 (C))

FIG. 5A shows the circuit obtained in the steps up to here as viewed from above. The numbers correspond to those in FIG. (FIG. 5A) Next, a polyimide layer 10 is formed as a second interlayer insulating material having a thickness of 8000 mm. Then, the polyimide layers 8 and 10 are etched to form holes for auxiliary capacitors. Further, a titanium film having a thickness of 1000 ° is formed by a sputtering method. Of course, a metal film such as a chromium film or an aluminum film may be used. Then, this is etched to form the black matrix 11. Black matrix 11
Is formed so as to cover the hole for the auxiliary capacitance formed earlier.
(Fig. 1 (D))

FIG. 5 shows the storage capacitor holes 14 and the black matrix 11 obtained in the steps up to here, as viewed from above.
It is shown in (B). The numbers correspond to those in FIG. A storage capacitor is formed in a portion where the storage capacitor hole 14 and the black matrix 11 overlap. (FIG. 5B) Further, a polyimide film 12 having a thickness of 5000 is formed as a third interlayer insulator, and polyimide films 8, 10 and 1 are formed.
2, the silicon nitride layer 7 and the silicon oxide film 3 are etched to form a contact hole reaching the drain 6. In addition, a 1000 mm thick ITO film is formed by sputtering.
A (indium tin oxide) film is formed and etched to form the pixel electrode 13. (FIG. 1 (E))

Thus, the active matrix circuit is completed. When an insulating layer is formed using a polyimide film as in this embodiment, planarization is easy and the effect is large. In this embodiment, the auxiliary capacitance is obtained at a portion 14 where the black matrix 11 and the drain 6 overlap, and the dielectric is a multilayer film of the silicon oxide film 3 and the silicon nitride layer 7 used as the gate insulating film. Of course, since the silicon oxide film 3 has been considerably damaged in the doping process thereafter, the silicon oxide film 3 does not have resistance enough to be used as a gate insulating film, but has sufficient insulating properties.

[Embodiment 2] FIG. 2 shows a manufacturing process of this embodiment. First, a quartz substrate 21 coated with a base film
An active layer 22 of a crystalline silicon film having a thickness of 1000 ° is formed thereon. Then, this is thermally oxidized to obtain a silicon oxide film 23 having a thickness of 1000 ° on its surface. The silicon oxide film 23 functions as a gate insulating film. Further, a polycrystalline silicon film containing phosphorus is formed to a thickness of 5000 ° by a low pressure CVD method, and is etched to form a gate wiring 2.
Get 4. (Fig. 2 (A))

Next, low-concentration impurity regions 28 are obtained by implanting ions of phosphorus, which is an impurity imparting N-type, at a dose of 5 × 10 ^{12 to} 5 × 10 ¹³ atoms / cm ³ . Further, the side wall 25 of the insulator is obtained on the side surface of the gate wiring 24 by using a known side wall forming technique utilizing an anisotropic etching technique. At this time, portions of the silicon oxide film 23 other than the gate wiring 24 and the side wall 26 are etched, and only the gate insulating film 26 remains.

Then, in this state, 5 × 1 phosphorus ions were added.
The source 29 and the drain 27 are formed by implanting at a dose of 0 ^{14 to} 5 × 10 ¹⁵ atoms / cm ³ . After the impurity ions are implanted, heat treatment is performed to activate the region into which the impurity ions have been implanted. For details of the above doping process, see, for example,
18055. (FIG. 2 (B))

Next, the silicon nitride layer 30 and the polyimide layer 3
1 is formed under the same conditions as in the first embodiment. Unlike the first embodiment, in this embodiment, the silicon nitride layer 30 is in direct contact with the source 29 and the drain 27. Next, the polyimide layer 30 and the silicon nitride layer 31 are etched to form a contact hole reaching the source 29. Further, an aluminum film having a thickness of 6000 ° is formed by a sputtering method, and is etched to form the data wiring 32. Data wiring 32 contacts source 29. The top view of the circuit obtained in the steps up to here is the same as that shown in FIG. (Fig. 2 (C))

Next, a polyimide layer 33 is formed as a second interlayer insulator having a thickness of 8000 °. Then, the polyimide layers 31 and 33 are etched to form holes for auxiliary capacitors. Further, a titanium film having a thickness of 1000 ° is formed by a sputtering method, and is etched to form a black matrix 34. The top view of the circuit obtained in the steps up to here is the same as that shown in FIG. (FIG. 2 (D))

Further, as a third interlayer insulator, a layer having a thickness of 5
000 polyimide film 35, and a polyimide film 3
1, 33 and 35 and the silicon nitride layer 30 are etched to form a contact hole reaching the drain 27. Further, an ITO (indium tin oxide) film having a thickness of 1000 ° is formed by a sputtering method, and is etched to form a pixel electrode 36. (Figure 1
(E))

Thus, the active matrix circuit is completed. In this embodiment, the auxiliary capacitance is obtained in a portion 37 where the black matrix 34 and the drain 27 overlap, and is the silicon nitride layer 30. Since silicon nitride has a high dielectric constant, a large capacitance can be obtained with a small area.

[0040]

By forming an auxiliary capacitor using an N-type or P-type active layer and a conductive film used as a black matrix as an electrode and a silicon nitride layer formed as a passivation film as a dielectric, It turned out that the problem was solved. As described above, the present invention is industrially useful.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing step of an active matrix circuit of Example 1.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of an active matrix circuit of Example 2.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a conventional active matrix circuit.

FIG. 4 is a circuit diagram of a general active matrix circuit.

FIG. 5 is a top view of the manufacturing process of the active matrix circuit of the first embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Glass substrate 2 Active layer 3 Silicon oxide film (gate insulating film) 4 Gate wiring 5 Source 6 Drain 7 Silicon nitride layer 8, 10, 12 Polyimide layer 9 Data wiring 11 Black matrix 13 Pixel electrode 14 Auxiliary capacitance

Claims (6)

[Claims] A top gate thin film transistor; an N-type or P-type active layer; a conductive film functioning as a black matrix and held at a constant potential; a gate wiring and a data wiring; An active matrix type comprising: a first interlayer insulator between the data wire and the data wiring, the first interlayer insulator having a silicon nitride layer and a polyimide layer; and a second interlayer insulator between the data wire and the conductive film. In the display circuit, in the first interlayer insulator, the silicon nitride layer is below the polyimide layer, and in the portion where the polyimide layer of the first interlayer insulator and the second interlayer insulator are etched, An active capacitor having an auxiliary capacitor formed by using the active layer and the conductive film as both electrodes and using at least the silicon nitride layer of the first interlayer insulator as a dielectric material. Torikusu type display circuit. 2. A top gate type thin film transistor; an N type or P type active layer; a conductive film functioning as a black matrix and held at a constant potential; a gate wiring and a data wiring; An active matrix type comprising: a first interlayer insulator between the data wire and the data wiring, the first interlayer insulator having a silicon nitride layer and a polyimide layer; and a second interlayer insulator between the data wire and the conductive film. In the display circuit, in the first interlayer insulator, the silicon nitride layer is below the polyimide layer, and the conductive coating is formed at a portion overlapping the active layer.
An active matrix display circuit having a portion in contact with the silicon nitride layer of the first interlayer insulator. 3. The active matrix display circuit according to claim 1, wherein the active layer is continuous with a source or a drain of the thin film transistor. 4. The active matrix display circuit according to claim 1, wherein said auxiliary capacitance is formed of only a silicon nitride layer of said first interlayer insulator as a dielectric. 5. The active matrix display circuit according to claim 1, wherein the thickness of the silicon nitride layer is 1000 ° or less. 6. A first step of forming a first interlayer insulator having an N-type or P-type active layer, a gate wiring, a silicon nitride layer and a polyimide layer, and etching the first interlayer insulator. A second step of forming a contact hole reaching the active layer; and a third step of forming a data line contacting the active layer.
A fourth step of forming a second interlayer insulator; and etching the second interlayer insulator and a part of the first interlayer insulator to expose an exposed capacitance of the silicon nitride layer. A fifth step of forming a hole, and a sixth step of forming a conductive film functioning as a black matrix in contact with the silicon nitride layer exposed in the fifth step; A method for manufacturing an active matrix display circuit, wherein the capacitor hole obtained by the step overlaps with the active layer.