JP2001053287A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a parasitic capacitance between multilayer interconnections to improve a semiconductor device in display characteristics. SOLUTION: A part or all of a gate electrode overlapping with the channel forming regions 213 and 214 of pixel TFTs is superposed on second wirings (source wire or drain wire) 154 and 157 to improve a semiconductor device in numerical aperture. A first interlayer insulating film 149 and a second interlayer insulating film 150c are provided between the gate electrode and the second wirings 154 and 157, to lessen the semiconductor device in parasitic capacitance.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit constituted by thin film transistors (hereinafter, referred to as TFTs) and a method for manufacturing the same. For example, the present invention relates to an electro-optical device typified by a liquid crystal display panel and an electronic device equipped with such an electro-optical device as a component.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0003]

2. Description of the Related Art Semiconductor devices having a large-area integrated circuit formed of TFTs on a substrate having an insulating surface have been developed. Active matrix liquid crystal display devices, EL display devices, and contact image sensors are known as typical examples. In particular, a TFT having a crystalline silicon film (typically, a polysilicon film) as an active layer (hereinafter referred to as a polysilicon TFT) has a high field-effect mobility.
Various functional circuits can be formed.

For example, an active matrix type liquid crystal display device controls a pixel circuit for displaying an image for each functional block, and a pixel circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, and a sampling circuit based on a CMOS circuit. Is formed on one substrate.

In a pixel circuit of an active matrix type liquid crystal display device, TFTs are arranged in tens to millions of pixels, and each of the TFTs is provided with a pixel electrode. A counter electrode is provided on the counter substrate side sandwiching the liquid crystal, and forms a kind of capacitor using the liquid crystal as a dielectric. Then, the voltage applied to each pixel is controlled by the switching function of the TFT, the liquid crystal is driven by controlling the charge to the capacitor, and the amount of transmitted light is controlled to display an image.

[0006]

When a pixel circuit and a driving circuit are formed on an insulating surface, a capacitance (parasitic capacitance) is inevitably generated between the formed multilayer wirings.

The magnitude of the parasitic capacitance is determined by the electrode area where the lower wiring and the upper wiring overlap, the thickness of the insulating film between the overlapping lower wiring and the upper wiring, and the like.

In recent years, as the size and power consumption of circuits have been reduced, the influence of the parasitic capacitance has become so large that it cannot be ignored. In order to reduce the influence of the parasitic capacitance, it has been proposed to increase the electrode area of the auxiliary capacitance. However, when the electrode area is increased, there is a problem that the aperture ratio of the pixel region decreases.

Further, if the lower wiring and the upper wiring are not overlapped, the aperture ratio of the pixel region similarly decreases.

Particularly, in an active matrix type liquid crystal display device having a diagonal of 1 inch or less, the aperture ratio is regarded as most important.

In order to improve the aperture ratio of the pixel area,
In order to reduce the wiring area, the width of the wiring is reduced, or a lower wiring and an upper wiring are overlapped as much as possible to form a multilayer wiring.

In addition, the size of a contact hole reaching a source region and a drain region of a TFT has been miniaturized due to miniaturization of a circuit. In order to obtain a good contact connection, the contact hole may be formed in a tapered shape so as to have a slope. However, if an extremely tapered shape is formed, the size of the contact hole becomes large. For example, when a minute contact hole having a diameter of about 0.5 to 1.5 μm is to be formed, the thickness of the source region and the drain region of the TFT is 10 nm to 50 nm.
Therefore, if the interlayer insulating film is thick, poor etching such as over-etching or remaining etching may occur depending on the etching conditions.

The present invention is a technique for solving such a problem, and an object of the present invention is to reduce a parasitic capacitance formed between multilayer wirings and improve display characteristics. Another object is to provide a manufacturing method for realizing such a semiconductor device.

[0014]

According to the invention disclosed in this specification, a first wiring is provided on an insulating surface, a first interlayer insulating film covering the first wiring, and a first interlayer insulating film is provided on the first interlayer insulating film. A region in which a second interlayer insulating film is in contact with a part thereof and a second wiring is provided on the first interlayer insulating film and the second interlayer insulating film, and the first wiring and the second wiring overlap each other; In the semiconductor device, the first interlayer insulating film and the second interlayer insulating film are stacked.

In the above structure, an etching rate of the first interlayer insulating film is smaller than an etching rate of the second interlayer insulating film.

In each of the above structures, it is preferable that a selectivity of an etching rate of the first interlayer insulating film to the second interlayer insulating film is 1.5 or more.

Further, in each of the above structures, the first interlayer insulating film has a thickness of 50 to 300 nm.

Further, in each of the above structures, the second interlayer insulating film has a thickness of 150 nm to 1 μm.

Further, in another embodiment of the present invention, T
In a semiconductor device including at least FT, the TFT
A first interlayer insulating film above the first wiring forming the
An interlayer insulating film and a second wiring are formed, and a gate insulating film, a first interlayer insulating film, and the second wiring are formed above a source region or a drain region of the TFT. Semiconductor device.

In the above structure, the sum of the thickness of the gate insulating film and the thickness of the first interlayer insulating film is 0.1 μm or more.

In another embodiment of the present invention, T
In a semiconductor device including at least FT, the TFT
A first interlayer insulating film and a second
A semiconductor device characterized in that a second wiring exists through an interlayer insulating film.

The above structure is characterized in that a first interlayer insulating film exists above the source region or the drain region of the TFT.

In each of the above structures, the TFT is an inverted stagger type TFT.

Further, in each of the above structures, the first wiring is a gate wiring.

According to another aspect of the invention, in a semiconductor device including at least a pixel circuit and a drive circuit for controlling the pixel circuit on the same substrate, a channel forming region of a pixel TFT forming the pixel circuit is A semiconductor which is formed so as to overlap a part of a gate wiring via a gate insulating film, and a part of the gate wiring overlaps the second wiring via a plurality of insulating films having different etching rates. Device.

In each of the above structures, the second wiring is a source line or a drain line.

In each of the above structures, at least a part or all of the LDD region of the n-channel TFT forming the driving circuit is formed so as to overlap with the gate wiring of the n-channel TFT to form the pixel circuit. Pixel T
The LDD region of the FT is formed so as not to overlap the gate electrode of the pixel TFT.

In each of the above structures, at least a part or the entirety of the LDD region of the n-channel TFT forming the driving circuit is formed so as to overlap the gate electrode of the n-channel TFT to form the pixel circuit. Pixel T
The LDD region of the FT is formed so as not to overlap with the gate electrode of the pixel TFT, and the storage capacitance of the pixel circuit is formed by a shielding film provided on an organic resin film, an oxide of the shielding film, and the pixel electrode. It is characterized by being.

The structure of the invention for realizing the above structure includes a first step of forming a first wiring on an insulating surface and a second step of forming a first interlayer insulating film covering the first wiring. A third step of forming a second interlayer insulating film on the first interlayer insulating film, a fourth step of selectively removing a part of the second interlayer insulating film, and a second step of overlapping the first wiring. A fifth step of forming a second wiring on the interlayer insulating film.

Another embodiment of the present invention provides a structure in which T
In a method for manufacturing a semiconductor device including at least FT,
A first step of forming an active layer on an insulating surface, a second step of forming a gate insulating film in contact with the active layer, and adding an n-type impurity element or a p-type impurity element to a part of the active layer. A third step of forming a source region or a drain region by forming a first interlayer insulating film covering the gate wiring and the gate electrode, and forming a second interlayer insulating film on the first interlayer insulating film. A fifth step, etching the second interlayer insulating film to remove the second interlayer insulating film above the source region or the drain region, and the first interlayer insulating film and the gate insulating film Forming a contact hole reaching the source region or the drain region, and contacting the source region or the drain region on the second interlayer insulating film overlapping the gate electrode. A method for manufacturing a semiconductor device, characterized in that it comprises an eighth step of forming a second wiring.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including at least a pixel circuit and a driving circuit for controlling the pixel circuit on the same substrate, wherein an active layer is formed on an insulating surface. One step, a second step of forming a gate insulating film in contact with the active layer, a third step of forming a gate wiring and a gate electrode on the gate insulating film, and an n-type impurity in a part of the active layer. A fourth step of adding an element or a p-type impurity element to form an n-type impurity region or a p-type impurity region, and a first step of covering a gate wiring and a gate electrode.
A fifth step of forming an interlayer insulating film, a sixth step of selectively forming a second interlayer insulating film on the first interlayer insulating film overlapping the gate electrode, and the first interlayer insulating film and the gate insulating film Forming a contact hole reaching the n-type impurity region or the p-type impurity region, and forming the n-type impurity region or the p-type impurity on the second interlayer insulating film overlapping the gate electrode. An eighth step of forming a second wiring in contact with the type impurity region.

According to another aspect of the invention, there is provided a method of manufacturing a semiconductor device including at least a pixel circuit and a driver circuit for controlling the pixel circuit on the same substrate, wherein an active layer is formed on an insulating surface. One step, a second step of forming a gate insulating film in contact with the active layer, a third step of forming a gate wiring and a gate electrode on the gate insulating film, and an n-type impurity in a part of the active layer. A fourth step of adding an element or a p-type impurity element to form an n-type impurity region or a p-type impurity region, and a first step of covering a gate wiring and a gate electrode.
A fifth step of forming an interlayer insulating film, a sixth step of etching the first interlayer insulating film and the gate insulating film to form a contact hole reaching the n-type impurity region or the p-type impurity region, A seventh step of selectively forming a second interlayer insulating film on the first interlayer insulating film; and forming the n-type impurity region or the p-type impurity region on the second interlayer insulating film overlapping the gate electrode. An eighth step of forming a second wiring in contact with the semiconductor device.

[0033]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG.

As shown in FIG. 5, in the present invention, in order to improve the aperture ratio, the channel forming region 21 of the pixel TFT is formed.
A part or all of the gate electrode overlapping
The wirings (source lines or drain lines) 154 and 157 are overlapped. A first interlayer insulating film 149 and a second interlayer insulating film 150 are provided between the gate electrode and the second wirings 154 and 157.
c to reduce the parasitic capacitance. Note that FIG. 8B is a top view of the display region corresponding to FIG.

Further, since the second interlayer insulating film 150c is selectively provided only in a region where the gate electrode and the second wiring overlap, it is easy to open a contact hole reaching the source region or the drain region of the pixel TFT.

In the drive circuit, the insulating film 115
The second interlayer insulating film 150b may be selectively formed in a region where the gate wiring provided above and the second wiring 151 intersect and overlap. Note that FIG. 7B is a top view of the driver circuit corresponding to FIG.

Note that an insulating film containing silicon is used as the first interlayer insulating film and the second interlayer insulating film. As the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. As a method for forming these films, a CVD method such as plasma CVD, low-pressure CVD, or ECRCVD, or a sputtering method may be used. If plasma CVD is used and an organic silane such as TEOS is used as a source gas as an Si source and O ₂ or O ₃ is used as an O source, T
An insulating film called an EOS film is formed. An inorganic silane such as SiH ₄ (monosilane) or disilane is used as a source gas as a Si source, and O ₂ , O _3, or N ₂ O is used as an O source.
Can be used. In addition, using a low pressure CVD method,
SiH ₄ (monosilane) as i source, O ₂ or O as O source
_{If 3} or N ₂ O is used, an insulating film called an LTO film is formed.

The silicon oxynitride film is an insulating film containing silicon, nitrogen and oxygen in predetermined amounts, and is made of SiOxNy.
Is an insulating film represented by Note that the concentration ratio of N to the concentration of Si in the silicon nitride oxide film is set to 0.1 or more and 0.8 or less. The control of the composition of the insulating film containing silicon, oxygen, nitrogen, etc. is performed by controlling the type, flow rate, substrate temperature, pressure,
The adjustment is performed by appropriately adjusting the RF power and the electrode interval.

The thickness of the first interlayer insulating film is not particularly limited. However, when the contact hole reaching the silicon layer is formed by etching simultaneously or sequentially with the gate insulating film, since the silicon layer is thin, it has a sufficient selectivity to the silicon layer. It is important to perform the etching under the conditions (such as the material of the insulating film, the film thickness, the etching gas, and the like) that can remove the gas. In consideration of these conditions, the thickness of the first interlayer insulating film is reduced (for example, 2
00 nm or less). However, a film thickness that protects the gate wiring from oxidation in the activation step is necessary. In forming a minute contact hole, it is preferable that the second interlayer insulating film does not exist in the contact hole formation region.

Since the manufacturing process of the present invention for realizing the above structure includes a step of selectively wet-etching only the second interlayer insulating film (FIG. 4B), the second interlayer insulating film is formed. Is preferably a material having an etching rate higher than that of the first interlayer insulating film.

Even when the second interlayer insulating film is formed using the same source gas as the first interlayer insulating film, if the film is formed at a temperature lower than the film forming temperature of the first interlayer insulating film by 10 ° C. or more, the etching rate becomes large. A membrane can be obtained.

Further, the thermal annealing (75) is applied to the first interlayer insulating film.
0 to 850 ° C. for 15 minutes to 4 hours) to reduce the etching rate of the first interlayer insulating film, thereby forming the second interlayer insulating film.
The selectivity with respect to the interlayer insulating film may be increased.

In the step of selectively etching only the second interlayer insulating film, it is possible to use dry etching, but it is possible to obtain a sufficient selectivity with the first interlayer insulating film and to obtain a wetted tapered shape. Etching is preferred.
The thickness of the second interlayer insulating film is not particularly limited as long as the thickness does not cause a problem in parasitic capacitance, for example, 0.5 μm or more. Further, anisotropic etching may be used.

As another method of forming a contact hole reaching a source region or a drain region, as shown in FIG. 12, a contact hole is formed in a gate insulating film and a first interlayer insulating film by dry etching, and then a second interlayer insulating film is formed. A contact hole may be formed in the second interlayer insulating film by wet etching again after laminating the insulating films.

Further, as a step of selectively etching only the second interlayer insulating film, a thin silicon nitride film, a DLC film, an AlN film, an AlNO film, etc. are laminated on the first interlayer insulating film. When used as an etching blocking layer, the second interlayer insulating film can be selectively etched using dry etching. Even if dry etching is used, a tapered shape can be obtained by changing the resist shape.

Here, two interlayer insulating films (a first interlayer insulating film and a second interlayer insulating film) are used between the gate wiring and the second wiring, but three or more interlayer insulating films are used. May be laminated.

By adopting the configuration of the present invention described above, it is possible to eliminate the adverse effect on the display characteristics due to the parasitic capacitance even in the layout in which the gate electrode and the second wiring are overlapped. Further, even in an active matrix type liquid crystal display device having a diagonal of 1 inch or less, the parasitic capacitance formed by the gate wiring and the second wiring is sufficiently small, and a small contact hole (having a diameter of about 0.5 μm to 1. 5 μm).

The present invention having the above configuration will be described in more detail with reference to the following embodiments.

[0049]

[Embodiment 1] An embodiment of the present invention will be described with reference to FIGS.
This will be described with reference to FIG. Here, a method for simultaneously manufacturing a pixel circuit and a driver circuit for controlling the pixel circuit over the same substrate will be described. However, for the sake of simplicity, the driving circuit shows a CMOS circuit which is a basic circuit such as a shift register circuit and a buffer circuit, and an n-channel TFT forming a sampling circuit.

In FIG. 1A, it is desirable to use a quartz substrate or a silicon substrate for the substrate 101. In this embodiment, a quartz substrate was used. Alternatively, a substrate obtained by forming an insulating film on the surface of a metal substrate or a stainless steel substrate may be used as the substrate. In the case of this embodiment, since heat resistance that can withstand a temperature of 800 ° C. or more is required, any substrate may be used as long as it meets the requirement.

The surface of the substrate 101 on which the TFT is to be formed has a thickness of 20 to 100 nm (preferably 40 to 80 nm).
A semiconductor film 102 having an amorphous structure with a thickness of m) is formed by a low pressure thermal CVD method, a plasma CVD method, or a sputtering method. In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed. However, since a thermal oxidation step is performed later, this film thickness does not necessarily become the final film thickness of the active layer of the TFT.

The semiconductor film having an amorphous structure includes an amorphous semiconductor film and a microcrystalline semiconductor film, and further includes a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film. .

It is also effective to continuously form a base film and an amorphous silicon film on a substrate without opening to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

Next, a mask film 103 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 102, and openings 104a and 104b are formed by patterning. The opening serves as an addition region for adding a catalyst element that promotes crystallization in the next crystallization step.
(Fig. 1 (A))

Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in predetermined amounts, and is an insulating film represented by SiOxNy. Silicon nitride oxide film is Si
H ₄ , N ₂ O, and NH ₃ can be produced as source gases, and the nitrogen concentration is 25 atomic% or more and 50 a
It is good to be less than tomic%.

At the same time as the patterning of the mask film 103 is performed, a marker pattern which is a reference for a subsequent patterning step is formed.

Next, a semiconductor film having a crystal structure is formed according to the technique described in Japanese Patent Application Laid-Open No. Hei 10-247735 (corresponding to US Application No. 09 / 034,041). The technology described in the publication discloses a catalyst element (nickel, cobalt, germanium, tin, lead, palladium, etc.) that promotes crystallization during crystallization of a semiconductor film having an amorphous structure.
Crystallization means using one or more elements selected from iron and copper).

Specifically, heat treatment is performed while a catalytic element is held on the surface of the semiconductor film having an amorphous structure to change the semiconductor film having an amorphous structure into a semiconductor film having a crystalline structure. It is to let. As the crystallization means, the technique described in Example 1 of JP-A-7-130652 may be used. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, and a semiconductor film including a crystal structure formed in the publication has a crystal grain boundary.

In this publication, a spin coat method is used when a layer containing a catalyst element is formed on a mask film.
Means for forming a thin film containing a catalytic element by a gas phase method such as a sputtering method or an evaporation method may be employed.

The amorphous silicon film is preferably subjected to a heat treatment at 400 to 550 ° C. for about one hour to crystallize after sufficient desorption of hydrogen, though it depends on the hydrogen content. . In this case, the hydrogen content is preferably set to 5 atom% or less.

The crystallization step is first performed at 400 to 500 ° C. for 1 hour.
After performing a heat treatment process for about an hour to desorb hydrogen from the film, the heat treatment is performed at 500 to 650 ° C. (preferably 550 to 600 ° C.).
C.) for 6 to 16 hours (preferably 8 to 14 hours).

In this embodiment, a heat treatment is performed at 570 ° C. for 14 hours using nickel as a catalyst element. as a result,
From the openings 104a and 104b as starting points, crystallization proceeds in a direction substantially parallel to the substrate (direction indicated by an arrow), and a semiconductor film having a crystal structure in which macroscopic crystal growth directions are aligned (in this embodiment, a crystalline film). Silicon films) 105a to 105d are formed. (Fig. 1 (B))

Next, a gettering step of removing nickel used in the crystallization step from the crystalline silicon film is performed.
In this embodiment, a step of adding an element belonging to Group XV (phosphorus in this embodiment) using the previously formed mask film 103 as a mask is performed, and the crystalline silicon film exposed in the openings 104a and 104b is added to the 1 × 10 4 ¹⁹ to 1 × 10 ²⁰ at
Phosphorus-added regions (hereinafter, referred to as gettering regions) 106a and 106b containing phosphorus at a concentration of oms / cm ³ are formed.
(Fig. 1 (C))

Next, at 450 to 650 ° C. in a nitrogen atmosphere.
(Preferably 500 to 550 ° C.) and a heat treatment step for 4 to 24 hours (preferably 6 to 12 hours) are performed. By this heat treatment step, nickel in the crystalline silicon film moves in the direction of the arrow, and is captured in the gettering regions 106a and 106b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 107a to 107d after gettering is 1 × 10 ¹⁷ atoms / cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ^3. / cm ³ .

Next, the mask film 103 is removed, and a protective film 108 is formed on the crystalline silicon films 107a to 107d for a later impurity doping step. The protective film 108 is 100 to
It is preferable to use a silicon nitride oxide film or a silicon oxide film with a thickness of 200 nm (preferably 130 to 170 nm). This protective film 108 has a meaning to prevent the crystalline silicon film from being directly exposed to plasma at the time of adding an impurity and to enable fine concentration control.

Then, a resist mask 109 is formed thereon, and an impurity element imparting p-type (hereinafter, referred to as a p-type impurity element) is added via the protective film 108. As the p-type impurity element, an element belonging to Group 13 typically, typically, boron or gallium can be used.
This step (called a channel doping step) is a step for controlling the threshold voltage of the TFT. Here, boron is added by an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.

By this step, 1 × 10 ¹⁵ to 1 × 10 ¹⁸ at
oms / cm ³ (typically 5 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / c
Impurity regions 110a and 110b containing a p-type impurity element (boron in this embodiment) at a concentration of m ³ ) are formed. Note that in this specification, an impurity region containing a p-type impurity element within the above concentration range (a region not containing phosphorus) is defined as a p-type impurity region (b). (Fig. 1 (D))

Next, the resist mask 109 is removed, and the crystalline silicon film is patterned to form island-shaped semiconductor layers (hereinafter, referred to as active layers) 111 to 114. In addition,
The active layers 111 to 114 are formed of a crystalline silicon film having extremely good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-shaped or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus.
14 had a concentration of 1 × 10 ¹⁷ atoms /
cm ³ or less, preferably 1 × 10 ¹⁶ atoms / cm ³ . (FIG. 1 (E))

The active layer 111 of the p-channel TFT
Is a region not containing an impurity element intentionally added, and the active layers 112 to 114 of the n-channel TFT are p-type impurity regions (b). In this specification, the active layers 111 to 114 in this state are all defined as being intrinsic or substantially intrinsic. That is, a region to which an impurity element is intentionally added to such an extent that the operation of the TFT is not hindered may be considered as a substantially intrinsic region.

Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by a plasma CVD method or a sputtering method. In this embodiment, a 30-nm-thick silicon nitride oxide film is formed. As the insulating film containing silicon, another insulating film containing silicon may be used as a single layer or a stacked layer.

Next, at 800-1150 ° C. (preferably 9 ° C.)
A heat treatment step at a temperature of (00 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added in an oxygen atmosphere. The boron added in the step of FIG. 1D is activated during this thermal oxidation step. (Figure 2
(A))

The oxidizing atmosphere may be a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer.
Further, in this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used, but the atmosphere may be performed in a 100% oxygen atmosphere.

During this thermal oxidation step, an oxidation reaction also proceeds at the interface between the insulating film containing silicon and the active layers 111 to 114 thereunder. In the present invention, in consideration of this, the thickness of the gate insulating film 115 finally formed is 50 to 200 nm.
(Preferably 100 to 150 nm). In the thermal oxidation step of this embodiment, 25 nm of the active layer having a thickness of 60 nm is oxidized, and the thickness of the active layers 111 to 114 becomes 45 nm. Further, since a 50-nm-thick thermal oxide film is added to the 30-nm-thick silicon-containing insulating film, the final gate insulating film 115 has a thickness of 110 nm.

Next, resist masks 116 to 11 are newly added.
9 is formed. Then, an impurity element imparting n-type (hereinafter referred to as an n-type impurity element) is added to form impurity regions 120 to 122 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group XV, typically, phosphorus or arsenic can be used. (Figure 2
(B))

The impurity regions 120 to 122 will be
N-channel type TF of MOS circuit and sampling circuit
T is an impurity region for functioning as an LDD region. The impurity region formed here has n
The type impurity element is contained at a concentration of 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ (typically, 5 × 10 ^{17 to} 5 × 10 ¹⁸ atoms / cm ³ ). In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).

Here, phosphorus is added at a concentration of 1 × 10 ¹⁸ atoms / cm ³ by an ion doping method in which phosphine (PH ₃ ) is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used. In this step, phosphorus is added to the crystalline silicon film via the gate film 115.

Next, at 600 to 1000 ° C. (preferably 7 ° C.)
Heat treatment is performed in an inert atmosphere (at 00 to 800 ° C.) to activate the phosphorus added in the step of FIG. In this embodiment, heat treatment at 800 ° C. for one hour is performed in a nitrogen atmosphere. (Fig. 2 (C))

At this time, it is possible to repair the active layer damaged at the time of adding phosphorus and the interface between the active layer and the gate insulating film. In this activation step, furnace annealing using an electric heating furnace is preferable, but optical annealing such as lamp annealing or laser annealing may be used together.

By this step, n-type impurity region (b) 12
The boundary portion between 0 and 122, that is, the junction with the intrinsic or substantially intrinsic region (including the p-type impurity region (b)) existing around the n-type impurity region (b) becomes clear. . This means that when the TFT is completed later, LDD
This means that the region and the channel forming region can form a very good junction.

Next, a conductive film to be a gate wiring is formed. Note that the gate wiring may be formed using a single-layer conductive film, but is preferably a stacked film such as two layers or three layers as necessary. In this embodiment, a stacked film including the first conductive film 123 and the second conductive film 124 is formed. (FIG. 2 (D))

Here, the first conductive film 123 and the second conductive film 12
4 include tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (C
r), an element selected from silicon (Si), or a conductive film containing the above element as a main component (typically, a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the above elements ( Typically, a Mo-W alloy film, a Mo-Ta alloy film, a tungsten silicide film, etc.)
Can be used.

The first conductive film 123 has a thickness of 10 to 50 nm.
(Preferably 20 to 30 nm) and the second conductive film 124
Is 200 to 400 nm (preferably 250 to 350 n
m). In this embodiment, a 50 nm thick tungsten nitride (WN) film is used as the first conductive film 123, and a 350 nm thick tungsten film is used as the second conductive film 124. Although not shown, it is effective to form a silicon film (doped with phosphorus) with a thickness of about 2 to 20 nm under the first conductive film 123. This can improve the adhesion of the conductive film formed thereon and prevent oxidation.

It is also effective to use a tantalum nitride film as the first conductive film 123 and a tantalum film as the second conductive film 124.

Next, the first conductive film 123 and the second conductive film 12
4 are collectively etched to form gate wirings 125 to 128 having a thickness of 400 nm. At this time, the gate wirings 126 and 127 formed in the driving circuit are n-type impurity regions (b).
The gate insulating film 115 is formed so as to overlap with a part of the gate insulating films 120 to 122. This overlapping portion will later become a Lov region. (FIG. 2 (E))

A top view in this state is shown in FIG.
(A) and FIG. 7 (A). AA ′ in FIG.
A cross section corresponds to FIG. In addition, B in FIG.
A cross section taken along line -B 'corresponds to FIG. Although the gate wirings 128a, 128b, and 128c in FIG. 2E appear to be three in cross section, they are actually formed from one continuous pattern.

After forming the gate wiring, in order to protect the second conductive film, a tantalum nitride film or a tungsten nitride film may be laminated and patterned again to form a gate electrode structure surrounding the second conductive film. .

Next, a resist mask 129 is formed, and p
The impurity regions 130 and 131 containing boron at a high concentration are formed by adding a type impurity element (boron in this embodiment).
In this embodiment, 3 × 10 ^{20 to} 3 × 10 ²¹ atoms / cm ³ (typically, 5 × 10 ^{21 to} 3 × 10 ²¹ atoms / cm ³ ) by an ion doping method (of course, an ion implantation method) using diborane (B ₂ H ₆ ).
Boron is added at a concentration of (× 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ ). In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (FIG. 3 (A))

Next, the resist mask 129 is removed, and resist masks 132 to 134 are formed so as to cover the gate wiring and the region to be the p-channel TFT. And n
The impurity regions 135 to 141 containing phosphorus at a high concentration are formed by adding a type impurity element (phosphorus in this embodiment). Also in this case, the ion doping method using phosphine (PH ₃ ) (of course, the ion implantation method may be used), and the concentration of phosphorus in this region is 1 × 10 ²⁰ to 1 × 10 ²¹ at.
oms / cm ³ (typically 2 × 10 ^{20 to} 5 × 10 ²¹ atoms / c
m ³ ). (FIG. 3 (B))

In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a). The region where the impurity regions 135 to 141 are formed contains phosphorus or boron already added in the previous step, but phosphorus is added at a sufficiently high concentration. You do not need to consider the effect of phosphorus or boron. Therefore, in this specification, the impurity regions 135 to 141 may be referred to as n-type impurity regions (a).

Next, an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate wirings 125 to 128 as a mask. The impurity region 143 thus formed
１４ to ６ of the n-type impurity region (b).
10 (typically 1/3 to 1/4) (however, 5% higher than the boron concentration added in the channel doping step described above).
〜１０10-fold higher concentration, typically 1 × 10 ¹⁶ -5 × 10 ¹⁸
atoms / cm ³ , typically 3 × 10 ^{17 to} 3 × 10 ¹⁸ atoms / c
Adjust so that phosphorus is added in m ³ ). Note that, in this specification, an impurity region containing an n-type impurity element (excluding the p-type impurity region (a)) in the above concentration range is defined as an n-type impurity region (c). (FIG. 3 (C))

In this step, 1 × 10 ^{16 to} 5 × 1 is applied to all the impurity regions except for the portion hidden by the gate wiring.
Although phosphorus is added at a concentration of 0 ¹⁸ atoms / cm ³ , the function is extremely low and does not affect the function of each impurity region. The n-type impurity regions (b) 143 to 146 have already been formed in the channel doping step at 1 × 10 ¹⁵ to 1 × 10 ¹⁸ atoms.
Although boron is added at a concentration of s / cm ³ , phosphorus is added at a concentration of 5 to 10 times that of boron contained in the p-type impurity region (b) in this step.
It may be considered that the function of the type impurity region (b) is not affected.

However, strictly speaking, the n-type impurity region (b) 14
7 and 148, the phosphorus concentration of the portion overlapping the gate wiring remains at 2 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , while the portion not overlapping the gate wiring is 1 × 10 ¹⁶
Phosphorus at a concentration of ~ 5 × 10 ¹⁸ atoms / cm ³ is added,
It will contain phosphorus at a slightly higher concentration.

In forming the n-type impurity region (c), the cap film (25) for preventing the oxidation of the gate wiring is formed in advance.
To 100 nm) to form an offset region. Note that the offset region refers to a high-resistance region which is formed in contact with the channel formation region and is formed of a semiconductor film having the same composition as the channel formation region, but does not form an inversion layer (channel region) because no gate voltage is applied. . In order to reduce the off-state current value, it is important to minimize the overlap between the LDD region and the gate wiring. In that sense, providing an offset region is effective.

Next, a first interlayer insulating film 149 is formed.
The first interlayer insulating film 149 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The thickness may be 100 to 400 nm, preferably 200 nm or less. In this embodiment, a silicon nitride oxide film having a thickness of 200 nm (here, the nitrogen concentration is less than 5 atomic%) is formed by a plasma CVD method at a deposition temperature of 325 ° C., using SiH ₄ and N ₂ O as source gases.

Thereafter, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by furnace annealing, laser annealing, lamp annealing, or a combination thereof. When performing the furnace annealing method,
The heat treatment may be performed at 500 to 800C, preferably 550 to 600C in an inert atmosphere. In this embodiment, 800
A heat treatment at 1 ° C. for one hour was performed to activate the impurity element, and to lower the etching rate of the first interlayer insulating film 149 to increase the selectivity with respect to the second interlayer insulating film formed later. The etching rate (the value of LAL500 at 20 ° C.) immediately after the formation of the first interlayer insulating film 149 is 260 n.
In contrast to m / min, the etching rate of the first interlayer insulating film 149 after thermal annealing could be reduced to 88 nm / min. (FIG. 3 (D))

Next, after the activation step, heat treatment is performed in an atmosphere containing 3 to 100% hydrogen at 300 to 450 ° C. for 1 to 4 hours to hydrogenate the active layer. In this step, dangling bonds in the semiconductor layer are terminated by thermally excited hydrogen. Plasma hydrogenation (using hydrogen excited by plasma) as another means of hydrogenation
May be performed.

After the activation step, the first interlayer insulating film 1
500 nm to 1.5 μm, preferably 500
second interlayer insulating film 150 having a thickness of 150 nm to 800 nm
a is formed. The second interlayer insulating film 150a is provided to reduce a parasitic capacitance generated in an overlapping portion between the gate wiring and the upper wiring or in an overlapping portion between the gate electrode (corresponding to above the channel formation region) and the upper wiring. is there. In addition,
The second interlayer insulating film 150a is made of a material having an etching rate higher than that of the first interlayer insulating film (a silicon nitride oxide film formed by a plasma CVD method at a deposition temperature of 400 ° C. and SiH ₄ or N ₂ O as a source gas; Nitrogen concentration is 10 atomic% or less),
An etching rate of 210 nm / min) was selected, and the film thickness was set to 500 nm.

Next, patterning by dry etching or wet etching is performed to leave the second interlayer insulating film only in regions (150b, 150c) where a source wiring or a drain wiring to be formed later overlaps with a gate wiring. In this embodiment, patterning is performed by wet etching using LAL500. As mentioned above, the second
While the etching rate of the interlayer insulating film is 210 nm / min, the etching rate of the first interlayer insulating film is 8 nm / min.
Since it is 8 nm / min, a sufficient selection ratio can be obtained. The selectivity between the first interlayer insulating film and the second interlayer insulating film is 1.5 or more,
Preferably, it is sufficient to have 3 to 5. (FIG. 4 (B))

After that, the first interlayer insulating film and the gate insulating film are patterned to form a contact hole reaching the source region or the drain region of the TFT. However, the thickness of the source region and the drain region is thin (10
nm to 50 nm), it is important to adjust the etching conditions so that the amount of over-etching (amount of reduction of the polysilicon film) does not exceed a predetermined value.

Table 1 shows theoretical values of the amount of reduction in the polysilicon film when forming the contact holes.

[0101]

[Table 1]

In Table 1, a precondition is that a gate insulating film (silicon oxide film containing nitrogen, film thickness 120 nm ± 5%) and a first interlayer insulating film (silicon oxide film containing nitrogen, film thickness (200 nm ± 5%), and dry etching is performed at an etching rate of 300 nm / min. Etching rates were 7.13% ammonium hydrogen fluoride and 15.3% ammonium fluoride.
Mixed solution containing 4% (trade name LAL, manufactured by Stella Chemifa)
500) at 20 ° C. The vertical axis shows the variation in the etching rate, and the horizontal axis shows the selectivity between the polysilicon film and the silicon oxide film containing nitrogen.

For example, if the variation in the etching rate is 5
%, And the over-etching amount is a predetermined value, for example, 5n.
m, the selection ratio should be 10 from Table 1.
It can be read that it is necessary to have a larger value. In this way, from Table 1, it is possible to determine how much the selectivity is required to make the overetching amount equal to or less than the predetermined value. In addition, when the selection ratio is set to a certain value, it is possible to determine how much the variation in the etching rate needs to be suppressed. In addition, when a table in which the first interlayer insulating film was larger than 200 nm was prepared in the same manner as in Table 1, it was found that it was difficult to form a contact hole unless the selectivity was large and the variation in the etching rate was not very small.

In the present embodiment, an insulating material having a selectivity to polysilicon of 12 to 15 was used, and the variation in etching rate was suppressed to 5% or less, so that a contact hole with almost no over-etching could be formed. .

Then, source wirings 151 to 154 and drain wirings 155 to 157 are formed. However, when the size of the contact hole is 1 μm or less, it is preferable to form the contact hole by dry etching. In order to form a CMOS circuit, the drain wiring 155 is shared between the p-channel TFT and the n-channel TFT. Although not shown, in this embodiment, the wiring is a three-layer laminated film in which a 200 nm thick Ti film, a 500 nm thick aluminum film containing Ti, and a 100 nm Ti film are continuously formed by a sputtering method.

Next, as a passivation film 158,
A silicon nitride film, a silicon oxide film, or a silicon nitride oxide film having a thickness of 50 to 500 nm (typically, 200 to 300 nm);
(nm). (FIG. 4C) FIGS. 6B and 7B are top views in this state.
An AA ′ cross section in FIG. 6B corresponds to FIG. 4C AA ′. Further, the cross section taken along the line BB 'in FIG.
(C) It corresponds to BB '.

At this time, in this embodiment, a plasma process is performed using a gas containing hydrogen such as H ₂ and NH ₃ before forming the film, and a heat treatment is performed after the film is formed. Hydrogen excited by this pretreatment is supplied into the first and second interlayer insulating films. By performing the heat treatment in this state, the film quality of the passivation film 158 is improved, and the hydrogen added to the first and second interlayer insulating films diffuses to the lower side, so that the active layer is effectively hydrogenated. be able to.

Further, after the passivation film 158 is formed, a hydrogenation step may be further performed. For example, 3
300 to 450 ° C. in an atmosphere containing １００100% hydrogen
The heat treatment is preferably performed for 1 to 12 hours, or the same effect can be obtained by using a plasma hydrogenation method. Note that an opening (not shown) may be formed in the passivation film 158 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed after the hydrogenation step.

Thereafter, a third interlayer insulating film 159 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. The advantages of using an organic resin film include that the film formation method is simple, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. Note that an organic resin film or an organic SiO compound other than those described above can also be used. Here, acrylic is used and formed by thermal firing.

Next, in a region to be a pixel circuit, the third
A shielding film 160 is formed over the interlayer insulating film 159. In addition,
In this specification, the term shielding film is used to mean that light and electromagnetic waves are shielded. The shielding film 160 is made of aluminum (A
1) A film made of an element selected from titanium (Ti) and tantalum (Ta) or a film containing any one of the elements as a main component and having a thickness of 100 to 300 nm. In this embodiment, 1w
An aluminum film containing t% titanium is formed to a thickness of 125 nm.

When an insulating film such as a silicon oxide film is formed on the third interlayer insulating film 159 in a thickness of 5 to 50 nm, the adhesion of the shielding film formed thereon can be improved. In addition, when plasma treatment using CF ₄ gas is performed on the surface of the third interlayer insulating film 159 formed of an organic resin, adhesion of a shielding film formed on the film can be improved by surface modification.

It is also possible to form not only a shielding film but also other connection wirings by using the titanium-containing aluminum film. For example, it is possible to form a connection wiring that connects circuits in a drive circuit. However, in that case, before forming the material for forming the shielding film or the connection wiring, the third
It is necessary to form a contact hole in the interlayer insulating film.

Next, an oxide 161 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 160 by an anodic oxidation method or a plasma oxidation method (in this embodiment, an anodic oxidation method). In this embodiment, the shielding film 160 is used.
As a result, an aluminum oxide film (alumina film) is formed as the anodic oxide 161.

In this anodizing treatment, an ethylene glycol tartrate solution having a sufficiently low alkali ion concentration is first prepared. This is a solution obtained by mixing a 15% aqueous solution of ammonium tartrate and ethylene glycol at a ratio of 2: 8, and ammonia water is added thereto to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, and the substrate on which the shielding film 160 is formed is immersed in the solution.
A DC current of several tens mA) is passed.

The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a constant current of 100 V / min at a step-up rate to reach the ultimate voltage of 45 V. By the way, the anodizing treatment is terminated. In this way, a thickness of about 50
nm anodic oxide 161 can be formed. As a result, the thickness of the shielding film 160 becomes 90 nm.
It is to be noted that the numerical values relating to the anodic oxidation method shown here are merely examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.

Although the insulating film is provided only on the surface of the shielding film using the anodic oxidation method here, the insulating film may be formed by a gas phase method such as a plasma CVD method, a thermal CVD method or a sputtering method. good. In this case, the film thickness is 20 to 1
It is preferably set to 00 nm (preferably 30 to 50 nm). In addition, silicon oxide film, silicon nitride film, silicon nitride oxide film, DLC (Diamond like carbon)
A film, a tantalum oxide film, or an organic resin film may be used.
Further, a stacked film combining these may be used.

Next, a contact hole reaching the drain wiring 157 is formed in the third interlayer insulating film 159 and the passivation film 158, and a pixel electrode 162 is formed. In addition,
The pixel electrode 163 is a pixel electrode of another adjacent pixel.
The pixel electrodes 162 and 163 may be formed using a transparent conductive film when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is formed. Here, in order to obtain a transmissive liquid crystal display device, indium tin oxide (IT
O) A film is formed to a thickness of 110 nm by a sputtering method.

At this time, the pixel electrode 162 and the shielding film 1
60 overlap with each other via the anodic oxide 161 to form a storage capacity (capacity striation) 164. Note that in this case, it is desirable that the shielding film 160 be set to a floating state (an electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).

Thus, an active matrix substrate having a drive circuit and a pixel circuit on the same substrate was completed. In FIG. 5, the driving circuit is a p-channel type TFT.
301 and n-channel TFTs 302 and 303 are formed.
304 is formed.

FIG. 8 is a top view corresponding to the sectional view of FIG.
(B), common symbols are used. FIG. 6 (B)
8A is a diagram showing a part of FIG.
A common code was used.

In the p-channel TFT 301 of the driving circuit, a channel forming region 201, a source region 202, and a drain region 203 are each formed of a p-type impurity region (a). However, strictly speaking, the source 202 region and the drain region 203 contain phosphorus at a concentration of 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ³ .

In the n-channel type TFT 302, the channel formation region 204, the source region 205, the drain region 206, and the region between the channel formation region and the drain region which overlaps with the gate wiring via the gate insulating film ( In this specification, such a region is referred to as an Lov region, where ov is assigned to overlap.) 207 is formed. At this time, the Lov region 207 is 2 × 10 ^{16 to} 5 × 10 ¹⁹
It is formed so as to contain phosphorus at a concentration of atoms / cm ³ and to completely overlap with the gate wiring.

In the n-channel TFT 303, the channel forming region 208, the source region 209, the drain region 210, and the L
DD regions 211 and 212 are formed. That is, an LDD region is formed between the source region and the channel formation region and between the drain region and the channel formation region.

In this structure, the LDD regions 211, 2
12 are arranged so as to overlap with the gate wiring, a region (Lov region) that overlaps with the gate wiring via the gate insulating film and a region that does not overlap with the gate wiring (such a region is referred to as Loff region, where off is
Affixed in the meaning of offset. ) Has been realized.

If the length (width) of the Lov region 207 of the n-channel TFT 302 is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, for a channel length of 3 to 7 μm. good. The length (width) of the Lov region of the n-channel TFT 303 is 0.3 to 3.0 μm, typically 0 to 3.0 μm.
5 to 1.5 μm, the length (width) of the Loff region is 1.0 to
The thickness may be 3.5 μm, typically 1.5 to 2.0 μm. The Loff region 2 provided in the pixel TFT 304
The length (width) of 17 to 220 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.

Although the gate wiring has a double gate structure in this embodiment, a multi-gate structure such as a triple gate structure may be used to improve the reliability of each circuit.
Further, a single gate structure may be employed.

In this embodiment, an alumina film having a relative dielectric constant as high as 7 to 9 is used as the dielectric of the storage capacitor.
The area occupied by the storage capacitor required to form the required capacitance can be reduced. Further, by using the shielding film formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the image display section of the active matrix type liquid crystal display device can be improved.

The present invention need not be limited to the structure of the storage capacitor shown in this embodiment. For example, the present applicant has filed Japanese Patent Application No. 9-316567 and Japanese Patent Application No. 9-2732.
A storage capacitor having a structure described in Japanese Patent Application No. 44 or Japanese Patent Application No. 10-254097 can also be used.

Further, the structure of the present invention is characterized in that a second interlayer insulating film is provided in a region where a gate wiring and an upper wiring overlap, and the other structures are appropriately determined by a practitioner. Good.

Here, a process of manufacturing an active matrix type liquid crystal display device from an active matrix substrate will be described. As shown in FIG. 9, the substrate in the state of FIG.
An alignment film 501 is formed. In this embodiment, a polyimide film is used as an alignment film. Further, a transparent conductive film 503 and an alignment film 504 are formed over the counter substrate 502. Note that a color filter and a shielding film may be formed on the counter substrate as needed.

Next, after forming the alignment film, a rubbing treatment is performed to adjust the liquid crystal molecules so as to be aligned with a certain pretilt angle. Then, the pixel circuit, the active matrix substrate on which the driver circuit is formed, and the counter substrate are attached to each other via a sealant 507, a spacer 506, or the like by a known cell assembling process. Thereafter, a liquid crystal 505 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix type liquid crystal display device shown in FIG. 9 is completed.

Next, the structure of the active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. In FIG. 10, common reference numerals are used to correspond to the cross-sectional structure diagrams of FIGS. 1 to 5. The active matrix substrate includes a pixel circuit 801 formed on a quartz substrate 101.
And a gate line (scanning line) side driving circuit 802 and a source line (signal line) side driving circuit 803. The pixel TFT 304 of the pixel circuit is an n-channel TFT, and a driving circuit provided in the periphery is configured based on a CMOS circuit. The gate line side driver circuit 802 and the source line side driver circuit 803 are connected to the pixel circuit 801 by a gate line 128 and a source line 154, respectively. Also, FP
Connection wirings 806 and 807 are provided from the external input / output terminal 805 to which the C 804 is connected to the input / output terminal of the drive circuit.

Next, FIG. 11 shows an example of a circuit configuration of the active matrix type liquid crystal display device shown in FIG. The active matrix type liquid crystal display device of this embodiment includes an image signal drive circuit 901, a gate line side drive circuit (A) 90
7, a gate line side drive circuit (B) 911, a precharge circuit 912, and a pixel circuit 906. Note that in this specification, a driving circuit includes a source line side driving circuit 901
And a gate line side driving circuit 907.

The source line side driving circuit 901 includes a shift register circuit 902, a level shifter circuit 903, a buffer circuit 904, and a sampling circuit 905. The gate line driver circuit (A) 907 includes a shift register circuit 908, a level shifter circuit 909, and a buffer circuit 910. Gate line side drive circuit (B) 911
Has a similar configuration.

As described above, the present invention provides a semiconductor device including at least a pixel circuit and a driving circuit for controlling the pixel circuit on the same substrate, for example, a signal processing circuit on the same substrate.
A semiconductor device including a driving circuit and a pixel circuit can be realized.

When the steps up to FIG. 2A of this embodiment are performed, a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice is formed. Hereinafter, the features of the crystal structure experimentally examined by the present applicant will be briefly described. In addition,
This feature coincides with the feature of the semiconductor layer forming the active layer of the TFT completed by this embodiment.

The crystalline silicon film has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter abbreviated as rod-like crystals) are gathered and lined up microscopically. This is T
It can be easily confirmed by observation by EM (transmission electron microscopy).

In addition, electron diffraction and X-ray (X-ray)
When diffraction is used, it can be confirmed that the surface of the crystalline silicon film (portion where a channel is formed) has a {110} plane as a main orientation plane, although the crystal axis has some deviation. At this time, if analysis is performed by electron beam diffraction,
It can be confirmed that diffraction spots corresponding to the 0 ° plane clearly appear. It can also be confirmed that each spot has a distribution on a concentric circle.

The crystal grain boundaries formed by the contact of the individual rod-shaped crystals are formed by HR-TEM (high-resolution transmission electron microscopy).
By observing the results, it can be confirmed that the crystal lattice has continuity at the crystal grain boundaries. This can be easily confirmed from the fact that the observed lattice fringes are continuously connected at the crystal grain boundaries.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of the planar grain boundary in this specification is `` Characterization of High-Efficiency Cast-Si
Solar Cell Wafers by MBICMeasurement; Ryuichi Shi
mokawa and Yutaka Hayashi, Japanese Journal of Appl
ied Physics vol.27, No.5, pp.751-758, 1988 ".

According to the above paper, the planar grain boundaries include twin grain boundaries, special stacking faults, special twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. In other words, since it is a crystal grain boundary but does not function as a trap that hinders the movement of carriers, it can be considered that it does not substantially exist.

In particular, the crystal axis (the axis perpendicular to the crystal plane) is <11
In the case of the <0> axis, the {211} twin grain boundaries are also called corresponding grain boundaries of {3}. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

When the crystalline silicon film of the present example was actually observed in detail using a TEM, it was found that almost all of the crystal grain boundaries (90%
It can be seen that (typically 95% or more) is the corresponding grain boundary of {3, typically {211} twin grain boundary.

In the grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3. In the crystalline silicon film of this embodiment, the lattice fringes of adjacent crystal grains at the crystal grain boundary are continuous at exactly an angle of about 70.5 °, which means that this crystal grain boundary is a corresponding grain boundary of Σ3. I can say.

When θ = 38.9 °, the corresponding grain boundary becomes Σ9, but there is another such corresponding grain boundary. In any case, it is still inert.

Such corresponding grain boundaries are formed only between crystal grains having the same plane orientation. That is, the crystalline silicon film of this embodiment can form such a corresponding grain boundary over a wide range only because the plane orientation is substantially {110}.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. Therefore, a semiconductor thin film having such a crystal structure can be regarded as having substantially no crystal grain boundaries.

Further, it was confirmed by TEM observation that defects existing in the crystal grains were almost completely eliminated by a heat treatment step (corresponding to the thermal oxidation step in Example 1) at a high temperature of 800 to 1150 ° C. ing. This is apparent from the fact that the number of defects is significantly reduced before and after this heat treatment step.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, it has been found that the spin density of the crystalline silicon film of this embodiment is at least 5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be lower.

From the above, the crystalline silicon film of this embodiment has extremely few defects in crystal grains and can be regarded as having substantially no crystal grain boundaries. It can be considered a silicon film.

[Embodiment 2] In Embodiment 1, as an example of a method of forming a semiconductor film having a crystal structure, a catalyst element that promotes crystallization is used. In this embodiment, such a catalyst element is used. A case where a semiconductor film including a crystal structure is formed by thermal crystallization or laser crystallization without using the same will be described.

In the case of thermal crystallization, after a semiconductor film having an amorphous structure is formed, a temperature of 600 to 650 ° C.
The heat treatment may be performed for 24 hours. That is, by performing heat treatment at a temperature exceeding 600 ° C., natural nuclei are generated, and crystallization proceeds.

In the case of laser crystallization, laser annealing may be performed after forming a semiconductor film having an amorphous structure. Thus, a semiconductor film including a crystal structure can be formed in a short time. Of course, lamp annealing may be used instead of laser annealing. Further, as the substrate, a glass substrate or a plastic substrate can be used in addition to the quartz substrate.

It is also effective to continuously form a base film and an amorphous silicon film on a substrate without opening them to the atmosphere. By doing so, it becomes possible to prevent contamination of the substrate surface from affecting the amorphous silicon film, and it is possible to reduce the variation in characteristics of the TFT to be manufactured.

As described above, the semiconductor film having a crystal structure used in the present invention can be formed by any known means.

[Embodiment 3] This embodiment is an example in which a contact hole is formed by a method different from that of Embodiment 1.
In this embodiment, after activation, a contact hole is formed, a second interlayer insulating film is laminated, and patterning is performed again to form a contact hole. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

First, according to the first embodiment, after the first interlayer insulating film 149 is laminated, activation is performed to obtain the state shown in FIG. FIG. 12 corresponds to FIG.
It is shown in (A).

Next, a contact hole reaching the source region or the drain region is formed. Note that the gate insulating film and the first interlayer insulating film are simultaneously or sequentially etched using the same mask. (FIG. 12B) If the etching at this time is performed by dry etching, a fine contact hole (0.5 μm to 1.5 μm) can be formed.

Next, a second interlayer insulating film 1201 is laminated to obtain a state shown in FIG. As the second interlayer insulating film, an insulating film having the same composition as in Example 1 was used. Next, after patterning the second interlayer insulating film 1201, a source wiring and a drain wiring are formed in the same manner as in the first embodiment.
FIG. 12D corresponding to FIG. 4C of the first embodiment is obtained. In patterning the second interlayer insulating film,
When wet etching is used, a tapered shape is obtained, so that coverage of a source wiring and a drain wiring formed thereon is improved. Subsequent steps are the same as in the first embodiment, and will not be described.

As described above, in the present embodiment, the first interlayer insulating film and the second interlayer insulating film having different film qualities are separately etched, so that a contact hole having a small shape and a good shape is formed. Can be. By doing so, reliable contact connection can be performed, so that the yield can be improved.

The structure of this embodiment can be freely combined with the structure of Embodiment 1 or 2.

[Embodiment 4] In this embodiment, the patterning of the gate insulating film is performed after the patterning of the gate electrode, thereby making it possible to easily form a contact hole. The basic configuration is almost the same as that of the first embodiment. Therefore, only the differences will be described.

First, the state of FIG. 2E is obtained according to the first embodiment. It should be noted that a diagram corresponding to FIG.
It is shown in (A).

Next, etching was performed using the gate electrode as a mask to form a gate insulating film 1301. (FIG. 13
(B)) Thereafter, a p-type impurity element is doped using the resist mask 1304 to form p-type impurity regions (a) 1302 and 1303 doped at the same concentration as in the first embodiment. However, since the doping is performed with the active layer exposed, the doping conditions must be changed from those of the first embodiment. (FIG. 13 (C))

Next, the resist mask 1304 is removed, and resist masks 1305 to 1308 are formed. And
The n-type impurity element is doped using the resist masks 1305 to 1308 to form n-type impurity regions (a) 1309 to 1315 doped at the same concentration as in the first embodiment. However, the practitioner has to change the doping conditions from the first embodiment in order to perform the doping with the active layer exposed. (FIG. 13D)

Next, the resist masks 1305 to 1308 are removed, and an n-type impurity element is doped using the gate electrode as a mask to form n-type impurity regions (c) 1401 to 1404 doped at the same concentration as in the first embodiment. I do. However, the practitioner has to change the doping conditions from the first embodiment in order to perform the doping with the active layer exposed. (FIG. 14A)

Next, after forming the first interlayer insulating film 1405 in the same manner as in Example 1, an activation step was performed.
(FIG. 14B) However, in this embodiment, since there is a portion where the active layer is covered only with the first interlayer insulating film,
A minimum thickness for protecting the active layer is required for the first interlayer insulating film. Here, the thickness of the first interlayer insulating film may be typically 50 nm to 200 nm.

Next, a second interlayer insulating film 1406 is formed as in the first embodiment. (FIG. 14C)

Next, the first interlayer insulating film and the second interlayer insulating film are simultaneously or sequentially etched in the same manner as in Example 1 to form a contact hole reaching the source region or the drain region. Form. The steps after (FIG. 14D) are the same as those in the first embodiment, and thus will be omitted.

In this embodiment, the example in which the gate insulating film is etched immediately after the formation of the gate wiring is described. However, the step of removing the gate insulating film is performed only after the formation of the gate wiring. What is necessary is just before the film formation.

By doing so, the number of laminated insulating films to be opened can be reduced, so that the yield can be improved. However, it is necessary to take into consideration the etching rates of the first interlayer insulating film and the second interlayer insulating film as in the first embodiment.

The structure of the present embodiment can be freely combined with the structures of the first to third embodiments.

[Embodiment 5] In this embodiment, a case will be described in which the present invention is applied to a semiconductor device manufactured on a silicon substrate. Typically, the present invention can be applied to a reflection type liquid crystal display device using a metal film having high reflectance as a pixel electrode.

In this embodiment, a silicon substrate (silicon wafer) is used as the substrate of the first embodiment, and an n-type or p-type impurity element is directly added to the silicon substrate to form an LDD region,
An impurity region such as a source region or a drain region is formed. At that time, the order of forming the impurity regions and the order of forming the gate insulating film are not limited.

The structure of this embodiment can be freely combined with any of the structures of the first to fourth embodiments.
However, since the semiconductor layer serving as the active layer is determined to be a single-crystal silicon substrate, the semiconductor layer is a combination other than the crystallization step.

[Embodiment 6] The present invention relates to a conventional MOSFET.
It is also possible to form an interlayer insulating film thereon and use it when forming a TFT thereon. That is, it is possible to realize a semiconductor device having a three-dimensional structure. In addition, S
An SOI substrate such as IMOX, Smart-Cut (registered trademark of SOITEC), ELTRAN (registered trademark of Canon Inc.) can also be used.

The structure of this embodiment can be freely combined with any of the structures of the first to fifth embodiments.

[Embodiment 7] In this embodiment, a case will be described in which the present invention is applied to a semiconductor device in which a memory portion and a driver circuit are formed over the same substrate.

The memory section is formed of a nonvolatile memory (here, an EEPROM), and FIG. 15 illustrates one memory transistor (also referred to as a memory cell transistor) formed in the memory cell. In practice, a plurality of memory cells are integrated to form a memory section. Here, a highly integrated flash memory (flash EEPROM
M).

The memory transistor is connected to the source region 150
5, drain region 1508, low concentration impurity region (LDD
1506) and a channel formation region 1507
Active layer containing, a gate insulating film 1500, a first interlayer insulating film 1501, a second interlayer insulating film 1502c, a floating gate electrode 1509, a third gate insulating film 11, a control gate electrode 15
10, and a common source wiring 1512 and a bit wiring (drain wiring) 1511 formed via the third interlayer insulating film 1503.

The source region 1505 has the floating gate electrode 15
09 to the common source wiring 1
It is an area to be extracted at 512 and can also be called an erase area. Although the LDD region 1506 is provided between the semiconductor device and the channel formation region 1507 in FIG. 15, the LDD region 1506 does not have to be formed. The drain region 1508 is a region for injecting carriers into the electrically isolated floating gate electrode 1509, and can be said to be a writing region. Further, the drain region 1508 also functions as a read region for reading data stored in the memory transistor to the bit wiring 1511.

As the gate insulating film 1500, an insulating film (thickness: 3 to 20 nm, preferably 5 to 10 n) is thin enough to allow a tunnel current (Fowler-Nordheim current) to flow.
Since it is necessary to use m), it is preferable to use an oxide film obtained by oxidizing the active layer (a silicon oxide film if the active layer is silicon). Of course, as long as uniformity of the film thickness is assured, the first gate insulating film can be formed by a vapor phase method such as a CVD method or a sputtering method.

In this embodiment, the control gate electrode 15
10 and bit wiring 1511 or common source wiring 151
The parasitic capacitance generated in the overlapping portion with the second interlayer insulating film 1
502c.

Further, a CMOS circuit will be described as a specific example of forming the drive circuit portion. Actually, logic circuits such as flip-flop circuits are formed using a CMOS circuit as a basic circuit, and they are integrated to form a drive circuit portion. CM
Also in the OS circuit, second interlayer insulating films 1502a and 1502a for reducing the parasitic capacitance between the gate wiring and the upper wiring.
2b is provided.

As described above, the present invention can be applied to various semiconductor devices.

The structure of this embodiment can be freely combined with any of the structures of the first to sixth embodiments.

[Embodiment 8] This embodiment is an example utilizing anisotropic etching. The basic configuration is almost the same as the first embodiment or the third embodiment. Therefore, only the differences will be described with reference to FIG.

In this embodiment, the gate insulating film is etched using the gate electrode as a mask, a first interlayer insulating film is formed, and activation is performed in the same manner as in the third embodiment.
4 (B).

Next, anisotropic etching is performed on the first interlayer insulating film to form a triangular insulator 160 on both sides of the gate electrode.
Form one. At this time, it is preferable to form a protective film (not shown) for protecting the gate wiring in advance.

Next, a second interlayer insulating film 1602 is formed. Then, after etching the second interlayer insulating film to form a contact hole reaching the source region or the drain region, a source wiring and a drain wiring are formed. Subsequent steps are the same as in the first embodiment, and will not be described.

By doing so, the number of laminated insulating films to be opened can be reduced, so that the formation of contact holes can be simplified and the yield can be improved.

[0192] Alternatively, a step may be performed in which a triangular insulator 1601 is formed immediately after the gate electrode is formed, and an impurity region such as an LDD region is formed using the insulator 1601.

The structure of this embodiment can be freely combined with any of the structures of Embodiments 1 to 7.

[Embodiment 9] In this embodiment, a case where the present invention is applied to a bottom gate type TFT will be described. Specifically, FIG. 17 shows a case where the present invention is used for an inverted stagger type TFT. In the case of the inverted stagger type TFT of the present invention, there is no particular difference from the top gate type TFT of Example 1 except that the positional relationship between the gate wiring and the active layer is different. Therefore, in the present embodiment, description will be made while paying attention to a point that is significantly different from the structure shown in FIG. 5, and the other parts are the same as those in FIG. As in the first embodiment, second interlayer insulating films 46 and 47 for reducing the parasitic capacitance are formed. This second interlayer insulating film is formed by the method described in the first embodiment.

In FIG. 17, reference numerals 11 and 12 denote a p-channel TFT and an n-channel TFT of a CMOS circuit forming a shift register circuit and the like, respectively, an n-channel TFT 13 forming a sampling circuit and the like, and 14 a pixel circuit. This is an n-channel TFT to be formed. These are formed on a substrate provided with a base film.

Reference numeral 15 denotes a gate wiring of the p-channel TFT 11, 16 denotes a gate wiring of the n-channel TFT 12, 17 denotes a gate wiring of the n-channel TFT 13, 18
Denotes a gate wiring of the n-channel TFT 14, which can be formed using the same material as the gate wiring described in the first embodiment. Reference numeral 19 denotes a gate insulating film, which can also be made of the same material as in the first embodiment.

The active layer (active layer) of each of the TFTs 11 to 14 is formed thereon. Note that at the time of manufacturing the gate insulating film and the semiconductor film included in the active layer, it is preferable to perform continuous film formation by a sputtering method or a PCVD method without touching the air. p-channel type TFT11
In the active layer, a source region 20, a drain region 21, and a channel forming region 22 are formed.

In the active layer of the n-channel TFT 12, a source region 23, a drain region 24, an LDD region (Lov region 25 in this case), and a channel forming region 26 are formed.

The active layer of the n-channel type TFT 13 includes a source region 27, a drain region 28, and an LDD region (in this case, Lov regions 29a, 30a and Loff region 29).
b, 30b), a channel forming region 31 is formed.

In the active layer of the n-channel TFT 14, a source region 32, a drain region 33, an LDD region (in this case, Loff regions 34 to 37), channel formation regions 38 and 39, and an n ⁺ region 40 are formed. You.

The insulating films 41 to 45 are formed for the purpose of protecting the channel formation region and the purpose of forming the LDD region.

As described above, it is easy to apply the present invention to a bottom gate type TFT represented by an inverted stagger type TFT. Note that in manufacturing the inverted staggered TFT of this embodiment, the manufacturing steps described in the other embodiments described in this specification may be applied to a known inverted staggered TFT manufacturing step.

The structure of this embodiment can be freely combined with any of the structures of the first to eighth embodiments.

[Embodiment 10] The present invention can also be applied to an active matrix type EL (electroluminescence) display. An example is shown in FIG.

FIG. 18 is a circuit diagram of an active matrix type EL display. Reference numeral 81 denotes a pixel circuit, around which an X-direction drive circuit 82 and a Y-direction drive circuit 83 are provided. Each pixel of the pixel circuit 81 has a switching TFT 84, a capacitor 85, a current controlling TFT 86, and an organic EL element 87.
The X direction signal line 88a (or 88b) and the Y direction signal line 89a (or 89b, 89c) are connected to the FT 84. The power supply lines 90a and 90b are connected to the current control TFT 86.

In the active matrix EL display of this embodiment, the TFTs used for the X-direction drive circuit 82, the Y-direction drive circuit 83 or the current control TFT 86 are five p-channel TFTs 301 and n-channel TFTs 3
02 or 303 in combination. Also, the TFT of the switching TFT 84 is the n-channel TFT of FIG.
Formed at 304.

The active matrix EL display of this embodiment may be combined with any of the structures of the first to ninth embodiments.

[Embodiment 11] Various liquid crystal materials can be used for a liquid crystal display device manufactured according to the present invention. Such materials include TN liquid crystal, PDLC (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal), AFLC
(An anti-strongly inducing electro-liquid crystal), or a mixture of FLC and AFLC.

For example, “H. Furue et al .; Charakteristi
cs and Drivng Scheme of Polymer-Stabilized Monosta
ble FLCD Exhibiting Fast Response Time and High Co
ntrast Ratio with Gray-Scale Capability, SID, 199
8 "," T. Yoshida et al .; A Full-Color Thresholdless "
Antiferroelectric LCD Exhibiting Wide Viewing Ang
le with Fast Response Time, 841, SID97DIGEST, 199
7 ", or the materials disclosed in US Pat. No. 5,594,569.

In particular, a thresholdless (non-threshold) antiferroelectric liquid crystal (Thresholdless Antiferroelectric LCD:
TL-AFLC) can be used to reduce the operating voltage of the liquid crystal to about ± 2.5 V.
In some cases, about 8 V may be enough. That is, the driver circuit and the pixel matrix circuit can be operated at the same power supply voltage, and the power consumption of the entire liquid crystal display device can be reduced.

Some thresholdless antiferroelectric liquid crystals exhibit V-shaped electro-optical response characteristics, and those having a driving voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) are also available. Have been found.

Here, FIG. 19 shows an example showing characteristics of light transmittance with respect to applied voltage of a thresholdless antiferroelectric mixed liquid crystal exhibiting a V-shaped electro-optical response. The vertical axis of the graph shown in FIG. 19 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. The transmission axis of the polarizing plate on the incident side of the liquid crystal panel is set substantially parallel to the normal direction of the smectic layer of the thresholdless antiferroelectric mixed liquid crystal, which substantially coincides with the rubbing direction of the liquid crystal panel. The transmission axis of the exit-side polarizing plate is substantially perpendicular to the transmission axis of the incidence-side polarizing plate (crossed Nicols).
Is set to

The ferroelectric liquid crystal and the antiferroelectric liquid crystal are T
There is an advantage that the response speed is faster than that of the N liquid crystal. Since the crystalline TFT used in the above embodiment can realize a TFT having a very high operation speed, a high image response speed utilizing the high response speed of the ferroelectric liquid crystal or the antiferroelectric liquid crystal can be realized. It is possible to realize a liquid crystal display device.

It is needless to say that it is effective to use the liquid crystal display device of this embodiment as a display for electronic equipment such as a personal computer.

The structure of this embodiment can be freely combined with any of the structures of the first to ninth embodiments.

[Embodiment 12] In this embodiment, an example in which an EL (electroluminescence) display device is manufactured by using the present invention will be described. Note that FIG. 20A is a top view of the EL display device of the present invention, and FIG. 20B is a cross-sectional view thereof.

In FIG. 20A, reference numeral 4001 denotes a substrate;
4002 is a pixel portion, 4003 is a source side driver circuit, 40
Reference numeral 04 denotes a gate-side drive circuit. Each drive circuit reaches an FPC (flexible print circuit) 4006 via a wiring 4005 and is connected to an external device.

At this time, a first sealant 4101, a cover 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side drive circuit 4003, and the gate side drive circuit 4004.

FIG. 20 (B) shows FIG.
The driving TFTs included in the source-side driving circuit 4003 on the substrate 4001 (however,
Here, an n-channel TFT and a p-channel TFT are illustrated. ) 4201 and a current controlling TFT (TF controlling the current to the EL element) included in the pixel portion 4002.
T) 4202 is formed.

In the present embodiment, a TFT having the same structure as the p-channel TFT or the n-channel TFT shown in FIG.
Uses a TFT having the same structure as the p-channel TFT of FIG. The pixel portion 4002 has a current controlling TFT.
A storage capacitor (not shown) connected to the gate of 4202 is provided.

Drive TFT 4201 and Pixel TFT 420
An interlayer insulating film (flattening film) 43 made of a resin material is formed on
01 is formed thereon, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide, tin oxide, or indium oxide can be used. Further, a material obtained by adding gallium to the transparent conductive film may be used.

Then, an insulating film 4303 is formed on the pixel electrode 4302, and the insulating film 4303 is formed on the pixel electrode 430.
2, an opening is formed. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. For the EL layer 4304, a known organic EL material or inorganic EL material can be used. As the organic EL material, there are a low-molecular (monomer) material and a high-molecular (polymer) material, and either may be used.

As a method for forming the EL layer 4304, a known evaporation technique or coating technique may be used. The EL layer may have a stacked structure or a single-layer structure by freely combining a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, or an electron injection layer.

[0224] On the EL layer 4304, a conductive film containing an element belonging to Group 1 or 2 of the periodic table (typically, aluminum, copper, or silver containing an alkali metal element or an alkaline earth metal element) is used. Cathode 43 made of conductive film)
05 is formed. Further, the cathode 4305 and the EL layer 430
It is desirable that moisture and oxygen existing at the interface of No. 4 be eliminated as much as possible. Therefore, the two layers are continuously formed in a vacuum or
It is necessary to devise a method in which the EL layer 4304 is formed in a nitrogen or rare gas atmosphere and the cathode 4305 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is made possible by using a multi-chamber type (cluster tool type) film formation apparatus.

The cathode 4305 is electrically connected to the wiring 4005 in a region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305, and an FPC through an anisotropic conductive film 4307.
4006.

As described above, the pixel electrode (anode) 43
02, an EL element including the EL layer 4304 and the cathode 4305 is formed. This EL element has a first sealing material 410
Are surrounded by a cover material 4102 bonded to the substrate 4001 by the first and first seal materials 4101,
3 enclosed.

As the cover material 4102, a glass material, a metal material (typically, a stainless steel material), a ceramic material, and a plastic material (including a plastic film) can be used. As a plastic material, FRP (Fi
Berglass-Reinforced Plast
ics) plate, PVF (polyvinyl fluoride) film, mylar film, polyester film or acrylic resin film. Further, a sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.

However, when the direction of light emission from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.

As the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used. Acetate) can be used. By providing a hygroscopic substance (preferably barium oxide) or a substance capable of adsorbing oxygen inside the filler 4103, deterioration of the EL element can be suppressed.

[0230] The filler 4103 may contain a spacer. At this time, if the spacer is made of barium oxide, the spacer itself can have hygroscopicity. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer for relaxing pressure from the spacer.

[0231] The wiring 4005 is electrically connected to the FPC 4006 via the anisotropic conductive film 4307. The wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source driver circuit 4003, and the gate driver circuit 4004 to the FPC 4006, and is electrically connected to an external device by the FPC 4006.

In this embodiment, the first sealing material 4101
A second sealing material 4104 is provided so as to cover the exposed part of the FPC 4006 and a part of the FPC 4006, and the EL element is completely shut off from the outside air. Thus, an EL display device having the cross-sectional structure in FIG.

Here, a more detailed sectional structure of the pixel portion is shown in FIG. 21, a top surface structure is shown in FIG. 22A, and a circuit diagram is shown in FIG.
It is shown in (B). FIGS. 21, 22 (A) and 22 (B)
Then, since a common code is used, they may be referred to each other.

In FIG. 21, a switching TFT 4402 provided on a substrate 4401 is formed using the n-channel TFT shown in FIG. Therefore, the description of the structure is n
See the description of the channel type TFT. Also, 44
The wiring denoted by 03 is a switching TFT 4402
This is a gate wiring for electrically connecting the gate electrodes 4404a and 4404b.

Although the embodiment has a double gate structure in which two channel formation regions are formed, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed. good.

The drain wiring 4405 of the switching TFT 4402 is electrically connected to the gate electrode 4407 of the current control TFT 4406. The current control TFT 4406 is the p-channel TFT 30 shown in FIG.
1 is formed. Therefore, for the description of the structure, the description of the p-channel TFT 301 may be referred to. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.

The first passivation film 4 is formed on the switching TFT 4402 and the current control TFT 4406.
408 are provided, and a planarizing film 44 made of resin is provided thereon.
09 is formed. It is very important to flatten the step due to the TFT using the flattening film 4409. Since an EL layer formed later is extremely thin, poor light emission may be caused by the presence of a step. Therefore, it is desirable that the EL layer be flattened before forming the pixel electrode so that the EL layer can be formed as flat as possible.

Reference numeral 4410 denotes a pixel electrode (anode of an EL element) made of a transparent conductive film.
06 is electrically connected to the drain wiring 4411. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, zinc oxide,
Tin oxide or indium oxide can be used.
Further, a material obtained by adding gallium to the transparent conductive film may be used.

An EL layer 4411 is provided on the pixel electrode 4410.
Is formed. Although only one pixel is shown in FIG. 21, in this embodiment, EL layers corresponding to each of R (red), G (green), and B (blue) are separately formed. In this embodiment, a low-molecular organic EL material is formed by an evaporation method. Specifically, a laminated structure in which a 20-nm-thick copper phthalocyanine (CuPc) film is provided as a hole injection layer, and a 70-nm-thick tris-8-quinolinolato aluminum complex (Alq ₃ ) film is provided as a light-emitting layer thereon And Al
quinacridone q _3, it is possible to control the luminescent color by adding a fluorescent dye such as perylene or DCM1.

However, the above example is an example of the organic EL material that can be used for the EL layer, and it is not necessary to limit the invention to this. An EL layer (a layer for performing light emission and carrier movement therefor) may be formed by freely combining a light emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, a low molecular organic EL material is
Although an example in which the layer is used as a layer has been described, a polymer organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used for these organic EL materials and inorganic materials.

Next, a cathode 4412 made of a conductive film is provided on the EL layer 4411. In this embodiment, an alloy film of aluminum and lithium is used as the conductive film.
Of course, a known MgAg film (an alloy film of magnesium and silver) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

At the time when the cathode 4412 is formed, E
The L element 4413 is completed. Note that the EL element 4413 here includes a pixel electrode (anode) 4410 and an EL layer 441.
1 and a capacitor formed by the cathode 4412.

Next, the top structure of the pixel in this embodiment will be described with reference to FIG. Switching TFT
The source of 4402 is connected to the source wiring 4415, and the drain is connected to the drain wiring 4405. Further, the drain wiring 4405 is electrically connected to the gate electrode 4407 of the current controlling TFT 4406. The source of the current control TFT 4406 is electrically connected to the current supply line 4416, and the drain is electrically connected to the drain wiring 4417. Further, the drain wiring 4417 is electrically connected to a pixel electrode (anode) 4418 shown by a dotted line.

At this time, a storage capacitor is formed in a region indicated by 4419. The storage capacitor 4419 is formed between the semiconductor film 4420 electrically connected to the current supply line 4416, an insulating film (not shown) in the same layer as the gate insulating film, and the gate electrode 4407. In addition, the gate electrode 440
7. A capacitor formed by the same layer (not shown) as the first interlayer insulating film and the current supply line 4416 can also be used as a storage capacitor.

[Embodiment 13] In this embodiment, Embodiment 12 will be described.
An EL display device having a pixel structure different from that described above will be described. FIG. 23 is used for the description. Note that the description of the twelfth embodiment may be referred to for the portions denoted by the same reference numerals as in FIG.

In FIG. 23, a TFT having the same structure as the n-channel TFT of FIG. 5 is used as the current control TFT 4501. Of course, the gate electrode 45 of the current control TFT 4501
02 is the drain wiring 4 of the switching TFT 4402
405 is electrically connected. In addition, the current control T
The drain wiring 4503 of the FT 4501 is connected to the pixel electrode 450
4 is electrically connected.

In this embodiment, the pixel electrode 4 made of a conductive film is used.
504 functions as a cathode of the EL element. In particular,
Although an alloy film of aluminum and lithium is used, a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film to which those elements are added may be used.

On the pixel electrode 4504, an EL layer 4505 is provided.
Is formed. Although only one pixel is shown in FIG. 23, in this embodiment, an EL layer corresponding to G (green) is formed by an evaporation method and a coating method (preferably a spin coating method). Specifically, 20n is used as the electron injection layer.
It has a laminated structure in which a m-thick lithium fluoride (LiF) film is provided, and a 70-nm-thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.

Next, an anode 4506 made of a transparent conductive film is provided on the EL layer 4505. In the case of this embodiment,
As the transparent conductive film, a conductive film including a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used.

When the anode 4506 is formed, E
The L element 4507 is completed. Note that the EL element 4507 used here includes a pixel electrode (cathode) 4504 and an EL layer 450.
5 and the anode 4506.

When the voltage applied to the EL element is as high as 10 V or more, deterioration of the current control TFT 4501 due to the hot carrier effect becomes apparent. In such a case, it is effective to use an n-channel TFT having the structure of the present invention as the current control TFT 4501.

Also, the current controlling TFT 450 of the present embodiment is used.
1 forms a parasitic capacitance called a gate capacitance between the gate electrode 4502 and the LDD region 4509. By adjusting the gate capacitance, a function equivalent to that of the storage capacitor 4418 shown in FIGS. 22A and 22B can be provided. In particular, when the EL display device is operated by the digital driving method, the capacitance of the storage capacitor can be smaller than when the EL display device is operated by the analog driving method.
The gate capacitance can substitute for the storage capacitance.

When the voltage applied to the EL element is 10 V or less, preferably 5 V or less, the deterioration due to the hot carrier effect does not become a significant problem.
In FIG. 23, n has a structure in which the LDD region 4509 is omitted.
A channel type TFT may be used.

[Embodiment 14] In this embodiment, Embodiment 12 will be described.
FIGS. 24A to 24C illustrate an example of a pixel structure that can be used in the pixel portion of the EL display device described in Embodiment 13.
Shown in In this embodiment, reference numeral 4601 denotes a source wiring of the switching TFT 4602, 4603 denotes a gate wiring of the switching TFT 4602, 4604 denotes a current controlling TFT, 4605 denotes a capacitor, 4606 and 46.
08 is a current supply line, and 4607 is an EL element.

FIG. 24A shows an example in which the current supply line 4606 is shared between two pixels. That is, it is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 4606. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 24B shows the current supply line 460.
8 is provided in parallel with the gate wiring 4603. Note that although FIG. 24B illustrates a structure in which the current supply line 4608 and the gate wiring 4603 are provided so as not to overlap with each other, if the wiring is formed in a different layer,
They can be provided so as to overlap with each other via an insulating film. In this case, the current supply line 4608 and the gate wiring 4603 can share an occupied area, so that the pixel portion can have higher definition.

In FIG. 24C, a current supply line 4608 is provided in parallel with the gate wiring 4603, and two pixels are connected to the current supply line 4608 in the same manner as in the structure of FIG.
It is characterized in that it is formed so as to be line-symmetric with respect to.
It is also effective to provide the current supply line 4608 so as to overlap with one of the gate wirings 4603. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

[Embodiment 15] In this embodiment, an example of a pixel structure of an EL display device embodying the present invention is shown in FIG.
It is shown in (B). In this embodiment, reference numeral 4701 denotes a source wiring of the switching TFT 4702, 4703 denotes a gate wiring of the switching TFT 4702, 4704.
Is a current control TFT, 4705 is a capacitor (may be omitted), 4706 is a current supply line, 4707 is a power control TFT, 4708 is a power control gate wiring,
709 is an EL element. For the operation of the power supply control TFT 4707, refer to Japanese Patent Application No. 11-341272.

In this embodiment, the power supply control TFT 47 is used.
07 is provided between the current controlling TFT 4704 and the EL element 4708, but the power controlling TFT 4707 and the EL
A current control TFT 4704 may be provided between the element 4708 and the element 4708. Also, the power supply control TFT 47
07 has the same structure as the current control TFT 4704,
It is preferable to form them in series with the same active layer.

FIG. 25A shows an example in which a current supply line 4706 is shared between two pixels. That is,
It is characterized in that the two pixels are formed to be line-symmetric with respect to the current supply line 4706. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 25B shows a gate wiring 470.
A current supply line 4710 is provided in parallel with
This is an example in the case where a power supply control gate wiring 4711 is provided in parallel with the line 01. Note that the current supply line 47 is shown in FIG.
Although the structure is such that 10 and the gate wiring 4703 are provided so as not to overlap with each other, the wiring may be provided so as to overlap via an insulating film as long as both are formed in different layers. In this case, the current supply line 4710 and the gate wiring 47
03 can share the occupied area, so that the pixel portion can be further refined.

[Embodiment 16] In this embodiment, an example of a pixel structure of an EL display device embodying the present invention will be described with reference to FIG.
It is shown in (B). In this embodiment, reference numeral 4801 denotes a source wiring of the switching TFT 4802, 4803 denotes a gate wiring of the switching TFT 4802, and 4804.
Is a current control TFT, 4805 is a capacitor (can be omitted), 4806 is a current supply line, 4807 is an erasing TFT, 4808 is an erasing gate wiring, and 4809 is an EL element. For the operation of the erasing TFT 4807, refer to Japanese Patent Application No. 11-338786.

The drain of the erasing TFT 4807 is connected to the gate of the current controlling TFT 4804,
The gate voltage of the FT4804 can be forcibly changed. The erasing TFT 4807
May be an n-channel TFT or a p-channel TFT, but preferably has the same structure as the switching TFT 4802 so that off-state current can be reduced.

FIG. 26A shows an example in which a current supply line 4806 is shared between two pixels. That is,
The feature is that two pixels are formed so as to be line-symmetric with respect to the current supply line 4806. In this case, the number of current supply lines can be reduced, so that the pixel portion can have higher definition.

FIG. 26B shows a gate wiring 480.
3, a current supply line 4810 is provided in parallel with the source line 48.
This is an example in which an erasing gate wiring 4811 is provided in parallel with the line 01. In FIG. 26B, the current supply line 4810
Although the gate wiring 4803 and the gate wiring 4803 are provided so as not to overlap with each other, they may be provided so as to overlap with each other via an insulating film as long as they are formed in different layers. In this case, the current supply line 4810 and the gate wiring 480
3 can share an occupied area, so that the pixel portion can be further refined.

[Embodiment 17] The EL display device may have a structure in which any number of TFTs are provided in a pixel. For example,
Four to six or more TFTs may be provided. The present invention can be implemented without being limited to the pixel structure of the EL display device. [Embodiment 18] In a CMOS circuit or a pixel portion formed by implementing the present invention, the parasitic capacitance could be sufficiently reduced even if the gate wiring and the second wiring were overlapped to improve the aperture ratio. Therefore, it is more effective to use it for an active matrix type liquid crystal display device having a diagonal of 1 inch or less.

An example of such an electronic device is a goggle type display device (head-mounted display). Referring to FIG. FIG. 27 is a schematic configuration diagram of the goggle type display device of the present embodiment. 1900 is a goggle type display device main body, 1901R and 1901L
Are lenses, 1902R and 1902L are liquid crystal panels,
1903R and 1903L are backlights.

The present invention relates to the liquid crystal panels 1902R, 190
It can be applied to 2L and other driving circuits.

The structure of this embodiment is similar to those of the first to eleventh embodiments.
Any configuration can be freely combined.

[Embodiment 19] A CMOS circuit and a pixel circuit formed by carrying out each of the above embodiments can be applied to various electro-optical devices (active matrix liquid crystal display, active matrix EL display, active matrix EC (electrochromic EC)). ) Display). That is, the present invention can be applied to all electronic apparatuses in which these electro-optical devices are incorporated as display units.

As such electronic equipment, a large-sized television,
Video cameras, digital cameras, wearable displays, car navigation systems, personal computers,
A portable information terminal (a mobile computer, a mobile phone, an electronic book, or the like) is included. FIG. 28 shows an example of them.
And FIG.

FIG. 28A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004. The present invention can be applied to the image input unit 2002, the display unit 2003, and other driving circuits.

FIG. 28B shows a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 210.
6. The present invention can be applied to the display portion 2102, the audio input portion 2103, and other driving circuits.

FIG. 28C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display section 2205. The invention of the present application is a display unit 2205.
And other drive circuits.

FIG. 28D shows a digital camera, which comprises a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown).
The present invention can be applied to the display portion 2502 and other driving circuits.

FIG. 28E shows a player that uses a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, and operation switches 2405. This apparatus uses a DVD (Dig) as a recording medium.
Tear Versatile Disc), a CD, or the like can be used for music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other driving circuits.

FIG. 30A shows a mobile phone,
01, audio output unit 2902, audio input unit 2903, display unit 2904, operation switch 2905, antenna 2906
And so on. The present invention can be applied to the audio output unit 2902, the audio input unit 2903, the display unit 2904, and other signal control circuits.

FIG. 30B shows a portable book (electronic book), which includes a main body 3001, display portions 3002 and 3003, a storage medium 3004, operation switches 3005, and an antenna 3006.
And so on. The present invention can be applied to the display units 3002 and 3003 and other signal circuits.

FIG. 30C shows a display, which includes a main body 3101, a support 3102, a display portion 3103, and the like.
The present invention can be applied to the display portion 3103. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using any combination of the embodiments 1 to 18.

[Embodiment 20] A liquid crystal display device formed by carrying out the present invention can be used for a projector (rear type or front type).

FIG. 29A shows a front type projector, which comprises a display portion 2601 and a screen 2602. The present invention can be applied to a display portion and other driving circuits.

FIG. 29B shows a rear type projector, which includes a main body 2701, a display portion 2702, a mirror 2703,
It comprises a screen 2704. The present invention can be applied to a display portion and other driving circuits.

[0284] FIG. 29C is a diagram showing an example of the structure of the display portions 2601 and 2702 in FIGS. 29A and 29B. Display units 2601, 2702
Are the light source optical system 2801, the mirrors 2802, 2804-
2806, dichroic mirror 2803, prism 2
807, a liquid crystal display device 2808, a retardation plate 2809, and a projection optical system 2810. Projection optical system 2810
Is composed of an optical system including a projection lens. In the present embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately place an optical lens, a film having a polarizing function, a film for adjusting a phase difference,
An optical system such as an IR film may be provided.

FIG. 29D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 29C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 29D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

The electronic apparatus of this embodiment is the same as those of the first to ninth embodiments.
Also, the present invention can be realized by using a configuration composed of any combination of Embodiment 11 and Embodiment 11.

[0287]

By using the present invention, it is possible to reduce the parasitic capacitance formed by the multi-layer wiring, and to greatly improve the operation performance and reliability of the semiconductor device (specifically, the electro-optical device here). did it.

In a pixel circuit of an electro-optical device typified by an active matrix type liquid crystal display device, the parasitic capacitance could be sufficiently reduced even if the gate wiring and the second wiring were overlapped to improve the aperture ratio. . Therefore, diagonal 1
Even in an active matrix type liquid crystal display device of inches or less, the aperture ratio can be improved, the parasitic capacitance can be reduced, and a sufficient storage capacitance can be secured.

Further, a semiconductor device having such an electro-optical device as a display medium (specifically, an electronic device in this case)
The operating performance and reliability of the device were also improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 2 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 3 is a view showing a manufacturing process of an AM-LCD.

FIG. 4 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 5 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 6 is a top view in a manufacturing process of an AM-LCD.

FIG. 7 is a top view in a manufacturing process of an AM-LCD.

FIG. 8 is a top view of a pixel circuit.

FIG. 9 is a cross-sectional structural view of a liquid crystal display device.

FIG. 10 is a diagram showing an appearance of an AM-LCD.

FIG. 11 is a circuit block diagram.

FIG. 12 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 13 is a view showing a manufacturing process of an AM-LCD.

FIG. 14 is a diagram showing a manufacturing process of an AM-LCD.

FIG. 15 illustrates a configuration of a memory unit and a CMOS circuit.

FIG. 16 illustrates a structure of a pixel circuit and a CMOS circuit.

FIG. 17 illustrates a structure of a pixel circuit and a CMOS circuit.

FIG. 18 illustrates a structure of an active matrix EL display device.

FIG. 19 is a graph showing characteristics of light transmittance with respect to an applied voltage of a thresholdless antiferroelectric mixed liquid crystal.

20A and 20B are a top view and a cross-sectional view of an active matrix EL display device.

FIG. 21 is a cross-sectional view illustrating a pixel structure of an active matrix EL display device.

FIG. 22 is a top view illustrating a pixel structure of an active matrix EL display device.

FIG. 23 is a cross-sectional view illustrating a pixel structure of an active matrix EL display device.

FIG. 24 is a circuit diagram of an active matrix EL display device.

FIG. 25 is a circuit diagram of an active matrix EL display device.

FIG. 26 is a circuit diagram of an active matrix EL display device.

FIG. 27 illustrates an example of a goggle-type display device.

FIG. 28 illustrates an example of an electronic device.

FIG. 29 illustrates an example of an electronic device.

FIG. 30 illustrates an example of an electronic device.

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Claims (22)

[Claims] A first wiring on the insulating surface; a first interlayer insulating film covering the first wiring; a second interlayer insulating film in contact with a part of the first interlayer insulating film; A second wiring formed on the interlayer insulating film and the second interlayer insulating film, and in a region where the first wiring and the second wiring overlap, the first interlayer insulating film and the second interlayer insulating film are provided. A semiconductor device, wherein a film and a film are stacked. 2. The semiconductor device according to claim 1, wherein an etching rate of said first interlayer insulating film is lower than an etching rate of said second interlayer insulating film. 3. The semiconductor device according to claim 1, wherein a selectivity of an etching rate of the first interlayer insulating film to the second interlayer insulating film is 1.5 or more. 4. The semiconductor device according to claim 1, wherein the first interlayer insulating film has a thickness of 50 to 300 nm. 5. The semiconductor device according to claim 1, wherein said second interlayer insulating film has a thickness of 150 nm to 1 μm. 6. A semiconductor device including at least a TFT on an insulating surface, wherein a first interlayer insulating film, a second interlayer insulating film, and a second wiring are formed above a first wiring forming the TFT. A semiconductor device, wherein a gate insulating film, a first interlayer insulating film, and the second wiring are formed above a source region or a drain region of the TFT. 7. The semiconductor device according to claim 6, wherein a sum of a thickness of said gate insulating film and a thickness of said first interlayer insulating film is 0.1 μm or more. 8. A semiconductor device including at least a TFT on an insulating surface, wherein a second wiring is present above a first wiring forming the TFT via a first interlayer insulating film and a second interlayer insulating film. A semiconductor device. 9. The semiconductor device according to claim 8, wherein a first interlayer insulating film exists above the source region or the drain region of the TFT. 10. The semiconductor device according to claim 8, wherein said TFT is an inverted stagger type TFT. 11. The semiconductor device according to claim 6, wherein said first wiring is a gate wiring. 12. A semiconductor device including at least a pixel circuit and a driving circuit for controlling the pixel circuit on the same substrate, wherein a channel forming region of a pixel TFT forming the pixel circuit is provided via a gate insulating film. A semiconductor device formed so as to overlap with a part of a gate wiring, and part of the gate wiring overlapping with the second wiring via a plurality of insulating films having different etching rates. 13. The semiconductor device according to claim 6, wherein said second wiring is a source line or a drain line. 14. The method according to claim 12, wherein
At least part or all of the LDD region of the n-channel TFT forming the driving circuit is formed of the n-channel TFT.
A semiconductor device which is formed so as to overlap with a gate wiring of an FT, and wherein an LDD region of a pixel TFT forming the pixel circuit is formed so as not to overlap with a gate electrode of the pixel TFT. 15. An LD of an n-channel TFT according to claim 12, wherein said LD is formed of an n-channel TFT forming said drive circuit.
The D region is formed so that at least part or all thereof overlaps with the gate electrode of the n-channel TFT, and the LDD region of the pixel TFT forming the pixel circuit does not overlap with the gate electrode of the pixel TFT. A semiconductor device, wherein the storage capacitor of the pixel circuit is formed of a shielding film provided on an organic resin film, an oxide of the shielding film, and a pixel electrode. 16. A semiconductor device according to claim 1, wherein the semiconductor device is an active matrix type liquid crystal display, an active matrix type EL display or an active matrix type EC display. 17. A goggle type display using the semiconductor device according to claim 16 as a display unit. 18. A video camera, a digital camera, a projector, a car navigation system, a personal computer, or a portable information terminal using the semiconductor device according to claim 16 as a display unit. 19. A first step of forming a first wiring on an insulating surface, a second step of forming a first interlayer insulating film covering the first wiring, and a second interlayer on the first interlayer insulating film. Third to form insulating film
A step of selectively removing a part of the second interlayer insulating film; and a fifth step of forming a second wiring on the second interlayer insulating film overlapping the first wiring. A method for manufacturing a semiconductor device. 20. A method for manufacturing a semiconductor device including at least a TFT on an insulating surface, comprising: a first step of forming an active layer on the insulating surface; and a second step of forming a gate insulating film in contact with the active layer. A third step of forming a source region or a drain region by adding an n-type impurity element or a p-type impurity element to a part of the active layer, and forming a first interlayer insulating film covering a gate wiring and a gate electrode. Fourth step, a fifth step of forming a second interlayer insulating film on the first interlayer insulating film, and etching the second interlayer insulating film to form a second interlayer insulating film above the source region or the drain region. A sixth step of removing a film; a seventh step of etching the first interlayer insulating film and the gate insulating film to form a contact hole reaching the source region or the drain region; On the second interlayer insulating film overlapping with the gate electrode, the first contact with the source region or the drain region 2
An eighth step of forming a wiring. 21. A method for manufacturing a semiconductor device including at least a pixel circuit and a driving circuit for controlling the pixel circuit on the same substrate, wherein a first active layer is formed on an insulating surface.
A second step of forming a gate insulating film in contact with the active layer, a third step of forming a gate wiring and a gate electrode on the gate insulating film, and forming an n-type impurity element in a part of the active layer. A fourth step of forming an n-type impurity region or a p-type impurity region by adding a p-type impurity element, a fifth step of forming a first interlayer insulating film covering a gate wiring and a gate electrode, A sixth step of selectively forming a second interlayer insulating film on the overlapping first interlayer insulating film; and etching the first interlayer insulating film and the gate insulating film to form the n-type impurity region or the p-type impurity. A seventh step of forming a contact hole reaching a region, and an eighth step of forming a second wiring in contact with the n-type impurity region or the p-type impurity region on the second interlayer insulating film overlapping the gate electrode. To The method for manufacturing a semiconductor device which is characterized in that. 22. A method for manufacturing a semiconductor device including at least a pixel circuit and a driving circuit for controlling the pixel circuit on the same substrate, wherein a first active layer is formed on an insulating surface.
A second step of forming a gate insulating film in contact with the active layer, a third step of forming a gate wiring and a gate electrode on the gate insulating film, and forming an n-type impurity element in a part of the active layer. A fourth step of forming an n-type impurity region or a p-type impurity region by adding a p-type impurity element; a fifth step of forming a first interlayer insulating film covering a gate wiring and a gate electrode; A sixth step of etching the insulating film and the gate insulating film to form a contact hole reaching the n-type impurity region or the p-type impurity region, and selecting a second interlayer insulating film on the first interlayer insulating film Forming a second wiring in contact with the n-type impurity region or the p-type impurity region on the second interlayer insulating film overlapping the gate electrode. Features and A method for manufacturing a semiconductor device that.