JP4531194B2 - Electro-optical device and electronic apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device formed by fabricating a semiconductor element (an element using a semiconductor thin film) on a substrate and an electronic apparatus (electronic device) having the electro-optical device. The present invention relates to a liquid crystal display device or an EL display device in which a thin film transistor (hereinafter referred to as TFT) is typically formed on a substrate, and an electronic apparatus having such a display device as a display (display unit).
[0002]
[Prior art]
In recent years, a technology for forming a TFT on a substrate has greatly advanced, and application development to an active matrix display device has been advanced. In particular, a TFT using a polysilicon film has a higher field effect mobility (also referred to as mobility) than a TFT using a conventional amorphous silicon film, and thus can operate at high speed. For this reason, it is possible to control a pixel, which has been conventionally performed by a drive circuit outside the substrate, with a drive circuit formed on the same substrate as the pixel.
[0003]
Such an active matrix display device has various advantages such as a reduction in manufacturing cost, a reduction in size of the display device, an increase in yield, and a reduction in throughput by forming various circuits and elements on the same substrate. It is attracting attention as.
[0004]
However, circuits and element portions having various functions are formed on the substrate of the active matrix display device. Accordingly, when forming a circuit or element with TFTs, the performance of the TFT required for each circuit or element also differs. For example, a driving circuit such as a shift register circuit requires a TFT having a high operating speed, and a switching element in the pixel portion requires a TFT having a sufficiently low off-current value (a drain current value that flows when the TFT is in an off operation). It is done.
[0005]
In such a case, it is difficult to ensure the performance required by all circuits or elements with only the TFTs having the same structure, which is a great adverse effect on improving the performance of the active matrix display device.
[0006]
Further, when an active matrix display device is used as part of an electronic device, various circuits are required in addition to the pixels and the driver circuit. In particular, forming a memory portion for temporarily storing image information on the same substrate is important in expanding the application of an active matrix display device.
[0007]
[Problems to be solved by the invention]
In the active matrix electro-optical device having a pixel portion and a drive circuit portion on the same substrate, the present invention uses a TFT having an appropriate structure according to the performance required by the circuit or element formed by the TFT, An object is to provide a highly reliable electro-optical device.
[0008]
Specifically, it is an object of the present invention to provide an electro-optical device with high operation performance and high reliability in which a pixel portion, a driver circuit portion, and a memory portion are formed using TFTs having appropriate structures on the same substrate.
[0009]
It is another object of the present invention to improve the performance by adding a memory function to an active matrix electro-optical device and improve the image quality of the display device. It is another object of the present invention to improve the quality of electronic equipment using the electro-optical device of the present invention as a display.
[0010]
[Means for Solving the Problems]
The configuration of the present invention is as follows:
A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the gate insulating film interposed therebetween;
A memory unit having a memory transistor;
On the same insulator.
[0011]
In addition, the configuration of other inventions is as follows:
A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator.
[0012]
In addition, the configuration of other inventions is as follows:
A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The third gate insulating film covers the gate electrode of the n-channel TFT and the gate electrode of the pixel TFT.
[0013]
In addition, the configuration of other inventions is as follows:
A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The floating gate electrode, the gate electrode of the n-channel TFT, and the gate electrode of the pixel TFT are made of the same material and covered with the third gate insulating film.
[0014]
In addition, the configuration of other inventions is as follows:
A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The third gate insulating film is an oxide of a material forming the floating gate electrode.
[0015]
In addition, the configuration of other inventions is as follows:
A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The floating gate electrode, the gate electrode of the n-channel TFT, and the gate electrode of the pixel TFT are made of the same material, and the third gate insulating film is an oxide of a material forming the floating gate electrode. Features.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG. FIG. 1 shows an active matrix substrate in which a memory portion, a drive circuit portion, and a pixel portion are integrally formed on the same substrate (on the same insulating surface or on the same insulator) (TFT formation side substrate before forming a liquid crystal or EL layer) ).
[0017]
Note that the memory portion is formed of a nonvolatile memory, here, an EEPROM (Electric Erasable Programmable Read Only Memory), and FIG. 1 illustrates one memory transistor (also referred to as a memory cell transistor) formed in the memory cell. Actually, a plurality of memory cells are integrated to form a memory portion.
[0018]
It is desirable to use a highly integrated flash memory (flash EEPROM) in the present invention. Therefore, unless otherwise specified in this specification, a flash memory is treated as a nonvolatile memory. The flash memory is a non-volatile memory that erases data for each sector. However, since the source wiring of each memory transistor is shared, it is called a common source wiring in this specification.
[0019]
A CMOS circuit is shown as a specific example of forming the driver circuit portion. In practice, shift registers, level shifters, latches, buffers, and the like are formed using a CMOS circuit as a basic circuit, and these are integrated to form a drive circuit portion.
[0020]
In addition, a pixel TFT and a storage capacitor are shown as specific examples for forming the pixel portion. Actually, a pixel TFT and a storage capacitor are formed in each of a plurality of pixels arranged in a matrix.
[0021]
In FIG. 1, reference numeral 101 denotes a substrate having an insulating surface and high heat resistance, and a quartz substrate, a silicon substrate, a ceramic substrate, or a metal substrate may be used. Whatever substrate is used, an insulating surface may be formed by providing a base film (preferably an insulating film containing silicon) as necessary. Note that in this specification, the “insulating film containing silicon” specifically includes silicon, oxygen, or nitrogen such as a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film (indicated by SiOxNy) at a predetermined ratio. An insulating film.
[0022]
Then, the semiconductor elements 301 to 304 are formed on the substrate 101. Here, each of the section semiconductor elements 301 to 304 will be described with reference to FIG.
[0023]
First, the memory transistor 301 includes a source region 102, a drain region 103, an active layer including a low concentration impurity region (also referred to as an LDD region) 104 and a channel formation region 105, a first gate insulating film 106, a floating gate electrode 107, and a third gate insulation. A common source line 109 and a bit line (drain line) 110 formed through the film 11, the control gate electrode 108, and the first interlayer insulating film 12 are formed.
[0024]
The source region 102 is a region for extracting carriers (electrons) captured by the floating gate electrode 107 to the common source wiring 109, and can also be called an erase region. Note that although the LDD region 104 is provided between the channel formation region 105 in FIG. 1, it may not be formed. The drain region 103 is a region for injecting carriers into the electrically isolated floating gate electrode 107, and can be said to be a writing region. Further, the drain region 103 also functions as a read region for reading data stored in the memory transistor 301 to the bit wiring 110.
[0025]
The drain region 103 is provided so as to overlap the floating gate electrode 107 with the first gate insulating film 106 interposed therebetween. The overlapping distance may be 0.1 to 0.5 μm (preferably 0.1 to 0.2 μm), and if it overlaps more than this, the parasitic capacitance becomes too large, which is not preferable. Further, when carriers are captured by the floating gate electrode 107, the control is performed by the control gate electrode 108 provided on the floating gate electrode 107 via the third gate insulating film 11.
[0026]
As the first gate insulating film 106, it is necessary to use an insulating film (film thickness is 3 to 20 nm, preferably 5 to 10 nm) that is thin enough to allow a tunnel current (Fauranoldheim current) to flow. It is preferable to use an oxide film obtained in this manner (a silicon oxide film if the active layer is silicon). Needless to say, the first gate insulating film can be formed by a vapor phase method such as a CVD method or a sputtering method as long as the film thickness is uniform and the film quality is good.
[0027]
The third gate insulating film 11 is preferably an insulating film having a high relative dielectric constant. Although not shown in FIG. 1, an insulating film having a laminated structure of silicon oxide film / silicon nitride film / silicon oxide film is used. Used. In this case, since the silicon nitride film is included in a part of the third gate insulating film 11, it is also effective as a passivation film that prevents intrusion of movable ions and moisture from the outside with respect to the other semiconductor elements 302 to 304. Can also be obtained. It is also possible to use an oxide film obtained by oxidizing the floating gate electrode 107 (a tantalum oxide film if the floating gate electrode is a tantalum film).
[0028]
Next, an N-channel TFT 302 that forms a CMOS circuit includes an active layer including a source region 112, a drain region 113, an LDD region 114, and a channel formation region 115, a second gate insulating film 13, a gate electrode 116, a source wiring 117, A drain wiring 118 is formed. At this time, the film thickness of the second gate insulating film 13 is 50 to 150 nm (preferably 80 to 120 nm), and a film thicker than the film thickness of the first gate insulating film 106 used for the memory transistor 301 is used.
[0029]
The N-channel TFT is characterized in that an LDD region 114 is provided between the drain region 113 and the channel formation region 115, and the LDD region 114 overlaps the gate electrode 116 with the second gate insulating film 13 interposed therebetween. Is a point. Such a structure is very effective in preventing deterioration due to hot carrier injection. However, since a parasitic capacitance is formed between the LDD region and the gate electrode, it is preferable that the parasitic capacitance is not provided between the source region 112 and the channel formation region 115.
[0030]
At this time, the length of the LDD region 114 may be 0.1 to 2 μm (preferably 0.3 to 0.5 μm). If it is too long, the parasitic capacitance is increased, and if it is too short, the effect of preventing deterioration due to hot carrier injection is weakened.
[0031]
Next, a P-channel TFT 303 that forms a CMOS circuit includes an active layer including a source region 120, a drain region 121, and a channel formation region 122, a second gate insulating film 13, a gate electrode 123, a source wiring 124, and a drain wiring 118. Formed. At this time, the same insulating film as the N-channel TFT 302 is used for the second gate insulating film, and the drain wiring is common to the N-channel TFT 302.
[0032]
Next, the pixel TFT 304 forming the pixel portion includes an active layer including the source region 126, the drain region 127, the LDD regions 128a to 128d, the channel formation regions 129a and 129b, and the impurity region 130, the second gate insulating film 13, and the gate electrode. 131a, 131b, source wiring 132, and drain wiring 133 are formed.
[0033]
At this time, in the pixel TFT 304, the LDD regions 128a to 128d are preferably provided so as not to overlap the gate electrodes 131a and 131b with the second gate insulating film 13 interposed therebetween. Note that it is more preferable to provide an offset region (a region formed of a semiconductor layer having the same composition as the channel formation region to which no gate voltage is applied) between the channel formation region and the LDD region.
[0034]
The structure used for the N-channel TFT 302 described above is certainly effective as a countermeasure against hot carriers, but on the other hand, the phenomenon that the off current value (the drain current value that flows when the TFT is in the off operation) becomes large is observed. It is done. This phenomenon is not a problem in the drive circuit (except for the sampling circuit), but becomes a fatal defect in the pixel TFT. Therefore, in the present invention, the off-current value is reduced by using the pixel TFT having the structure as shown in FIG. Further, the impurity region 130 is very effective in reducing the off-current value.
[0035]
Further, a passivation film 14 common to all elements is provided on the pixel TFT, and an insulating film (second interlayer insulating film) 15 having high flatness such as a resin film is formed thereon. A pixel TFT 304 is formed on the second interlayer insulating film 15 through a shielding film 134 made of a metal film, an oxide 135 obtained by oxidizing the shielding film 134, and a contact hole formed in the second interlayer insulating film. A pixel electrode 136 connected to is formed.
[0036]
Note that reference numeral 137 denotes a pixel electrode of another adjacent pixel, and the pixel electrode 136 overlaps the shielding film 135 with the oxide 135 therebetween, thereby forming a storage capacitor 138. That is, one of the features of the structure shown in FIG. 1 is that the storage capacitor 138 can function as a light shielding film and an electric field shielding film. However, the present invention is not limited to the structure of the storage capacitor shown in FIG.
[0037]
As described above, the memory transistor 301, the N-channel TFT 302 that forms the CMOS circuit, the P-channel TFT 303 that forms the CMOS circuit, and the pixel TFT 304 have an appropriate structure according to the required performance, so that the active matrix display The operating performance and reliability of the device are greatly improved.
[0038]
In addition, the memory part can be formed on the same substrate together with the driver circuit part and the pixel part without adding a complicated process, so that the active matrix type has higher performance than the conventional active matrix type display device. A display device can be formed.
[0039]
In addition to the memory portion, the drive circuit portion, or the pixel portion, other signal processing circuits can be formed. Other signal processing circuits include a signal dividing circuit, a D / A converter, a γ correction circuit, a booster circuit, a differential amplifier circuit, and the like.
[0040]
The present invention having the above-described configuration will be described in more detail with the following examples.
[0041]
[Example 1]
An embodiment of the present invention will be described with reference to FIGS. In this embodiment, a method for simultaneously manufacturing a pixel portion, a driver circuit portion for driving the pixel portion, and a memory portion for temporarily storing signal information to the pixel portion on the same substrate will be described. Finally, an active matrix substrate having the structure shown in FIG. 1 is manufactured.
[0042]
In FIG. 2A, it is preferable to use a quartz substrate or a silicon substrate for the substrate 201. In this example, a quartz substrate was used. In addition, a substrate in which an insulating film is formed on the surface of a metal substrate may be used. In the case of the present embodiment, heat resistance that can withstand a temperature of 800 ° C. or higher is required, so any substrate that satisfies this requirement may be used.
[0043]
Then, a semiconductor film 202 having an amorphous structure with a thickness of 20 to 100 nm (preferably 40 to 80 nm) is formed on the surface of the substrate 201 on which the TFT is formed by low pressure CVD, plasma CVD, or sputtering. Form. In this embodiment, an amorphous silicon film having a thickness of 60 nm is formed. However, since there is a thermal oxidation process later, this film thickness does not necessarily become the film thickness of the active layer of the TFT.
[0044]
As the semiconductor film including an amorphous structure, there are an amorphous semiconductor film and a microcrystalline semiconductor film, and a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used. Further, it is also effective to continuously form the base film and the amorphous silicon film on the substrate without releasing to the atmosphere. By doing so, it becomes possible to prevent the contamination of the substrate surface from affecting the amorphous silicon film and to reduce the characteristic variation of the manufactured TFT.
[0045]
Next, a mask film 203 made of an insulating film containing silicon (silicon) is formed on the amorphous silicon film 202, and openings 204a and 204b are formed by patterning. This opening becomes an addition region for adding a catalytic element that promotes crystallization in the next crystallization step. (Fig. 2 (A))
[0046]
Note that as the insulating film containing silicon, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. The silicon nitride oxide film is an insulating film containing silicon, nitrogen, and oxygen in a predetermined amount, and is an insulating film represented by SiOxNy. The silicon nitride oxide film can be produced using SiH4, N2O, NH3, or the like as a source gas, and the concentration of nitrogen contained can be changed in the range of 5 to 50 atomic%.
[0047]
Further, at the same time as patterning of the mask film 203, a marker pattern serving as a reference for a subsequent patterning process is formed. When the mask film 203 is etched, the amorphous silicon film 202 is also slightly etched, but this step can be used as a marker pattern when the mask is aligned later.
[0048]
Next, a semiconductor film including a crystal structure is formed according to the technique described in Japanese Patent Laid-Open No. 10-247735. The technology described in this publication is a catalyst element (one or more selected from nickel, cobalt, germanium, tin, lead, palladium, iron, copper) that promotes crystallization when a semiconductor film including an amorphous structure is crystallized. Crystallization means using seed elements).
[0049]
Specifically, heat treatment is performed with the catalytic element held on the surface of a semiconductor film including an amorphous structure, and the semiconductor film including the amorphous structure is changed to a semiconductor film including a crystalline structure. is there. In addition, as a crystallization means, you may use the technique described in Example 1 of Unexamined-Japanese-Patent No. 7-130652. In addition, a semiconductor film including a crystalline structure includes a so-called single crystal semiconductor film and a polycrystalline semiconductor film, but the semiconductor film including a crystal structure formed in this publication has a crystal grain boundary.
[0050]
In this publication, the spin coating method is used when forming the layer containing the catalytic element on the mask film, but means for forming the thin film containing the catalytic element using a vapor phase method such as sputtering or vapor deposition. You may take.
[0051]
Further, although the amorphous silicon film depends on the amount of hydrogen contained, it is preferable to perform heat treatment at 400 to 550 ° C. for about 1 hour to crystallize after sufficiently desorbing hydrogen. In that case, the hydrogen content is preferably 5 atom% or less.
[0052]
In the crystallization step, first, a heat treatment step is performed at 400 to 500 ° C. for about 1 hour to desorb hydrogen from the film, and then 500 to 650 ° C. (preferably 550 to 600 ° C.) for 6 to 16 hours (preferably For 8-14 hours).
[0053]
In this embodiment, nickel is used as a catalyst element and heat treatment is performed at 570 ° C. for 14 hours. As a result, a semiconductor film including a crystal structure in which crystallization progresses in a direction substantially parallel to the substrate (direction indicated by an arrow) starting from the openings 204a and 204b and the macroscopic crystal growth directions are aligned (this embodiment) Then, crystalline silicon films) 205a to 205d are formed. (Fig. 2 (B))
[0054]
Next, a gettering step for removing nickel used in the crystallization step from the crystalline silicon film is performed. In this embodiment, an element belonging to Group 15 (phosphorus in this embodiment) is added using the mask film 203 formed as it is as a mask, and 1 × 10 6 is applied to the crystalline silicon film exposed at the openings 204a and 204b. ¹⁹ ~ 1x10 ²⁰ atoms / cm ^Three Phosphorus-added regions (hereinafter, referred to as gettering regions) 206a and 206b containing phosphorus at a concentration of 5 are formed. (Fig. 2 (C))
[0055]
Next, a heat treatment step of 450 to 650 ° C. (preferably 500 to 550 ° C.) and 4 to 24 hours (preferably 6 to 12 hours) is performed in a nitrogen atmosphere. By this heat treatment process, nickel in the crystalline silicon film moves in the direction of the arrow and is captured in the gettering regions 206a and 206b by the gettering action of phosphorus. That is, since nickel is removed from the crystalline silicon film, the concentration of nickel contained in the crystalline silicon films 207a to 207d after gettering is 1 × 10 ¹⁷ atms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atms / cm ^Three It can be reduced to the following.
[0056]
Next, the mask film 203 is removed, and a protective film 208 is formed on the crystalline silicon films 207a to 207d for later impurity addition. As the protective film 208, a silicon nitride oxide film or a silicon oxide film with a thickness of 100 to 200 nm (preferably 130 to 170 nm) is preferably used. This protective film 208 is meaningful in order to prevent the crystalline silicon film from being directly exposed to plasma when impurities are added and to enable fine concentration control.
[0057]
Then, resist masks 209a and 209b are formed thereon, and an impurity element imparting p-type (hereinafter referred to as a p-type impurity element) is added through the protective film 208. As the p-type impurity element, typically, an element belonging to Group 13, typically boron or gallium can be used. This step (referred to as channel doping step) is a step for controlling the threshold voltage of the TFT. Here, diborane (B ₂ H ₆ Boron is added by ion doping that is plasma-excited without mass separation. Of course, an ion implantation method for performing mass separation may be used.
[0058]
1x10 by this process ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three (Typically 5 × 10 ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three ) Impurity regions 210a to 210c containing a p-type impurity element (boron in this embodiment) are formed. In the present specification, an impurity region containing a p-type impurity element in the above concentration range (however, a region not containing phosphorus) is defined as a p-type impurity region (b). (Fig. 2 (D))
[0059]
Next, the resist masks 209a and 209b are removed, and the crystalline silicon film is patterned to form island-like semiconductor layers (hereinafter referred to as active layers) 211 to 214. The active layers 211 to 214 are formed of a crystalline silicon film having very good crystallinity by selectively adding nickel and crystallizing. Specifically, it has a crystal structure in which rod-like or columnar crystals are arranged with a specific direction. Further, after crystallization, nickel is removed or reduced by the gettering action of phosphorus, and the concentration of the catalytic element remaining in the active layers 211 to 214 is 1 × 10 ¹⁷ atms / cm ^Three Or less, preferably 1 × 10 ¹⁶ atms / cm ^Three It is as follows. (Figure 2 (E))
[0060]
The active layer 213 of the p-channel TFT is a region that does not contain the impurity element added intentionally, and the active layers 211, 212, and 214 of the n-channel TFT are p-type impurity regions (b). . In this specification, it is defined that all the active layers 211 to 214 in this state are intrinsic or substantially intrinsic. In other words, a region where an impurity element is intentionally added to such an extent that does not hinder the operation of the TFT may be considered as a substantially intrinsic region.
[0061]
Next, an insulating film containing silicon having a thickness of 10 to 100 nm is formed by plasma CVD or sputtering. In this embodiment, a silicon nitride oxide film having a thickness of 30 nm is formed. This insulating film containing silicon may be used in a stacked structure. Then, patterning is performed, and the other regions are removed except for the regions to be the driver circuit portion and the pixel portion, and the active layer 211 is exposed.
[0062]
Next, a heat treatment step at a temperature of 800 to 1150 ° C. (preferably 900 to 1000 ° C.) for 15 minutes to 8 hours (preferably 30 minutes to 2 hours) is performed in an oxidizing atmosphere (thermal oxidation step). In this embodiment, a heat treatment step is performed at 950 ° C. for 80 minutes in an atmosphere in which 3% by volume of hydrogen chloride is added to an oxygen atmosphere. Note that boron added in the step of FIG. 2D is activated during this thermal oxidation step. (Fig. 3 (A))
[0063]
Note that the oxidizing atmosphere may be either a dry oxygen atmosphere or a wet oxygen atmosphere, but a dry oxygen atmosphere is suitable for reducing crystal defects in the semiconductor layer. In this embodiment, an atmosphere in which a halogen element is included in an oxygen atmosphere is used. However, a 100% oxygen atmosphere may be used.
[0064]
A thermal oxide film (silicon oxide film) 215 having a thickness of 3 to 20 nm (preferably 5 to 10 nm) is formed on the surface of the active layer 211 exposed in this manner. This thermal oxide film 215 finally becomes a first gate insulating film formed between the channel formation region of the memory transistor and the floating gate electrode.
[0065]
At the same time, an oxidation reaction also proceeds at the interface between the insulating film 116 containing silicon and the active layers 211 to 214 therebelow. In the present invention, in consideration thereof, the thickness of the insulating film 216 to be finally formed is adjusted to be 50 to 150 nm (preferably 80 to 120 nm). This insulating film 216 containing silicon is a gate insulating film of a TFT that finally forms a drive circuit portion and a pixel portion, and is referred to as a second gate insulating film.
[0066]
In the thermal oxidation process of the present embodiment, 25 nm of the 60 nm thick active layer is oxidized, and the thickness of the active layers 211 to 214 is 45 nm. This is the thickness of the active layer of the final TFT. Further, since a thermal oxide film having a thickness of 50 nm is added to an insulating film containing silicon having a thickness of 30 nm, the film thickness of the second gate insulating film 216 is finally 110 nm.
[0067]
Next, resist masks 217a to 217c are newly formed. Then, an impurity element imparting n-type (hereinafter referred to as n-type impurity element) is added to form impurity regions 218 and 219 exhibiting n-type. Note that as the n-type impurity element, an element belonging to Group 15 typically, phosphorus or arsenic can be used. (Fig. 3 (B))
[0068]
The impurity regions 218 and 219 are impurity regions for functioning as LDD regions later in the N-channel TFT of the memory transistor and the CMOS circuit. Note that the impurity region formed here contains 2 × 10 n-type impurity elements. ¹⁶ ~ 5x10 ¹⁹ atoms / cm ^Three (Typically 5 × 10 ¹⁷ ~ 5x10 ¹⁸ atoms / cm ^Three ) Concentration. In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (b).
[0069]
Here, phosphine (PH _Three ) By mass-separated plasma-excited ion doping method with 1 × 10 phosphorus ¹⁸ atoms / cm ^Three Add at a concentration of Of course, an ion implantation method for performing mass separation may be used.
[0070]
Further, in this step, the thickness of the gate insulating film differs between the region to be the memory transistor and the region to be the n-channel TFT of the CMOS circuit. Therefore, both may be performed in two addition steps, or the concentration profile in the depth direction at the time of impurity addition is adjusted, and phosphorus is added to the region indicated by 218 and 219 at substantially the same concentration. It is desirable to do so.
[0071]
Next, the resist masks 217a to 217c are removed, and new resist masks 220a to 220c are formed. Then, n-type impurity elements are added to form n-type impurity regions 221 and 222. Note that as the n-type impurity element, an element belonging to Group 15 typically, phosphorus or arsenic can be used. (Figure 3 (C))
[0072]
The impurity regions 221 and 222 are impurity regions for functioning as a source region and a drain region later in the memory transistor. Note that the n-type impurity element is 1 × 10 5 in the impurity region formed here. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three ) Concentration. In this specification, an impurity region containing an n-type impurity element in the above concentration range is defined as an n-type impurity region (a).
[0073]
Here, phosphine (PH _Three ) 3 × 10 3 by phosphorous ion-excited without plasma separation ²⁰ atoms / cm ^Three Add at a concentration of Of course, an ion implantation method for performing mass separation may be used.
[0074]
Next, heat treatment is performed in an inert atmosphere at 600 to 1000 ° C. (preferably 700 to 800 ° C.) to activate phosphorus added in the step of FIG. In this embodiment, heat treatment at 800 ° C. for 1 hour is performed in a nitrogen atmosphere. (Fig. 3 (D))
[0075]
At the same time, it is possible to repair the crystallinity of the active layer damaged during the addition of phosphorus and the interface between the active layer and the gate insulating film. This activation step is preferably furnace annealing using an electric furnace, but may be light annealing such as lamp annealing or laser annealing, or may be used in combination with furnace annealing.
[0076]
By this step, the intrinsic region existing at the boundary between the n-type impurity region (a) 222 and the n-type impurity regions (b) 218 and 219, that is, around the n-type impurity region (a) or the n-type impurity region (b) A junction with a substantially intrinsic region (of course, including the p-type impurity region (b)) becomes clear. This means that when the TFT is later completed, the LDD region and the channel formation region can form a very good junction.
[0077]
Next, first gate electrodes 223 to 225, 226a, and 226b are formed to a thickness of 200 to 400 nm (preferably 250 to 350 nm). When the first gate electrodes 223 to 225, 226a, and 226b are formed, a first gate wiring that electrically connects the first gate electrodes is also formed at the same time. However, the first gate electrode 223 is not electrically connected to any gate electrode and functions as a floating gate electrode of the memory transistor later. (Fig. 3 (E)
[0078]
Actually, floating gate electrodes are formed in all of the plurality of memory transistors formed in the memory portion, but they are in an electrically isolated state, that is, in a floating state. By doing so, it functions as a charge storage layer.
[0079]
As a material of the gate electrodes 223 to 225, 226a, and 226b, an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), and silicon (Si), or A conductive film containing the element as a main component (typically a tantalum nitride film, a tungsten nitride film, a titanium nitride film), or an alloy film combining the elements (typically a Mo—W alloy film or a Mo—Ta alloy). Film, tungsten silicide film, or the like).
[0080]
In this embodiment, a tantalum nitride (TaN) film having a thickness of 50 nm and a tantalum (Ta) film having a thickness of 350 nm are stacked. It is also effective to form a silicon film with a thickness of about 2 to 20 nm under the first gate electrode. As a result, it is possible to improve adhesion and prevent oxidation of the gate electrode formed thereon.
[0081]
At this time, the gate electrode 223 formed in the memory transistor is formed so as to overlap a part of the n-type impurity regions (a) 221 and 222 and the n-type impurity region (b) 218 with the gate insulating film 215 interposed therebetween. Further, the gate electrode 224 formed in the N-channel TFT of the CMOS circuit is formed so as to overlap a part of the n-type impurity region (b) 219 with the gate insulating film 216 interposed therebetween. Although the gate electrodes 226a and 226b appear to be two in the cross section, they are actually electrically connected.
[0082]
Next, resist masks 227a and 227b are formed, and a p-type impurity element (boron in this embodiment) is added to form impurity regions 228 and 229 containing boron at a high concentration. In this example, diborane (B ₂ H ₆ 3 × 10 by an ion doping method (which may of course be an ion implantation method). ²⁰ ~ 3x10 ^{twenty one} atoms / cm ^Three (Typically 5 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three ) Add boron at a concentration. In this specification, an impurity region containing a p-type impurity element in the above concentration range is defined as a p-type impurity region (a). (Fig. 4 (A))
[0083]
Note that before adding the p-type impurity element, the active layer may be exposed by etching the gate insulating film using the resist masks 227a and 227b and the gate electrode 225 as masks. By doing so, the acceleration voltage and the dose can be reduced, and the throughput of the process can be increased.
[0084]
Next, the resist masks 227a and 227b are removed, and resist masks 230a to 230d are formed. Then, an n-type impurity element (phosphorus in this embodiment) is added to form impurity regions 231 to 235 containing phosphorus at a high concentration. This step may be performed in the same manner as the step of FIG. 3C, and the concentration of phosphorus to be added is 1 × 10. ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ^{twenty one} atoms / cm ^Three ). Therefore, the impurity regions 231 to 235 may be called n-type impurity regions (a). (Fig. 4 (B))
[0085]
In addition, the region where the impurity regions 231 to 235 are formed already contains phosphorus or boron added in the previous step. However, since phosphorus is added at a sufficiently high concentration, it was added in the previous step. Don't worry about the effects of phosphorus or boron.
[0086]
Note that before adding the n-type impurity element, the active layer may be exposed by etching the gate insulating film using the resist masks 230a to 230d and the gate electrode 224 as a mask. By doing so, the acceleration voltage and the dose can be reduced, and the throughput of the process can be increased.
[0087]
Next, the resist masks 230a to 230d are removed, and an n-type impurity element (phosphorus in this embodiment) is added in a self-aligning manner using the gate electrodes 223 to 225, 226a and 226b as masks. The impurity regions 236 to 239 thus formed have a concentration of 1/2 to 1/10 (typically 1/3 to 1/4) of the n-type impurity region (b) (however, the above-described channel doping step) Concentration 5-10 times higher than the boron concentration added, typically 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three , Typically 3x10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three )) So that phosphorus is added. Note that in this specification, an impurity region containing an n-type impurity element in the above concentration range (however, excluding a p-type impurity region) is defined as an n-type impurity region (c). (Fig. 4 (C))
[0088]
In this step, all impurity regions except for the portion hidden by the gate electrode are also 1 × 10 6. ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three However, since the concentration is very low, the function of each impurity region is not affected. In addition, the n-type impurity regions (b) 236 to 239 are already 1 × 10 3 in the channel doping process. ¹⁵ ~ 1x10 ¹⁸ atoms / cm ^Three In this step, phosphorus is added at a concentration 5 to 10 times that of boron contained in the p-type impurity region (b). In this case as well, boron is added to the n-type impurity region ( It may be considered that the function of b) is not affected.
[0089]
Next, a heat treatment step was performed to activate the n-type or p-type impurity element added at each concentration. This step can be performed by any one of furnace annealing, laser annealing, lamp annealing, or a combination thereof. In the case of performing the furnace annealing method, it may be performed at 500 to 800 ° C., preferably 550 to 600 ° C. in an inert atmosphere. In this embodiment, heat treatment is performed at 550 ° C. for 4 hours to activate the impurity element. (Fig. 4 (D))
[0090]
In this embodiment, a laminated film made of a tantalum nitride film and a tantalum film is used as the gate electrode material. However, the tantalum film is very vulnerable to oxidation. Therefore, this activation process needs to be performed in an inert atmosphere containing as little oxygen as possible. Specifically, an inert atmosphere in which oxygen is 1 ppm or less (preferably 0.1 ppm or less) is preferable.
[0091]
In this embodiment, heat treatment is performed at 550 ° C. for 4 hours in a 100% nitrogen atmosphere. At that time, the substrate is put into the furnace at a temperature sufficiently low (100 to 200 ° C.) so that oxidation does not proceed. Heat treatment is performed after a long period (30 minutes to 1 hour) of a nitrogen purge period. When taking out the substrate, care should be taken to release the air to the atmosphere after the furnace temperature has dropped to the sufficiently low temperature.
[0092]
If the heat treatment (activation step) is performed with great care in this way, the surface of the gate electrode is slightly nitrided, but the oxidation reaction can be prevented, and there is no problem that the resistance is greatly increased.
[0093]
Next, a third gate insulating film 240 is formed to cover the first gate electrodes 223 to 225, 226a, and 226b. Note that only a portion corresponding to the first gate electrode 223 actually functions as a gate insulating film, but for the sake of convenience of description, they are not particularly distinguished.
[0094]
The third gate insulating film 240 may be formed by a known vapor phase method. In this embodiment, the third gate insulating film 240 is formed by a low pressure thermal CVD method in order to obtain a thin film with good film quality. In this embodiment, a laminated film having a three-layer structure in which a silicon nitride film is sandwiched between silicon oxide films is used as the third gate insulating film. The total film thickness may be 15 to 50 nm (preferably 20 to 40 nm). In this embodiment, a silicon oxide film (film thickness: 10 nm) / a silicon nitride film (film thickness: 20 nm) / a silicon oxide film (film thickness: 10 nm) is used. However, the present invention is not limited to this, and the coupling ratio is considered. And then decide.
[0095]
Then, the second gate electrode 241 is formed at a position overlapping the first gate electrode 223 with the third gate insulating film 240 interposed therebetween. The second gate electrode 241 functions later as a control gate electrode of the memory transistor. The film thickness may be selected in the range of 200 to 400 nm. (Fig. 5 (A))
[0096]
As the material of the second gate electrode (control gate electrode) 241, the same material as that of the first gate electrode can be used. However, since the temperature does not rise to 450 ° C. or higher in the subsequent steps, the temperature Any material may be used as long as it is a heat-resistant conductive film that can withstand heat. In particular, a metal film containing low resistance aluminum or copper is preferable.
[0097]
Next, a first interlayer insulating film 242 is formed. The first interlayer insulating film 242 may be formed using an insulating film containing silicon, specifically, a silicon nitride film, a silicon oxide film, a silicon nitride oxide film, or a stacked film including a combination thereof. The film thickness may be 400 nm to 1.5 μm. In this embodiment, a silicon oxide film having a thickness of 1 μm is formed by plasma CVD.
[0098]
Next, heat treatment is performed at 300 to 450 ° C. for 1 to 4 hours in an atmosphere containing 3 to 100% hydrogen to hydrogenate the active layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another means of hydrogenation, plasma hydrogenation (hydrogenation treatment using hydrogen excited by plasma) may be performed.
[0099]
Next, contact holes reaching the source region or the drain region of each TFT are formed, and common source wiring 243, bit wiring 244, source wirings 245 to 247, and drain wirings 248 and 249 are formed. In order to form a CMOS circuit, the drain wiring 248 is common between the N-channel TFT and the P-channel TFT. Although not shown, in this embodiment, this wiring is a laminated film having a three-layer structure in which a Ti film is 200 nm, an aluminum film containing Ti is 500 nm, and a TiN film 100 nm is continuously formed by sputtering. (Fig. 5 (B))
[0100]
Further, an insulating film containing silicon is formed to a thickness of 50 to 500 nm (typically 200 to 300 nm) as a protective film (also referred to as a passivation film) 250 that protects the TFT from external contamination. In this embodiment, a silicon nitride oxide film having a thickness of 300 nm is used, and H is formed prior to the formation of the passivation film. ₂ , NH _Three A film is formed after plasma treatment is performed using a gas containing hydrogen.
[0101]
Hydrogen excited by plasma by this pretreatment is supplied into the first interlayer insulating film. By performing heat treatment (temperature of 300 to 420 ° C.) in this state, the film quality of the passivation film 250 is improved, and hydrogen added to the first interlayer insulating film diffuses to the lower layer side, so that it is effective. The active layer can be hydrogenated.
[0102]
After this heat treatment step, an opening (not shown) may be formed in the passivation film 250 at a position where a contact hole for connecting the pixel electrode and the drain wiring is formed later. Further, when this process is performed, if the passivation film in the image display area in the pixel is removed, the transmitted light amount increases in the transmissive liquid crystal display device, and a bright image is obtained.
[0103]
Next, a second interlayer insulating film 251 made of an organic resin is formed to a thickness of about 1 μm. As the organic resin, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. Advantages of using the organic resin film are that the film forming method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above, organic SiO compounds, and the like can also be used. Here, after applying to the substrate, a thermal polymerization type polyimide is used and baked at 300 ° C.
[0104]
Next, a shielding film 252 is formed on the second interlayer insulating film 251 in a region to be a pixel portion. In the present specification, the term “shielding film” is used to mean that light and electromagnetic waves are shielded. The shielding film 252 is formed of a conductive film made of an element selected from aluminum (Al), titanium (Ti), and tantalum (Ta) or a conductive film containing any one of the elements as a main component and has a thickness of 100 to 300 nm. In this embodiment, an aluminum film containing 1 wt% titanium is formed to a thickness of 125 nm.
[0105]
If an insulating film such as a silicon oxide film is formed on the second interlayer insulating film 251 in a thickness of 5 to 50 nm, the adhesion of the shielding film formed thereon can be improved. This effect can also be obtained by using a conductive film such as a titanium nitride film. Further, CF is formed on the surface of the second interlayer insulating film 251 formed of an organic resin. _Four When plasma treatment using gas is performed, the adhesion of the shielding film formed on the film can be improved by surface modification.
[0106]
Further, it is possible to form not only the shielding film but also other connection wirings by using the aluminum film containing titanium. For example, it is possible to form a connection wiring that connects circuits in the drive circuit. In this case, however, it is necessary to form a contact hole in the second interlayer insulating film in advance before forming a material for forming the shielding film or the connection wiring.
[0107]
Next, an oxide (anodic oxide) 253 having a thickness of 20 to 100 nm (preferably 30 to 50 nm) is formed on the surface of the shielding film 252 by an anodic oxidation method or a plasma oxidation method (an anodic oxidation method in this embodiment). To do. In this embodiment, since a film containing aluminum as a main component is used as the shielding film 252, an aluminum oxide film (alumina film) is formed as the oxide 253.
[0108]
In this anodizing treatment, an ethylene glycol tartrate solution is first prepared. This is a solution of 15% ammonium tartrate aqueous solution and ethylene glycol mixed at 2: 8, and ammonia water is added to this to adjust the pH to 7 ± 0.5. Then, a platinum electrode serving as a cathode is provided in the solution, the substrate on which the shielding film 252 is formed is immersed in the solution, and a constant (several mA to several tens mA) direct current is passed using the shielding film 252 as an anode.
[0109]
The voltage between the cathode and the anode in the solution changes with time according to the growth of the anodic oxide, but the voltage is increased at a step-up rate of 100 V / min with a constant current, and when the voltage reaches 45 V, anodization is performed. End the process. In this manner, the oxide 253 having a thickness of about 50 nm can be formed on the surface of the shielding film 252. As a result, the thickness of the shielding film 252 is 90 nm.
[0110]
The numerical values related to the anodic oxidation method shown here are only examples, and the optimum values can naturally vary depending on the size of the element to be manufactured.
[0111]
Here, the insulating film is provided only on the surface of the shielding film by using the anodic oxidation method, but the insulating film may be formed by a vapor phase method such as a plasma CVD method, a thermal CVD method, or a sputtering method. Also in that case, the film thickness is preferably 20 to 100 nm (preferably 30 to 50 nm). Alternatively, a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, a carbon film such as DLC, a tantalum oxide film, or an organic resin film may be used. Or you may use the laminated film which combined these.
[0112]
Next, a contact hole reaching the drain wiring 249 is formed in the second interlayer insulating film 251 and the passivation film 250, and a pixel electrode 254 is formed. Note that the pixel electrode 255 is a pixel electrode of another adjacent pixel. For the pixel electrodes 254 and 255, a transparent conductive film is used when a transmissive liquid crystal display device is used, and a metal film may be used when a reflective liquid crystal display device is used. Here, in order to obtain a transmissive liquid crystal display device, a compound film (ITO film) of indium oxide and tin oxide is formed to a thickness of 110 nm by a sputtering method.
[0113]
At this time, the pixel electrode 254 and the shielding film 252 overlap with each other through the oxide 253, thereby forming a storage capacitor (capacitance storage) 256. In this case, the shielding film 252 is desirably set to a floating state (electrically isolated state) or a fixed potential, preferably a common potential (an intermediate potential of an image signal transmitted as data).
[0114]
Thus, an active matrix substrate having a memory portion, a drive circuit portion, and a pixel portion is completed on the same substrate. The active matrix substrate shown in FIG. 5C has the same structure as the active matrix substrate described in FIG.
[0115]
In the present invention, the structure of the TFT forming each circuit or element can be optimized according to the performance required by the memory unit, the drive circuit unit, and the pixel unit, and the operation performance and reliability of the electro-optical device can be improved. Specifically, a TFT structure that emphasizes operation speed or hot carrier countermeasures is used for the driver circuit portion, and a TFT structure that emphasizes reduction of off-current value operation is used for the pixel portion. In addition, a memory transistor is formed in the memory portion while minimizing an increase in the number of processes.
[0116]
Here, the case of an active matrix liquid crystal display device will be described with reference to FIG.
[0117]
First, the memory transistor 301 uses a TFT having a two-layer gate structure having a floating gate electrode 107 and a control gate electrode 108 as a memory transistor. This memory transistor writing operation is performed by injecting hot carriers generated at the junction between the channel formation region 105 and the drain region 103 into the floating gate electrode 107. The erasing operation is performed by an FN (Fowler-Nordheim) current that flows between the floating gate electrode 107 and the source region 102.
[0118]
The LDD region 104 is a buffer region for preventing an interband tunnel current between the source region 102 and the channel formation region 105, and has an effect of improving reliability and reducing current consumption. The LDD region 104 may have a length (width) of 0.1 to 2.0 μm, typically 0.5 to 1.5 μm.
[0119]
The n-channel TFT 302 is suitable for a drive circuit such as a shift register, a level shifter, or a buffer that places importance on high-speed operation. That is, by forming the LDD region 114 overlapping the gate electrode only between the channel formation region 115 and the drain region 113, a structure in which a countermeasure against hot carriers is taken while reducing the resistance component as much as possible.
[0120]
The reason why it is sufficient to provide the LDD region only on the drain region side is that the function of the source region and the drain region is not changed and the direction of movement of carriers (electrons) is constant in the above driving circuit. However, the LDD region can also be formed with the channel formation region interposed as necessary. In other words, it can be formed between the source region and the channel formation region and between the drain region and the channel formation region. Note that the length (width) of the LDD region 114 is 0.1 to 2.0 μm, preferably 0.5 to 1.5 μm.
[0121]
In addition, the pixel TFT 304 is suitable for a pixel portion in which low off-current operation is important. That is, the low off-current operation is realized by forming the LDD regions 128a to 128d so as not to overlap the gate electrodes 131a and 131b. Further, an LDD region having an impurity concentration lower than that of the LDD region formed in the memory portion or the driver circuit portion is used, so that an off current value is further reduced. Further, the impurity region 130 greatly contributes to the reduction of the off-current value.
[0122]
Note that the length (width) of the LDD regions 128a to 128b provided in the pixel TFT 304 may be 0.5 to 3.5 μm, typically 2.0 to 2.5 μm.
[0123]
Further, in this embodiment, by using an aluminum oxide film having a high relative dielectric constant of 7 to 9 as the dielectric of the storage capacitor, it is possible to reduce the exclusive area of the storage capacitor necessary for forming a desired capacitance. it can. Furthermore, by using the shielding film formed on the pixel TFT as one electrode of the storage capacitor as in this embodiment, the aperture ratio of the image display portion of the active matrix liquid crystal display device can be improved.
[0124]
Note that the present invention is not necessarily limited to the structure of the storage capacitor shown in this embodiment. For example, the storage capacity of the structure described in Japanese Patent Application No. 9-316567, Japanese Patent Application No. 9-273444, or Japanese Patent Application No. 10-254097 by the present applicant can be used.
[0125]
[Example 2]
In this embodiment, a case where a cell assembling process is performed on the active matrix substrate (shown in FIG. 5C) formed in Embodiment 1 to manufacture an active matrix liquid crystal display device will be described with reference to FIGS. To do.
[0126]
As shown in FIG. 6, an alignment film 601 is formed on the substrate in the state of FIG. In this embodiment, a polyimide film is used as the alignment film. In addition, a counter electrode 603 made of a transparent conductive film and an alignment film 604 are formed on the counter substrate 602. Note that a color filter or a shielding film may be formed on the counter substrate as necessary.
[0127]
Next, after forming an alignment film, a rubbing process is performed to adjust the liquid crystal molecules so that they are aligned with a certain pretilt angle. Then, the active matrix substrate on which the pixel portion, the drive circuit portion are formed, and the counter substrate are bonded to each other through a sealing material, a spacer (both not shown), or the like by a known cell assembling process. Thereafter, liquid crystal 605 is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal. Thus, the active matrix type liquid crystal display device shown in FIG. 6 is completed.
[0128]
Next, the configuration of the active matrix liquid crystal display device will be described with reference to the perspective view of FIG. The liquid crystal display device of the present invention includes a pixel portion 702 formed on an active matrix substrate 701, a source wiring driving circuit (image signal transmission circuit) 703, and a gate wiring driving circuit (scanning signal transmission circuit) 704. Reference numeral 707 denotes a counter substrate provided to face the active matrix substrate.
[0129]
In the pixel portion 702, a plurality of pixels including the pixel TFT 304 illustrated in FIG. 1 are arranged in a matrix. The pixel TFT is connected to an intersection of a source wiring extended from the source wiring driving circuit 703 and a gate wiring extended from the gate wiring driving circuit 704.
[0130]
Further, an FPC (flexible printed circuit) 705 is connected to the active matrix substrate 701, and a signal including information such as an image signal and a clock signal is input to the liquid crystal display device.
[0131]
Further, a memory portion 706 in which the memory transistors 301 shown in FIG. 1 are integrated is formed on the active matrix substrate 701. The memory unit 706 may be a nonvolatile memory in which memory cells each including a selection transistor and a memory transistor are integrated, but a flash memory in which bit lines of a plurality of memory transistors are shared is more highly integrated. It is suitable for conversion.
[0132]
Example 3
In the active matrix liquid crystal display device shown in Embodiment 2, the source line driver circuit 703 typically includes a shift register, a level shifter, a buffer, and a sampling circuit (sample and hold circuit). This is an example in the case of processing an analog signal, but in the case of processing a digital signal, a latch and a D / A converter are included instead of the sampling circuit. In addition, the gate wiring driving circuit includes a shift register, a level shifter, and a buffer.
[0133]
Here, the shift register has a driving voltage of 3.5 to 16 V (typically 5 V or 10 V), and the structure indicated by 302 in FIG. 1 is suitable for the N-channel TFT used in the CMOS circuit forming the circuit. Yes. Further, although the level shifter and the buffer have a drive voltage as high as 14 to 16 V, a CMOS circuit including the N-channel TFT 302 shown in FIG. 1 is suitable like the shift register. In the case of a level shifter or a buffer, it is effective to improve the reliability of the circuit that the gate electrode has a multi-gate structure such as a double gate structure or a triple gate structure.
[0134]
However, the sampling circuit included in the source wiring driving circuit has a driving voltage of 14 to 16 V. However, since the source region and the drain region are inverted, it is necessary to reduce the off-current value. Both value measures must be taken.
[0135]
Therefore, in this embodiment, the N-channel TFT 205 having the structure shown in FIG. 8 is used as the sampling circuit. Note that although only an n-channel TFT is shown in FIG. 8, it is preferable to form a combination of an n-channel TFT and a p-channel TFT when actually forming a sampling circuit because a large current can easily flow.
[0136]
The structure of the n-channel TFT used as a sampling circuit in this embodiment is an active layer including a source region 21, a drain region 22, LDD regions 23a and 23b, and a channel formation region 24, a second gate insulating film 13, a gate electrode 25, A source wiring 26 and a drain wiring 27 are provided. Note that the source region and the drain region (or the source wiring and the drain wiring) are inverted by the operation.
[0137]
The most significant feature of the n-channel TFT 205 is that the LDD regions 23a and 23b are provided with the channel formation region 24 interposed therebetween, and the LDD region overlaps with the region overlapping the gate electrode 25 via the second gate insulating film 13. It is in the point which has the area | region which must not be.
[0138]
That is, in the LDD regions 23a and 23b, the region overlapping the gate electrode 25 reduces deterioration due to hot carrier injection, as in the LDD region 114 of the n-channel TFT 302 shown in FIG. Further, in the LDD regions 23a and 23b, the region that does not overlap with the gate electrode 25 reduces the off-current value similarly to the LDD regions 128a to 128d of the pixel TFT 304 shown in FIG.
[0139]
By using the n-channel TFT having the above structure in the sampling circuit, a switching operation with a low off-current value can be performed with little deterioration due to hot carriers. At this time, the length (width) of the LDD region overlapping with the gate electrode is 0.3 to 3.0 μm, typically 0.5 to 1.5 μm, and the length of the LDD region not overlapping with the gate electrode ( The width) may be 1.0 to 3.5 μm, typically 1.5 to 2.0 μm.
[0140]
Note that the structure of the n-channel TFT 205 shown in this embodiment can be formed without adding a special process according to the process shown in FIGS. In addition, it is effective to use the structure of this embodiment for the sampling circuit of the active matrix liquid crystal display device shown in Embodiment 2.
[0141]
Example 4
An active layer (especially a channel formation region) of a TFT manufactured according to the first embodiment is formed of a crystalline silicon film having a unique crystal structure having continuity in the crystal lattice. For details on such a crystalline silicon film, see the applications of Japanese Patent Application No. 10-044659, Japanese Patent Application No. 10-152316, Japanese Patent Application No. 10-152308 or Japanese Patent Application No. 10-152305 filed by the present applicant. Just do it. Hereinafter, an outline of the characteristics of the crystal structure experimentally investigated by the applicant will be described. This feature coincides with the feature of the semiconductor film forming the active layer of the TFT completed by this embodiment.
[0142]
The crystalline silicon film has a crystal structure in which a plurality of needle-like or rod-like crystals (hereinafter referred to as rod-like crystals) are gathered and arranged in a microscopic view. This can be easily confirmed by observation with TEM (transmission electron microscopy).
[0143]
Further, when the electron diffraction method is used, many {110} planes can be confirmed on the surface (portion forming portion) of the crystalline silicon film. This can be easily confirmed because the diffraction spots corresponding to the {110} plane appear neatly if analysis is performed with an electron diffraction photograph. It can also be confirmed that each spot has a distribution (spread) of about ± 1 ° on a concentric circle.
[0144]
When the orientation ratio is calculated using an X-ray diffraction method (strictly, an X-ray diffraction method using the θ-2θ method), the orientation ratio of the {220} plane is 0.7 or more (typically 0.85 or more). In addition, the method described in Unexamined-Japanese-Patent No. 7-321339 is used for the calculation method of orientation ratio.
[0145]
Further, when a crystal grain boundary formed by contact of individual rod-like crystals is observed by HR-TEM (high resolution transmission electron microscopy), it can be confirmed that the crystal lattice has continuity at the crystal grain boundary. This can be easily confirmed because the observed lattice fringes are continuously connected at the grain boundaries.
[0146]
Note that the continuity of the crystal lattice at the crystal grain boundary results from the fact that the crystal grain boundary is a grain boundary called a “planar grain boundary”. The definition of the planar grain boundary in this specification is “Characterization of High-Efficiency Cast-Si Solar Cell Wafers by MBIC Measurement; Ryuichi Shimokawa and Yutaka Hayashi, Japanese Journal of Applied Physics vol.27, No.5, pp.751”. -758, 1988 ”is the“ Planar boundary ”.
[0147]
According to the above paper, planar grain boundaries include twin grain boundaries, special stacking faults, and special twist grain boundaries. This planar grain boundary is characterized by being electrically inactive. That is, although it is a crystal grain boundary, it does not function as a trap that inhibits the movement of carriers, and thus can be regarded as substantially nonexistent.
[0148]
In particular, when the crystal axis (axis perpendicular to the crystal plane) is the <110> axis, the {211} twin grain boundary is also called a corresponding grain boundary of Σ3. The Σ value is a parameter that serves as a guideline indicating the degree of consistency of the corresponding grain boundary. It is known that the smaller the Σ value, the better the grain boundary. For example, in a crystal grain boundary formed between two crystal grains, if the plane orientation of both crystals is {110}, θ = 70.5 °, where θ is the angle formed by lattice fringes corresponding to the {111} plane. It is known that it becomes a corresponding grain boundary of Σ3.
[0149]
In the crystalline silicon film obtained by carrying out this example, when a crystal grain boundary formed between two crystal grains having a crystal axis <110> is observed by HR-TEM, each of adjacent crystal grains is observed. In many cases, the lattice pattern is continuous at an angle of about 70.5 °. Therefore, it can be inferred that the grain boundary is the corresponding grain boundary of Σ3, that is, the {211} twin boundary.
[0150]
Actually, when the crystalline silicon film of this example is observed in detail using TEM, most of the crystal grain boundaries (90% or more, typically 95% or more) are the corresponding grain boundaries of Σ3, typically Presumed to be {211} twin grain boundaries.
[0151]
Such a crystal structure (exactly, the structure of the crystal grain boundary) indicates that two different crystal grains are joined with extremely good consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and the trap level caused by crystal defects or the like is very difficult to create. Therefore, the semiconductor thin film having such a crystal structure can be regarded as having substantially no grain boundary.
[0152]
Furthermore, it was confirmed by TEM observation that defects (stacking faults) existing in the crystal grains were almost disappeared by the heat treatment step (corresponding to the thermal oxidation step in Example 1) at a high temperature of 800 to 1150 ° C. Has been. This is also clear from the fact that the number of stacking faults and the like is greatly reduced before and after this heat treatment step.
[0153]
The difference in the number of defects appears as a difference in spin density by electron spin resonance analysis (Electron Spin Resonance: ESR). At present, the spin density of the crystalline silicon film of this example is at least 5 × 10 ¹⁷ spins / cm ^Three The following (typically 3x10 ¹⁷ spins / cm ^Three The following): However, since this measured value is close to the detection limit of existing measuring devices, the actual spin density is expected to be even lower.
[0154]
From the above, since the crystalline silicon film manufactured according to Example 1 has extremely few defects in crystal grains and it can be considered that there is substantially no crystal grain boundary, the single crystal silicon film or the substantially single crystal silicon film You can think of it as a membrane.
[0155]
Example 5
The storage capacitor provided in each pixel of the pixel portion can be formed by setting the electrode (shielding film in the present invention) not connected to the pixel electrode to a fixed potential. In that case, it is desirable to set the shielding film to a floating state (electrically isolated state) or a common potential (an intermediate potential of an image signal sent as data).
[0156]
Therefore, in this embodiment, a connection method when the shielding film is set to a fixed potential will be described with reference to FIG. Since the basic structure is the same as that of the pixel portion described in FIG. 1, the same portions are described using the same reference numerals.
[0157]
In FIG. 9A, 304 is a pixel TFT (n-channel TFT) manufactured in the same manner as in Example 1, and 134 is a shielding film that functions as one electrode of a storage capacitor. The shielding film 901 extending to the outside of the pixel portion is connected to a current supply line 903 that applies a common potential through a contact hole 902 provided in the second interlayer insulating film 15 and the passivation film 14. Therefore, in this case, a step of etching the second interlayer insulating film 159 and the passivation film 158 to form a contact hole before forming the shielding film 901 is required. The current supply line 903 may be formed simultaneously with the source wiring or the drain wiring.
[0158]
As described above, the shielding film 134 can be held at the common potential by electrically connecting the shielding film 901 and the current supply line 903 for applying a common potential outside the pixel portion.
[0159]
Next, in FIG. 9B, 304 is a pixel TFT manufactured in the same manner as in Example 1, and 134 is a shielding film that functions as one electrode of a storage capacitor. The shielding film 904 extending to the outside of the pixel portion overlaps with the conductive film 906 and the oxide 907 in a region indicated by 905. The conductive film 906 is formed simultaneously with the pixel electrode 136, and the oxide 907 is formed simultaneously with the oxide 135.
[0160]
The conductive film 906 is connected to a current supply line 909 that applies a common potential via a contact hole 908 provided in the third interlayer insulating film 15 and the passivation film 14. At this time, a capacitor including the shielding film 904, the oxide 907, and the conductive film 906 is formed in the region 905. When the capacity of this capacitor is sufficiently large (in the case of about 10 times the total capacity of all the storage capacitors connected to all the pixels for one scan line), the shielding films 904 and 134 are formed by electrostatic coupling formed in the region 905. Can be reduced.
[0161]
In the case of employing the structure of FIG. 9B, it is preferable to employ source line inversion driving as a driving method of the active matrix liquid crystal display device. In the case of source line inversion driving, the voltage polarity applied to the pixel electrode is inverted every frame. Therefore, if the time is averaged, the amount of charge accumulated in the shielding film 134 becomes almost zero. That is, a state in which the potential fluctuation is extremely small can be maintained, so that a stable storage capacitor can be formed.
[0162]
By adopting the structure of FIG. 9B in this way, the shielding film can be held at a common potential without increasing the number of steps.
[0163]
Note that the configuration of this example can be realized by only partially changing the manufacturing process of Example 1, and the other processes may be similar to those of Example 1. Therefore, the present invention can be applied to the active matrix liquid crystal display device shown in Embodiment 2. In addition, any of the configurations shown in Embodiments 3 and 4 can be freely combined.
[0164]
Example 6
In this embodiment, a case where an active matrix substrate having a structure different from that in FIG. 1 is manufactured will be described. FIG. 10 is used for the description. Since this embodiment is an example in which a part of the structure shown in FIG. 1 is changed, the same reference numerals as those in FIG. Further, the parts that are not changed correspond to FIG.
[0165]
First, the active matrix substrate illustrated in FIG. 10A uses the oxide 31 as the third gate insulating film. The oxide 31 is an oxide film obtained by oxidizing the floating gate electrode 107, and is a tantalum oxide film in this embodiment. The oxidation method may be any one of a thermal oxidation method, an anodic oxidation method, and a plasma oxidation method, but a thermal oxidation method is preferable in order to improve the film quality. The film thickness to be formed may be 3 to 20 nm (preferably 5 to 10 nm) as in the first embodiment.
[0166]
At the same time, oxides 32, 33, 34a, and 34b are also formed on the surfaces of the gate electrodes 116, 123, 131a, and 131b of the TFTs formed in the driver circuit portion and the pixel portion. However, it is also possible to form an oxide only on the floating gate electrode of the memory transistor by masking the driver circuit portion or the pixel portion and performing the oxidation step. Of course, when the anodic oxidation method is used, it is possible to selectively form an oxide by selectively flowing a current only to the floating gate electrode.
[0167]
Further, this oxidation step is preferably performed between the step of FIG. 4B and the step of FIG. 4C in Example 1. This is because the offset regions 35a to 35d as shown in FIG. 11 are formed by performing the process of FIG. 4C with the surfaces of the gate electrodes 131a and 131b covered with the oxides 34a and 34b. is there. FIG. 11 is an enlarged cross-sectional view of a part of the pixel TFT (near the drain region) shown in FIG.
[0168]
In this case, as shown in FIG. 11, offset regions 35a to 35b exist between the channel formation regions 129a and 129b and the LDD regions 128a to 128d made of the n-type impurity region (c). The length of the offset regions 35a to 35b substantially corresponds to the film thickness of the oxides 34a and 34b (the film thickness here is strictly the film thickness of the portion formed on the side wall of the gate electrode).
[0169]
However, it goes without saying that the lengths of the offset regions 35a to 35b become shorter than the film thicknesses of the oxides 34a and 34b due to the wraparound when adding phosphorus.
[0170]
In the present invention, the length of the offset regions 35a to 35b is zero or 1 to 200 nm (preferably 20 to 100 nm, more preferably 30 to 70 nm). This length can be controlled by the thickness of the oxides 34a and 34b.
[0171]
A pixel TFT having a structure as shown in FIG. 10A can have an extremely low off-state current value. That is, when the TFT is completely turned off such that the source-drain voltage is 14V and the gate voltage is -17.5V, an off-current value of 5 pA or less (preferably 1 pA or less) can be achieved.
[0172]
The structure of FIG. 10B is similar to that of FIG. 10A, but is characterized in that the control gate electrode 36 is formed simultaneously with the source wiring 109 and the drain wiring 110. Such a structure can be realized by providing an opening also above the floating gate electrode 107 when forming a contact hole for connecting a source wiring and a source region (or a drain wiring and a drain region). .
[0173]
It should be noted that the formation of this opening is better as the etching selectivity between the first interlayer insulating film 12 and the third gate insulating film 31 is larger.
[0174]
Similarly to FIG. 10A, the pixel TFT has offset regions 35a to 35b between the channel formation regions 129a and 129b and the LDD regions 128a to 128d formed of the n-type impurity region (c). The effect has already been described in the description of FIG.
[0175]
The configuration of this embodiment can be implemented only by replacing the film formation process of the third gate insulating film 240 with the thermal oxidation process, the anodic oxidation process, or the plasma oxidation process in the first embodiment. Any of the configurations described can be freely combined.
[0176]
Example 7
In this embodiment, a case where an active matrix substrate having a structure different from that in FIG. 1 is manufactured will be described. FIG. 12 is used for the description. Since this embodiment is an example in which a part of the structure shown in FIG. 1 is changed, the same reference numerals as those in FIG. Further, the parts that are not changed correspond to FIG.
[0177]
The active matrix substrate shown in FIG. 12 uses an insulating film 1201 formed by a low pressure CVD method as the first gate insulating film. In this embodiment, SiH is used as a film forming gas. _Four Gas (flow rate 0.3 × 10 ^-6 m ^Three / S) and N ₂ O gas (flow rate 1.5 × 10 ^-Five m ^Three / S), the film formation temperature may be 800 ° C., and the film formation pressure may be 40 Pa. The film thickness may be 3 to 20 nm (preferably 5 to 10 nm) as in the first embodiment. Needless to say, after the first gate insulating film 1201 is formed, the same thermal oxidation process as that in the first embodiment may be performed.
[0178]
In the case where this embodiment is implemented, in the pixel portion, a laminated film of the second gate insulating film 13 and the first gate insulating film 1201 (including the thermal oxide film when the thermal oxidation process is performed) functions as a gate insulating film. Will do.
[0179]
In addition, since there is no particular change in the present embodiment except that the first gate insulating film 1201 is added in the first embodiment, it can be easily implemented by referring to the first embodiment. . Moreover, it is possible to implement freely combining with any structure of Example 2-6.
[0180]
Example 8
The present invention can be implemented even when glass or plastic is used as the substrate. Of course, in this case, the TFT must be formed in consideration of the heat resistance of the substrate made of glass or plastic.
[0181]
In order to form a crystalline silicon film to be an active layer, an amorphous silicon film can be crystallized by combining laser crystallization technology or solid phase growth technology (thermal crystallization technology) and laser crystallization technology. preferable. If a laser crystallization technique is used, a crystalline silicon film can be formed on a plastic substrate or plastic film.
[0182]
The first gate insulating film, the second gate insulating film, and the third gate insulating film are formed by a plasma CVD method or a sputtering method. In particular, an ECR (Electron Cyclotron Resonance) plasma CVD method or a remote plasma CVD method is preferable because a high-quality insulating film can be formed while suppressing damage to the active layer.
[0183]
In this embodiment, there is no process to be changed except for changing the film formation process of the first gate insulating film, the second gate insulating film, and the third gate insulating film in the first embodiment. If it is, it is possible to carry out easily. Moreover, it is possible to implement freely combining with any structure of Example 2-6.
[0184]
Example 9
In this embodiment, a circuit configuration of a nonvolatile memory capable of forming a memory portion in the present invention will be described. Specifically, the case where the memory portion 706 is a NOR flash memory in the liquid crystal display device (liquid crystal module) illustrated in FIG. 7 will be described with reference to FIG. Although FIG. 13 shows two sectors in which four memory transistors are connected in parallel, it is not necessary to limit to this configuration.
[0185]
In FIG. 13A, four memory transistors 42 to 45 are connected to the bit line 41 indicated by B1. The same applies to B2. Further, each of the memory transistors 42 to 45 is controlled by using word lines 47 to 50 indicated by W1 to W4 as control gate electrodes.
[0186]
In the present specification, a region of the word wiring that overlaps with the active layer of the TFT is particularly called a control gate electrode. Although not shown, there is actually a floating gate electrode under the control gate electrode.
[0187]
The NOR flash memory shown in the circuit diagram of FIG. 13A is actually represented as an element pattern as shown in FIG. 13B. Each symbol used corresponds to that in FIG.
[0188]
The configuration of the present embodiment can be implemented by freely combining with any configuration shown in the first to eighth embodiments.
[0189]
Example 10
In this embodiment, a circuit configuration of a nonvolatile memory capable of forming a memory portion in the present invention will be described. Specifically, a case where the memory portion 706 is a NAND flash memory in the liquid crystal display device (liquid crystal module) illustrated in FIG. 7 will be described with reference to FIG. Although FIG. 14 shows two sectors in which eight memory transistors are connected in series, it is not necessary to limit to this configuration.
[0190]
In FIG. 14A, two selection transistors 51 and 52 and eight memory transistors 56 to 63 are connected to the bit line 55 indicated by B1. The same applies to B2. The selection transistors 51 and 52 are controlled by selection gate wirings 53 and 54 indicated by S1 and S2, respectively, and the memory transistors 56 to 63 are respectively controlled by word wirings 64 to 71 indicated by W1 to W8 as control gate electrodes. Be controlled.
[0191]
In the present specification, a region of the word wiring that overlaps with the active layer of the TFT is particularly called a control gate electrode. Although not shown, there is actually a floating gate electrode under the control gate electrode.
[0192]
The NAND flash memory shown in the circuit diagram of FIG. 14A is actually represented as an element pattern as shown in FIG. 14B. Each symbol used corresponds to that in FIG.
[0193]
The configuration of the present embodiment can be implemented by freely combining with any configuration shown in the first to eighth embodiments. Further, the memory portion can be formed in combination with the NOR type flash memory shown in the ninth embodiment.
[0194]
Example 11
In this embodiment, a case where a γ (gamma) correction circuit is added as a signal processing circuit other than the memory unit, the drive circuit unit, or the pixel unit in the electro-optical device of the present invention will be described.
[0195]
The γ correction circuit is a circuit for performing γ correction. The γ correction is a correction for creating a linear relationship between the voltage applied to the pixel electrode and the transmitted light intensity of the liquid crystal or EL layer thereon by applying an appropriate voltage to the image signal.
[0196]
FIG. 15 is a block diagram of an active matrix substrate used in the liquid crystal display device (may be an EL display device) of this embodiment. A source wiring driving circuit 76 and a gate wiring driving circuit 77 are provided around the pixel portion 75, and a γ correction circuit 78 and a nonvolatile memory (flash memory in this embodiment) 79 are further provided. An image signal, a clock signal, a synchronization signal, or the like is sent via an FPC (flexible printed circuit) 80.
[0197]
The nonvolatile memory 79 stores (stores) correction data for applying γ correction to an image signal transmitted from a personal computer main body, a television receiving antenna, or the like. The γ correction circuit 78 is referred to the correction data. Performs γ correction on the image signal.
[0198]
Data for γ correction may be stored once before shipping the liquid crystal display device, but the correction data can be rewritten periodically. In addition, even in a liquid crystal display device produced in the same way, the optical response characteristics of the liquid crystal (such as the relationship between the transmitted light intensity and the applied voltage) may differ slightly. Also in this case, in this embodiment, different γ correction data can be stored for each liquid crystal display device, so that the same image quality can always be obtained.
[0199]
When storing correction data for γ correction in the non-volatile memory 79, it is preferable to use the means described in Japanese Patent Application No. 10-156696 by the present applicant. Further, the application regarding γ correction is also made in the same application.
[0200]
Since the correction data stored in the nonvolatile memory is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.
[0201]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-10.
[0202]
Example 12
In this embodiment, a case where a memory controller circuit is added as another signal processing circuit other than the memory unit, the drive circuit unit, or the pixel unit in the electro-optical device of the present invention will be described. The memory controller circuit here is a control circuit for controlling operations such as storing and reading image data in a nonvolatile memory.
[0203]
FIG. 16 is a block diagram of an active matrix substrate used in the liquid crystal display device (may be an EL display device) of this embodiment. A source wiring driving circuit 82 and a gate wiring driving circuit 83 are provided around the pixel portion 81, and a memory controller circuit 84 and a nonvolatile memory (flash memory in this embodiment) 85 are further provided. In addition, an image signal, a clock signal, a synchronization signal, or the like is sent via an FPC (flexible printed circuit) 86.
[0204]
The nonvolatile memory 85 stores (stores) image signals sent from a personal computer main body, a television receiving antenna or the like for each frame, and sequentially inputs the image signals to the pixel portion for display. The nonvolatile memory 85 stores image information for one frame displayed on the pixel unit 81. For example, when a 6-bit digital signal is sent as an image signal, a memory capacity corresponding to the number of pixels × 6 bits is required.
[0205]
Since the correction data stored in the nonvolatile memory is a digital signal, it is desirable to form a D / A converter or an A / D converter on the same substrate as necessary.
[0206]
As described above, with the configuration of this embodiment, the image displayed on the pixel portion 81 is always stored in the nonvolatile memory 85, and operations such as temporary suspension of the image can be easily performed. That is, the image signal stored in the non-volatile memory 85 is always sent to the pixel unit 81 by the memory controller circuit 84, so that the television broadcast can be freely paused without recording on a video deck or the like. Become.
[0207]
In this embodiment, an example of storing one frame is shown. However, if the memory capacity of the non-volatile memory 85 can be increased to the extent that image information such as several hundred frames or thousands of frames can be stored. For example, it is possible to reproduce (replay) an image several seconds or several minutes ago, in addition to pausing.
[0208]
In addition, the structure of a present Example can be implemented in combination freely with any structure of Examples 1-10.
[0209]
Example 13
In the manufacturing process example shown in Embodiment 1, it is assumed that the n-type impurity region (b) is formed in advance before forming the gate electrode of the n-channel TFT. The p-type impurity region (a) and the n-type impurity region (c) are both formed in a self-aligned manner.
[0210]
However, in order to obtain the effect of the present invention, the final structure may be a structure as shown in FIG. 5C, and the process reaching the final structure is not limited thereto. Therefore, the practitioner may appropriately change the formation order of the impurity regions. In some cases, the p-type impurity region (a) and the n-type impurity region (c) can be formed using a resist mask. That is, as shown in FIG. 5C, as long as different structure TFTs are formed depending on each circuit, any combination of process orders may be employed.
[0211]
Example 14
The present invention can also be used when an interlayer insulating film is formed on a conventional MOSFET and a TFT is formed thereon. That is, it is possible to realize a three-dimensional semiconductor device.
[0212]
Alternatively, an SOI substrate such as SIMOX, Smart-Cut (registered trademark of SOITEC) or ELTRAN (registered trademark of Canon Inc.) can be used as the substrate, and a single crystal semiconductor thin film can be used as the active layer.
[0213]
In addition, the structure of a present Example can be freely combined with any structure of Examples 1-13.
[0214]
Example 15
The liquid crystal display device manufactured according to the present invention can use various liquid crystal materials. As such materials, TN liquid crystal, PDLC (polymer dispersed liquid crystal), FLC (ferroelectric liquid crystal), AFLC (antiferroelectric liquid crystal), or a mixture of FLC and AFLC (antiferroelectric mixed liquid crystal). Can be mentioned.
[0215]
For example, `` H.Furue et al.; Characteristics and Drivng Scheme of Polymer-Stabilized Monostable FLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-Scale Capability, SID, 1998 '', `` T.Yoshida et al.; A Full- Color Thresholdless Antiferroelectric LCD Exhibiting Wide Viewing Angle with Fast Response Time, 841, SID97DIGEST, 1997 '', `` S.Inui et al.; Thresholdless antiferroelectricity in liquid crystals and its application to displays, 671-673, J.Mater.Chem.6 (4), 1996 "or the material disclosed in US Pat. No. 5,594,569 can be used.
[0216]
In particular, a threshold-less antiferroelectric mixed liquid crystal (Thresholdless Antiferroelectric LCD: abbreviated as TL-AFLC) that exhibits electro-optic response characteristics in which transmittance continuously changes with respect to an electric field is V-shaped (or U-shaped). Some have shown electro-optic response characteristics, and a drive voltage of about ± 2.5 V (cell thickness of about 1 μm to 2 μm) has been found. For this reason, the power supply voltage for the pixel circuit may be about 5 to 8 V, which suggests the possibility of operating the control circuit and the pixel circuit with the same power supply voltage. That is, the power consumption of the entire liquid crystal display device can be reduced.
[0217]
Further, the ferroelectric liquid crystal and the antiferroelectric liquid crystal have an advantage that the response speed is faster than that of the TN liquid crystal. Since the TFT as used in the present invention can realize a TFT having a very high operation speed, a liquid crystal display device having a high image response speed that makes full use of the response speed of a ferroelectric liquid crystal or an anti-ferroelectric liquid crystal. Can be realized.
[0218]
In general, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization, and the dielectric constant of the liquid crystal itself is high. For this reason, when a thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a relatively large storage capacitor is required for the pixel. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization. In this sense, the storage capacitor shown in FIG. 1 of the first embodiment is preferable because a large capacitor can be stored in a small area.
[0219]
Needless to say, it is effective to use the liquid crystal display device of this embodiment as a display for an electronic device such as a personal computer.
[0220]
Moreover, the structure of a present Example can be freely combined with any structure of Examples 1-14.
[0221]
Example 16
The present invention can also be applied to an active matrix EL (electroluminescence) display (also referred to as an EL display device). An example is shown in FIG.
[0222]
FIG. 17 is a circuit diagram of the active matrix EL display of this embodiment. Reference numeral 91 denotes a display area, and an X direction (source side) drive circuit 92 and a Y direction (gate side) drive circuit 93 are provided around the display area. Each pixel in the display area 91 includes a switching TFT 94, a capacitor 95, a current control TFT 96, and an EL element 97. The switching TFT 94 includes an X direction signal line (source signal line) 98a (or 98b) and a Y direction. A signal line (gate signal line) 99a (or 99b, 99c) is connected. Further, power supply lines 100 a and 100 b are connected to the current control TFT 96.
[0223]
In addition, you may combine any structure of Example 1, 4, 6-13 with respect to the active matrix type EL display of a present Example.
[0224]
Example 17
In this example, an example in which an EL (electroluminescence) display device is manufactured using the present invention will be described. 18A is a top view of the EL display device of the present invention, and FIG. 18B is a cross-sectional view thereof.
[0225]
In FIG. 18A, reference numeral 4001 denotes a substrate, 4002 denotes a pixel portion, 4003 denotes a source side driver circuit, 4004 denotes a gate side driver circuit, and each driver circuit reaches an FPC (flexible printed circuit) 4006 through a wiring 4005. Connected to an external device.
[0226]
At this time, a first sealant 4101, a cover material 4102, a filler 4103, and a second sealant 4104 are provided so as to surround the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004.
[0227]
FIG. 18B corresponds to a cross-sectional view taken along line AA ′ of FIG. 18A. A driving TFT included in the source side driver circuit 4003 on the substrate 4001 (here, an n-channel type is used here). TFTs and p-channel TFTs are shown.) 4201 and a current control TFT (TFT for controlling current to the EL element) 4202 included in the pixel portion 4002 are formed.
[0228]
In this embodiment, a TFT having the same structure as the n-channel TFT 302 and the p-channel TFT 303 in FIG. 1 is used for the driving TFT 4201, and a TFT having the same structure as the p-channel TFT 303 in FIG. It is done. Further, a memory portion is formed over the same substrate, and a TFT having the same structure as that of the memory transistor 301 in FIG. 1 is used. Further, the pixel portion 4002 is provided with a storage capacitor (not shown) connected to the gate of the current control TFT 4202.
[0229]
An interlayer insulating film (planarization film) 4301 made of a resin material is formed on the driving TFT 4201 and the pixel TFT 4202, and a pixel electrode (anode) 4302 electrically connected to the drain of the pixel TFT 4202 is formed thereon. As the pixel electrode 4302, a transparent conductive film having a large work function is used. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.
[0230]
An insulating film 4303 is formed over the pixel electrode 4302, and an opening is formed in the insulating film 4303 over the pixel electrode 4302. In this opening, an EL (electroluminescence) layer 4304 is formed on the pixel electrode 4302. A known organic EL material or inorganic EL material can be used for the EL layer 4304. The organic EL material includes a low molecular (monomer) material and a high molecular (polymer) material, either of which may be used.
[0231]
As a method for forming the EL layer 4304, a known vapor deposition technique or coating technique may be used. The EL layer may have a stacked structure or a single layer structure by freely combining a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, or an electron injection layer.
[0232]
Over the EL layer 4304, a cathode 4305 made of a light-shielding conductive film (typically a conductive film containing aluminum, copper, or silver as its main component or a stacked film of these with another conductive film) is formed. . In addition, it is preferable to remove moisture and oxygen present at the interface between the cathode 4305 and the EL layer 4304 as much as possible. Therefore, it is necessary to devise such that the both are continuously formed in vacuum, or the EL layer 4304 is formed in a nitrogen or rare gas atmosphere, and the cathode 4305 is formed without being exposed to oxygen or moisture. In this embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film formation apparatus.
[0233]
The cathode 4305 is electrically connected to the wiring 4005 in a region indicated by 4306. A wiring 4005 is a wiring for applying a predetermined voltage to the cathode 4305 and is electrically connected to the FPC 4006 through the anisotropic conductive film 4307.
[0234]
As described above, an EL element including the pixel electrode (anode) 4302, the EL layer 4304, and the cathode 4305 is formed. This EL element is surrounded by a first sealing material 4101 and a cover material 4102 bonded to the substrate 4001 by the first sealing material 4101, and is enclosed by a filler 4103.
[0235]
As the cover material 4102, a glass material, a metal material (typically stainless steel), a ceramic material, or a plastic material (including a plastic film) can be used. As the plastic material, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a mylar film, a polyester film, or an acrylic resin film can be used. A sheet having a structure in which an aluminum foil is sandwiched between PVF films or mylar films can also be used.
[0236]
However, when the emission direction of light from the EL element is directed toward the cover material, the cover material must be transparent. In that case, a transparent material such as a glass plate, a plastic plate, a polyester film or an acrylic film is used.
[0237]
Further, as the filler 4103, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) is used. Can be used. When a hygroscopic substance (preferably barium oxide) is provided inside the filler 4103, deterioration of the EL element can be suppressed.
[0238]
Further, the filler 4103 may contain a spacer. At this time, if the spacer is formed of barium oxide, the spacer itself can be hygroscopic. In the case where a spacer is provided, it is also effective to provide a resin film on the cathode 4305 as a buffer layer that relieves pressure from the spacer.
[0239]
The wiring 4005 is electrically connected to the FPC 4006 through the anisotropic conductive film 4307. The wiring 4005 transmits a signal transmitted to the pixel portion 4002, the source side driver circuit 4003, and the gate side driver circuit 4004 to the FPC 4006, and is electrically connected to an external device by the FPC 4006.
[0240]
In this embodiment, the second sealing material 4104 is provided so as to cover the exposed portion of the first sealing material 4101 and a part of the FPC 4006, and the EL element is thoroughly shielded from the outside air. Thus, an EL display device having the cross-sectional structure of FIG. Note that the EL display device of this embodiment may be manufactured by combining any of the configurations of Embodiments 1, 4, 6 to 13, and 16.
[0241]
Here, a more detailed cross-sectional structure of the pixel portion is shown in FIG. 19, a top structure is shown in FIG. 20A, and a circuit diagram is shown in FIG. 20B. 19, 20 </ b> A, and 20 </ b> B use the same reference numerals and may be referred to each other.
[0242]
In FIG. 19, a switching TFT 4402 provided over a substrate 4401 is formed using an n-channel TFT 304 provided in the pixel portion of FIG. Therefore, the description of the n-channel TFT 304 may be referred to for the description of the structure. A wiring indicated by 4403 is a gate wiring that electrically connects the gate electrodes 4404 a and 4404 b of the switching TFT 4402.
[0243]
Note that although a double gate structure in which two channel formation regions are formed is used in this embodiment, a single gate structure in which one channel formation region is formed or a triple gate structure in which three channel formation regions are formed may be used.
[0244]
Further, the drain wiring 4405 of the switching TFT 4402 is electrically connected to the gate electrode 4407 of the current control TFT 4406. Note that the current control TFT 4406 is formed using the p-channel TFT 303 of FIG. Therefore, the description of the structure may be referred to the description of the p-channel TFT 303. In this embodiment, a single gate structure is used, but a double gate structure or a triple gate structure may be used.
[0245]
A first passivation film 4408 is provided on the switching TFT 4402 and the current control TFT 4406, and a planarizing film 4409 made of resin is formed thereon. It is very important to flatten the step due to the TFT using the flattening film 4409. Since an EL layer to be formed later is very thin, a light emission defect may occur due to the presence of a step. Therefore, it is desirable to planarize the pixel electrode before forming the pixel electrode so that the EL layer can be formed as flat as possible.
[0246]
Reference numeral 4410 denotes a pixel electrode (EL element anode) made of a transparent conductive film, which is electrically connected to the drain wiring 4411 of the current control TFT 4406. As the pixel electrode 4410, a conductive film formed using a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used.
[0247]
An EL layer 4412 is formed over the pixel electrode 4410. Although only one pixel is shown in FIG. 19, in this embodiment, EL layers corresponding to each color of R (red), G (green), and B (blue) are separately formed. In this embodiment, a low molecular organic EL material is formed by a vapor deposition method. Specifically, a copper phthalocyanine (CuPc) film having a thickness of 20 nm is provided as a hole injection layer, and a tris-8-quinolinolato aluminum complex (Alq) having a thickness of 70 nm is formed thereon as a light emitting layer. _Three ) A laminated structure provided with a film. Alq _Three The emission color can be controlled by adding a fluorescent dye.
[0248]
However, the above example is an example of an organic EL material that can be used as an EL layer, and is not necessarily limited to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining a light-emitting layer, a charge transport layer, or a charge injection layer. For example, in this embodiment, an example in which a low molecular weight organic EL material is used as an EL layer is shown, but a high molecular weight organic EL material may be used. It is also possible to use an inorganic material such as silicon carbide for the charge transport layer or the charge injection layer. As these organic EL materials and inorganic materials, known materials can be used.
[0249]
Next, a cathode 4413 made of a light-shielding conductive film is provided over the EL layer 4412. In this embodiment, an aluminum / lithium alloy film is used as the light-shielding conductive film. Of course, a known MgAg film (magnesium and silver alloy film) may be used. As the cathode material, a conductive film made of an element belonging to Group 1 or Group 2 of the periodic table or a conductive film added with these elements may be used.
[0250]
When the cathode 4413 is formed, the EL element 4414 is completed. Note that the EL element 4414 here refers to a capacitor formed of a pixel electrode (anode) 4410, an EL layer 4412, and a cathode 4413.
[0251]
Next, the top structure of the pixel in this embodiment is described with reference to FIG. The source of the switching TFT 4402 is connected to the source wiring 4415, and the drain is connected to the drain wiring 4405. The drain wiring 4405 is electrically connected to the gate electrode 4407 of the current control TFT 4406. The source of the current control TFT 4406 is electrically connected to the current supply line 4416, and the drain is electrically connected to the drain wiring 4417. The drain wiring 4417 is electrically connected to a pixel electrode (anode) 4418 indicated by a dotted line.
[0252]
At this time, a storage capacitor is formed in the region indicated by 4419. The storage capacitor 4419 is formed between the semiconductor film 4420 electrically connected to the current supply line 4416, an insulating film (not shown) in the same layer as the gate insulating film, and the gate electrode 4407. Further, a capacitor formed by the gate electrode 4407, the same layer (not shown) as the first interlayer insulating film, and the current supply line 4416 can also be used as the storage capacitor.
[0253]
In addition, the structure of a present Example can be implemented in combination with any structure of Example 1, 4, 6-13, and 16 freely.
[0254]
Example 18
In this embodiment, an EL display device having a pixel structure different from that of Embodiment 17 will be described. FIG. 21 is used for the description. In addition, what is necessary is just to refer description of Example 17 about the part to which the code | symbol same as FIG. 19 is attached | subjected.
[0255]
In FIG. 21, a TFT having the same structure as that of the n-channel TFT 302 in FIG. Of course, the gate electrode 4502 of the current control TFT 4501 is connected to the drain wiring 4405 of the switching TFT 4402. Further, the drain wiring 4503 of the current control TFT 4501 is electrically connected to the pixel electrode 4504.
[0256]
When the voltage applied to the EL element becomes 10 V or more, deterioration due to the hot carrier effect becomes remarkable. Therefore, it is effective to use a TFT having the same structure as the n-channel TFT 302 in FIG. In addition, if the voltage applied to the EL element is 10 V or less, deterioration due to the hot carrier effect is not a serious problem. Therefore, a TFT having a structure in which the LDD region 114 is omitted from the n-channel TFT 302 may be used.
[0257]
In this embodiment, the pixel electrode 4504 functions as a cathode of the EL element and is formed using a light-shielding conductive film. Specifically, an alloy film of aluminum and lithium is used, but a conductive film made of an element belonging to Group 1 or 2 of the periodic table or a conductive film added with these elements may be used.
[0258]
An EL layer 4505 is formed over the pixel electrode 4504. Although only one pixel is shown in FIG. 21, an EL layer corresponding to G (green) is formed by an evaporation method and a coating method (preferably a spin coating method) in this embodiment. Specifically, a 20 nm thick lithium fluoride (LiF) film is provided as an electron injection layer, and a 70 nm thick PPV (polyparaphenylene vinylene) film is provided thereon as a light emitting layer.
[0259]
Next, an anode 4506 made of a transparent conductive film is provided over the EL layer 4505. In this embodiment, a conductive film made of a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide is used as the transparent conductive film.
[0260]
When the anode 4506 is formed, the EL element 4507 is completed. Note that the EL element 4507 here refers to a capacitor formed of a pixel electrode (cathode) 4504, an EL layer 4505, and an anode 4506.
[0261]
Note that the current control TFT 4501 of this embodiment forms a parasitic capacitance called a gate capacitance between the gate electrode 4502 and the LDD regions 4509a and 4509b. By adjusting the gate capacitance, a function equivalent to that of the storage capacitor 4418 shown in FIGS. 20A and 20B can be provided. In particular, when the EL display device is operated by the digital driving method, the holding capacitor can be replaced with a gate capacitor because the capacitance of the holding capacitor is smaller than that when the EL display device is operated by the analog driving method.
[0262]
In addition, the structure of a present Example can be implemented in combination with any structure of Example 1, 4, 6-13, and 16 freely.
[0263]
Example 19
In this example, examples of the pixel structure of the EL display device shown in Example 17 or Example 18 are shown in FIGS. In this embodiment, 4601 is a source wiring of the switching TFT 4602, 4603 is a gate wiring of the switching TFT 4602, 4604 is a current control TFT, 4605 is a capacitor, 4606 and 4608 are current supply lines, and 4607 is an EL element. .
[0264]
FIG. 22A illustrates an example in which the current supply line 4606 is shared between two pixels. That is, there is a feature in that the two pixels are formed so as to be symmetrical with respect to the current supply line 4606. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0265]
FIG. 22B illustrates an example in which the current supply line 4608 is provided in parallel with the gate wiring 4603. In FIG. 22B, the current supply line 4608 and the gate wiring 4603 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the current supply line 4608 and the gate wiring 4603 can share an exclusive area, so that the pixel portion can be further refined.
[0266]
22C, the current supply line 4608 is provided in parallel with the gate wiring 4603 similarly to the structure of FIG. 22B, and two pixels are symmetrical with respect to the current supply line 4608. It is characterized in that it is formed. It is also effective to provide the current supply line 4608 so as to overlap with any one of the gate wirings 4603. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0267]
Example 20
In this embodiment, an example of a pixel structure of the EL display device shown in Embodiment 17 or Embodiment 18 is shown in FIGS. In this embodiment, 4701 is a source wiring of the switching TFT 4702, 4703 is a gate wiring of the switching TFT 4702, 4704 is a current control TFT, 4705 is a capacitor (can be omitted), 4706 is a current supply line, Reference numeral 4707 denotes a power supply control TFT, 4708 denotes a power supply control gate wiring, and 4709 denotes an EL element. Refer to Japanese Patent Application No. 11-341272 for the operation of the power supply control TFT 4707.
[0268]
In this embodiment, the power supply control TFT 4707 is provided between the current control TFT 4704 and the EL element 4708. However, the current control TFT 4704 is provided between the power supply control TFT 4707 and the EL element 4708. Also good. The power supply control TFT 4707 preferably has the same structure as the current control TFT 4704 or is formed in series with the same active layer.
[0269]
FIG. 23A illustrates an example in which the current supply line 4706 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 4706. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0270]
FIG. 23B shows an example in which a current supply line 4710 is provided in parallel with the gate wiring 4703 and a power supply control gate wiring 4711 is provided in parallel with the source wiring 4701. Note that in FIG. 23B, the current supply line 4710 and the gate wiring 4703 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the current supply line 4710 and the gate wiring 4703 can share an exclusive area, so that the pixel portion can be further refined.
[0271]
Example 21
In this example, examples of the pixel structure of the EL display device shown in Example 17 or Example 18 are shown in FIGS. In this embodiment, 4801 is a source wiring of the switching TFT 4802, 4803 is a gate wiring of the switching TFT 4802, 4804 is a current control TFT, 4805 is a capacitor (can be omitted), 4806 is a current supply line, Reference numeral 4807 denotes an erasing TFT, 4808 denotes an erasing gate wiring, and 4809 denotes an EL element. For the operation of the erasing TFT 4807, refer to Japanese Patent Application No. 11-338786.
[0272]
The drain of the erasing TFT 4807 is connected to the gate of the current control TFT 4804 so that the gate voltage of the current control TFT 4804 can be forcibly changed. Note that the erasing TFT 4807 may be either an n-channel TFT or a p-channel TFT, but preferably has the same structure as the switching TFT 4802 so that the off-state current can be reduced.
[0273]
FIG. 24A illustrates an example in which the current supply line 4806 is shared between two pixels. In other words, the two pixels are formed so as to be symmetrical about the current supply line 4806. In this case, since the number of current supply lines can be reduced, the pixel portion can be further refined.
[0274]
FIG. 24B shows an example in which a current supply line 4810 is provided in parallel with the gate wiring 4803 and an erasing gate wiring 4811 is provided in parallel with the source wiring 4801. Note that in FIG. 24B, the current supply line 4810 and the gate wiring 4803 are provided so as not to overlap with each other. However, if the wirings are formed in different layers, they overlap with each other through an insulating film. It can also be provided. In this case, the current supply line 4810 and the gate wiring 4803 can share an exclusive area, so that the pixel portion can be further refined.
[0275]
[Example 22]
The EL display device of the present invention may have a structure in which any number of TFTs are provided in a pixel. In Examples 20 and 21, three TFTs are provided, but four to six TFTs may be provided. The present invention can be practiced without being limited to the pixel structure of an EL display device.
[0276]
Example 23
The electro-optical device and the semiconductor circuit of the present invention can be used as a display unit or a signal processing circuit of an electric appliance. Such electric appliances include video cameras, digital cameras, projectors, projection TVs, goggles type displays (head mounted displays), navigation systems, sound playback devices, notebook personal computers, game machines, portable information terminals (mobile computers, Mobile phones, portable game machines, electronic books, etc.), image playback devices equipped with recording media, and the like. Specific examples of these electric appliances are shown in FIGS.
[0277]
FIG. 25A illustrates a mobile phone, which includes a main body 2001, an audio output portion 2002, an audio input portion 2003, a display portion 2004, operation switches 2005, and an antenna 2006. The electro-optical device of the present invention can be used for the display portion 2004, and the semiconductor circuit of the present invention can be used for the sound output portion 2002, the sound input portion 2003, or a CPU or memory.
[0278]
FIG. 25B illustrates a video camera, which includes a main body 2101, a display portion 2102, an audio input portion 2103, operation switches 2104, a battery 2105, and an image receiving portion 2106. The electro-optical device of the present invention can be used for the display portion 2102, and the semiconductor circuit of the present invention can be used for the audio input portion 2103, CPU, memory, or the like.
[0279]
FIG. 25C illustrates a mobile computer, which includes a main body 2201, a camera unit 2202, an image receiving unit 2203, operation switches 2204, and a display unit 2205. The electro-optical device of the present invention can be used for the display portion 2205, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0280]
FIG. 25D illustrates a goggle type display which includes a main body 2301, a display portion 2302, and an arm portion 2303. The electro-optical device of the present invention can be used for the display portion 2302, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0281]
FIG. 25E shows a rear projector (projection TV), which includes a main body 2401, a light source 2402, a liquid crystal display device 2403, a polarizing beam splitter 2404, reflectors 2405 and 2406, and a screen 2407. The present invention can be used for the liquid crystal display device 2403, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0282]
FIG. 25F illustrates a front projector which includes a main body 2501, a light source 2502, a liquid crystal display device 2503, an optical system 2504, and a screen 2505. The present invention can be used for the liquid crystal display device 2503, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0283]
FIG. 26A shows a personal computer, which includes a main body 2601, a video input portion 2602, a display portion 2603, a keyboard 2604, and the like. The electro-optical device of the present invention can be used for the display portion 2603, and the semiconductor circuit of the present invention can be used for a CPU, a memory, or the like.
[0284]
FIG. 26B shows an electronic game machine (game machine), which includes a main body 2701, a recording medium 2702, a display portion 2703, and a controller 2704. Audio and video output from the electronic gaming machine are reproduced on a display including a housing 2705 and a display unit 2706. As a communication means between the controller 2704 and the main body 2701 or a communication means between the electronic gaming machine and the display, wired communication, wireless communication or optical communication can be used. In this embodiment, infrared rays are detected by the sensor units 2707 and 2708. The electro-optical device of the present invention can be used for the display portions 2703 and 2706, and the semiconductor circuit of the present invention can be used for a CPU, a memory, and the like.
[0285]
FIG. 26C shows a player (image reproduction apparatus) that uses a recording medium (hereinafter referred to as a recording medium) in which a program is recorded. A main body 2801, a display portion 2802, a speaker portion 2803, a recording medium 2804, and an operation switch 2805 are provided. Including. Note that this image reproducing apparatus uses a DVD (Digital Versatile Disc), a CD, or the like as a recording medium, and can perform music appreciation, movie appreciation, games, and the Internet. The electro-optical device of the present invention can be used for the display portion 2802, a CPU, a memory, and the like.
[0286]
FIG. 26D shows a digital camera, which includes a main body 2901, a display portion 2902, an eyepiece portion 2903, operation switches 2904, and an image receiving portion (not shown). The electro-optical device of the present invention can be used for the display portion 2902, a CPU, a memory, and the like.
[0287]
A detailed description of an optical engine that can be used in the rear projector of FIG. 25E and the front projector of FIG. 25F is shown in FIG. FIG. 27A shows an optical engine, and FIG. 27B shows a light source optical system built in the optical engine.
[0288]
The optical engine shown in FIG. 27A includes a light source optical system 3001, mirrors 3002, 3005 to 3007, dichroic mirrors 3003 and 3004, optical lenses 3008a to 3008c, a prism 3011, a liquid crystal display device 3010, and a projection optical system 3012. The projection optical system 3012 is an optical system that includes a projection lens. In this embodiment, an example of a three-plate type using three liquid crystal display devices 3010 is shown, but a single-plate type may be used. In addition, an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like may be provided in an optical path indicated by an arrow in FIG.
[0289]
27B, the light source optical system 3001 includes light sources 3013 and 3014, a combining prism 3015, collimator lenses 3016 and 3020, lens arrays 3017 and 3018, and a polarization conversion element 3019. Note that the light source optical system illustrated in FIG. 27B uses two light sources, but may be one, or may be three or more. Further, an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film, or the like may be provided somewhere in the optical path of the light source optical system.
[0290]
As described above, the application range of the present invention is extremely wide and can be applied to electric appliances in various fields. Moreover, the electric appliance of a present Example is realizable by combining the structure of Examples 1-22 as needed.
[0291]
【The invention's effect】
By using the present invention, it becomes possible to dispose TFTs with appropriate performance according to the specifications required by the circuit or element on the same substrate, which can greatly improve the operation performance and reliability of the electro-optical device. it can.
[0292]
Further, since the memory portion can be provided on the same substrate in addition to the pixel portion and the drive circuit portion, the performance of the electro-optical device can be greatly improved. Further, the electronic apparatus having the electro-optical device as described above as a display (display unit) can be widely used, and can realize high operation performance and high reliability.
[Brief description of the drawings]
FIG. 1 illustrates a configuration of a pixel portion, a driver circuit, and a memory portion.
FIGS. 2A and 2B illustrate a manufacturing process of a pixel portion, a driver circuit, and a memory portion. FIGS.
FIGS. 3A and 3B illustrate a manufacturing process of a pixel portion, a driver circuit, and a memory portion. FIGS.
4A and 4B illustrate a manufacturing process of a pixel portion, a driver circuit, and a memory portion.
FIG. 5 illustrates a manufacturing process of a pixel portion, a driver circuit, and a memory portion.
FIG. 6 is a cross-sectional structure diagram of an active matrix liquid crystal display device.
FIG. 7 is a perspective view of an active matrix liquid crystal display device.
FIG. 8 is a diagram showing a driving circuit.
FIG. 9 illustrates a pixel portion.
FIG. 10 illustrates a structure of a pixel portion, a driver circuit, and a memory portion.
FIG. 11 illustrates a pixel portion.
FIG. 12 illustrates a structure of a pixel portion, a driver circuit, and a memory portion.
FIG. 13 shows a structure of a flash memory.
FIG. 14 shows a structure of a flash memory.
FIG. 15 is a block diagram of an active matrix substrate.
FIG. 16 is a block diagram of an active matrix substrate.
FIG. 17 illustrates a structure of an active matrix EL display device.
18A and 18B are a top view and a cross-sectional view of an EL display device.
FIG 19 illustrates a cross-sectional structure of an EL display device.
FIG. 20 is a diagram showing a top structure of a pixel portion of an EL display device.
FIG 21 illustrates a cross-sectional structure of an EL display device.
FIG 22 illustrates a circuit configuration of a pixel portion of an EL display device.
FIG 23 illustrates a circuit configuration of a pixel portion of an EL display device.
FIG 24 illustrates a circuit configuration of an EL display device.
FIG 25 illustrates an example of an electric appliance.
FIG 26 illustrates an example of an electric appliance.
FIG. 27 is a diagram showing a configuration of an optical engine.

Claims (10)

A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The electro-optical device, wherein the third gate insulating film covers a gate electrode of the n-channel TFT and a gate electrode of the pixel TFT. A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The electro-optical device, wherein the floating gate electrode, the gate electrode of the n-channel TFT, and the gate electrode of the pixel TFT are made of the same material and are covered with the third gate insulating film. A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The electro-optical device, wherein the third gate insulating film is an oxide of a material forming the floating gate electrode. A drive circuit portion having an n-channel TFT formed so that part or all of the LDD region overlaps the gate electrode with the second gate insulating film interposed therebetween;
A pixel portion having a pixel TFT formed so that the LDD region does not overlap the gate electrode with the second gate insulating film interposed therebetween;
A memory unit having a memory transistor including an active layer, a first gate insulating film, a floating gate electrode, a third gate insulating film, and a control gate electrode;
On the same insulator,
The floating gate electrode, the gate electrode of the n-channel TFT, and the gate electrode of the pixel TFT are made of the same material, and the third gate insulating film is an oxide of a material forming the floating gate electrode. An electro-optical device. In any one of Claims 1 thru | or 4 ,
The active layer of the memory transistor includes a source region, a drain region, a channel formation region and an LDD region sandwiched between the source region and the drain region,
The LDD region of the n-channel TFT and the LDD region included in the active layer of the memory transistor contain an n-type impurity element at the same concentration.
2. The electro-optical device according to claim 1, wherein the LDD region of the pixel TFT includes an n-type impurity element at a lower concentration than the LDD region of the LDD region of the n-channel TFT and the active layer of the memory transistor. In claim 5,
An electro-optical device, wherein an LDD region included in an active layer of the memory transistor is provided in contact with the source region. In claim 5 or claim 6,
An electro-optical device, wherein a part of a drain region included in an active layer of the memory transistor is formed to overlap the floating gate electrode with the first gate insulating film interposed therebetween. In any one of Claims 1 thru | or 7 ,
2. The electro-optical device according to claim 1, wherein the first gate insulating film is thinner than the second gate insulating film. In any one of Claims 1 thru | or 8,
An electro-optical device, wherein an EL element is provided in the pixel portion. An electronic apparatus, comprising a display unit an electro-optical device according to any one of claims 1 to 9.

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