JPH05210364A - Liquid crystal panel display device - Google Patents

Abstract

PURPOSE:To obtain the display device which is reduce in the number of components and mount space and prevents deterioration in the frequency characteristics of a video signal and the mixture of a noise and displays a flickerless image of high picture quality by integrating a control circuit which is necessary for noninterlaced driving on the same substrate with an active matrix liquid crystal panel. CONSTITUTION:All blocks are composed of single-crystal silicon transistors(TR) formed on the SOI substrate. Image signals of a 1st and a 2nd field are written in memory circuits 104 and 105 in real time. A synchronizing signal generating circuit 110 supplies a necessary timing signal to the respective circuits according to a synchronizing signal applied from outside through a synchronizing signal input terminal 102. An image output signal 112 is inputted to an active matrix part 114. Then a shift register signal generation part 120 drives a gate line driver 115 and a source line driver 116 with a control signal for noninterlaced driving according to the synchronizing signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display liquid crystal panel.

[0002]

2. Description of the Related Art In an image display device using a liquid crystal display unit, when interlace driving similar to a normal CRT is performed, a video data rewriting frequency of the liquid crystal display unit is 30 Hz.
In the case of liquid crystal, AC drive is required.
The liquid crystal drive frequency is half of 30 Hz 1
The frequency becomes 5 Hz, and flicker occurs when liquid crystal is used for the display unit. Also, because the writing cycle for pixels becomes longer,
Due to the charge retention characteristics of the pixel, the effective value of the signal voltage applied to the liquid crystal is lowered, and the contrast ratio is lowered. Therefore, some liquid crystal driving methods by non-interlaced conversion using an image memory have been proposed.

FIG. 5 shows an example of a liquid crystal driving system using non-interlaced conversion using a conventional image memory.

The image signal input to the image input terminal 200 is written in the image memory 202. The sync signal generation circuit 204 generates a signal for controlling the memory control circuit 203 and the shift register control circuit 205 by the sync signal input to the sync signal input terminal 201. The data written in the image memory 202 is processed line by line, read at a half cycle of the write cycle, and compressed to half on the time axis. This output is the polarity inversion circuit 206
Is converted into an alternating signal for driving the liquid crystal and input to the liquid crystal panel 207 to complete the display of one line. Originally, when non-interlacing a video signal such as NTSC / PAL, it is necessary to bring the data of the next field to the scanning line next to the display line, but in the conventional example, the data of the display line is next. Display again on the line. That is, the image data for one line is time-compressed to ½ and the scanning line for two lines of the liquid crystal panel is driven. As a result, 525 non-interlaced drives were realized in one field.

[0005]

However, in the driving method by the non-interlace conversion of the above-mentioned conventional example, there is a problem of a decrease in vertical resolution and an image memory for realizing perfect non-interlace in frame units, A circuit (IC) such as a control circuit is required, and there is a problem that the space and cost required for this are large.

Further, conventionally, a driving transistor for driving an image matrix is composed of a thin film transistor having a channel of polysilicon or amorphous silicon formed on an SOI substrate and a metal wiring electrically connecting them. It was In this conventional structure, since polysilicon or amorphous silicon is used as the channel, the mobility of electrons through the channel is 0.1 to 1
It was 00 cm ² / V · S, and the variation was large. The mobility of electrons determines the switching speed and current driving force of a transistor, and a high-speed logic circuit, SRAM, and high-speed analog circuit are built with a transistor using polycrystalline silicon such as polysilicon or amorphous silicon as a channel. Things were impossible. Therefore, when the liquid crystal panel is non-interlaced converted and driven, the image memory, the control circuit, and the like are the SOs forming the liquid crystal panel.
It is impossible to assemble with a polycrystalline silicon transistor on the I substrate, and it has been configured with another chip by using a normal LSI technology using single crystal silicon. FIG. 3 shows an overall external view when the conventional non-interlaced drive is realized. Three
01 is a liquid crystal matrix panel, 302 is flexible, 303
Is a signal processing substrate, 304 to 306 are non-interlaced driving ICs, and 307 is a video input terminal. If the non-interlaced driving IC is constructed by another chip in this way, the number of parts is increased and the mounting space is widened, which is a problem particularly when applied to a viewfinder such as an 8 mm camcorder. Further, the non-interlaced driving IC 30
4 to 306 and the liquid crystal matrix panel 301 are connected by the flexible cable 302, the output of the non-interlaced driving ICs 304 to 306 has a parasitic capacitance,
This caused the following problems. (1) Due to the parasitic capacitance of the flexible cable 302 and the signal processing substrate 303, the frequency characteristics of the video signal are degraded and the resolution is reduced. (2) The control pulse for driving the shift register built in the liquid crystal matrix panel 301 is output from the non-interlace driving ICs 304 to 306. When the pulse transmits the flex 302, the parasitic capacitance is charged. A rush current for discharging flows, which becomes noise and mixes with the liquid crystal matrix panel 301 to deteriorate the image quality.

[0007]

According to the present invention, the control circuit required for non-interlaced driving is integrated on the same substrate as the active matrix liquid crystal panel, thereby reducing the number of parts and mounting space. It is possible to realize a high-quality and flicker-free liquid crystal panel display that prevents deterioration of frequency characteristics of a video signal and mixing of noise.

That is, according to the present invention, in an active matrix liquid crystal panel comprising a driving transistor for driving a pixel matrix and a shift register for controlling the driving transistor, first and second video signals are provided.
Memory means for controlling the image of the field, address control means for controlling writing and reading to and from the memory means, and liquid crystal drive signal generating means for converting the image information read from the memory means into a liquid crystal drive signal. A liquid crystal panel display device comprising: a driving transistor; and a circuit forming each of the above-mentioned means on the same substrate as a liquid crystal panel.

The present invention is characterized in that the drive circuit for the liquid crystal panel is provided on the same substrate as the liquid crystal panel.
The semiconductor active layer in which the semiconductor element forming the circuit is formed must be a semiconductor single crystal layer having extremely excellent crystallinity formed on a light transmissive substrate.

An example of a method of manufacturing a semiconductor device according to the present invention will be described below with reference to FIG.

First, a substrate as shown in FIG. 4 (a) is prepared. That is, the silicon substrate 4 having a thickness of several hundred μm
01 has an insulating layer 402 on which 100Å to 1
This structure has a single crystal silicon 403 of μm. Such a structure can be obtained by a SIMOX method or an ELTRAN method in which an epitaxial layer on a porous silicon layer is bonded to another substrate and then the porous substrate is removed by etching.

In the ELTRAN method applied to the present invention, the single crystal Si layer 403 is formed by using a porous Si substrate obtained by making the single crystal Si substrate porous.

According to observation with a transmission electron microscope, holes having an average diameter of about 600 Å are formed in this porous Si substrate, and the density thereof is less than half that of single crystal Si. Nevertheless, its single crystallinity is maintained, and it is possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, at 1000 ° C. or higher, rearrangement of internal holes occurs and the characteristics of enhanced etching are impaired. Therefore, for the epitaxial growth of the Si layer, the molecular beam epitaxial growth method, plasma CV
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid crystal growth method, etc. is suitable.

Here, a method of epitaxially growing a single crystal layer after making P-type Si porous will be described.

First, a Si single crystal substrate is prepared, and H
It is made porous by the anodization method using the F solution. The density of single crystal Si is 2.33 g / cm ³ , but the density of the porous Si substrate changes to 0.6 to 1.1 g / cm ³ by changing the HF solution concentration to 20 to 50% by weight. Can be made. This porous layer is P because of the following reasons.
It is easily formed on the mold Si substrate.

Porous Si was discovered in the research process of electrolytic polishing of semiconductors, and Si in anodization was used.
In the dissolution reaction of 1), holes are required for the anodic reaction of Si in the HF solution, and the reaction is shown as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + n
e ⁻ SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λ
e ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the numbers of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type Si in which holes are present
Can easily be said to be porous.

On the other hand, it has been reported that high-concentration N-type Si can also be made porous, so that it can be made porous regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, its density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The conditions for making single crystal Si porous by anodization are shown below. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having another crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1: 1
1 hour: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) Si is epitaxially grown on the porous Si substrate thus formed to form a single crystal Si thin film. To do.
The thickness of the single crystal Si thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, after oxidizing the surface of the above-mentioned single crystal Si thin film, a substrate which will eventually form a substrate is prepared,
The oxide film on the surface of the single crystal Si and the above substrate are bonded together. Alternatively, after the surface of a newly prepared single crystal Si substrate is oxidized, it is attached to the single crystal Si layer on the porous Si substrate. The reason for providing this oxide film between the substrate and the single crystal Si layer is that, for example, when glass is used as the substrate, the interface level generated by the underlying interface of the Si active layer is higher than that of the glass interface. This is because the level can be lowered and the characteristics of the electronic device can be significantly improved. Furthermore, only the single crystal Si thin film obtained by etching away the porous Si substrate by selective etching described below may be attached to a new substrate. The bonding is such that the surfaces are sufficiently adhered so that they cannot be easily peeled off by Van der Waals force only by bringing them into contact with each other at room temperature after cleaning, but this is further 200 to 900 ° C., preferably 600 to 900 ° C. Heat treatment is performed in a nitrogen atmosphere at the temperature of 1 to completely bond them.

Further, a Si ₃ N ₄ layer is deposited as an etching prevention film on the whole of the above-mentioned two bonded substrates, and only the Si ₃ N ₄ layer on the surface of the porous Si substrate is removed.
Apiezon wax may be used instead of the Si ₃ N ₄ layer. Then, the porous Si substrate is entirely removed by a method such as etching to obtain a semiconductor substrate having a thin film single crystal Si layer.

A selective etching method for electroless wet etching only this porous Si substrate will be described.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, a buffered material such as hydrofluoric acid, ammonium fluoride (NH ₄ F) or hydrogen fluoride (HF) is used. Hydrofluoric acid, mixed solution of hydrofluoric acid or buffered hydrofluoric acid with hydrogen peroxide solution, hydrofluoric acid with alcohol or buffered hydrofluoric acid, hydrofluoric acid with hydrogen peroxide solution and alcohol or buffer A mixed solution of dehydrofluoric acid is preferably used. Etching is performed by moistening the substrate bonded to these solutions. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with that without addition. By further changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, it is possible to instantaneously remove the bubbles of the reaction product gas due to etching from the etching surface without stirring, and it is possible to uniformly and efficiently etch the porous Si.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, still more preferably 1 to 70% by weight, based on the etching solution. The NH ₄ F concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The HF concentration is preferably set in the range of 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 10 to 80% by weight, and is set within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, and further preferably 5 to 60 ° C.

As the alcohol used in this step, in addition to ethyl alcohol, isopropyl alcohol or the like which can be practically used in the manufacturing process and which is desired to have the above-mentioned alcohol addition effect can be used.

In the semiconductor substrate thus obtained, a single crystal Si layer equivalent to that of an ordinary Si wafer is flatly and uniformly thinned to have a large area over the entire substrate.

Next, FIG. 4 obtained as described above.
After forming a silicon oxide film of 200 to 1000 Å on the substrate of (a) by thermal oxidation, 10 by a LPCVD method.
A silicon nitride film of 0 to 500Å is formed, the nitride film is patterned into a desired shape, and selective oxidation (LOCOS) of silicon is performed at 1000 ° C. for 1 to 6 hours. At this time,
The selectively-oxidized portion 404 as in (b) can reach a lower insulating layer and have a structure in which adjacent active portions are completely separated. Further, for example, by forming a channel stop layer, It is also possible to have a structure in which single crystal silicon layers are connected to the left and right. After that, a p-type active portion and an n-type active portion are formed as shown in FIG. 4B by a photolithography process and an ion implantation method.

Next, polysilicon is deposited to a thickness of 500 to 5000 Å by the LPCVD method. The polysilicon layer is M
Since it can be used not only as a material for the gate electrode of the OSFET but also as a wiring layer, it is desirable that the film thickness is large in order to reduce the resistance. Alternatively, the resistance may be lowered by stacking metal silicide (tungsten, titanium, etc.) to a thickness of about 2000Å. Next, polysilicon is patterned, and arsenic or phosphorus is ion-implanted in the NMOS part, and boron or boron fluoride is ion-implanted in the PMOS part, and then heat treatment is performed at 500 to 1000 ° C.
The structure of (c) is obtained.

In this case, both NMOS and PMOS are n
^A single drain structure in which the ⁺ layer and the p ⁺ layer are in direct contact with the channel region is shown. However, if the number of processes is increased, for example, the n ⁻ layer, the p ⁻ layer are the n ⁺ layer, and the p ⁺ layer is between the p ⁺ layer and the channel region. It is also possible to drive the transistor at a higher voltage by forming the above structure and relaxing the electric field generated in the PN junction. Experiments conducted by the present inventor have also revealed that the above-described electric field relaxation structure is effective when a power supply voltage of 10 V or higher is required.

After that, a BPSG film is formed by CVD to 3
000 to 8000 Å is deposited to form a first interlayer insulating layer 405. After opening a contact hole for electrode extraction, the aluminum electrode is sputtered to 3000
~ 8000Å form. After patterning aluminum, a silicon nitriding or silicon oxide film is deposited by plasma excitation or thermal CVD to 3000 to 10000Å
accumulate. This film becomes the second interlayer insulating film 406. At this time, it is effective to make the semiconductor surface as flat as possible by spin-on glass for the following reason. Firstly, by flattening, when multi-layer wiring is performed, a failure caused by disconnection is reduced due to a steep step in the second and subsequent wiring layers. Secondly, by flattening, the alignment treatment for aligning the liquid crystal becomes uniform, and the image quality when the matrix panel is formed is improved.

The subsequent steps are for forming the storage capacitor of the display pixel section, and do not add a function to the drive circuit section, the peripheral logic circuit and the driver circuit section. However, on the contrary, it does not hinder the operation of the MOSFET. That is, the transparent electrode 40 of the first layer
ITO (indium-tin oxide film) 500 as No. 7
2000Å, deposited in a mixed gas of argon and oxygen by a sputtering method. Next, a silicon oxide film is formed in a thickness of 300 to 3000 by a sputtering method or a CVD method.
Å Accumulate. This film is a film 40 that determines the storage capacity.
8, and the thickness is determined by the necessary gradation, the area of the storage capacitor portion, the parasitic capacitance parasitic on the pixel side electrode of the pixel transistor, and the like. For example, in order to secure 64 gradations, the storage capacitance can be 120 fF and the silicon oxide film thickness can be 2000 Å. Finally, the contact hole is opened again, and the second transparent electrode 409 I
Deposit 500 to 2000 liters of TO. After that, patterning is shown in FIG. Although not shown, the steps of depositing an alignment film, performing an alignment treatment, and filling a liquid crystal material into the display unit after that are the same as those in the conventional liquid crystal panel manufacturing method.

The semiconductor device thus manufactured is shown in FIG.
As shown in (d), since the display element part and its drive circuit, and the peripheral logic and driver circuit are formed on the same chip, the total cost including mounting can be significantly reduced. In addition, a very compact module can be constructed. If we try to realize the same circuit with the polysilicon TFT technology that has been used,
The entire chip is expected to be about 10 times larger than the present invention.

[0040]

EXAMPLES Examples according to the present invention will be described below.

(Embodiment 1) FIG. 1 is an overall block diagram of this embodiment, in which all blocks are composed of single crystal silicon transistors formed on an SOI substrate, and a frame indicating that is 119. is there.

An image signal is supplied from the image signal input terminal 101 to the demultiplexer 103.

By the demultiplexer 103, the first
And the image signals of the second field are written in the memory circuit A 104 and the memory circuit B 105 in real time, respectively.

Memory circuit A 104 and memory circuit B
The image signal stored in 105 is sent to the multiplexer 10
6 is combined into one frame by the polarity reversing circuit 11
It is sent to the image signal output terminal 112 via 1.

The write address generation circuit 108 supplies a write address signal to these memory circuits through the address switching circuit 107 during the respective write periods of the memory circuit A 104 and the memory circuit B 105.

The read address generation circuit 109 supplies read address signals to these memory circuits through the address switching circuit 107 during the respective read periods of the memory circuit A 104 and the memory circuit B 105.

The address switching circuit 107 switches the write address and the read address in correspondence with the write and read periods of the memory circuit.

The sync signal generating circuit 110 supplies a necessary timing signal to each circuit with reference to the sync signal applied from the outside through the sync signal input terminal 102.

The image output signal 112 is input to the active liquid crystal matrix section 114. Reference numeral 115 is a gate line driver, 116 is a source line driver, 117 is a pixel matrix, and 120 a shift register signal generator controls non-interlaced driving based on the synchronization signal. The gate line driver 115 and the source line driver 116. To drive. FIG. 2 is a mounting outline view of the present embodiment. Reference numeral 202 is a liquid crystal panel unit in which a liquid crystal panel unit and a control unit are integrated on the same SOI substrate, and 201 is a video input terminal. In this way, by integrating them on the same SOI substrate, the number of parts is reduced and a space advantage is brought out.

[0050]

According to the present invention, a non-interlaced driving unit for improving flicker and contrast ratio is formed on the same SOI substrate as a liquid crystal panel unit by using a thin film transistor formed of single crystal silicon. The number of points and the mounting space are reduced, and the deterioration of the frequency characteristics of the video signal and the mixing of digital noise due to the parasitic capacitance of the flexible cable that conventionally connects the non-interlaced drive section and the liquid crystal panel section are prevented. A liquid crystal display system can be assembled.

[Brief description of drawings]

FIG. 1 is an overall block diagram of an embodiment according to the present invention.

FIG. 2 is a mounting outline diagram of an embodiment according to the present invention.

FIG. 3 is an overall outline view when a conventional non-interlaced drive is realized.

FIG. 4 is a schematic view showing an example of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a block diagram showing an example of a drive system by non-interlace conversion using a conventional image memory.

[Explanation of symbols]

101 image signal input terminal 102 synchronization signal input terminal 103 demultiplexer 104 memory circuit A 105 memory circuit B 106 multiplexer 107 address switching circuit 108 write address generation circuit 109 read address generation circuit 110 synchronization signal generation circuit 111 polarity inversion circuit 112 image Signal output terminal 113 Polarity inversion control terminal 114 Active liquid crystal matrix section 115 Gate line driver 116 Source line driver 117 Pixel matrix 118 Pixel control signal 119 Frame that means integrated on the same substrate 120 Shift register signal generation circuit 201 Video input terminal 202 Liquid crystal panel section 301 Liquid crystal matrix panel 302 Flexible 303 Signal processing board 304 to 306 Non-interlaced drive IC 3 07 Video input terminal 401 Silicon substrate 402 Insulating layer 403 Single crystal silicon layer 404 SiO ₂ separation film 405 First interlayer insulating layer 406 Second interlayer insulating layer 407 First transparent electrode 408 Capacitive film 409 Second transparent electrode

Claims (1)

[Claims] 1. An active matrix liquid crystal panel comprising a driving transistor for driving a pixel matrix and a shift register for controlling the driving transistor, and a memory for controlling images of first and second fields of a video signal. Means, an address control means for controlling writing and reading with respect to the memory means, and a liquid crystal drive signal generating means for converting image information read from the memory means into a liquid crystal drive signal, A liquid crystal panel display device, comprising a transistor and circuits constituting each of the above means on the same substrate as a liquid crystal panel.