JPH05203991A - Liquid crystal panel display device - Google Patents

Abstract

PURPOSE:To increase the degree of integration and decrease the number of chips, to reduce the component cost and assembly cost, and to improve the reliability and miniaturizing the size. CONSTITUTION:The active matrix liquid crystal panel display device which has a picture element matrix 7 consisting of transistors is constituted by integrating at least a video signal processing circuit 1 which converts a video signal into a three-primary-color signal 11, a liquid crystal driving circuit block 2 which converts the primary-color signal into a liquid crystal driving signal 12, vertical and horizontal shift registers 6 and 5 for driving the transistors of the picture element matrix 7, a panel control signal generating circuit block 3 for driving the shift registers, and an active matrix panel 4 in a semiconductor layer on the same substrate 14.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal panel display device for image display.

[0002]

2. Description of the Related Art First, a matrix substrate used in a conventional image display liquid crystal panel display device and a method for manufacturing the same will be described.

A conventional matrix substrate is composed of a thin film transistor having a channel of polysilicon or amorphous silicon and a metal wiring for electrically connecting them. The detailed manufacturing method is described in, for example, Japanese Patent Application No. 61-255018.

FIG. 3 shows an overall block diagram of a conventional liquid crystal panel display device. FIG. 3 shows an apparatus for displaying TV signals on a liquid crystal panel.

In the figure, reference numeral 1 is a video signal processing circuit block, to which a composite signal 8 is inputted, and R (red), G
The signals are converted into the three primary color signals 11 of (green) and B (blue). The video signal processing circuit block 1 also generates a synchronizing signal 9 necessary for driving the panel. 3 is a panel control signal generation circuit block (panel control timing generator)
Generates various control signals. Reference numeral 2 is a liquid crystal drive block, in which the AC drive required for liquid crystal drive, gamma correction, and bright
A bias (Bright Bias) is added and a rotation operation is performed. Reference numeral 4 is an active matrix liquid crystal panel, 5 is a source line driver (hereinafter abbreviated as X driver) configured by a horizontal shift register, and 6 is a gate line driver (hereinafter abbreviated as Y driver) configured by a vertical shift register. ) And 7 are pixel matrices.

The three primary color signals 11 are gamma-corrected by the liquid crystal drive circuit block 2, and AC control is performed by the control signal 1 which is the output 13 of the panel controller 3, bright bias (Bright Bias) is added, and a rotation operation is performed. Done.

Reference numeral 12 is a liquid crystal drive signal, which is input to the active matrix liquid crystal panel 4. Reference numeral 10 is a control signal 2 for controlling the X driver 5 and the Y driver 6 in the active matrix liquid crystal panel 4.

In the case of constructing a system with such a configuration, the video signal processing circuit block 1 and the liquid crystal drive block 2 are mainly used for analog processing, so that they are integrated into a semiconductor integrated circuit of a high speed bipolar process. On the other hand, since the panel control timing generator 3 is a digital signal processing circuit, it has been integrated into a semiconductor integrated circuit by a CMOS process.

FIG. 4 is a schematic plan view showing a conventional state when the structure of FIG. 3 is mounted. In the figure, numeral 20 is a wiring for an input video signal, to which the composite signal 8 of FIG. 3 is inputted. Reference numeral 17 is a video signal processing IC corresponding to the video signal processing circuit block 1 in FIG. 3, 18 is a liquid crystal driving IC corresponding to the liquid crystal driving circuit block 2 in FIG. 3, and 19 is a pulse timing generator IC. Three
This corresponds to the panel control timing generator 3 of FIG. 16 is a board on which these ICs are mounted,
The liquid crystal drive signal is input to the active matrix liquid crystal panel 4 through the flexible cable 15.

[0010]

However, in the above-mentioned conventional structure, since polysilicon or amorphous silicon is used as the channel of the transistor, the electron mobility through the channel is 0.1 to 100 cm.
² / v. s, and the variation was large.

This electron mobility makes it extremely difficult to increase the number of pixels because it controls the switching speed of the transistor and the current driving force. That is, the speed of the transistor that drives the signal line and the current driving force are not sufficient.
The number of pixels of about 300 pixels in a line (90,000 pixels in the XY directions) is at most, and there is a problem that further integration is difficult.

Further, the peripheral driving circuits described above, such as the liquid crystal signal processing circuit and the signal generating circuit for driving the transistors, are circuits which are required to have high speed and high driving force, and polysilicon or amorphous silicon is used. In order to obtain the high speed and high driving force, it is necessary to make the transistor large in size, which is not practical in terms of chip size. Therefore, as described above, it is usually integrated and formed on the single crystal silicon of another chip.

For this reason, as shown in FIG. 4, it has a plurality of chips, and the overall structure is a large one having a matrix substrate and a few silicon chips, and a flexible cable as wiring. 1
5 and the substrate 16 are also required, which is an inefficient device in terms of component cost, assembly cost, reliability, and space utilization.

(Object of the Invention) An object of the present invention is to provide a liquid crystal panel display device in which the number of chips is reduced by increasing integration, the cost of parts and assembly are reduced, and the reliability and the size are improved. It is to be realized.

[0015]

As a means for solving the above problems, the present invention provides an active matrix liquid crystal panel display device having a pixel matrix formed of transistors, in which at least a video signal is converted into three primary color signals. A video signal processing circuit block for conversion;
A liquid crystal driving circuit block for converting a primary color signal into a liquid crystal driving signal, vertical and horizontal shift registers for driving the transistors of the pixel matrix, and a panel control signal generating circuit block for driving the shift register. The present invention provides a liquid crystal panel display device characterized in that the pixel matrix and the pixel matrix are integrated and integrally formed on a semiconductor layer on the same substrate.

At least the pixel matrix transistor, the video signal processing circuit block, and
Transistors forming the liquid crystal drive circuit block, the vertical and horizontal shift registers, and the panel control signal generation circuit block are formed in a single crystal silicon layer on the same insulating substrate. ..

In addition, the same substrate has a second substrate which has an insulating support on the side of the single crystal silicon layer of the first substrate having the single crystal silicon layer epitaxially grown on the porous silicon layer. A substrate obtained by etching and removing the porous silicon layer after bonding to a substrate,
The liquid crystal panel display device is characterized in that the semiconductor layers on the same substrate are the single crystal silicon layers.

[0018]

According to the present invention, transistors constituting a pixel matrix and various signal circuits are integrated on the same substrate as an active matrix panel, so that all the constituent blocks are formed on the same substrate and the number of parts is increased. It is possible to reduce the assembly process and build an efficient system in terms of reliability, cost and space.

The SOI substrate used in the present invention is an SOI substrate.
Since the thin film substrate is manufactured by a method for manufacturing it uniformly and at low cost, it is suitable for manufacturing the matrix substrate according to the present invention.

[0020]

FIG. 1 shows an embodiment of the present invention.

The inside of the frame 14 in FIG. 1 means that they are all integrated on the same substrate. In the figure, reference numeral 1 denotes a video signal processing circuit block to which a composite signal 8 is input, and three primary color signals 1 of R (red), G (green) and B (blue)
Convert to 1. Also, the video signal processing circuit block 1
Also generates a synchronization signal 9 necessary for driving the panel. A panel control signal generation circuit block (panel control timing generator) 3 generates various control signals. Reference numeral 2 denotes a liquid crystal drive circuit block, which performs AC drive necessary for liquid crystal drive, γ correction, addition of bright bias (BrightBias), and rotation operation. Reference numeral 4 is an active matrix liquid crystal panel, 5 is a source line driver (X driver) including a horizontal shift register, 6 is a gate line driver (Y driver) including a vertical shift register, and 7 is a pixel matrix.

The three primary color signals 11 are γ-corrected by the liquid crystal drive circuit block 2 and are AC driven by the control signal 1 which is the output 13 of the panel control timing generator, and the bright bias (Bright Bia).
s) Addition and rotation operations are performed.

Reference numeral 12 is a liquid crystal drive signal, which is input to the active matrix liquid crystal panel 4. Reference numeral 10 is a control signal 2 for controlling the X driver 5 and the Y driver 6 in the active matrix liquid crystal panel.

FIG. 2 is a schematic plan view showing a state of mounting with such a structure. As shown in the figure, the input video signal 8 is input to the integrated matrix substrate 4'in which peripheral circuits are integrally formed by the wiring 20.

Next, a method of manufacturing the integrated matrix substrate 4'of the present invention will be described.

First, an SOI substrate is prepared. The SOI substrate used in the present invention is based on a method in which a first substrate having an epitaxial layer formed on a porous silicon layer is bonded to a second substrate and then the porous silicon layer is removed by etching. Is.

This method is a method for uniformly and inexpensively producing an SOI thin film substrate, and is also suitable for producing the matrix substrate according to the present invention.

An example of a method for manufacturing an SOI substrate by the ELTRAN method used in the present invention will be described below.

FIGS. 5A to 5E are process drawings for explaining the method for manufacturing a semiconductor substrate according to the present invention, each of which is shown as a schematic sectional view in each process.

In this embodiment, P type or high concentration N
A method of epitaxially growing a non-porous single crystal Si layer after making all of the type Si substrate porous will be described.

First, a P-type Si substrate was prepared, and a porous Si substrate 50 in which the whole was made porous (FIG. 5).
(A)).

The P-type Si substrate can be made porous by the anodization method using an HF solution.
The i layer has a H content higher than the density of single crystal Si of 2.33 g / cm ^3.
By changing the F solution concentration to 50 to 20%, the density can be changed to the range of 1.1 to 0.6 g / cm ³ .

Further, in the porous Si layer, when observed by a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half.
As a result, the surface area is remarkably increased as compared with the volume, so that the chemical etching rate thereof is remarkably increased as compared with the etching rate of a normal single crystal layer.

Next, epitaxial growth is performed on the surface of the porous substrate 50 by various growth methods to obtain a single crystal S.
The i layer 53 was formed (FIG.5 (b)).

According to observation with a transmission electron microscope, pores having an average diameter of about 600 angstroms are formed in the porous Si layer, and the density thereof is less than half that of single crystal Si. Nevertheless, single crystallinity is maintained, and it is possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, 1000 ° C
In the above, rearrangement of the internal holes occurs, and the characteristics of the enhanced etching are impaired. Therefore, molecular beam epitaxial growth, plasma CV
D, low pressure CVD method, photo CVD, bias sputtering
The low temperature growth such as the liquid crystal growth method and the liquid phase growth method is suitable.

Next, as shown in FIG. 5C, the surface of the single crystal Si layer 53 on the porous Si substrate 50 is oxidized to form an oxide film 52. The oxide film 52 is formed in order to reduce the interface state of the single crystal silicon layer 53 which will be the final active layer.

Next, the insulating substrate 51 as the second substrate B is attached to the surface of the oxide film 52 of the first substrate A produced as described above to the extent that they are attracted to each other by Van der Waals force, or bonded. The bonding is performed at room temperature or by heating so that the interface does not separate due to the difference in the thermal expansion coefficient of both substrates (primary bonding). The bonding strength of this primary bonding is such a strength that the primary bonding state can be maintained without peeling off due to the steps up to the subsequent secondary bonding by complete bonding (Fig. 5 ( d)).

Next, the entire porous Si substrate 50 is immersed in a mixed solution of buffered hydrofluoric acid and alcohol to remove only the porous Si 50 by electroless wet chemical etching to remove the insulating substrates 51, 52. The thinned single crystal Si layer 53 is left on the top.

Further, a heat treatment is performed to carry out secondary bonding to more firmly and completely bond the Si / SiO ₂ layer (51/52) and the insulating substrate 51, as shown in FIG. 5 (e). The semiconductor substrate used in the present invention can be obtained.

As mentioned above, according to the method of the present invention,
Since the Si single crystal thin film and the insulating substrate are bonded together, the bonding is performed so that the thin film is aligned with the substrate, and peeling or cracking of the substrate due to the difference in thermal expansion coefficient can be prevented.

The crystallinity is S on the insulating substrates 51 and 52.
The single-crystal Si layer 53 equivalent to that of the i-wafer is flattened and uniformly thinned to have a large area over the entire wafer.

The semiconductor substrate thus obtained can be suitably used from the viewpoint of manufacturing an electronic element which is insulated and separated.

In the present embodiment, the selective etching method by electroless wet etching using a mixed solution of buffered hydrofluoric acid and alcohol as an etching solution has been described, but the etching solution is not limited to this. Absent.

Further, FIGS. 6A to 6D are process cross-sectional views for explaining the manufacturing process of the semiconductor device of this embodiment.

FIG. 10A shows a substrate obtained by the above-mentioned ELTRAN method, which has an insulating layer 52 on a silicon substrate 51 having a thickness of several hundred μm, and a single crystal of 100 Å to 1 μm on it. It has a silicon layer 53 of.

Then, a silicon oxide film having a thickness of 200 to 1000 Å is formed on the substrate shown in FIG. 4A by thermal oxidation, and then a silicon nitride film having a thickness of 100 to 500 Å is formed by the LPCVD method. Pattern in the shape of
Selective oxidation of silicon (LOCO
S). In this embodiment, the selectively oxidized portion (LOCOS: 57) as shown in FIG.
2 was reached, and the adjacent active parts were completely separated. It is also possible to form a structure in which single-crystal silicon layers are connected to the left and right by forming a channel stop layer, for example. After that, a p-type active region and an n-type active region are formed as shown in FIG.
Form a mold active part.

Next, polysilicon 55 is deposited by 500 to 5000 Å by the LPCVD method. Since the polysilicon layer 55 can be used not only as a material for the gate electrode of the MOSFET but also as a wiring layer, it is preferable that the film thickness is large in order to reduce the resistance. Also, 2000
Å About the thickness of metal silicide (tungsten,
The resistance may be lowered by laminating titanium). Next, the polysilicon 55 is patterned, arsenic or phosphorus is ion-implanted into the NMOS portion, and boron or boron fluoride is ion-implanted into the PMOS portion, and then heat treatment is performed at 500 to 1000 ° C., and the structure of FIG. To get

In the present invention, the single drain structure in which the n ⁺ layer and the p ⁺ layer are in direct contact with the channel region in both the NMOS and the PMOS has been described, but if the number of processes is increased, for example, the n ⁻ layer and the p ⁻ layer are formed. , N ⁺ layer, p ⁺ layer and the channel region to relax the electric field generated in the PN junction, the transistor can be driven at a higher voltage. In our experiments, it was found that the electric field relaxation structure as described above is effective when a power supply voltage of 10 V or higher is required.

After that, a BPSG film is formed by CVD to 3
000 to 8000 Å are deposited to form a first interlayer insulating film 57. Further, after opening a contact hole for taking out the electrode, the aluminum electrode 56 is formed to 3 by the sputtering method.
000-8000Å is formed. After patterning the aluminum, the silicon nitride film or the silicon oxide film is exposed to 3000 to 1 by a plasma excitation method or a thermal CVD method.
0000Å is deposited. This film becomes the second interlayer insulating film 58.

At this time, it is effective to make the semiconductor surface as flat as possible by spin-on glass for the following reason.

First, by flattening, when multi-layered wiring is performed, a failure such as disconnection due to steep steps in the second and subsequent wiring layers is reduced.

Secondly, by flattening, the alignment treatment for aligning the liquid crystal becomes uniform, and the image quality when the matrix panel is formed is improved.

The subsequent steps are for forming the storage capacitor of the display pixel section, and do not add a function to the drive circuit section, the peripheral logic circuit and the driver circuit section. However, on the contrary, it does not hinder the operation of the MOSFET. That is, the transparent electrode 59 of the first layer
ITO (indium-tin oxide film) as 500 to 2
000 Å, deposited by a sputtering method in a mixed gas of argon and oxygen.

Next, a silicon oxide film 61 is deposited by 300 to 3000 Å by the sputtering method or the CVD method. This film is a film that determines the capacitance of the storage capacitor, and its thickness is determined by the necessary gradation, the area of the storage capacitor portion, the parasitic capacitance parasitic on the pixel side electrode of the pixel transistor, and the like. In the present invention, in order to secure 64 gradations, the storage capacitance is 120 fF and the silicon oxide film thickness is 2000 Å.

Finally, the contact hole is opened again, and the second
ITO, which is the transparent electrode 60, is deposited to 500 to 2000 liters. After that, the patterning is shown in FIG.

Although not shown, the steps of depositing an alignment film, performing an alignment treatment, and filling a liquid crystal material into the display section are the same as those in the conventional liquid crystal panel manufacturing method.

In the present invention, the transistor in the pixel section is a PMOS, but it goes without saying that an NMOS can also realize the same function in the same step.

Further, although the present embodiment has been described by taking the color liquid crystal panel as an example, it is not limited to the color one.
Obviously, it can be applied to a monochrome liquid crystal panel.

The semiconductor device thus manufactured is
As shown in (d), the pixel matrix part, its drive circuit, and the peripheral logic circuit and driver circuit are formed on the same chip, so that the total cost including mounting can be significantly reduced. it can. Moreover, since it is formed in single crystal silicon, an extremely compact module can be constructed. If the same circuit is to be realized by the conventionally used polysilicon TFT technology, the entire chip is expected to be about 10 times larger than the present invention.

[0061]

As described above, according to the present invention, an NM having a channel of single crystal silicon is provided in the substrate.
The OSFET and the PMOSFET are integrated, and the switching speed and driving force thereof are several tens to several hundreds of times that of the conventional polysilicon or amorphous silicon channel MOSFET.

Therefore, with the high speed of this single crystal silicon, it became possible to sufficiently form the peripheral circuit on the same substrate without increasing the area of the matrix substrate so much.

Also, it is obvious that all circuit elements which can be constituted by NMOS and PMOS can be manufactured in the same process.

The SOI substrate used in the present invention is an SOI substrate.
Since the thin film substrate is manufactured by a method for manufacturing it uniformly and at low cost, it is suitable for manufacturing the matrix substrate according to the present invention.

That is, according to the present invention, by integrating various circuit blocks on the same substrate as the liquid crystal matrix panel, all the constituent blocks are formed on the same substrate,
It is possible to reduce the number of parts and the assembly process, and to build an efficient system in terms of reliability, cost and space.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a schematic plan view of a mounting example of the present invention.

FIG. 3 is a block diagram of a conventional example.

FIG. 4 is a schematic plan view of a conventional example during mounting.

FIG. 5 is a sectional view of a step of manufacturing an SOI substrate according to an embodiment of the present invention.

FIG. 6 is a sectional view showing a step of manufacturing a semiconductor device according to an embodiment of the invention.

[Explanation of symbols]

1 Video signal processing circuit block 2 Liquid crystal drive circuit block 3 Panel control signal generation circuit block (panel control timing generator) 4, 4'Active matrix liquid crystal panel 5 Source line driver (horizontal shift register) (X
Driver) 6 Gate line driver (vertical shift register) (Y
Driver) 7 Pixel matrix 8 Composite signal 9 Sync signal 10 Control signal 2 11 3 Primary color signal 12 Liquid crystal drive signal 13 Control signal 1 14 Frame that means integrated on the same board 15 Flexible cable 16 Board 17 Video signal Processing IC 18 Liquid crystal driving IC 19 Pulse timing generator IC 20 Input video signal wiring

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication H04N 5/66 102 B 9068-5C 9/30 8943-5C

Claims (3)

[Claims] 1. An active matrix liquid crystal panel display device having a pixel matrix formed of transistors, at least a video signal processing circuit block for converting a video signal into three primary color signals, and a liquid crystal driving signal for the three primary color signals. A liquid crystal drive circuit block for converting the pixel matrix, vertical and horizontal shift registers for driving the transistors of the pixel matrix, a panel control signal generating circuit block for driving the shift register, and the pixel matrix. A liquid crystal panel display device characterized by being integrally formed on a semiconductor layer on the same substrate. 2. A transistor forming at least the pixel matrix, the video signal processing circuit block, the liquid crystal drive circuit block, the vertical and horizontal shift registers, and the panel control signal generation circuit block. 2. The liquid crystal panel display device according to claim 1, wherein the single crystal silicon layer is formed on the same insulating substrate. 3. The second substrate, wherein the same substrate has a single crystal silicon layer epitaxially grown on a porous silicon layer, and the single crystal silicon layer side of the first substrate serves as an insulating support. 2. A substrate obtained by etching and removing the porous silicon layer after being bonded to a substrate, and the semiconductor layer on the same substrate is the single crystal silicon layer. 2. The liquid crystal panel display device according to item 2.