JPH05210108A - Image display device - Google Patents

Abstract

PURPOSE:To decrease the time constant of a sampling and to speed up a driving circuit by constituting sampling transistors(TRs) of a sampling circuit by using single crystal semiconductors. CONSTITUTION:The data sampling circuit is constituted of shift transistors and consists of a transfer clock 10, input timing data 11 and delay flip-flop 13. The sampling TRs 14 of the respective data lines are constituted of the Si single crystals and a part of control circuits for controlling these TRs are connected by terminals 15, 16, 17. The sampling TRs 14 in such a case are constituted of the single crystals, by which the on resistance and hold capacity to determine the time constants of the sampling TRs 14 are decreased and the time constant of sampling is decreased. Further, even if the sampling time is shortened to the time obtd. by dividing the one effective horizontal scanning time by the number of picture elements in a transverse direction or below by decreasing the time constant, the display device follows up such sampling time and, therefore, the resolution is enhanced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device which has a high resolution and is compatible with a display panel having a large number of pixels.

[0002]

2. Description of the Related Art In a matrix type image display device, an example of a concrete circuit of a matrix display portion is shown in FIG. 8 taking a liquid crystal display device as an example.

In the figure, 81 and 82 are data sampling circuits, 80 is a vertical scanning timing signal generating circuit of the matrix display unit 86, and the output of the data sampling circuit 82 is each pixel of the matrix display unit 86. Distribute to. Reference numeral 83 is a pixel selection transistor arranged for each pixel of the matrix, 84 is a capacitor inserted for auxiliary pixel capacitance, and 85 is a liquid crystal of each pixel.

Conventionally, the data sampling circuits 81 and 82 are used.
As such, a circuit composed of a shift register has been proposed. An example of the above-mentioned conventional circuit and an example of the data sample pulse are shown in FIG.

In the figure, 10 is a transfer clock, 11 is input timing data, 12 is an image signal line, and 13 is a delay flip-flop. A part of the control circuit for switching the sample circuit of each data line is 15, 16, and 17. Reference numeral 14 is a switch composed of a transistor or the like. The switch 14 supplies the input image signal 12 maintained in the ON state, that is, the short-circuited state to the sample-hold circuit in the subsequent stage by the sample pulse supplied from 15.

Conventionally, the thin film transistor as the sample switch 14 is composed of a thin film transistor having a channel of polysilicon or amorphous silicon formed on an SOI substrate, and a metal wiring for electrically connecting them. In this conventional structure, since polysilicon or amorphous silicon is used as a channel, the mobility of electrons passing through the channel is 0.1 to 100.
It was cm ² / vs, and the variation was large.

The mobility of electrons determines the switching speed of the transistor and the current driving force, making it extremely difficult to increase the number of pixels. That is, the number of pixels of about 300 pixels (90,000 pixels in the XY direction) per line is at most because the speed of the transistor for driving the signal line and the current driving force are not sufficient, and further integration is impossible. there were. Furthermore, a peripheral drive circuit, for example, a liquid crystal signal processing circuit,
A signal generation circuit for driving a transistor is a circuit that requires high speed and high driving force, and it has been impossible to form a transistor using polysilicon or amorphous silicon even in terms of chip size. For these reasons, it is usually a good idea to construct the above peripheral circuit as a separate chip integrated on single crystal silicon, but on the other hand, the overall configuration is composed of a matrix substrate and 2-3 separate silicon chips. It's a big one.

Further, as described above, in the conventional sampling transistor of the sampling circuit, the current driving force is not sufficient, so that the resistance value in the ON state is large, the sampling time constant is larger than the sampling period, and the width is wide. An accurate sample of data could not be obtained with a small sampling gate pulse of. As a countermeasure, conventionally,
In order to make the ON time of the sampling transistor longer than the sampling time constant determined by the wiring resistance of the data wiring, the wiring capacitance, and the ON resistance of the sampling transistor, as shown by 18 in FIG. The width was made longer than the sampling period.

[0009]

However, the above-mentioned conventional method cannot follow a signal having a frequency higher than the reciprocal of the sampling time constant and is integrated during the sampling period, resulting in a decrease in resolution. I had.

[0010]

According to the present invention, the sampling transistor is made of a single crystal so that the ON resistance and the holding capacitance of the sampling transistor that determine the time constant of the sampling transistor are reduced. , The sampling time constant can be reduced.

That is, according to the present invention, in a matrix type image display device in which a temporally serial analog image signal is sequentially sampled for each data line of a matrix and then distributed to each pixel for display, The image display device is characterized in that the sampling transistor is formed of a single crystal.

In the present invention, by reducing the sampling time constant, even if the sampling time is equal to or less than one horizontal effective scanning time divided by the number of pixels in the horizontal direction, a high frequency component signal is obtained. Since it also follows, the resolution can be increased. The single crystal used in the present invention is a high quality single crystal semiconductor that is manufactured using a porous substrate and has few defects. A method for forming this single crystal thin film will be described by taking a single crystal Si thin film as an example. The single crystal Si layer is formed by using a porous Si substrate obtained by making the single crystal Si substrate porous.

According to observation with a transmission electron microscope, holes having an average diameter of about 600 Å are formed in this porous Si substrate, and the density thereof is less than half that of single crystal Si. Nevertheless, its single crystallinity is maintained, and it is possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, at 1000 ° C. or higher, rearrangement of internal holes occurs and the characteristics of enhanced etching are impaired. Therefore, for the epitaxial growth of the Si layer, the molecular beam epitaxial growth method, plasma CV
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid crystal growth method, etc. is suitable.

Here, a method of epitaxially growing a single crystal layer after making P-type Si porous will be described.

First, a Si single crystal substrate is prepared, and H
It is made porous by the anodization method using the F solution. The density of single crystal Si is 2.33 g / cm ³ , but the density of the porous Si substrate changes to 0.6 to 1.1 g / cm ³ by changing the HF solution concentration to 20 to 50% by weight. Can be made. This porous layer is P because of the following reasons.
It is easily formed on the mold Si substrate.

Porous Si was discovered in the course of research on electrolytic polishing of semiconductors, and in anodization,
Holes are required for the anodic reaction of Si in HF solution, and the reaction is shown as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + n
e ⁻ SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λ
e ⁻ SiF ₄ + 2HF → H ₂ SiF ₆ Here, e ⁺ and e ⁻ represent a hole and an electron, respectively. Further, n and λ are the numbers of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type Si in which holes are present
Can easily be said to be porous.

On the other hand, it has been reported that high-concentration N-type Si can also be made porous, so that it can be made porous regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, its density is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The conditions for making single crystal Si porous by anodization are shown below. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having another crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ^-2 ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) Single crystal Si thin film prepared by epitaxially growing Si on the porous Si substrate thus formed. To form.
The thickness of the single crystal Si thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, after oxidizing the surface of the above-mentioned single crystal Si thin film, a substrate which will eventually form a substrate is prepared,
The oxide film on the surface of the single crystal Si and the above substrate are bonded together. Alternatively, after the surface of a newly prepared single crystal Si substrate is oxidized, it is attached to the single crystal Si layer on the porous Si substrate. The reason for providing this oxide film between the substrate and the single crystal Si layer is that, for example, when glass is used as the substrate, the interface level generated by the underlying interface of the Si active layer is higher than that of the glass interface. This is because the level can be lowered and the characteristics of the electronic device can be significantly improved. Furthermore, only the single crystal Si thin film obtained by etching away the porous Si substrate by selective etching described below may be attached to a new substrate. The bonding is such that the surfaces are sufficiently adhered so that they cannot be easily peeled off by Van der Waals forces only by bringing them into contact with each other at room temperature after cleaning. Heat treatment is performed in a nitrogen atmosphere at a temperature of 600 to 900 ° C. to completely bond them.

Further, a Si ₃ N ₄ layer is deposited as an etching prevention film on the whole of the above-mentioned two bonded substrates, and only the Si ₃ N ₄ layer on the surface of the porous Si substrate is removed.
Apiezon wax may be used instead of the Si ₃ N ₄ layer. Then, the porous Si substrate is entirely removed by a method such as etching to obtain a semiconductor substrate having a thin film single crystal Si layer.

A selective etching method for electroless wet etching only this porous Si substrate will be described.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, a buffered material such as hydrofluoric acid, ammonium fluoride (NH ₄ F) or hydrogen fluoride (HF) is used. Hydrofluoric acid, mixed solution of hydrofluoric acid or buffered hydrofluoric acid with hydrogen peroxide solution, hydrofluoric acid with alcohol or buffered hydrofluoric acid, hydrofluoric acid with hydrogen peroxide solution and alcohol or buffer A mixed solution of dehydrofluoric acid is preferably used. Etching is performed by moistening the substrate bonded to these solutions. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with that without addition. By further changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, it is possible to instantaneously remove the bubbles of the reaction product gas due to etching from the etching surface without stirring, and it is possible to uniformly and efficiently etch the porous Si.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, still more preferably 1 to 70% by weight, based on the etching solution. The NH ₄ F concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The HF concentration is preferably set in the range of 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 10 to 80% by weight, and is set within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, and further preferably 5 to 60 ° C.

As the alcohol used in this step, in addition to ethyl alcohol, isopropyl alcohol or the like which can be practically used in the manufacturing process and which is desired to have the above-mentioned alcohol addition effect can be used.

In the semiconductor substrate thus obtained, a single crystal Si layer equivalent to that of an ordinary Si wafer is flatly and uniformly thinned to have a large area over the entire substrate.

The single crystal Si layer of this semiconductor substrate is separated by a partial oxidation method or is etched into an island shape, and is doped with impurities to form ap or n channel transistor.

Next, an example of a method for producing the above transistor will be described.

On the semiconductor substrate of FIG. 7 (a) obtained as described above, a silicon oxide film of 200 to 1000 Å is formed by thermal oxidation, and then 100 to 100 by the LPCVD method.
A 500 Å silicon nitride film is formed, the nitride film is patterned into a desired shape, and selective oxidation (LOCOS) of silicon is performed at 1000 ° C. for 1 to 6 hours. In this case,
The selectively oxidized portion 74 as in (b) may reach the lower insulating layer and have a structure in which adjacent active portions are completely separated. For example, by forming a channel stop layer, single crystal silicon is formed. It is also possible to have a structure in which layers are connected to the left and right. After that, a p-type active portion and an n-type active portion are formed as shown in FIG. 7B by a photolithography process and an ion implantation method.

Next, polysilicon is deposited to a thickness of 500 to 5000 Å by the LPCVD method. The polysilicon layer is not only used as the material of the gate electrode of MOSFET,
Since it can be used also as a wiring layer, it is desirable that the film thickness is thick in order to reduce the resistance. Alternatively, the resistance may be lowered by stacking metal silicide (tungsten, titanium, etc.) to a thickness of about 2000Å.

Next, by patterning polysilicon,
Arsenic or phosphorus is ion-implanted into the NMOS part, and boron or boron fluoride is ion-implanted into the PMOS part.
Heat treatment is performed at 00 ° C. to obtain the structure of FIG. Here, the single drain structure in which the n ⁺ layer and the p ⁺ layer are in direct contact with the channel region has been described for both NMOS and PMOS.
If the number of steps is increased, for example, n ⁻ layer and p ⁻ layer are n ⁺
It is also possible to drive the transistor at a higher voltage by forming it between the layer, the p ⁺ layer and the channel region and relaxing the electric field generated in the PN junction. Experiments conducted by the present inventor have also found that the electric field relaxation structure as described above is effective when a power supply voltage of 10 V or higher is required.

Next, a BPSG film is formed by CVD using a CVD method.
The first interlayer insulating layer 75 is formed by depositing 00 to 8000Å. After opening a contact hole for taking out the electrode, the aluminum electrode 3000
Form 8000Å. After patterning aluminum, a silicon nitride film or a silicon oxide film is deposited by 3000 to 10000Å by a plasma excitation method or a thermal CVD method. This film becomes the second interlayer insulating film 76. At this time, it is effective to make the semiconductor surface as flat as possible by spin-on glass for the following reason.

First, by flattening, when multi-layer wiring is performed, the failure of disconnection due to steep steps in the second and subsequent wiring layers is reduced. Secondly, by flattening, the alignment treatment for aligning the liquid crystal becomes uniform, and the image quality when the matrix panel is formed is improved.

The subsequent steps are for forming the storage capacitor of the display pixel section, and do not add a function to the drive circuit section, the peripheral logic circuit and the driver circuit section. However, on the contrary, it does not hinder the operation of the MOSFET.

That is, IT is used as the transparent electrode 77 of the first layer.
O (indium-tin oxide film) 500-2000Å,
It is deposited in a mixed gas of argon and oxygen by a sputtering method. Next, a silicon oxide film is deposited by 300 to 3000 Å by the sputtering method or the CVD method.
This film is a film 78 that determines the capacitance of the storage capacitor, and its thickness is determined by the necessary gradation, the area of the storage capacitor portion, the parasitic capacitance parasitic on the pixel side electrode of the pixel transistor, and the like.

For example, in order to secure 64 gradations, the storage capacitance can be 120 fF and the silicon oxide film thickness can be 2000 Å.

Finally, the contact hole is opened again, and ITO, which is the second transparent electrode 79, is deposited by 500 to 2000 liters. After that, the pattern is shown in FIG. 7 (d). Although not shown, the steps of depositing an alignment film, performing an alignment treatment, and filling a liquid crystal material into the display unit are the same as those in the conventional liquid crystal panel manufacturing method.

In FIG. 7D, the transistor in the pixel portion is a PMOS, but it goes without saying that an NMOS can realize the same function in the same step.

The semiconductor device thus manufactured has the display pixel portion and its drive circuit, and the peripheral logic and driver circuit formed on the same chip as shown in FIG. The total cost of the product can be greatly reduced, and the module is extremely compact.
Can be configured. If the same circuit is to be realized by the conventionally used polysilicon TFT technology, the entire chip will be about 10 times as large as the present invention.

[0047]

The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 shows a data sampling circuit of this embodiment of the present invention. The circuit is composed of a shift register. In the figure, 10 is a transfer clock, 11 is input timing data, and 13 is a delay flip-flop. The sampling transistor 14 of each data line is made of Si single crystal, and a part of a control circuit for controlling this is 15, 16, and 17.

Sampling is performed as shown in the data sample pulse of FIG. T in the figure
_{(S / H)} is the sampling period, t _{(S / H)} is the ON time of the sampling transistor, that is, the sampling time, t
_(pitch) is a time obtained by dividing one horizontal effective scanning time by the number of pixels in the horizontal direction, that is, a time corresponding to one pixel in the horizontal direction.

FIG. 3 shows a part of the data sampling time chart and the equivalent circuit of the data sampling circuit.

Here, the ON resistance of the sampling transistor 14, the wiring resistance 31 of the data wiring, and the same wiring capacitance 3
2, if the sampling time constant τ _{(S / H)} determined by the hold capacitance 33 is τ _{(S / H)} ≤ t _{(S / H)} , as shown in FIG. − Hold the capacitance 33
Match image signals 9 between the voltage) t _{(S / H)} to be field, then higher up into frequency components to follow, t _{(S / H} falling time point b of the image signal _voltage) Hold, so that it reliably responds to an image signal having a high frequency component.

Further, as shown in FIG. 2, t _(pitch) ≧ t _{(S / H)}
By so doing, the image signal in the section of each pixel can be surely sampled and held, so that the resolution is improved.

Since the blanking period is 10.8 μsec in one horizontal scanning period of 63.5 μsec, the effective scanning period is 52.7 μsec. For example, when the vertical resolution is 490 lines and the aspect ratio is 4/3, The directional resolution is 652 lines and t _(pitch) = 52.7 μsec / 652≈80 nsec.

When the sampling transistor 14 is made of polysilicon or amorphous silicon as in the conventional case, the sampling transistor 14 is turned on.
Resistance + wiring resistance is 10 kΩ, hold capacitance + wiring capacitance is about 30 pF, and sampling time constant τ _{(S / H)} is τ _{(S / H)} = 10 kΩ × 30 pF = 300 nsec, t _{(S / H)} ≧ τ _{(S / H)} cannot be satisfied.

On the other hand, when the sampling transistor 14 is made of a single crystal as in the present embodiment, the ON resistance of the sampling transistor 14 + the wiring resistance is 1 kΩ,
Hold capacity (composed of MOS capacity) + wiring capacity is 10p
It becomes about F, and the sampling time constant τ _{(S / H)} is τ _{(S / H)} = 1 kΩ × 10 pF = 10 nsec, which is 1/30 of the conventional value. The frequency of the image signal that can be followed at this time is 100 MHz, and t _{(S / H)} ≥
τ _{(S / H)} can be fully satisfied.

Further, even a display panel having a high pixel count of 1000 or more in the horizontal direction can sufficiently handle τ _{(S / H)} of 50 nsec or less.

(Embodiment 2) As in Embodiment 1, this embodiment uses the data sampling circuit of FIG. 1 in which the sampling transistor 14 is made of Si single crystal, and has the sampling waveform shown in FIG. This is an example.

As shown in FIG. 3, t _{(S / H)} ≥ τ _{(S / H)}
However, if τ _{(S / H)} is small enough to follow the frequency of the image signal, the voltage of the image signal to be sampled is determined by the trailing edge of the sampling pulses 15 to 17.

Therefore, as shown in FIG. 4, the sampling timing is set so that the falling edges of the sampling pulses 15 to 17 are located at the center of the image signal corresponding to each pixel, so that the image at the center of the image signal is displayed. Can be reproduced.

As described above, sampling can be performed in any portion within the horizontal pixel pitch.

(Embodiment 3) FIG. 5 is a data sample circuit corresponding to the color of this embodiment of the present invention. The sampling transistor 14 of the circuit is composed of Si single crystal. Further, FIG. 6 shows a sampling waveform.

A signal obtained by cyclically recombining R, G, and B3 primary colors is input to the image signal line 12 at every horizontal period according to the arrangement of the horizontal color filters of the color matrix panel, and is shifted. Signal from register 50 ~
The image signals 12 of three lines are sequentially sampled and held by 53 and the like.

In this case, by setting t _(pitch) ≧ t _{(S / H) so} that the trailing edge of the sampling pulse falls within the period of each pixel, the color located in that pixel can be sampled reliably. The resolution can also be increased for color image signals.

[0064]

As described above, in the image display device according to the present invention, by configuring the sampling transistor of the sampling circuit using a single crystal semiconductor, the sampling time constant can be reduced and the driving circuit can be operated at high speed.
As a result, it is possible to provide a high-definition image with a larger number of pixels than ever before, and a large-area screen for clear display.

[Brief description of drawings]

FIG. 1 is a data sample circuit diagram showing one embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data sample pulse.

FIG. 3 is a diagram showing an equivalent circuit of a data sampling circuit and a time chart of data sampling.

FIG. 4 is a diagram showing an example of a data sample pulse.

FIG. 5 is a data sample circuit diagram showing one embodiment of the present invention.

FIG. 6 is a diagram showing a data sample time chart of a data sample circuit.

FIG. 7 is a schematic diagram showing a method for manufacturing a semiconductor device according to the present invention.

FIG. 8 is a diagram illustrating an example of a circuit of a matrix display unit.

FIG. 9 is a diagram showing an example of a conventional data sampling circuit.

[Explanation of symbols]

10 Transfer Clock 11 Input Timing Data 12 Image Signal Line 13 Delay Flip-Flop 14 Sampling Transistor 15 to 17 Terminal as Part of Control Circuit 18 Data Sample Pulse 19 Image Signal Waveform 30 Hold in Hold Capacity Voltage 31 Wiring resistance of data wiring 32 Wiring capacitance 33 Hold capacitance 50 to 53 Terminals which are part of control circuit 71 Silicon substrate 72 Insulating layer 73 Single crystal silicon layer 74 SiO ₂ separation film 75 First Interlayer insulating layer 76 Second interlayer insulating layer 77 First transparent electrode 78 Capacitive film 79 Second transparent electrode 80 Vertical scanning timing generation circuit 81,82 Data sample circuit 83 Transistor 84 Capacitor 85 Liquid crystal of each pixel 86 Matrix display

Claims (1)

[Claims] 1. An analog image signal that is temporally serial is sampled sequentially for each data line of a matrix, and
An image display device in which a sampling transistor in a sampling circuit is composed of a single crystal in a matrix type image display device which is distributed to each pixel for display.