JPH05218326A - Semiconductor device and liquid crystal display device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device in which NMOS and PMOS transistors are electrically isolated from each other by epitaxially growing a monocrystal semiconductor on a porous base and forming a dielectric layer by ion implantation. CONSTITUTION:In an active layer 2 of a PMOS transistor, an n-type channel section 24, a p-type drain region 25 and a source region 26 are formed. In an active layer 12 of an NMOS transistor, a p-type channel region 27, an n<+>-type drain region 28 and a source region 29 are formed. Second gates of the PMOS and NMOS transistors are doped to form an n-type semiconductor and a p-type semiconductor, respectively. The second gates 1 and 11 and the active layers 2 and 12 are made of a monocrystal Si thin-film. A monocrystal Si thin-film between the transistors is oxidized to SiO2 which acts as a dielectric layer by the LOCOS oxidation method. Other areas are simultaneously subjected to the doping of Si when ions are implanted into the second gates. Accordingly, first and second gate connecting sections 6 and 16 are located near to the transistors, whereby excessive interconnections are hardly produced. Hence, the first and second gates can be controlled simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a semiconductor device having a PMOS (P-channel type MOS; Metal Oxide Silicon) transistor and an NMOS (N-channel type MOS) transistor, and uses the semiconductor device in a peripheral drive circuit. The present invention relates to a liquid crystal display device using a PMOS transistor as a switching element of the pixel electrode.

[0002]

2. Description of the Related Art In recent years, semiconductor technology has made remarkable progress, and there is a demand for semiconductor elements and devices that are smaller, faster, and consume less power. MOS F
ET (MOS field effect transistor) is one of them, and there are a PMOS transistor using an n-type substrate and an NMOS transistor using a P-type substrate, each of which is composed of a gate, a source, and a drain. An active element that controls the current between drains by applying a voltage to the gate electrode.

More recently, a semiconductor layer having a source and a drain formed thereon has a second layer on the side opposite to the gate via an insulating layer.
A double-gate type MOS having a gate is also developed. An example of this double gate type MOS is shown in FIG. In the figure, 61 is a substrate, 62 to 62 ″ are insulating layers, 63 is a second gate, 64 is a source region, 65 is a drain region, and 67 source electrodes and 68 drain electrodes are connected to each other. Source 64 and drain 66 sandwiched between 65
Is a channel portion, and 69 is a first gate for controlling this channel portion. It is known that such a double gate type MOS has an effect of improving a short channel effect and an effect of increasing a current driving force.

The manufacturing process of such a double gate type MOS is shown in FIG. First single crystal Si71 to form a field SiO ₂ film 72 and the CVD SiO ₂ film 73 as a substrate, the areas of the second gate is removed by etching (a). By the thermal oxidation on the part removed by etching, the first
An insulating layer 74 between the gate and the second gate is formed. Next, polycrystalline Si that will become the second gate is deposited (63), and is flattened by a polishing process (b). CVD on it
Then, a SiO ₂ film is formed to form an insulating layer 75, and the surface is polished and flattened (c). Support substrate 76 having a BPSG (boron-phosphorus silicon glass) film 77 deposited on its surface
Are bonded together by a heat bonding method using vacuum electrostatic adsorption (d). The single crystal Si 71 is polished from the lower surface of (d) using the field SiO ₂ film as an etching stopper to form a single crystal Si thin film 78 forming an active layer. Then, polycrystalline Si is deposited on the single crystal Si thin film via the insulating layer 79 to form a first gate. The subsequent steps are the same as the normal MOS FET manufacturing steps.

[0005]

As described above, the manufacturing process of the double gate type MOS transistor is very complicated and expensive. Also, judging from the manufacturing process, the connection between the first gate and the second gate is made at a position at least several μm away from the transistor. To obtain the effect of the double gate type MOS transistor,
Although it is necessary to control the first gate and the second gate at the same time, it is disadvantageous in that point that the distance to the connection point is long. Further, if the number of wirings is increased, not only the integration degree is lowered, but also the characteristics of the transistor, such as crosstalk between the wirings and the parasitic capacitance attached to the wirings, and the operating speed of the circuit are lowered.

Due to the above problems,
Although the double gate type semiconductor device is expected to be effective, it has not been put to practical use.

[0007]

Means for Solving the Problems As a result of intensive studies to solve the above problems, the present inventors have found that a single crystal semiconductor thin film obtained by epitaxially growing a single crystal semiconductor on a porous substrate is provided with an insulating layer by ion implantation. The present invention has been completed, focusing on the fact that a double gate can be easily formed by forming the double gate.

That is, the present invention is a semiconductor device having an NMOS transistor and a PMOS transistor, wherein the active layers of the both transistors are formed of the first single crystal semiconductor, and the second active layer is separated from the active layer by an insulating layer. And a second single crystal semiconductor layer, wherein the second single crystal semiconductor layer is electrically isolated between the NMOS transistor and the PMOS transistor. Using the semiconductor device in a peripheral drive circuit,
A liquid crystal display device using a PMOS transistor as a switching element of a display unit.

A method of manufacturing a single crystal semiconductor thin film according to the present invention will be described by taking Si as an example.

The single crystal Si layer is formed by using a porous Si substrate obtained by making the single crystal Si substrate porous.

According to observation with a transmission electron microscope, holes having an average diameter of about 600 Å are formed in this porous Si substrate, and the density thereof is less than half that of single crystal Si. Nevertheless, its single crystallinity is maintained, and it is possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, at 1000 ° C. or higher, rearrangement of internal holes occurs and the characteristics of enhanced etching are impaired. Therefore, for the epitaxial growth of the Si layer, the molecular beam epitaxial growth method, plasma CV
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid crystal growth method, etc. is suitable.

Here, a method of epitaxially growing a single crystal layer after making P-type Si porous will be described.

First, a Si single crystal substrate is prepared, and H
It is made porous by the anodization method using the F solution. The density of single crystal Si is 2.33 g / cm ³ , but the density of the porous Si substrate changes to 0.6 to 1.1 g / cm ³ by changing the HF solution concentration to 20 to 50% by weight. Can be made. This porous layer is P because of the following reasons.
It is easily formed on the mold Si substrate.

Porous Si was discovered in the research process of electrolytic polishing of semiconductors, and Si in anodization is used.
In the dissolution reaction of 1), holes are required for the anodic reaction of Si in the HF solution, and the reaction is shown as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- where _{SiF 4 + 2HF → H 2 SiF} 6, e + and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the numbers of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type Si in which holes are present
Can easily be said to be porous.

On the other hand, it has been reported that high-concentration N-type Si can be made porous, so that it can be made porous regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The conditions for making single crystal Si porous by anodization are shown below. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having another crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1:
1: 1 time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) Single crystal Si thin film prepared by epitaxially growing Si on the porous Si substrate thus formed. To form.
The thickness of the single crystal Si thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, after the surface of the single crystal Si thin film is oxidized, a base body which will eventually form a substrate is prepared,
The oxide film on the surface of the single crystal Si and the above substrate are bonded together. Alternatively, after the surface of a newly prepared single crystal Si substrate is oxidized, it is attached to the single crystal Si layer on the porous Si substrate. The reason for providing this oxide film between the substrate and the single crystal Si layer is that, for example, when glass is used as the substrate, the interface level generated by the underlying interface of the Si active layer is higher than that of the glass interface. This is because the level can be lowered and the characteristics of the electronic device can be significantly improved. Furthermore, only the single crystal Si thin film from which the porous Si gas has been removed by etching by selective etching described below may be attached to a new substrate. The bonding is such that the surfaces are sufficiently adhered so that they cannot be easily peeled off by Van der Waals force only by bringing them into contact with each other at room temperature, but this is further 200 to 900 ° C, preferably 600 to 900 ° C. Heat treatment under a nitrogen atmosphere at the temperature of and bond them completely.

Further, a Si ₃ N ₄ layer is deposited as an etching prevention film on the whole of the above-mentioned two bonded substrates, and only the Si ₃ N ₄ layer on the surface of the porous Si substrate is removed.
Apiezon wax may be used instead of the Si ₃ N ₄ layer. Then, the porous Si substrate is entirely removed by a method such as etching to obtain a semiconductor substrate having a thin film single crystal Si layer.

A selective etching method for electroless wet etching only this porous Si substrate will be described.

As an etching solution which does not have an etching effect on crystalline Si and can selectively etch only porous Si, buffered solutions such as hydrofluoric acid, ammonium fluoride (NH ₄ F) and hydrogen fluoride (HF) can be used. Hydrofluoric acid, mixed solution of hydrofluoric acid or buffered hydrofluoric acid with hydrogen peroxide solution, hydrofluoric acid with alcohol or buffered hydrofluoric acid, hydrofluoric acid with hydrogen peroxide solution and alcohol or buffer A mixed solution of dehydrofluoric acid is preferably used. Etching is performed by moistening the substrate bonded to these solutions. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with that without addition. By further changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, it is possible to instantaneously remove the bubbles of the reaction product gas due to etching from the etching surface without stirring, and it is possible to uniformly and efficiently etch the porous Si.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, further preferably 1 to 70% by weight, based on the etching solution. The NH ₄ F concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The HF concentration is preferably set in the range of 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 10 to 80% by weight, and is set within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, further preferably 5 to 60 ° C.

As the alcohol used in this step, in addition to ethyl alcohol, isopropyl alcohol or the like which can be practically used in the manufacturing process and which is desired to have the above-mentioned alcohol addition effect can be used.

By injecting O ₂ into the single crystal Si thin film layer thus obtained, or by adhering a Si wafer having an insulating film on the surface, an insulating film having a single crystal Si thin film on both sides is formed. Can be configured.

In the case of ion implantation, the Si film thickness before implantation is
It is desirable to set the thickness to about 1 to 5 μm according to the purpose.
Ion implantation is 5 × 10 at an acceleration energy of 200 KeV.
Inject ^{17 to} 5 × 10 ¹⁸ cm ^-2 . Then 1100-12
Heat treatment is performed at 00 ° C. for several hours. By doing this, 2
000-4000Å single crystal Si, 1000-under it
It is possible to form a 5000 Å SiO ₂ layer.

In the case of the bonding method, the insulating film is 50
The thickness of Si on the outermost surface can be adjusted to 2000 Å to several μm by laminating again after adjusting the thickness to 0 to 10000 Å. In the present invention, the former ion implantation method is preferably used.

In the semiconductor device of the present invention, when a double gate MOS transistor is formed, the film thickness of the first gate is preferably 500Å or more, more preferably 200.
Form it to be 0Å or more. In a thin region where the film thickness is less than 500Å, there is a concern that the resistance value of the gate may increase, which is not preferable. Further, in the liquid crystal display device of the present invention, the film thickness of the first gate is 500 to 10000Å, more preferably 2
000 to 6000Å is preferable. When the film thickness is 500 Å or less, there is a concern that the resistance value of the gate may increase, while when it is too thick, it becomes difficult to completely make the pixel portion transparent.

In the present invention, the area ratio of the first gate and the second gate is not particularly limited, but considering the characteristics as a double gate, when the first gate and the second gate are used in a one-to-one relationship. Second gate / first gate is 1/1 to
10/1 is preferred. If the first gate is too small or the second gate is too large, as shown in the conventional example,
There are problems such as a connection problem between the first gate and the second gate, an alignment problem, and a difference in complexity of manufacturing processes, resulting in a high manufacturing cost, which is not preferable. Further, as will be described in a second embodiment to be described later, it is also possible to make the second gate common to all the NMOS transistors and the second gate common to all the PMOS transistors so that they can be controlled simultaneously. In this case, the first gate and the second gate are individually controlled without being connected, and the area ratio of the first gate and the second gate is not particularly limited.

[0036]

EXAMPLES AND OPERATION The present invention will be described in detail below with reference to examples, but the present invention is not limited thereto.

Example 1 FIG. 1 shows a simplified plan view of an example of a semiconductor device of the present invention. In this figure, the insulating layer is omitted.
2A, 2B, and 3 show the AA ′ cross section, the BB ′ cross section, and the CC ′ cross section of this figure, respectively.

In this embodiment, in a double-gate CMOS inverter, the corresponding second gates are formed below the PMOS transistor and the NMOS transistor, respectively, and they are electrically separated from each other, and each is connected to the first gate at the end. Is.

1 to 8 and 24 to 26 in FIGS.
On the OS transistor side, 1 is a second gate, 2 is an active layer, 3
Is a drain region connecting portion of the output wiring, 4 is a source area connecting portion of the high voltage side power source wiring, 5 is a first gate, 6 is a connecting portion between the first gate and the second gate, and 7 is a high voltage side power source (V _DD ). In the active layer 2, an n-type channel portion 24, a P ⁺ -type drain region 25 and a source region 26 are formed.
On the other hand, 11 to 17 and 27 to 29 are on the NMOS transistor side, 11 is a second gate, 12 is an active layer, 13 is a drain region connecting portion of an output wiring, 14 is a source region connecting portion of a high voltage side power wiring, and 15 is a first portion. The gate, 16 is a connecting portion between the first gate and the second gate, 17 is a low voltage side power supply (V _SS ) and the active layer 12 is a P-type channel portion 27 and an n ⁺ -type drain region 28 and a source region. 29 is formed. The second gate on the side of the PMOS transistor is n-type,
The second gates on the side of the MOS transistors are P-type doped. Further, 8 is a connecting portion between the first gate and the second gates 1 and 11, and 9 is an output portion (V
_out ), 10 is an input part (V _in ), 21 is a Si substrate, 22
-23 are insulating layers.

In this embodiment, the second gates 1 and 11 and the active layers 2 and 12 are the above-mentioned single crystal Si thin films, and the single crystal Si thin films between the transistors are LOCOS.
(Local Oxidation of Silic
on) SiO ₂ was used as an insulating layer by an oxidation method, or an unnecessary single crystal thin film was removed by etching to form a new insulating layer. In addition, Si doping was performed at the same time in other portions when ions were implanted in the second gate.

An equivalent circuit of the CMOS inverter of this embodiment is shown in FIG.

In this embodiment, first, the manufacturing process is very simple and can be manufactured at a much lower cost than before, and as is apparent from FIG. 3, the connecting portion 6 between the first gate and the second gate 6 is formed. And 16 are in the vicinity of the transistor, there is almost no extra wiring, and the excellent effects that the first gate and the second gate can be controlled sufficiently at the same time are obtained. The connection form of the first gate and the second gate does not have to be the same as that of this embodiment, but it is desirable to eliminate the wiring portion substantially involved in the connection as in this embodiment.

Embodiment 2 FIG. 4 is a simplified sectional view of a main part of an embodiment of the liquid crystal display device of the present invention. The description of the same parts as those in the first embodiment is omitted and the same reference numerals are given. In the present embodiment, the second gates 1 and 11 are provided in the NMOS transistor group and the PMOS transistor group, respectively, and the potentials V _backn and V _backp are separately controlled for control. V _backn and V in this embodiment
The role of _backp is as follows.

That is, V_backn The gate electrode, underlying insulating film
A parasitic NMOS transistor having a gate insulating film 22;
And V_backp The gate electrode and the base insulating film 22
Both of the parasitic PMOS transistors used as the edge film do not operate.
Like V_backn , V_backpTo control. under
If the ground insulating film is formed by ion implantation,
It is about 5000Å at most. on the other hand. As shown in FIG.
Tens of thousands of pixels in the liquid crystal display device as the power supply voltage for the inverter
To obtain high quality images on the above scale, V_DD-V_SS
> 10V or more is required. Conventional inverter is V_backp 
Area 11 and V _backn Region 1 of the same potential was the same
A parasitic NMOS transistor and a parasitic PMOS transistor
It is difficult to find the conditions under which the
It was In the configuration of this embodiment, for example, V_backn = V_SS, V
_backp = V_DDThe above-mentioned parasitic MOS transistor
The condition that the transistor is not completely operated can be surely obtained.

Further, the switching element of the display section is a PMO.
It is an S transistor and I connected to its drain region
TO (Indium Tin Oxide) is the first IT
The O layer 41 constitutes a pixel electrode, and a second ITO layer is provided as a storage capacitor via an insulating layer 43 from the first ITO layer.

The Si substrate on the lower side of the display portion is removed by etching to make it transparent. This hollow portion may be filled with a light-transmissive filler material for reinforcement.

In the liquid crystal display device of this embodiment, an insulating layer and an orientation control film are further formed on the substrate shown in FIG.
It is arranged so as to face the other substrate on which the insulating layer and the orientation control film are formed with a spacer interposed therebetween, and is filled with liquid crystal.

FIG. 5B shows a transparent circuit diagram of the peripheral drive circuit of this embodiment.

In this embodiment, the driving characteristics of the MOS FET used in the peripheral drive circuit are excellent, and the manufacture is simple. Therefore, the driving characteristics of the present liquid crystal display device can be improved, and the manufacturing cost can be reduced.

[0050]

As described above, the semiconductor device of the present invention is simpler to manufacture than conventional ones, and there is no fear of deterioration of characteristics due to connection wiring. Is high. Further, in the liquid crystal display device of the present invention in which the semiconductor device is used in the peripheral drive circuit, not only is it possible to drive at a higher power supply voltage than in the past, but also the freedom of voltage setting is achieved while reducing the manufacturing cost. Since the degree of image quality increases, it becomes easier to study higher image quality because of the circuit configuration. For example, since the voltage margin for obtaining a higher gradation display is expanded, the maximum allowable value of the parasitic capacitance of the pixel section is also increased. Further, various combinations of circuit driving timings required for that purpose are possible, and it can be said that the conditions are indispensable for realizing future high-definition and high-quality display devices. In the liquid crystal display device of the present invention in which the semiconductor device is used as the peripheral drive circuit, the peripheral drive circuit having excellent characteristics is used to speed up the drive circuit and improve the drive characteristics while reducing the manufacturing cost. Can be planned.

[Brief description of drawings]

FIG. 1 is a plan view showing an embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor device shown in FIG.

3 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 4 is a cross-sectional view of main parts of an embodiment of the liquid crystal display device of the present invention.

FIG. 5 is an equivalent circuit according to an embodiment of the present invention.

FIG. 6 is a sectional view of a conventional double gate type MOS FET.

FIG. 7 is an explanatory diagram of a manufacturing process of a conventional double gate MOS FET.

[Explanation of symbols]

1 2nd gate 2 active layer 3 drain region connection part 4 source region connection part 5 1st gate 6 2nd gate connection part 7 high voltage side power supply 8 1st gate connection part 9 output part 10 input part 11 2nd gate 12 active layer 13 Drain Region Connection Portion 14 Source Region Connection Portion 15 First Gate 16 Second Gate Connection Portion 17 Low Voltage Side Power Supply 21 Substrate 22, 22 ', 22 "Insulation Layer 23 Insulation Layer 24 Channel Part 25 Drain Region 26 Source Region 27 Channel Part 28 drain region 29 source region 41 first ITO layer 42 second ITO layer 43 insulating layer 61 substrate 62, 62 ′, 62 ″ insulating layer 63 second gate 64 source region 65 drain region 66 channel portion 67 source electrode 68 drain electrode 69 first gate 71 monocrystalline Si 72 field SiO ₂ film 73 CVD SiO ₂ 74 insulating layer 75 insulating layer 76 the support substrate 77 BPSG layer 78 single-crystal Si thin film 79 insulating layer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location G09F 9/30 338 6447-5G

Claims (2)

[Claims] 1. A semiconductor device having an NMOS transistor and a PMOS transistor, wherein active layers of the both transistors are formed of a first single crystal semiconductor, and a second single crystal is formed through an insulating layer from the active layer. A semiconductor device having a semiconductor layer, wherein the second single crystal semiconductor layer is electrically isolated between the NMOS transistor and the PMOS transistor. 2. A liquid crystal display device, wherein the semiconductor device according to claim 1 is used for a peripheral drive circuit, and a PMOS transistor is used for switching a pixel electrode.