JPH05243579A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH05243579A
JPH05243579A JP7598192A JP7598192A JPH05243579A JP H05243579 A JPH05243579 A JP H05243579A JP 7598192 A JP7598192 A JP 7598192A JP 7598192 A JP7598192 A JP 7598192A JP H05243579 A JPH05243579 A JP H05243579A
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JP
Japan
Prior art keywords
formed
si
contact
patterned
semiconductor device
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Pending
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JP7598192A
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Japanese (ja)
Inventor
Masaru Sakamoto
勝 坂本
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Canon Inc
キヤノン株式会社
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Application filed by Canon Inc, キヤノン株式会社 filed Critical Canon Inc
Priority to JP7598192A priority Critical patent/JPH05243579A/en
Publication of JPH05243579A publication Critical patent/JPH05243579A/en
Application status is Pending legal-status Critical

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating, or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To obtain a semiconductor device which exhibits excellent contact characteristics and has a high speed and a low power consumption by providing at least a layer made of Ti compound between an ITO thin film and an Si region. CONSTITUTION:A polycrystalline silicon 202 to become a channel is formed on a glass board 201, patterned, a gate film 203 is then formed, a gate electrode 204 is formed, patterned, source.drain 205 are then ion implanted with the patterned electrode as a mask, and then an interlayer insulating film 206 is formed. Then, a through hole window is opened at the region 205 by RIE, Ti 207 is then formed by a CVD method or a sputtering method, and patterned to form an ITO. A contact resistance is measured, and a contact resistance of 50OMEGA or less can be obtained in a contact size of 3X3mum. A semiconductor device which has excellent and stable contact characteristics can be obtained.

Description

【発明の詳細な説明】 DETAILED DESCRIPTION OF THE INVENTION

【0001】 [0001]

【産業上の利用分野】本発明は半導体装置、特に液晶表示装置、光電交換装置等に好適に使用し得る、安定かつ優れたコンタクト特性を示す半導体装置に関する。 The present invention relates to a semiconductor device, particularly a liquid crystal display device, a photoelectric switching apparatus or the like can be preferably used in a semiconductor device showing a stable and good contact characteristic.

【0002】 [0002]

【従来の技術】従来、n型又はp型SiとITO膜とのコンタクト構造として、SiとITO膜のコンタクトを直接取る構造(特開昭58−190063号公報)、S Conventionally, as a contact structure between the n-type or p-type Si and ITO film, the structure to contact the Si and ITO film directly (JP 58-190063 JP), S
iとITO膜をIn、Sn等のバリアメタルを介してコンタクトを取る構造(特開昭59−22361号公報、 I and ITO film In, structures making contact via the barrier metal such as Sn (JP 59-22361, JP-
特開昭59−40582号公報)等があった。 It had Sho 59-40582 JP) or the like.

【0003】しかし、上記従来の方法ではオーミックコンタクトを取りにくい、或いはコンタクト抵抗値がKΩ [0003] However, it is difficult to take an ohmic contact in the above conventional method, or the contact resistance value is KΩ
〜MΩ代と大きくなる、更には、ITOの蒸着後、層間絶縁膜を蒸着する工程(250℃以上の熱処理)でコンタクト値が更に上昇するという問題もあり、電子特性のばらつき、遅延時間を大きくし、信頼性低下の原因となっていた。 As large as ~MΩ allowance, even after the deposition of ITO, there is also a problem that the contact value is further increased in the step (250 ° C. or more heat treatment) depositing an interlayer insulating film, variation in electron properties, increase the delay time then, it has been a cause of reduced reliability.

【0004】 [0004]

【発明が解決しようとする課題】本発明は上記問題点を解決し、優れたコンタクト特性を示す高速かつ低消費電力の半導体装置を提供し、更に、該半導体装置を利用した画像品質の高い液晶表示装置、光電交換装置を提供することを目的とする。 The present invention invention is to solve the above solves the above problems, high speed and showing a contact characteristic to provide a semiconductor device with low power consumption, furthermore, a high image quality by using the semiconductor device LCD and to provide a display device, a photoelectric transfer device.

【0005】 [0005]

【課題を解決するための手段】即ち本発明は、ITO薄膜とSi領域との間に少なくともTi化合物よりなる層を設けたことを特徴とする半導体装置である。 SUMMARY OF THE INVENTION Namely, the present invention is a semiconductor device which is characterized in that a layer made of at least a Ti compound between the ITO film and the Si region.

【0006】本発明の半導体装置はガラス基板上に形成しても良いし、Si基板上に形成しても良い。 [0006] The semiconductor device of the present invention may be formed on a glass substrate, it may be formed on the Si substrate.

【0007】特に、本発明の半導体装置を液晶表示装置に適用する場合には、以下に示す方法により製造される単結晶Si層を有する半導体基板を用いることにより、 [0007] Particularly, in the case of applying the semiconductor device of the present invention to a liquid crystal display device, by using a semiconductor substrate having a monocrystalline Si layer produced by the following method,
液晶素子、液晶駆動回路及びその他の周辺駆動回路を同時に同一基板上に作成することができ、好ましい。 A liquid crystal element, a liquid crystal drive circuit and other peripheral driver circuits can be simultaneously fabricated on the same substrate, preferably. 以下、その方法につき説明する。 Below, it will be described that way.

【0008】半導体基板の単結晶Si層は単結晶Si基体を多孔質化した多孔質Si基体を用いて形成したものである。 [0008] Single-crystal Si layer of the semiconductor substrate is one formed by using a porous Si substrate a single crystal Si substrate was made porous.

【0009】この多孔質Si基体には、透過型電子顕微鏡による観察によれば、平均約600Å程度の径の孔が形成されており、その密度は単結晶Siに比べると、半分以下になるにもかかわらず、その単結晶性は維持されており、多孔質層の上部へ単結晶Si層をエピタキシャル成長させることも可能である。 [0009] The porous Si substrate, according to the observation by a transmission electron microscope, are an average of about 600Å approximately the diameter of the hole is formed, on the its density compared to the single-crystal Si, becomes less than half Despite its single crystallinity is maintained, it is possible to epitaxially grow a single-crystal Si layer to the top of the porous layer. ただし、1000℃以上では、内部の孔の再配列が起こり、増速エッチングの特性が損なわれる。 However, in the 1000 ° C. or more, it occurs rearrangement of internal pores, is impaired characteristics of accelerated etching. このため、Si層のエピタキシャル成長には、分子線エピタキシャル成長法、プラズマCV Therefore, the epitaxial growth of the Si layer, molecular beam epitaxy, plasma CV
D法、熱CVD法、光CVD法、バイアス・スパッタ法、液晶成長法等の低温成長が好適とされる。 D, thermal CVD, photo CVD, bias sputtering, low temperature growth such as a liquid crystal growth method is the preferred.

【0010】ここでP型Siを多孔質化した後に単結晶層をエピタキシャル成長させる方法について説明する。 [0010] describes a method of a single crystal layer is epitaxially grown after porous P-type Si here.

【0011】先ず、Si単結晶基体を用意し、それをH [0011] First, a Si single crystal substrate, it H
F溶液を用いた陽極化成法によって、多孔質化する。 By anodization using F solution, it made porous. 単結晶Siの密度は2.33g/cm 3であるが、多孔質Si基体の密度はHF溶液濃度を20〜50重量%に変化させることで、0.6〜1.1g/cm 3に変化させることができる。 Density of monocrystalline Si is a 2.33 g / cm 3, the density of the porous Si substrate by changing the HF solution concentration to 20 to 50 wt%, the change in 0.6~1.1g / cm 3 it can be. この多孔質層は下記の理由により、P The porous layer for the following reason, P
型Si基体に形成され易い。 It tends to be formed in the type Si substrate.

【0012】多孔質Siは半導体の電解研磨の研究過程において発見されたものであり、陽極化成におけるSi [0012] The porous Si has been discovered in the research process of a semiconductor electropolishing, Si in anodization
の溶解反応において、HF溶液中のSiの陽極反応には正孔が必要であり、その反応は、次のように示される。 In the dissolution reaction, the anode reaction of Si in HF solution requires positive holes, the reaction is shown as follows.

【0013】 Si+2HF+(2−n)e + →SiF 2 +2H + +ne - SiF 2 +2HF→SiF 4 +H 2 SiF 4 +2HF→H 2 SiF 6又は、 Si+4HF+(4−λ)e + →SiF 4 +4H + +λe - SiF 4 +2HF→H 2 SiF 6ここで、e +及び、e -はそれぞれ、正孔と電子を表している。 [0013] Si + 2HF + (2-n ) e + → SiF 2 + 2H + + ne - SiF 2 + 2HF → SiF 4 + H 2 SiF 4 + 2HF → H 2 SiF 6 or, Si + 4HF + (4- λ) e + → SiF 4 + 4H + + λe - where SiF 4 + 2HF → H 2 SiF 6, e + and, e - respectively represent a positive hole and an electron. また、n及びλはそれぞれSi1原子が溶解するために必要な正孔の数であり、n>2又は、λ>4なる条件が満たされた場合に多孔質Siが形成されるとしている。 Further, the n and lambda are the number of holes required for Si1 atom respectively is dissolved, and the porous Si is formed when n> 2 or, where lambda> 4 following condition is satisfied.

【0014】以上のことから、正孔の存在するP型Si [0014] From the above, P-type Si in which the presence of holes to
は、多孔質化され易いと言える。 It can be said to easily made porous.

【0015】一方、高濃度N型Siも多孔質化されうることが報告されているおり、従って、P型、N型の別にこだわらずに多孔質化を行うことができる。 Meanwhile, the high concentration N-type Si also has been reported that may be porous, thus, it is possible to perform the porous without particular about P-type, to another N-type.

【0016】また、多孔質層はその内部に大量の空隙が形成されているために、密度が半分以下に減少する。 Further, the porous layer in a large amount of voids are formed therein, the density is reduced to less than half. その結果、体積に比べて表面積が飛躍的に増大するため、 As a result, the surface area is increased dramatically compared to the volume,
その化学エッチング速度は、通常の単結晶層のエッチング速度に比べて著しく増速される。 Its chemical etching rate is remarkably accelerated as compared with the etching rate of the ordinary monocrystalline layer.

【0017】単結晶Siを陽極化成によって多孔質化する条件を以下に示す。 [0017] The conditions under which the single-crystal Si is made porous by anodization are shown below. 尚、陽極化成によって形成する多孔質Siの出発材料は、単結晶Siに限定されるものではなく、他の結晶構造のSiでも可能である。 Incidentally, the starting material of porous Si formed by anodization is not limited to monocrystalline Si, it is possible in Si of other crystalline structure.

【0018】 印加電圧: 2.6(V) 電流密度: 30(mA・cm -2 ) 陽極化成溶液: HF:H 2 O:C 25 OH=1: The applied voltage: 2.6 (V) Current density: 30 (mA · cm -2) Anodization solution: HF: H 2 O: C 2 H 5 OH = 1:
1:1 時間: 2.4(時間) 多孔質Siの厚み: 300(μm) Porosity: 56(%) このようにして形成した多孔質化Si基体の上にSiをエピタキシャル成長させて単結晶Si薄膜を形成する。 1: 1 Time: 2.4 (hours) porous Si thickness: 300 (μm) Porosity: 56 (%) monocrystalline Si thin film is epitaxially grown Si over this way was formed by porous Si substrate to form.
単結晶Si薄膜の厚さは好ましくは50μm以下、さらに好ましくは20μm以下である。 The thickness of the monocrystalline Si thin film preferably 50μm or less, more preferably 20μm or less.

【0019】次に上記単結晶Si薄膜表面を酸化した後、最終的に基板を構成することになる基体を用意し、 [0019] Then after oxidizing the single-crystal Si thin film surface, eventually providing a substrate which will constitute the substrate,
単結晶Si表面の酸化膜と上記基体を貼り合わせる。 Bonding the oxide film and the substrate of the single crystal Si surface. 或いは新たに用意した単結晶Si基体の表面を酸化した後、上記多孔質Si基体上の単結晶Si層と貼り合わせる。 Or after oxidizing the freshly prepared surfaces of the monocrystalline Si substrate, bonded to the single-crystal Si layer on the porous Si substrate. この酸化膜を基体と単結晶Si層の間に設ける理由は、例えば基体としてガラスを用いた場合、Si活性層の下地界面により発生する界面準位は上記ガラス界面に比べて、酸化膜界面の方が準位を低くできるため、電子デバイスの特性を、著しく向上させることができるためである。 The reason for providing the oxide film between the substrate and the single crystal Si layer, for example when using glass as the substrate, the interface state caused by the underlying surface of the Si active layer as compared to the glass interface, the oxide film interface since it is possible to lower the level, the characteristics of the electronic device, it is because it is possible to remarkably improve. さらに、後述する選択エッチングにより多孔質Si気体をエッチング除去した単結晶Si薄膜のみを新しい基体に貼り合わせても良い。 Furthermore, it may be bonded only to the new base single-crystal Si thin film porous Si gas was removed by etching by selective etching to be described later. 貼り合わせはそれぞれの表面を洗浄後に室温で接触させるだけでファン デル ワールス力で簡単には剥すことができない程充分に密着しているが、これをさらに200〜900℃、好ましくは600〜900℃の温度で窒素雰囲気下熱処理し完全に貼り合わせる。 Bonding but is easily adhesion sufficiently enough can not detach it by simply van der Waals forces are contacted at room temperature for each of the surfaces after cleaning, further 200 to 900 ° C. This preferably 600 to 900 ° C. heat treatment under a nitrogen atmosphere at a temperature and bonded to complete.

【0020】さらに、上記の貼り合わせた2枚の基体全体にSi 34層をエッチング防止膜として堆積し、多孔質Si基体の表面上のSi 34層のみを除去する。 Furthermore, the Si 3 N 4 layer on the entire two substrates bonded together in the deposited as an etching prevention film is removed only Si 3 N 4 layer on the surface of porous Si substrate.
このSi 34層の代わりにアピエゾンワックスを用いても良い。 It may be used Apiezon wax in place of the Si 3 N 4 layer. この後、多孔質Si基体を全部エッチング等の手段で除去することにより薄膜単結晶Si層を有する半導体基板が得られる。 Thereafter, the semiconductor substrate having a thin film monocrystalline Si layer by removing the porous Si substrate by means of total etching is obtained.

【0021】この多孔質Si基体のみを無電解湿式エッチングする選択エッチング法についていて説明する。 [0021] To describes the the selective etching method to electroless wet etch only the porous Si substrate.

【0022】結晶Siに対してはエッチング作用を持たず、多孔質Siのみを選択エッチング可能なエッチング液としては、弗酸、フッ化アンモニウム(NH 4 F)やフッ化水素(HF)等バッファード弗酸、過酸化水素水を加えた弗酸又はバッファード弗酸の混合液、アルコールを加えた弗酸又はバッファード弗酸の混合液、過酸化水素水とアルコールとを加えた弗酸又はバッファード弗酸の混合液が好適に用いられる。 [0022] no etching effect on crystal Si, as the only selective etchable etchant porous Si, hydrofluoric acid, ammonium fluoride (NH 4 F) and hydrogen fluoride (HF) or the like buffered hydrofluoric acid, hydrofluoric acid or buffer was added a mixture of aqueous hydrogen peroxide was added hydrofluoric acid or buffered hydrofluoric acid, a mixed solution of hydrofluoric acid or buffered hydrofluoric acid plus alcohol, and aqueous hydrogen peroxide and alcohol a mixture of hydrofluoric acid is preferably used. これらの溶液に貼り合わせた基板を湿潤させてエッチングを行う。 Wetted substrate was bonded to these solutions etching is performed. エッチング速度は弗酸、バッファード弗酸、過酸化水素水の溶液濃度及び温度に依存する。 The etching rate depends on hydrofluoric acid, buffered hydrofluoric acid, the solution concentration and temperature of the hydrogen peroxide. 過酸化水素水を添加することによって、Siの酸化を増速し、反応速度を無添加に比べて増速することが可能となり、さらに過酸化水素水の比率を変えることにより、その反応速度を制御することができる。 By addition of hydrogen peroxide, Hayashi increase the oxidation of Si, it is possible to increase speed than the reaction rate without addition, by further changing the ratio of hydrogen peroxide, the reaction rate it is possible to control. またアルコールを添加することにより、エッチングによる反応生成気体の気泡を、瞬時にエッチング表面から攪拌することなく除去でき、均一に且つ効率よく多孔質Siをエッチングすることができる。 Also by the addition of alcohol, bubbles of reaction product gases by etching instantaneously can be removed without agitation from the etched surface can be etched uniformly and efficiently porous Si.

【0023】バッファード弗酸中のHF濃度は、エッチング液に対して、好ましくは1〜95重量%、より好ましくは1〜85重量%、さらに好ましくは1〜70重量%の範囲で設定され、バッファード弗酸中のNH 4 F濃度は、エッチング液に対して、好ましくは1〜95重量%、より好ましくは5〜90重量%、さらに好ましくは5〜80重量%の範囲で設定される。 The HF concentration in the buffered hydrofluoric acid with respect to the etching solution, preferably 1 to 95 wt%, more preferably 1 to 85 wt%, more preferably set in a range of 1 to 70 wt%, NH 4 F concentration in the buffered hydrofluoric acid with respect to the etching solution, preferably 1 to 95 wt%, more preferably 5 to 90 wt%, more preferably set in a range of 5 to 80 wt%.

【0024】HF濃度は、エッチング液に対して、好ましくは1〜95重量%、より好ましくは5〜90重量%、さらに好ましくは5〜80重量%の範囲で設定される。 The HF concentration with respect to the etching solution, preferably 1 to 95 wt%, more preferably 5 to 90 wt%, more preferably set in a range of 5 to 80 wt%.

【0025】H 22濃度は、エッチング液に対して、 [0025] H 2 O 2 concentration with respect to the etching solution,
好ましくは1〜95重量%、より好ましくは5〜90重量%、さらに好ましくは10〜80重量%で、且つ上記過酸化水素水の効果を奏する範囲で設定される。 Preferably 1 to 95% by weight, more preferably 5 to 90 wt%, more preferably 10 to 80 wt%, is set in a range and the effect of the hydrogen peroxide.

【0026】アルコール濃度は、エッチング液に対して、好ましくは80重量%、より好ましくは60重量% The concentration of alcohol with respect to the etching solution, preferably 80% by weight, more preferably 60 wt%
以下、さらに好ましくは40重量%以下で、且つ上記アルコールの効果を奏する範囲で設定される。 Or less, more preferably 40 wt% or less, is set in a range and the effect of the alcohol.

【0027】温度は、好ましくは0〜100℃、より好ましくは5〜80℃、さらに好ましくは5〜60℃の範囲で設定される。 The temperature is preferably 0 to 100 ° C., more preferably 5 to 80 ° C., and more preferably set in the range of 5 to 60 ° C..

【0028】本工程に用いられるアルコールはエチルアルコールの他、イソプロピルアルコールなど製造工程等に実用上差し支えなく、さらに上記アルコール添加効果を望むことのできるアルコールを用いることができる。 The alcohol used in this process Other ethyl alcohol, not harm practically the manufacturing process or the like such as isopropyl alcohol, can be further used an alcohol capable of overlooking the alcohol addition effect.

【0029】このようにして得られた半導体基板は、通常のSiウエハーと同等な単結晶Si層が平坦にしかも均一に薄層化されて基板全域に大面積に形成されている。 The semiconductor substrate thus obtained, the equivalent single-crystal Si layer and the ordinary Si wafer is formed in a large area in the whole substrate is flat and uniform thinned.

【0030】この半導体基板の単結晶Si層を部分酸化法或いは島状にエッチングすることにより分離し、不純物をドープしてp或いはnチャネルトランジスタを形成する。 [0030] The single crystal Si layer of the semiconductor substrate is separated by etching the partial oxidation method or islands, the impurity is doped to form a p or n-channel transistor.

【0031】 [0031]

【実施例】以下、実施例により本発明を詳細に説明する。 EXAMPLES The following examples illustrate the present invention in detail.

【0032】(実施例1)図1は本実施例のコンタクト構造の断面図である。 [0032] (Embodiment 1) FIG. 1 is a cross-sectional view of the contact structure of the present embodiment. 図1において、ガラス基板101 In Figure 1, a glass substrate 101
上にポリシリコンTFTが形成され、絶縁膜106を介してITO膜108が形成されている。 Polysilicon TFT is formed on the upper, ITO film 108 is formed over the insulating film 106. 102〜105 102 to 105
はそれぞれポリシリコンTFTのチャンネル部、層間絶縁膜、ゲート電極、ソース・ドレイン領域である。 Each channel of the polysilicon TFT, the interlayer insulating film, a gate electrode, a source-drain region.

【0033】本実施例においては酸素がソースドレイン領域105まで拡散しない様に、ソースドレイン領域1 [0033] As the oxygen in this embodiment do not diffuse to the source drain region 105, source drain regions 1
05とITO膜108の接触部にバリアメタルとしてT T to the contact portion 05 and the ITO film 108 as a barrier metal
i化合物107を設けている。 The i Compound 107 is provided. Ti化合物107を形成することにより、ITO膜108に含まれる酸素が後工程の熱処理によってソースドレイン領域105まで移動し、コンタクト特性を劣化することを防止できる。 By forming the Ti compound 107, moved to the source drain region 105 by the heat treatment in the subsequent step of oxygen contained in the ITO film 108 can be prevented from being deteriorated the contact characteristics.

【0034】以下、図2を用いて製造工程の概略を説明する。 [0034] Hereinafter, an outline of the manufacturing process will be described with reference to FIG.

【0035】図2(a)に示す様にガラス基板201にチャンネル部となる多結晶シリコン202を形成し、パターニング後、ゲート膜203を形成する。 [0035] The polycrystalline silicon 202 serving as a channel portion is formed on a glass substrate 201 as shown in FIG. 2 (a), after patterning, to form the gate layer 203.

【0036】続いて、図2(b)に示す様に、ゲート電極204を形成し、パターニング後、ゲート電極204 [0036] Subsequently, as shown in FIG. 2 (b), a gate electrode 204, after patterning, the gate electrode 204
をマスクとしてソース・ドレイン205をイオン注入した後、層間絶縁膜206を形成する。 After ion implantation of the source and drain 205 as a mask, the interlayer insulating film 206.

【0037】更に、図2(c)に示す様に、ソース・ドレイン領域205にRIEを用いてスルーホール(コンタクト)窓開けを行う。 Furthermore, as shown in FIG. 2 (c), performing the open through holes (contact) window by RIE on the source and drain regions 205. 続いてCVD法、またはスパッタ法を用いてTi207を形成する。 Subsequently forming a Ti207 using CVD method or sputtering method. 膜厚は500オングストローム以上であれば、酸素に対する阻止能は十分であるが、成膜方法等により粒径等が異なることにより1000オングストローム以上が望ましい。 If the film thickness is 500 angstroms or more, but stopping power for oxygen is sufficient, more than 1000 Å by the particle diameter and the like are different desirable by a deposition method or the like.

【0038】その後、このTi層207をパターニングし、ITOを形成する。 [0038] Then, the Ti layer 207 is patterned to form the ITO. ITOはスパッタ法により形成するのがよい。 ITO is preferably formed by sputtering. CVD法では、ITOの酸素含有量により膜特性が変化するため、抵抗値の小さいITOを形成するのは困難である。 In the CVD method, for changing the film properties by the oxygen content of the ITO, it is difficult to form a small resistance ITO.

【0039】ITOの蒸着条件は、基板温度200℃、 The deposition conditions of the ITO, substrate temperature 200 ° C.,
ArとO 2 (1%)の雰囲気中(1Pa)、300Wのパワーでスパッタした。 In an atmosphere of Ar and O 2 (1%) (1Pa ), it was sputtered at power of 300 W.

【0040】その後、コンタクト抵抗の測定を行った。 [0040] This was followed by the measurement of the contact resistance.
3μm×3μmのコンタクトサイズにおいて、50Ω以下のコンタクト抵抗を得ることができた。 In contact size of 3 [mu] m × 3 [mu] m, it was possible to obtain the following contact resistance 50 [Omega.

【0041】(実施例2)Ti107をTiONまたはTiNとした以外は実施例1と同様にして、実施例1に比べコンタクト抵抗は更に低減され、20Ω以下のコンタクト抵抗を得ることができた。 [0041] except that (Example 2) Ti107 was TiON or TiN in the same manner as in Example 1, is further reduced contact resistance compared with Example 1, were obtained following the contact resistance 20 [Omega. また、膜厚を1000 In addition, the film thickness 1000
オングストロームから2000オングストロームに増加するとコンタクト抵抗は更に安定した。 Contact resistance was more stable and increases from angstroms to 2000 angstroms.

【0042】(実施例3)図3は本実施例のコンタクト構造の断面図である。 [0042] (Embodiment 3) FIG. 3 is a sectional view of the contact structure of the present embodiment. スルーホールを開けた後、Al1 After opening the through-hole, Al1
11とTiN又はTiON107を連続でスパッタしてパターニング後、ITO膜108を堆積した以外は実施例1と同様である。 After patterning of the 11 and TiN or TiON107 by sputtering in a continuous, except that the deposition of the ITO film 108 are the same as in the first embodiment.

【0043】スルーホールサイズが2〜2.5μm□においても30〜50Ωのコンタクト抵抗を維持することができた。 The through-hole size was able to maintain the contact resistance of 30~50Ω also in 2~2.5μm □.

【0044】本実施例によれば、Siの不純物濃度が1 [0044] According to this embodiment, impurity concentration of Si 1
20以下と低い場合でも良好なコンタクト特性を得ることができる。 Even if 0 20 or less and low it is possible to obtain a good contact characteristic.

【0045】 [0045]

【発明の効果】以上説明の様に、本発明によれば、良好かつ安定なコンタクト特性を有する半導体装置を得ることができ、該半導体装置を適用することにより、画像品質の高い液晶表示装置、光電交換装置を得ることができる。 As the foregoing description, according to the present invention, it is possible to obtain a semiconductor device having a good and stable contact characteristics, by applying the semiconductor device, high image quality liquid crystal display device, it is possible to obtain a photoelectric switching apparatus.

【図面の簡単な説明】 BRIEF DESCRIPTION OF THE DRAWINGS

【図1】実施例1のコンタクト構造の断面図。 FIG. 1 is a cross-sectional view of the contact structure of the first embodiment.

【図2】実施例1のコンタクト構造の概略工程図。 2 is a schematic process diagram of a contact structure of the first embodiment.

【図3】実施例3のコンタクト構造の断面図。 3 is a cross-sectional view of a contact structure of Embodiment 3.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl. 5識別記号 庁内整理番号 FI 技術表示箇所 H01L 31/04 ────────────────────────────────────────────────── ─── front page continued (51) Int.Cl. 5 in identification symbol Agency Docket No. FI art display portion H01L 31/04

Claims (1)

    【特許請求の範囲】 [The claims]
  1. 【請求項1】ITO薄膜とSi領域との間に少なくともTi化合物よりなる層を設けたことを特徴とする半導体装置。 1. A semiconductor device characterized in that a layer made of at least a Ti compound between the ITO film and the Si region.
JP7598192A 1992-02-28 1992-02-28 Semiconductor device Pending JPH05243579A (en)

Priority Applications (1)

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JP7598192A JPH05243579A (en) 1992-02-28 1992-02-28 Semiconductor device
US08/021,670 US5650664A (en) 1992-02-28 1993-02-24 Connector effecting an improved electrical connection and a semiconductor apparatus using such connector
DE1993621499 DE69321499D1 (en) 1992-02-28 1993-02-25 Electrical connection between a silicon surface and an oxide layer having an indium content
DE1993621499 DE69321499T2 (en) 1992-02-28 1993-02-25 Electrical connection between a silicon surface and an oxide layer having an indium content
EP19930102982 EP0558007B1 (en) 1992-02-28 1993-02-25 Electrical connection between a region of silicon and a film of oxide containing indium

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EP0558007A2 (en) 1993-09-01
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DE69321499D1 (en) 1998-11-19
US5650664A (en) 1997-07-22

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