JPH05243579A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device which exhibits excellent contact characteristics and has a high speed and a low power consumption by providing at least a layer made of Ti compound between an ITO thin film and an Si region. CONSTITUTION:A polycrystalline silicon 202 to become a channel is formed on a glass board 201, patterned, a gate film 203 is then formed, a gate electrode 204 is formed, patterned, source.drain 205 are then ion implanted with the patterned electrode as a mask, and then an interlayer insulating film 206 is formed. Then, a through hole window is opened at the region 205 by RIE, Ti 207 is then formed by a CVD method or a sputtering method, and patterned to form an ITO. A contact resistance is measured, and a contact resistance of 50OMEGA or less can be obtained in a contact size of 3X3mum. A semiconductor device which has excellent and stable contact characteristics can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having stable and excellent contact characteristics, which can be suitably used for liquid crystal display devices, photoelectric exchange devices and the like.

[0002]

2. Description of the Related Art Conventionally, as a contact structure between an n-type or p-type Si film and an ITO film, a structure in which the Si film and the ITO film are directly contacted with each other (JP-A-58-190063), S
A structure in which i and the ITO film are in contact with each other through a barrier metal such as In or Sn (Japanese Patent Laid-Open No. 59-22361,
JP-A-59-40582) and the like.

However, it is difficult to make ohmic contact with the above-mentioned conventional method, or the contact resistance value is KΩ.
There is also a problem that the contact value further increases in the step of depositing the interlayer insulating film (heat treatment at 250 ° C. or higher) after vapor deposition of ITO, which causes a large variation in electronic characteristics and a large delay time. However, this has caused a decrease in reliability.

[0004]

SUMMARY OF THE INVENTION The present invention solves the above problems and provides a high speed and low power consumption semiconductor device exhibiting excellent contact characteristics, and further, a liquid crystal having high image quality using the semiconductor device. An object is to provide a display device and a photoelectric conversion device.

[0005]

That is, the present invention is a semiconductor device characterized in that a layer made of at least a Ti compound is provided between an ITO thin film and a Si region.

The semiconductor device of the present invention may be formed on a glass substrate or a Si substrate.

In particular, when the semiconductor device of the present invention is applied to a liquid crystal display device, by using a semiconductor substrate having a single crystal Si layer manufactured by the method described below,
A liquid crystal element, a liquid crystal drive circuit and other peripheral drive circuits can be simultaneously formed on the same substrate, which is preferable. The method will be described below.

The single crystal Si layer of the semiconductor substrate is formed by using a porous Si substrate obtained by making the single crystal Si substrate porous.

According to observation with a transmission electron microscope, pores having an average diameter of about 600 Å are formed in this porous Si substrate, and the density thereof is less than half that of single crystal Si. Nevertheless, its single crystallinity is maintained, and it is possible to epitaxially grow a single crystal Si layer on top of the porous layer. However, at 1000 ° C. or higher, rearrangement of internal holes occurs and the characteristics of enhanced etching are impaired. Therefore, for the epitaxial growth of the Si layer, the molecular beam epitaxial growth method, plasma CV
Low temperature growth such as D method, thermal CVD method, photo CVD method, bias sputtering method, liquid crystal growth method, etc. is suitable.

Here, a method for epitaxially growing a single crystal layer after making P-type Si porous will be described.

First, a Si single crystal substrate is prepared, and H
It is made porous by the anodization method using the F solution. The density of single crystal Si is 2.33 g / cm ³ , but the density of the porous Si substrate changes to 0.6 to 1.1 g / cm ³ by changing the HF solution concentration to 20 to 50% by weight. Can be made. This porous layer is P because of the following reasons.
It is easily formed on the mold Si substrate.

Porous Si was discovered in the course of research on electrolytic polishing of semiconductors, and Si in anodization was used.
In the dissolution reaction of 1), holes are required for the anodic reaction of Si in the HF solution, and the reaction is shown as follows.

Si + 2HF + (2-n) e ⁺ → SiF ₂ + 2H ⁺ + ne ^- SiF ₂ + 2HF → SiF ₄ + H ₂ SiF ₄ + 2HF → H ₂ SiF ₆ or Si + 4HF + (4-λ) e ⁺ → SiF ₄ + 4H ⁺ + λe ^- where _{SiF 4 + 2HF → H 2 SiF} 6, e + and, e ^- respectively represent a positive hole and an electron. Further, n and λ are the numbers of holes necessary for dissolving Si1 atoms, respectively, and porous Si is formed when the condition of n> 2 or λ> 4 is satisfied.

From the above, P-type Si in which holes are present
Can easily be said to be porous.

On the other hand, it has been reported that high-concentration N-type Si can also be made porous, so that it can be made porous regardless of whether it is P-type or N-type.

Further, since the porous layer has a large amount of voids formed therein, the density thereof is reduced to less than half. As a result, the surface area increases dramatically compared to the volume,
Its chemical etching rate is significantly increased as compared with the etching rate of a normal single crystal layer.

The conditions for making single crystal Si porous by anodization are shown below. The starting material of porous Si formed by anodization is not limited to single crystal Si, and Si having another crystal structure may be used.

Applied voltage: 2.6 (V) Current density: 30 (mA · cm ⁻² ) Anodizing solution: HF: H ₂ O: C ₂ H ₅ OH = 1: 1
1: 1 time: 2.4 (hour) Thickness of porous Si: 300 (μm) Porosity: 56 (%) Single crystal Si thin film prepared by epitaxially growing Si on the porous Si substrate thus formed. To form.
The thickness of the single crystal Si thin film is preferably 50 μm or less, more preferably 20 μm or less.

Next, after oxidizing the surface of the above-mentioned single crystal Si thin film, a substrate which will eventually form a substrate is prepared,
The oxide film on the surface of the single crystal Si and the above substrate are bonded together. Alternatively, after the surface of a newly prepared single crystal Si substrate is oxidized, it is attached to the single crystal Si layer on the porous Si substrate. The reason for providing this oxide film between the substrate and the single crystal Si layer is that, for example, when glass is used as the substrate, the interface level generated by the underlying interface of the Si active layer is higher than that of the glass interface. This is because the level can be lowered and the characteristics of the electronic device can be significantly improved. Furthermore, only the single crystal Si thin film from which the porous Si gas has been removed by etching by selective etching described below may be attached to a new substrate. The bonding is such that the surfaces are sufficiently adhered so that they cannot be easily peeled off by Van der Waals force only by bringing them into contact with each other at room temperature, but this is further 200 to 900 ° C, preferably 600 to 900 ° C. Heat treatment under a nitrogen atmosphere at the temperature of and bond them completely.

Further, a Si ₃ N ₄ layer is deposited as an etching prevention film on the whole of the above-mentioned two bonded substrates, and only the Si ₃ N ₄ layer on the surface of the porous Si substrate is removed.
Apiezon wax may be used instead of the Si ₃ N ₄ layer. Then, the porous Si substrate is entirely removed by a method such as etching to obtain a semiconductor substrate having a thin film single crystal Si layer.

A selective etching method for electroless wet etching only this porous Si substrate will be described.

As an etching solution which does not have an etching effect on crystalline Si but can selectively etch only porous Si, a buffered material such as hydrofluoric acid, ammonium fluoride (NH ₄ F) or hydrogen fluoride (HF) can be used. Hydrofluoric acid, mixed solution of hydrofluoric acid or buffered hydrofluoric acid with hydrogen peroxide solution, hydrofluoric acid with alcohol or buffered hydrofluoric acid, hydrofluoric acid with hydrogen peroxide solution and alcohol or buffer A mixed solution of dehydrofluoric acid is preferably used. Etching is performed by moistening the substrate bonded to these solutions. The etching rate depends on the solution concentration and temperature of hydrofluoric acid, buffered hydrofluoric acid, and hydrogen peroxide solution. By adding hydrogen peroxide solution, the oxidation of Si can be accelerated and the reaction rate can be increased as compared with that without addition. By further changing the ratio of hydrogen peroxide solution, the reaction rate can be increased. Can be controlled. Further, by adding alcohol, it is possible to instantaneously remove the bubbles of the reaction product gas due to etching from the etching surface without stirring, and it is possible to uniformly and efficiently etch the porous Si.

The HF concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 1 to 85% by weight, still more preferably 1 to 70% by weight, based on the etching solution. The NH ₄ F concentration in the buffered hydrofluoric acid is set in the range of preferably 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The HF concentration is preferably set in the range of 1 to 95% by weight, more preferably 5 to 90% by weight, further preferably 5 to 80% by weight, based on the etching solution.

The H ₂ O ₂ concentration depends on the etching solution.
It is preferably 1 to 95% by weight, more preferably 5 to 90% by weight, still more preferably 10 to 80% by weight, and is set within a range in which the effect of the hydrogen peroxide solution is exhibited.

The alcohol concentration is preferably 80% by weight, more preferably 60% by weight, based on the etching solution.
Hereafter, it is more preferably set to 40% by weight or less and within the range in which the effect of the alcohol is exhibited.

The temperature is preferably set in the range of 0 to 100 ° C, more preferably 5 to 80 ° C, and further preferably 5 to 60 ° C.

As the alcohol used in this step, in addition to ethyl alcohol, isopropyl alcohol or the like which can be used practically in the production step and which is desired to have the above-mentioned alcohol addition effect can be used.

In the semiconductor substrate thus obtained, a single crystal Si layer equivalent to that of an ordinary Si wafer is flatly and uniformly thinned to have a large area over the entire substrate.

The single crystal Si layer of this semiconductor substrate is separated by a partial oxidation method or etched into an island shape, and is doped with impurities to form a p- or n-channel transistor.

[0031]

The present invention will be described in detail below with reference to examples.

(Embodiment 1) FIG. 1 is a sectional view of a contact structure of this embodiment. In FIG. 1, a glass substrate 101
A polysilicon TFT is formed on top, and an ITO film 108 is formed via an insulating film 106. 102-105
Are a channel portion of a polysilicon TFT, an interlayer insulating film, a gate electrode, and a source / drain region, respectively.

In this embodiment, the source / drain region 1 is formed so that oxygen does not diffuse to the source / drain region 105.
05 as a barrier metal at the contact portion between the ITO film and the ITO film 108.
i-compound 107 is provided. By forming the Ti compound 107, it is possible to prevent the oxygen contained in the ITO film 108 from moving to the source / drain region 105 due to the heat treatment in the subsequent step and deteriorating the contact characteristics.

The manufacturing process will be outlined below with reference to FIG.

As shown in FIG. 2A, a polycrystalline silicon 202 which will be a channel portion is formed on a glass substrate 201, and after patterning, a gate film 203 is formed.

Subsequently, as shown in FIG. 2B, a gate electrode 204 is formed and patterned, and then the gate electrode 204 is formed.
After the source / drain 205 is ion-implanted using as a mask, an interlayer insulating film 206 is formed.

Further, as shown in FIG. 2C, a through hole (contact) window is formed in the source / drain region 205 by using RIE. Subsequently, Ti 207 is formed by using the CVD method or the sputtering method. If the film thickness is 500 angstroms or more, the ability to block oxygen is sufficient, but it is preferably 1000 angstroms or more because the particle size and the like vary depending on the film forming method and the like.

Then, the Ti layer 207 is patterned to form ITO. ITO is preferably formed by a sputtering method. In the CVD method, it is difficult to form ITO having a small resistance value because the film characteristics change depending on the oxygen content of ITO.

The ITO deposition conditions are: substrate temperature 200 ° C.
Sputtering was performed at a power of 300 W in an atmosphere of Ar and O ₂ (1%) (1 Pa).

After that, the contact resistance was measured.
With a contact size of 3 μm × 3 μm, a contact resistance of 50Ω or less could be obtained.

(Example 2) The contact resistance was further reduced as compared with Example 1 except that Ti107 was TiON or TiN, and a contact resistance of 20Ω or less could be obtained. In addition, the film thickness is 1000
The contact resistance became more stable when increasing from angstrom to 2000 angstrom.

(Embodiment 3) FIG. 3 is a sectional view of a contact structure of this embodiment. After opening the through hole, Al1
Example 11 is the same as Example 1 except that the ITO film 108 was deposited after 11 and TiN or TiON 107 were successively sputtered and patterned.

A contact resistance of 30 to 50Ω could be maintained even when the through hole size was 2 to 2.5 μm.

According to this embodiment, the impurity concentration of Si is 1
Good contact characteristics can be obtained even when it is as low as 0 ²⁰ or less.

[0045]

As described above, according to the present invention, a semiconductor device having good and stable contact characteristics can be obtained, and by applying the semiconductor device, a liquid crystal display device having high image quality, A photoelectric conversion device can be obtained.

[Brief description of drawings]

FIG. 1 is a sectional view of a contact structure of Example 1.

2A to 2C are schematic process diagrams of the contact structure of Example 1. FIG.

FIG. 3 is a cross-sectional view of a contact structure of Example 3.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 31/04

Claims (1)

[Claims] 1. A semiconductor device comprising a layer made of at least a Ti compound between an ITO thin film and a Si region.