JPH10293322A - Liquid crystal display and manufacture therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display not causing a malfunction by the light, integrally molded with a driving circuit. SOLUTION: This liquid crystal display has a picture element switch 3 composed of a nonmonocrystal semiconductor in a position where data wiring and scanning wiring in an image display part cross each other and has an active matrix base board having a peripheral driving circuit 4, which drives the picture element switch and is composed of a monocrystal semiconductor, on a periphery of the image display part and a counter base board 8 opposed to the active matrix base board through a liquid crystal material 10. The picture element switch 3 and the peripheral driving circuit 4 are formed on base boards 1 and 2 on which at least a surface has insulating performance. Therefore, the switch 3 of a picture element part composed of a polycrystal semiconductor, does not cause a malfunction by the light, and becomes highly reliable. Therefore, a high definition liquid crystal display can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a glass substrate or
It is an object of the present invention to provide a high-definition, high-pixel active matrix liquid crystal display device formed on an insulating semiconductor substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, display devices have been widely used mainly for CRTs, but in recent years, flat displays of liquid crystal display have become quite popular. In a relatively large liquid crystal display device, stripe-shaped electrodes are provided on two opposing parallel flat glass plates, and two plates are arranged so that the electrodes face each other at right angles. Liquid crystal is injected into the gap. A so-called simple matrix type is often used. In this case, a drive IC for applying a voltage to the pixel region is to bond an IC chip formed on a semiconductor substrate to a glass substrate later.

On the other hand, a small and high-definition liquid crystal display device requires an active matrix type display device in which a switching transistor is provided for each pixel. Almost all electronic viewfinders (EVF) and the like currently mounted on video integrated cameras are of this type. This active matrix type liquid crystal display device will be described.

FIG. 15 shows a schematic configuration diagram of a drive circuit of a conventionally used active matrix liquid crystal display device. 401 is a pixel switch, 405 is a liquid crystal pixel, 40
Reference numeral 6 denotes a transparent substrate, 402 denotes a buffer unit, 403 denotes a horizontal shift register unit, and 404 denotes a vertical shift register unit. The luminance signal and audio signal of the television are compressed into a certain band, driven by a horizontal shift register 403 having a driving ability capable of following the frequency, and sent to a buffer unit 402. Next, a signal is transferred to the liquid crystal by the vertical shift register 404 while the pixel switch 401 is ON. 407 is a vertical shift register 4
This is a scanning line for sending a scanning signal from the pixel switch 401 to the pixel switch 401. Reference numeral 408 denotes a data line for sending a luminance signal from the buffer unit 402.

[0005] The performance required of each circuit is as follows, considering a high-definition television, a frame frequency is 60 Hz, the number of scanning lines is about 1,000, and a horizontal scanning period is about 30 μsec. If the number of horizontal pixels is about 1500 (effective scanning period 27 μsec.), The television signal is transferred to the buffer unit at a frequency of about 45 MHz. Therefore, the performance required of each element circuit is as follows: 1) The driving capability of the horizontal shift register is 45 MHz or more. 2) The driving capability of the vertical shift register is 500 kHz
that's all. 3) The drive capability of the transfer switch driven by the horizontal register and transferring the TV signal to the buffer unit is 4
5MHz or more. 4) The driving capability of the pixel switch is 500 kHz or more. It turns out that. The driving capability referred to here is a voltage that gives the maximum or minimum transmittance of the liquid crystal when trying to obtain a certain number of gradations N in a liquid crystal pixel.
Assuming that the threshold voltage of the liquid crystal obtained from the transmittance curve) is Vt, it means that a voltage equal to or higher than Vm- (Vm-Vt) / N [V] is transferred within the above period.

As is apparent from the above, the pixel switches and the vertical shift registers may have relatively small driving capacities, but the horizontal shift registers and the buffer units require high-speed driving. As described above, conventionally, pixel switches and vertical shift registers are monolithically formed with liquid crystal using polycrystalline or amorphous silicon TFTs deposited on a glass substrate, and other peripheral circuits are handled by mounting an IC chip from the outside I've been. However, as the size of the screen becomes smaller, it becomes more difficult to provide an external drive circuit. In particular, when the number of pixels is increased in order to increase the resolution of the screen, connecting the driving IC and the signal line to each switching transistor by wire bonding is disadvantageous not only in terms of cost but also technically. It becomes extremely difficult.

At present, attempts have been made to monolithically form peripheral circuits using polycrystalline silicon. However, since the driving capability of each TFT is small, it is necessary to increase the transistor size or to make the circuit complicated. Has become. If the driving capability of the peripheral circuit is to be increased more than that using polycrystalline silicon, this is nothing more than using monocrystalline silicon. However, few techniques have been reported for forming a single-crystal thin film on a glass substrate with a uniform thickness and good controllability. Among the reported examples, a method of providing a high-quality single-crystal silicon thin film on a glass substrate includes a method using a wafer bonding technique and a porous silicon selective etching technique (Japanese Patent Laid-Open No. 21338/1993).

[0008]

SUMMARY OF THE INVENTION Even if a single-crystal silicon thin film can be formed on a transparent substrate or an insulating semiconductor substrate, and a switching transistor and peripheral circuits can be monolithically formed in a liquid crystal display device using the same, there is another problem. Problems may occur. That is, the material of single crystal silicon is not only an overspec for a pixel switching transistor, but also generates light carriers in the layer when light (for example, backlight of liquid crystal display) is applied, and the transistor is turned off. However, this causes a so-called light leak that generates a current in spite of the above. For this reason, all the pixels are in the same state as the ON state, and as a result, the screen becomes white.

That is, as described above, the higher the charge mobility in the semiconductor layer is, the faster the semiconductor device can be driven. However, the higher the charge mobility in the semiconductor layer is, the more the TFT is turned off. The leakage current increases.
This causes a problem that a light leakage current excited by light incident on the TFT from the outside increases. In the case of the above amorphous silicon TFT, the leakage current at the time of OFF is about 10 ⁻¹¹ to 10 ⁻¹³ A, whereas
In the case of a polycrystalline silicon TFT, the leakage current at the time of OFF is about 10 ⁻⁹ to 10 ⁻¹⁰ A. This is because the specific resistance of polycrystalline silicon is lower than that of amorphous silicon. In the case of a polycrystalline silicon TFT, a dual gate or L
At present, the TFT structure is improved and used, such as adoption of the DD system.
In a single-crystal silicon TFT having a lower specific resistance than T and a large leak current at the time of OFF, a more complicated device is required. The above-described increase in the light leakage current is caused by, for example, a light-transmissive TFT active matrix liquid crystal display device having an illuminance of 1400 to 1600 LX by a backlight having a luminance of 3000 to 4000 cd / m ² .
When a polycrystalline silicon element is used as a TFT, 10
A contrast of 0: 1 or more can be obtained, but when a single crystal silicon element (SOI element) is used, 70 to
There may be a problem in display quality, such as the fact that only about 80: 1 contrast can be obtained.

In view of the above problems, the present invention provides a technique for monolithically forming a peripheral circuit having a high driving capability and a pixel switching transistor having no light leakage on a transparent substrate such as glass or an insulating semiconductor substrate. Offer to,
It is another object of the present invention to provide a high-density, high-definition liquid crystal display device and a method for manufacturing the same.

[0011]

Means for Solving the Problems In order to solve the above-mentioned problems, the present inventors have made intensive efforts and, as a result, have obtained the following invention. That is, the liquid crystal display device of the present invention includes a pixel switch made of a non-single-crystal semiconductor at a position where a data line and a scanning line intersect in the image display unit, and drives the pixel switch around the image display unit to drive the pixel switch. An active matrix substrate including a peripheral drive circuit made of a crystalline semiconductor,
In a liquid crystal display device having a counter substrate facing the active matrix substrate with a liquid crystal material interposed therebetween, the pixel switch and the peripheral driving circuit are formed on a substrate having at least an insulating surface. I do. Here, the substrate having at least an insulating surface may be a quartz substrate or a semiconductor substrate having an insulating layer on the surface.

The present invention also includes an invention of a method for manufacturing a liquid crystal display device. That is, the manufacturing method of the liquid crystal display device of the present invention includes a pixel switch made of a non-single-crystal semiconductor at a position where a data wiring and a scanning wiring in the image display section intersect, and the pixel switch is provided around the image display section. A step of manufacturing the active matrix substrate in a method of manufacturing a liquid crystal display device having an active matrix substrate which is driven and has a peripheral driving circuit made of a single crystal semiconductor, and a counter substrate which faces the active matrix substrate via a liquid crystal material; Forming a porous semiconductor layer on the surface of the semiconductor substrate, forming a non-porous semiconductor layer on the surface of the porous semiconductor layer, forming an insulating layer on the surface of the non-porous semiconductor layer, the semiconductor substrate Removing the porous semiconductor layer, forming the peripheral drive circuit in the non-porous semiconductor layer, and removing the non-porous Remove the semiconductor layer,
Forming the pixel switch on the insulating layer. Here, when an insulating layer is formed on the surface of the non-porous semiconductor layer, a quartz substrate may be attached or a semiconductor substrate having an insulating layer on the surface may be attached.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1 First, a method of forming a single-crystal silicon thin film on a transparent substrate in the present invention will be described with reference to FIGS.

(FIG. 1A) Single crystal silicon substrate 100
Is anodized to form porous silicon 101. At this time, the thickness for making the substrate porous may be several μm to several tens μm on one surface layer of the substrate. Alternatively, the entire substrate may be anodized. A method for forming porous silicon will be described with reference to FIG. First, a P-type single crystal silicon substrate 300 is prepared as a substrate. Although it is not impossible even with an N-type, in that case, it is necessary to limit the substrate to a low-resistance substrate, or to irradiate light to the substrate surface to promote generation of holes. The substrate 300 is set in an apparatus as shown in FIG. That is, one side of the substrate is in contact with the hydrofluoric acid-based solution 304, the negative electrode 306 is provided on the solution side, and the other side is in contact with the positive metal electrode 305. FIG.
As shown in (b), the positive electrode side 305 'is also the solution 304'.
The potential may be taken via the. In any case, porosity occurs from the negative electrode side in contact with the hydrofluoric acid-based solution. Generally, concentrated hydrofluoric acid (49% HF) is used as the hydrofluoric acid solution 304. It is not preferable to dilute with pure (H ₂ O), since etching occurs at a certain concentration, depending on the value of the flowing current. In addition, bubbles may be generated from the surface of the substrate 300 during anodization, and alcohol may be added as a surfactant for the purpose of efficiently removing the bubbles. As the alcohol, methanol, ethanol, propanol, isopropanol and the like are used. Alternatively, anodizing may be performed while stirring the solution using a stirrer instead of the surfactant. For the negative electrode 306, a material that is not eroded by the hydrofluoric acid solution, for example, gold (Au), platinum (Pt), or the like is used. The material of the positive electrode 305 may be a commonly used metal material, but when the anodization is performed on all the substrates 300, the hydrofluoric acid-based solution 304 is changed to the positive electrode 305.
Therefore, the surface of the positive electrode 305 may be coated with a metal film resistant to a hydrofluoric acid solution. The current value for performing anodization is several hundred mA / cm ² at the maximum, and the minimum value need not be zero. This value is determined within a range where good quality epitaxial growth can be performed on the surface of the porous silicon. Usually, when the current value is large, the rate of anodization increases, and at the same time, the density of the porous silicon layer decreases. That is, the volume occupied by the holes increases. This changes the conditions for epitaxial growth.

(FIG. 1B) On the porous layer 101 formed as described above, a non-porous single-crystal silicon layer 10 is formed.
2 is epitaxially grown. The epitaxial growth is performed by general thermal CVD, low pressure CVD, plasma CVD, molecular beam epitaxy, sputtering, or the like. The grown film thickness may be the same as the design value of the active layer thickness.

(FIG. 1C) The surface of the epitaxial layer 102 is oxidized (103). This is because, when the epitaxial layer is directly bonded to the supporting substrate in the next step, impurities tend to segregate at the bonding interface, and the number of dangling bonds at the interface increases, resulting in the characteristics of a thin film device. This is a cause of instability. However, this step is not necessarily essential, and may be omitted if a device configuration that does not cause the above phenomenon to be considered is considered.

In the case of oxidation, the thickness of the oxide film only needs to be thick enough not to be affected by the contamination from the air taken into the bonding interface.

(FIG. 1D) A substrate 100 having an oxidized epitaxial surface and a transparent insulating substrate 110 serving as a support substrate are prepared, and both substrates are cleaned and then bonded. The support substrate 110 includes quartz glass, crystallized glass, and other high heat resistant glass. The cleaning method is performed in accordance with a general step of cleaning a semiconductor substrate (for example, before oxidation). Pressing the entire surface of the substrate after bonding has the effect of increasing the bonding strength.

Then, the bonded substrates are heat-treated.
It is preferable that the heat treatment temperature is high. However, if the heat treatment temperature is too high, the porous layer 101 may cause a structural change or impurities contained in the substrate may diffuse into the epitaxial layer. You need to choose a time. Specifically, about 600 to 1100 ° C. is preferable. Some substrates cannot be heat-treated at high temperatures. For example, when the support substrate 110 is made of quartz glass, a temperature difference of 200 ° C.
The heat treatment can be performed only at a temperature lower than about. If the temperature is exceeded, the bonded substrates are peeled off or broken by stress. However, the heat treatment only needs to be able to withstand the stress during grinding or etching of the bulk silicon 100 performed in a later step. Therefore, even at a temperature of 200 ° C. or less, the process can be performed by optimizing the surface treatment conditions for activation.

(FIG. 1E) Next, the silicon substrate portion 100 and the porous portion 1 except the epitaxial growth layer 102 are left.
01 is selectively removed. First, the silicon substrate portion 100
Is ground with a surface grinder or the like, or an alkaline solution such as potassium hydroxide, ammonia water, or TM
AH (tetramethylammonium hydroxide)
And the like. In the case of etching, it is effective to perform the etching in a solution at a temperature of 80 ° C. or higher. Since the alkaline solution hardly etches SiO ₂ , if the supporting substrate is glass, only the silicon substrate portion can be selectively etched. It is also possible to remove by etching with hydrofluoric acid and nitric acid, or an acid mixture obtained by adding acetic acid or the like thereto. However, since the hydrofluoric-nitric acid-based etchant also slightly etches the supporting substrate, it is better to avoid using it for a long time.

Etching the silicon substrate portion 100,
Etching is temporarily stopped when the porous portion 101 is exposed, and the exposed porous portion 101 is selectively etched using a mixed solution of hydrofluoric acid / hydrogen peroxide or an alkaline solution. By appropriately controlling the concentration of the etching solution at this time, the etching selectivity between porous silicon and single crystal silicon can be about 100,000 times at the maximum. In the case of a hydrofluoric acid system, the concentration of the hydrofluoric acid is several percent to several ppm, preferably about 0.1% to 10 ppm. In the case of an alkaline system, ammonia, TMAH (tetramethylammonium hydroxide), ethylenediamine, and the like can be used. Etching is preferably performed at the same concentration as in the case of the hydrofluoric acid system. It is preferable to use an ultrasonic cleaning device in order to efficiently penetrate the etching solution into the porous holes at the time of etching, to promote etching, and to perform uniform etching. However, care must be taken because the etching rate is slightly increased by the ultrasonic wave.

Next, a procedure for forming a liquid crystal display device on the substrate obtained by the above steps will be described with reference to FIG.

(FIG. 2A) Single-crystal silicon thin film 202
In the transparent substrate 210 provided with the above, the region other than the transistor corresponding to the peripheral circuit of the liquid crystal display device and the entire pixel region are etched. That is, the transistors of the peripheral circuit are separated into mesas. This is because when a transistor is separated by LOCOS or the like, the area of the continuous portion of the film becomes large, and a slip or crack occurs in the thin film due to the internal stress due to a large difference in the thermal expansion coefficient between the glass substrate and the silicon film. It is. If the single crystal silicon film is an ultra-thin film of several hundred angstroms or the whole process is formed by a low-temperature process, the mesa separation is not required since the absolute value of the stress tends to be suppressed.

(FIG. 2B) In order to form a switching transistor in a pixel region, amorphous or polycrystalline silicon 203 is deposited. Deposition under reduced pressure CV
D, sputtering or the like is used.

(FIG. 2C) Amorphous or polycrystalline silicon deposited in regions other than the pixel switching transistor is etched.

(FIG. 2D) A peripheral driving circuit 204 and a pixel switching transistor 205 are formed by a normal semiconductor process.

(FIG. 2E) The liquid crystal 206 is sealed and mounted.

By performing the above-described steps, a liquid crystal display device having a high driving capability, in which peripheral circuits are provided on a single-crystal thin film on a transparent glass substrate and pixel transistors are provided on a non-single-crystal thin film, respectively. .

(Embodiment 2) FIG. 4 is a sectional view showing Embodiment 2 of a liquid crystal display device according to the present invention. Here, an insulating layer 2 is formed on a silicon substrate 1, and an amorphous silicon layer 3 and a single-crystal silicon layer 4 are formed on the insulating layer 2. At least one or more amorphous silicon elements 5 are provided on the amorphous silicon layer 3, and at least one or more single crystal silicon elements 6 are provided on the single crystal silicon layer 4. The amorphous silicon element 5 and the single crystal silicon element 6 are electrically connected. Immediately below the portion where the amorphous silicon layer 3 is formed, an exposed opening 7 of the insulating layer 2 from which the silicon substrate 1 has been removed is provided. Further, a liquid crystal 10 is sealed in a cover glass 8 arranged opposite to the amorphous silicon element 5 and a surrounding sealing material 9. Here, the amorphous silicon element 5 is a TFT.

The semiconductor device shown in FIG. 4 is a transmission type TFT active matrix liquid crystal display device. In the above structure, light incident from the outside passes through the liquid crystal layer, so that the display of the liquid crystal is visualized. Note that the liquid crystal display device requires an alignment film, a pixel electrode, a counter electrode, a filter, a polarizing plate, and the like, but these are omitted here.

FIGS. 5 and 6 are process diagrams showing a method of manufacturing the liquid crystal display device according to the present embodiment. Here, 1 to 10 correspond to FIG.
Is the same as The steps in FIG. 5 are as follows.
(A) An insulating layer 2 is formed on a silicon substrate 1. (B)
After patterning the insulating layer 2 to expose a part of the silicon substrate 1, the amorphous silicon layer 3 is laminated.
(C) Amorphous silicon layer 3 from the exposed portion of silicon substrate 1
Is recrystallized. However, the entire amorphous silicon layer 3 is not recrystallized, and the amorphous silicon layer 3 and the single-crystal silicon layer 4 are formed on the insulating layer 2. (D) An amorphous silicon element 5 and a single crystal silicon element 6 are formed on the amorphous silicon layer 3 and the single crystal silicon layer 4. Here, an nMOS transistor is used as the amorphous silicon element 5,
Only the CMOS transistor is shown as the single crystal silicon element 6. Although not shown, the amorphous silicon element 5 and the single crystal silicon element 6 are electrically connected by metal electrodes. Hereinafter, description will be made with reference to FIG.
(A) Cover glass 8 facing amorphous silicon element 5
Is disposed, the liquid crystal 10 is sealed, and the periphery is sealed with the sealing material 9. Although not shown here, a transparent insulating film, a transparent pixel electrode, an alignment film, and the like are formed on the amorphous silicon element 5, and a transparent insulating film, a transparent counter electrode, and an alignment film are formed on the cover glass 8. , A filter and the like are formed. Similarly, although not shown, an insulating protective film is formed on the single crystal silicon element 6. (B) A part of the silicon substrate 1 is removed, and an opening 7 is provided immediately below the amorphous silicon element 5. Thereby, the region where the amorphous silicon element 5 is formed becomes light-transmissive. Through the above steps, the transmission type TFT active matrix liquid crystal display device shown in FIG. 1 can be obtained.

An example in which the above-described semiconductor device is specifically manufactured using the steps shown in FIGS. Plane orientation <
100>, an oxide film is formed by thermal oxidation on a P-type silicon wafer having a diameter of 125 mm, a thickness of 625 μm, and a specific resistance of 0.1 Ωcm. Here, an oxygen / hydrogen mixed gas (O
₂ : H ₂ = 4: 6), temperature 1000 ° C., oxidation rate 4.3
This was performed under the condition of nm / min to form an oxide film having a thickness of 1.0 μm (pyrogenic oxidation). Next, RIE
After patterning the oxide film by (reactive ion etching) to expose a part of the p-type silicon wafer, an amorphous silicon layer is laminated by a low pressure CVD method. Here, temperature 570 ° C., pressure 18 Torr, Si
₂ H ₆ flow rate 10 sccm, N ₂ flow rate 3 slm, N ₂ 10%
The diluted Ph is added at a deposition rate of 110 nm / mi.
Under the condition of n, a p-type amorphous silicon layer having a thickness of 0.2 μm was laminated. At this time, the Ph concentration in the p-type amorphous silicon layer was 1 × 10 ¹¹ cm ⁻² .

Subsequently, the amorphous silicon layer is irradiated with a pulse beam of an argon laser having a diameter of 50 μm to melt the amorphous silicon layer from the exposed portion of the p-type silicon wafer.
By performing recrystallization, a single-crystal silicon layer having a thickness of 0.2 μm is formed over the oxide film. At this time, only the portion for forming the peripheral drive circuit is recrystallized, and the portion for forming the pixel switching element (the liquid crystal display portion) is not recrystallized and remains as an amorphous silicon layer. Thereafter, using a known semiconductor integrated circuit manufacturing process, a pixel switching element is formed in an nMOS configuration on an amorphous silicon layer, and a frequency drive circuit is formed in a CMOS configuration on a single crystal silicon layer. Here, the MOS transistor has a coplanar structure with gate self-alignment. The gate oxide film has a temperature of 1150 ° C. and an oxidation rate of 3.4 nm / m by dry oxidation.
It was formed under the condition of “in” and the thickness was 50 nm. Subsequently, after depositing a polycrystalline silicon layer having a thickness of 440 nm, anisotropic dry etching is performed to form a gate electrode. Here, using a low pressure CVD method, the temperature is 656 ° C., and the pressure is 0.
In a mixed gas of 25 Torr, SiH ₄ and H ₂ , Si
H ₄ partial pressure 0.15 Torr, deposition rate 300 nm / mi
n.

Thereafter, ion implantation is performed to form source / drain regions of the MOS transistor. Here, the dose is 2 × 10 ¹⁵ cm for the pixel switching element.
^-2 As ions are implanted to form the source / drain regions of the nMOS transistor, and the peripheral drive circuit is implanted with As ions at a dose of 1 × 10 ¹⁶ cm ^-2 to form the nMO transistor.
The source / drain regions of the S transistor are formed, and BF ₂ ions at a dose of 2 × 10 ¹⁵ cm ⁻² are implanted to form pMO.
Source / drain regions of the S transistor were formed. After the ion implantation, a heat treatment is performed in nitrogen at 1000 ° C. for 10 minutes. Subsequently, a 500 nm thick BPSG film (Borono-Phospho Silicate)
After stacking (Glass), anisotropic dry etching is performed to form a contact hole. Furthermore, a metal electrode material such as aluminum is deposited by a sputtering method,
A wiring portion is formed by performing dry etching on a predetermined wiring shape.

Subsequently, using a transparent electrode material such as ITO,
After forming a pixel electrode which also serves as a capacitor portion, the entire surface is covered with a transparent insulating film. Thereafter, a known liquid crystal display device assembling process is performed to manufacture a liquid crystal cell. Finally T at 90 ° C
MAH (tetramethylammonium hydroxide)
Is performed to remove a part of the p-type silicon wafer. Here, the thermal oxide film becomes an etching stopper layer. This makes the liquid crystal portion light transmissive.

The transmissive TFT active matrix liquid crystal display device shown in the second embodiment can be integrally mounted with a peripheral drive circuit having higher performance than the conventional one.

The method of manufacturing the transmission type TFT active matrix liquid crystal display device shown in the present embodiment is not limited to the above-described specific examples, but various methods and conditions can be applied. For example, the amorphous silicon layer may be formed by a glow discharge method, an arc discharge method, a reactive sputtering method, a thermal CVD method, a photo CVD method, in addition to the above-described low pressure CVD method.
Lamination can be performed by a plasma CVD method, an evaporation method, or the like. As a laminating condition, for example, in a glow discharge method, SiH ₄ , Si ₂ H ₆ , SiCl ₄ or the like can be used. In this case, the pressure in the SiH ₄ 0.5~2.0
Torr, temperature 250-350 ° C, glow oscillation frequency 5
An amorphous silicon layer can be stacked in the range of 0 to 450 Hz. It is also possible to perform recrystallization after depositing polycrystalline silicon in addition to amorphous silicon.
As a lamination method, a normal pressure CVD method, a low pressure CVD method, a plasma CVD method, or the like can be used. In this case, for example, in the low pressure CVD method, the pressure is 0.1 to 5.0 Torr.
r, SiH ₄ , Si ₂ H ₆ , Si at a temperature of 450 to 900 ° C.
H ₂ Cl ₂ or the like can be diluted with hydrogen or nitrogen. When diluting SiH ₄ with nitrogen, the concentration of SiH ₄ can be set in the range of 20 to 30%. Also S
When laminating a polycrystalline silicon layer using thermal decomposition of iH ₄ , there is no need to dilute SiH ₄ .

In this embodiment, the single crystal silicon layer is formed by irradiating a pulse beam of an argon laser. However, a CW laser beam, a Q switch pulse laser beam, an excimer laser beam such as KrF or XeCl, an electron beam It is also possible to use a beam or the like. This can be similarly applied to the case where the polycrystalline silicon layer is single-crystallized. In addition to the laser annealing solid phase growth method described above, it is also possible to perform single crystallization of an amorphous silicon layer or a polycrystalline silicon layer by a solid phase growth method using heat treatment. In this case, the amorphous silicon layer has a temperature of 500-12.
In the range of 00 ° C., the polycrystalline silicon layer has a temperature of 800 to 12 ° C.
The single crystallization can be performed by heating in an infrared lamp or a strip heater in hydrogen or nitrogen in the range of 00 ° C. The formation of the oxide film can be performed by a normal pressure CVD method, a low pressure CVD method, or a plasma CVD method in addition to the above-described thermal oxidation. The thermal oxidation can be performed by dry oxidation, wet oxidation, steam oxidation, halogen oxidation using hydrochloric acid, or the like, in addition to the above-described pyrogenic oxidation. In the CVD method, TEOS (tatraet
hoxysilane) can also be used.

The pixel switching element is a pMOS
It is also possible to use a transistor. As for the peripheral driving circuit, in addition to the CMOS configuration, a Bi-CMO including a bipolar transistor for further improving the driving capability is used.
An S configuration is also possible. As for the manufacturing conditions and method of the details, those which can satisfy the performance required for the manufactured liquid crystal display device can be freely adopted. Regarding the etching of the silicon substrate, in addition to the above-mentioned TMAH, EDP (ethylenediamine pyrocatechol), hydrazine aqueous solution, KOH solution (KOH /
Isopropanol, KOH / hydrazine mixed solution, etc.)
It is possible to use an alkaline solution such as

In this embodiment, the liquid crystal display portion remains a cavity formed on a silicon wafer, but a light-transmissive insulating material such as silicon rubber, epoxy resin or silicon oxide film or silicon nitride film is used in this portion. By filling or depositing, the mechanical strength of the liquid crystal display part can be improved.

Here, the mechanical strength of the liquid crystal display portion will be described in more detail. In the transmission type TFT active matrix liquid crystal display device shown in FIG. 4, when the silicon substrate immediately below the liquid crystal display portion is removed as shown in FIG. 6 (b), a certain amount of tensile stress must be applied to the insulating film 2. If an excessive compressive stress is applied to the insulating film 2, when the silicon substrate immediately below the liquid crystal display portion is removed, the insulating film 2 may be wrinkled, or the insulating film 2 may sag due to the weight of the injected liquid crystal. This causes problems such as an uneven cell thickness. Conversely, if an excessive tensile stress is applied to the insulating film 2,
When the silicon substrate immediately below the liquid crystal display portion is removed, problems such as cracks in the insulating film 2 occur. Therefore, in the case of the transmission type liquid crystal display device described in this embodiment, it is very important to control the stress applied to the insulating film 2 on which the pixel switching elements and the like are formed.

In this embodiment, an oxide film is used as the insulating film. However, a nitride film and a stacked film of an oxide film and a nitride film can be used. For example, when a nitride film was laminated to a thickness of 400 nm, a tensile stress was applied to the nitride film, and the amount of warpage was about 30 μm. Liquid crystal display area is diagonal 0.7
In a transmission type TFT active matrix liquid crystal display device having an inch and a cell thickness of 4 μm, a tensile stress is applied to the TFT array substrate, and the warpage may be in the range of 0 to 100 μm. When a nitride film is used as an insulating film, 1
A film thickness of 00 to 600 nm is required. However, since the TFT array is actually formed on the insulating film, the amount of stress and warpage must be set so as to satisfy the above range in the state where the TFT array is formed. The amount of warpage is 1
If it exceeds 00 μm, the film will be broken due to high tensile strength. Thermal nitride method, normal pressure C
A VD method, a low-pressure CVD method, a plasma CVD method, or the like can be used.

(Embodiment 3) FIG. 7 is a sectional view showing a third embodiment of the liquid crystal display device according to the present invention. Here, an insulating layer 2 is formed on the silicon substrate 1, and a polycrystalline silicon layer 12 and a single-crystal silicon layer 4 are formed on the insulating layer 2. At least one or more polycrystalline silicon elements 13 are provided on the polycrystalline silicon layer 12,
At least one single-crystal silicon element 6 is provided on the single-crystal silicon layer 4. The pixel electrode 11 is formed on the polycrystalline silicon element 13, and the polycrystalline silicon element 13 and the single crystal silicon element 6 are electrically connected. Further, a liquid crystal 10 is sealed in a cover glass 8 disposed to face the polycrystalline silicon element 13 and a surrounding sealing material 9. Here, the polycrystalline silicon element 13 was a TFT.

The liquid crystal display shown in FIG. 7 is a reflective TFT active matrix liquid crystal display. In the above structure, the light incident on the liquid crystal layer is reflected by the pixel electrode, so that the display of the liquid crystal is visualized. Note that the liquid crystal display device requires an alignment film, a counter electrode, a filter, a polarizing plate, and the like, but these are omitted here.

8 and 9 are process diagrams showing a method for manufacturing the liquid crystal display device according to the present embodiment. Here, 1 to 13 correspond to FIG.
Is the same as The steps in FIG. 8 are as follows.
(A) An insulating layer 2 is formed on a silicon substrate 1. (B)
After patterning the insulating layer 2 to expose a part of the silicon substrate 1, a polycrystalline silicon layer 12 is laminated.
(C) Polycrystalline silicon layer 1 from exposed portion of silicon substrate 1
2 is recrystallized. However, the entire polycrystalline silicon layer 12 is not recrystallized, and the polycrystalline silicon layer 12 and the single crystal silicon layer 4 are formed on the insulating layer 2. (D) On the polycrystalline silicon layer 12 and the monocrystalline silicon layer 4, a polycrystalline silicon element 13 and a monocrystalline silicon element 6 are formed. Here, pMOS is used as the polycrystalline silicon element 13.
Only CMOS transistors are shown as transistors and single crystal silicon elements 6. Although not shown, the polycrystalline silicon element 13 and the single crystal silicon element 6 are electrically connected by metal electrodes.

The pixel electrode 11 is formed on the polycrystalline silicon element 13.
Is formed, a cover glass 8 is disposed so as to face the polycrystalline silicon element 13, and after the liquid crystal 10 is sealed, the periphery is sealed with a sealing material 9 (FIG. 9). Although not shown here, a transparent insulating film, an alignment film, and the like are formed on the polycrystalline silicon element 13, and a transparent insulating film, a transparent counter electrode, an alignment film, a filter, and the like are formed on the cover glass 7. Have been. Similarly, although not shown, the single crystal silicon element 6
An insulating protective film is formed thereon. Thereby, the region where the polycrystalline silicon element 13 is formed becomes light reflective. Through the above steps, the reflective TFT active matrix liquid crystal display device shown in FIG. 7 can be obtained.

The reflective TFT active matrix liquid crystal display device according to the third embodiment can be integrally mounted with a peripheral drive circuit having higher performance than the conventional one.

The method of manufacturing the reflection type TFT active matrix liquid crystal display device shown in this embodiment is not limited to the above-mentioned specific examples, but various methods and conditions can be applied. This embodiment is the same as Embodiment 1 except that the pixel electrode is made of a light-reflective material and that the silicon substrate is not etched. Therefore, details of the present embodiment other than the above are implemented. The same conditions and methods as those described in Embodiment 2 can be applied. Further, the insulating film does not suffer from the problem described in the second embodiment, so that the degree of freedom in designing the insulating film is increased.

(Embodiment 4) FIG. 10 is a process chart showing an embodiment of a method of manufacturing a liquid crystal display device shown in Embodiment 4. Here, 1 to 13 are the same as those in FIGS.
This is an OI substrate. The steps in FIG. 10 are as follows. (A) In the SOI substrate 14, (b) patterning is performed to expose a part of the insulating layer 2. (C) The polycrystalline silicon layer 12 is laminated and patterned to form the polycrystalline silicon layer 12 on the insulating layer 2. (D) A polycrystalline silicon element 13 and a single crystal silicon element 6 are formed on the polycrystalline silicon layer 12 and the single crystal silicon layer 4. Here, pMO is used as the polycrystalline silicon element 13.
CMOS as S transistor and single crystal silicon element 6
Only transistors are shown. Although not shown, the polycrystalline silicon element 13 and the single crystal silicon element 6 are electrically connected by metal electrodes. Thereafter, the transmission type TFT active matrix liquid crystal display device can be obtained according to the process of FIG. 6, and the reflection type TFT active matrix liquid crystal display device can be obtained according to the process of FIG.

The transmission type or reflection type TFT active matrix liquid crystal display device shown in the fourth embodiment can be integrally mounted with a peripheral drive circuit having higher performance than the conventional one.

As a method for manufacturing an SOI substrate, an ion implantation method, a direct bonding method, or the like is used. In the ion implantation method, an insulating layer is buried by implanting ions into a silicon substrate. In particular, a method of fabricating an SOI substrate by implanting oxygen ions is widely called a SIMOX method. In the direct bonding method, two silicon substrates are bonded together via an insulating layer, and then one of the silicon substrates is thinned. Polishing or etching is used as a thinning method. .

The SOI substrate used in this embodiment can be manufactured by any method. For example, when an ion implantation method is used, an oxide film can be formed by implanting oxygen ions into a silicon substrate, and a nitride film can be formed by implanting nitrogen ions. , And laminates thereof. When the direct bonding method is used, there is no limitation on the insulating layer, and the formation method, the film thickness, and the like can be freely selected depending on the purpose of the semiconductor device to be manufactured. Regarding the bonding conditions, in the air, in oxygen, in nitrogen, in an inert gas such as argon and in a mixed gas with any of these,
It can be performed in a vacuum, pure water, or the like. The conditions of the heat treatment after bonding can be freely selected within the range of 900 to 1200 ° C. in oxygen, nitrogen, or a mixed gas of oxygen and nitrogen.

In this embodiment, the steps after the formation of the pixel switching element and the peripheral drive circuit are the same as those shown in the second or third embodiment. Therefore, the details of this embodiment other than the above are described in the second or third embodiment. Similar conditions, shown in
It is possible to apply the method. In the present embodiment, a TFD (Thin Film Diode) may be used as a pixel switching element in addition to the above-described TFT which is a three-terminal element, as a two-terminal element. TFD is usually MIM (Metal-Insu
Since it has a (later-metal) structure, it is not necessary to form an amorphous silicon layer or a polycrystalline silicon layer. TF
In D, Ta is used as a lower electrode, and Cr or T is used as an upper electrode.
i, Ta ₂ O ₅ or the like is often used as an insulating layer between electrodes. In the device structure, it is possible to arrange a TFD element in parallel to take a tandem structure in which characteristics as a switching element are improved.

(Fifth Embodiment) FIGS. 11 and 12 are process diagrams showing a fifth embodiment of the liquid crystal display device. Here, 1 to 13 are the same as those in FIG. 10, and 15 is an insulator. The steps in FIG. 11 are as follows. (A) The silicon substrate 1 and the insulator 15 are bonded. (B) After forming the single crystal silicon layer 4 by thinning the silicon substrate 1, patterning is performed to expose a part of the insulator 15. (C) By laminating and patterning the polycrystalline silicon layer 12,
The polycrystalline silicon layer 12 is formed on the insulator 15.
(D) A polycrystalline silicon element 13 and a single crystal silicon element 6 are formed on the polycrystalline silicon layer 12 and the single crystal silicon layer 4. Here, only an nMOS transistor is shown as the polycrystalline silicon element 13 and only a CMOS transistor is shown as the single crystal silicon element 6. Although not shown, the polycrystalline silicon element 13 and the single crystal silicon element 6 are electrically connected by metal electrodes. (FIG. 12)
After disposing the cover glass 8 facing the polycrystalline silicon element 13, the liquid crystal 10 is sealed and the periphery is sealed with a sealing material 9. Although not shown here, the polycrystalline silicon element 1
A transparent insulating film, a transparent pixel electrode, an alignment film, and the like are formed on 3, and a transparent insulating film, a transparent counter electrode, an alignment film, a filter, and the like are formed on the cover glass 8. Similarly, although not shown, an insulating protective film is formed on the single crystal silicon element 6. Through the above steps, the transmission type T
An FT active matrix liquid crystal display device can be obtained.

An example in which the above-mentioned liquid crystal display device is specifically manufactured using the steps shown in FIGS. A p-type silicon wafer having a <100> plane orientation, a diameter of 125 mm, a thickness of 625 μm, and a specific resistance of 0.1 Ωcm;
After bonding with synthetic quartz glass having a thickness of 625 μm and a thickness of 625 μm, heat treatment is performed to completely bond the two. Here, after bonding the p-type silicon wafer and the synthetic quartz glass in nitrogen, heat treatment was performed at 450 ° C. for 2 hours in nitrogen to completely bond the two. Next, after the p-type silicon wafer is thinned to a thickness of 0.3 μm, the single crystal silicon layer is patterned by RIE (reactive ion etching) to expose a part of the synthetic quartz glass. Here, the p-type silicon wafer is 1.0 μm thick.
After thinning by grinding and polishing until the pressure several Torr,
Plasma etching was performed at an acceleration voltage of 1 eV or less to obtain a single crystal silicon layer having the above thickness. In addition, decompression C
A polycrystalline silicon layer is stacked by the VD method. Here, a polycrystalline silicon layer having a thickness of 0.2 μm is formed at a temperature of 656 ° C., a pressure of 0.25 Torr, a mixed gas of SiH ₄ and H _{2 at} a partial pressure of SiH _{4 of} 0.15 Torr and a deposition rate of 300 nm / min. Laminated.

Subsequently, the polycrystalline silicon layer is patterned. Thereafter, using a known semiconductor integrated circuit manufacturing process, a pixel switching element is formed in an nMOS configuration on a polycrystalline silicon layer, and a peripheral driving circuit is formed in a CMOS configuration on a single crystal silicon layer. After that including this step, the liquid crystal display device was manufactured according to the specific example shown in the second embodiment. However, in this embodiment, a synthetic quartz glass, which is a light-transmitting insulator, is used instead of the silicon substrate, and the silicon substrate etching step shown in the second embodiment is omitted.

The transmissive TFT active matrix liquid crystal display device shown in the fifth embodiment can be integrally mounted with a peripheral drive circuit having higher performance than the conventional one.

In this embodiment, synthetic quartz glass is used as the insulator, but other materials such as fused quartz glass, high melting point glass, borosilicate glass, and quartz glass can be used. In addition, as the heat treatment conditions after bonding, in oxygen,
In nitrogen, mixed gas of oxygen and nitrogen, temperature 200-500
It can be freely selected in the range of ° C.

This embodiment is implemented except that a SOI substrate manufactured by a direct bonding method between a single crystal silicon substrate and an insulator is used and that a transmission type liquid crystal display device is manufactured without etching the silicon substrate. The method is the same as the method of manufacturing a semiconductor device by the direct bonding method described in the fourth embodiment. Therefore, the same conditions and methods as those described in the fourth embodiment can be applied to the details of the present embodiment other than those described above. However, only the transmission type liquid crystal display device is manufactured in this embodiment.

(Embodiment 6) FIGS. 13 and 14 are process drawings showing Embodiment 6 of the liquid crystal display device. Here, 1 to 13 are the same as those in FIG. 10, 16 is a first silicon substrate, 17 is a high concentration impurity layer, 18 is a second silicon substrate, and 19 is a mask material. The steps in FIG. 13 are as follows. (A) Ion implantation is performed on the first silicon substrate 16 to form a high-concentration impurity layer 17. (B) After bonding the high-concentration impurity layer 17 and the second silicon substrate 18, (c) the first silicon substrate 16 is thinned to form the single crystal silicon layer 4. (D) First silicon substrate 1
6 is performed to expose a part of the high-concentration impurity layer 17. (E) The polycrystalline silicon layer 12 is formed on the high concentration impurity layer 17 by stacking and patterning the polycrystalline silicon layer 12. (F) Polycrystalline silicon layer 1
Polycrystalline silicon element 13 and single crystal silicon element 6 are formed on 2 and single crystal silicon layer 4. Here, only an nMOS transistor is shown as the polycrystalline silicon element 13 and only a CMOS transistor is shown as the single crystal silicon element 6. Although not shown, the polycrystalline silicon element 13 and the single crystal silicon element 6 are electrically connected by metal electrodes. (G) After laminating and patterning the mask material 19 on the first silicon substrate 16, the first silicon substrate 16 is etched to expose a part of the high-concentration impurity layer 17. (H) The high concentration impurity layer 17 is oxidized from the exposed portion to form the insulating layer 2. (I) After disposing the cover glass 8 so as to face the polycrystalline silicon element 13, the liquid crystal 10 is sealed and the periphery is sealed with the sealing material 9. Although not shown here, a transparent insulating film, a transparent pixel electrode, an alignment film, and the like are formed on the polycrystalline silicon element 13, and a transparent insulating film, a transparent counter electrode, an alignment film, A filter and the like are formed. Similarly, although not shown, the single crystal silicon element 6
An insulating protective film is formed thereon. Through the above steps, a transmission type TFT active matrix liquid crystal display device can be obtained.

An example in which the above-described semiconductor device is specifically manufactured using the steps shown in FIGS. A high-concentration n-type impurity layer is formed by ion implantation on a p-type silicon wafer having a <100> plane orientation, a diameter of 125 mm, a thickness of 625 μm, and a specific resistance of 20 Ωcm. After an oxide film having a thickness of 50 nm is formed on the surface of the p-type silicon wafer by thermal oxidation, P ions are dosed at a dose of 1 × 10 ¹¹ to 1 × 10 ¹⁴ c.
Implantation was performed at m ⁻² and an acceleration voltage of 60 to 100 keV, and heat treatment was performed in nitrogen at 1000 ° C. for 1 hour. As a result, an n-type impurity layer having a thickness of 500 nm was formed on the p-type silicon wafer. This n-type impurity layer has a plane orientation <100>, a diameter of 1
A 25 mm, 625 μm thick, 30 Ωcm p-type silicon wafer is bonded in nitrogen, and
Heat treatment was performed at 100 ° C. for 1 hour to completely bond the two. Subsequently, a single-crystal silicon layer having a thickness of 0.5 μm was formed by thinning using a p-type silicon wafer having a specific resistance of 20 Ωcm. The single crystal silicon layer is patterned by RIE dry etching to expose a part of the n-type impurity layer. Further, a polycrystalline silicon layer is laminated by a low pressure CVD method. Here, the temperature is 656 ° C and the pressure is 0.25T.
In a mixed gas of orr, SiH ₄ and H ₂ , a polycrystalline silicon layer having a thickness of 0.2 μm was stacked under the conditions of a SiH ₄ partial pressure of 0.15 Torr and a deposition rate of 300 nm / min.
Subsequently, the polycrystalline silicon layer is patterned. Thickness 5
00 nm BPSG film (Borono-Phospho
After stacking (Silicate Glass), anisotropic dry etching is performed to form a contact hole. Further, a metal electrode material such as aluminum is deposited by a sputtering method, and dry etching is performed on a predetermined wiring shape to form a wiring portion.

Thereafter, using a known semiconductor integrated circuit manufacturing process, a pixel switching element is formed on the polycrystalline silicon layer in an nMOS configuration, and a peripheral drive circuit is formed on a single crystal silicon layer in a CMOS configuration. After that including this step, the liquid crystal display device was manufactured according to the specific example shown in the second embodiment. Subsequently, a nitride film having a thickness of 20 nm is formed as a mask material on a p-type silicon wafer having a specific resistance of 30 Ωcm, and then resist patterning is performed to form a 30 Ωcm specific resistance.
Exposing a part of the p-type silicon wafer. After this 110
Anisotropic electrolytic etching using EDP (herein, a mixed solution of 7.5 liters of ethylenediamine, 1.2 kg of pyrocatechol, and 2.4 liters of water) was performed.
A part of the p-type silicon wafer is removed. Here, the n-type impurity layer becomes an etching stopper layer. Further, this n-type impurity layer is selectively oxidized by thermal oxidation to have a thickness of 5 nm.
A 00 nm oxide film is formed.

In the transmission type TFT active matrix liquid crystal display device shown in the sixth embodiment, a peripheral drive circuit having a higher performance than the conventional one can be integrated and mounted.

In the present embodiment, various combinations can be applied to the combination of the first silicon substrate / the high-concentration impurity layer / the second silicon substrate as shown in the present embodiment. For example, if the concentration of the impurity layer is 5 × 1
If it is 0 ¹⁸ cm ^-2 or more, a combination of n-type silicon wafer / n-type impurity layer / p-type silicon wafer, p-type silicon wafer / p-type impurity layer / n-type silicon wafer is also possible. A combination of an n-type silicon wafer / p-type impurity layer / n-type silicon wafer is also possible. As the bonding condition, the same condition as described in Embodiment Mode 5 can be applied. In electrolytic etching, KOH,
TMAH or the like can be used.

This embodiment is the same as the method of manufacturing a semiconductor device by the direct bonding method shown in the fourth embodiment, except that a single crystal silicon substrate is directly bonded and an insulating layer is formed after etching the silicon substrate. Therefore, the same conditions and methods shown in the fourth embodiment can be applied to the details of the present embodiment other than the above.

[0066]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed embodiment using the first embodiment of the present invention will be described with reference to FIGS. 1, 2 and 3. FIG.

Example 1 (FIG. 1A) A 5-inch P-type (100) single-crystal silicon substrate having a thickness of 625 microns (0.1 to 0.2 Ω)
cm) was prepared and set in an apparatus as shown in FIG. 3-1 to perform anodization, whereby the surface of the silicon substrate 100 was formed into porous silicon 101 by 20 μm. At this time, the solution 304 used was a 49% HF solution, and the current density was 1 mA.
/ Cm ² . At this time, the rate of making porous is about 1
μm / min, a porous layer having a thickness of 20 μm was obtained in about 20 minutes.

(FIG. 1B) The porous silicon 101
The single crystal silicon layer 102 is formed on the
5 μm epitaxial growth was performed. The deposition conditions are as follows.

Gas used: SiH ₄ / H ₂ gas flow rate: 0.62 / 140 (l / min) Temperature: 850 ° C. Pressure: 80 Torr Growth rate: 0.12 μm / min

(FIG. 1C) The substrate prepared by the above method was treated in a steam atmosphere at 900 ° C.
Oxide film 103 was obtained.

(FIG. 1 (d)) The substrate whose surface has been oxidized and the previously prepared 5-inch quartz substrate 110 are washed with a system using acid / ammonia and spin-dried. Stuck together. Then, the bonded substrates were pressed with a roller, and heat-treated at 120 ° C. for 24 hours.

(FIG. 1E) The silicon substrate portion 100 of about 600 μm is subjected to a 1: 1 hydrofluoric / nitric acid / acetic acid heat treatment.
Etching was performed with a 0:10 mixed solution. The reason why the silicon substrate portion is removed by etching is that the heat treatment after bonding the substrates cannot be performed at a high temperature, so that the bonding strength is weak and cannot withstand a shear stress such as grinding.

When the porous silicon 102 is exposed, the substrate is immersed in a selective etching solution,
Only the porous portion 101 was selectively etched while applying ultrasonic waves. At this time, the composition of the selective etching solution, the etching rate for single crystal silicon, and the etching rate for SiO ₂ are as follows.

Selective etching solution = TMAH aqueous solution (24 ppm) vs. silicon etching rate = 5 Å / min vs. SiO ₂ etching rate = 1 angstrom / min or less As a result, a single crystal silicon film of about 0.2 μm is provided on a transparent quartz substrate. The completed substrate is completed.

(FIG. 2A) All single-crystal silicon thin films except for the transistor portion 202 of the peripheral drive circuit portion when a liquid crystal display device was manufactured were dry-etched by a plasma source.

(FIG. 2B) The patterned single-crystal silicon thin film 202 is oxidized for 200 Å in a dry oxygen atmosphere at 1000 ° C. for the purpose of strengthening the bonding strength of the bonding interface.
At a temperature of 20 ° C., a polycrystalline silicon thin film 203 was deposited by 800 Å.

(FIG. 2C) Except for the pixel transistor portion 203 of the active matrix, all the polycrystalline silicon films were dry-etched.

(FIG. 2D) A peripheral driving transistor circuit 204 and a pixel switching transistor 205 were each formed by using a normal IC process.

(FIG. 2E) Finally, a known technique, I
The capacitor part is formed by a transparent electrode material such as TO,
The whole was covered with a transparent insulating film 209, a sealing material 207 and a glass cover 208 were further attached, and a liquid crystal 206 was sealed.

Through all the above steps, an active matrix liquid crystal display device was completed.

(Embodiment 2) Embodiment 2 of the present invention will be described in detail with reference to FIGS.

From FIG. 1 (a) to (FIG. 1 (c)), the same procedure as in Example 1 was performed.

(FIG. 1D) The substrate 100 having an oxidized epitaxial silicon surface and the previously prepared 5-inch quartz substrate 110 are washed, and then each electrode of a plasma generator having a parallel plate electrode. The wafer was placed in between, and a treatment was performed for 30 seconds in a plasma of CF ₄ + O ₂ gas. By this treatment, the surface SiO ₂ of each substrate was activated. Subsequently, the substrates were washed with pure water only, and then their mirror surfaces were bonded together.

(FIG. 1E) The silicon substrate 100 side was ground by 610 μm using a surface grinding device to expose the porous silicon layer 101 on the surface. The silicon substrate could be removed by grinding because the bonding surface was activated in the previous step and the bonding strength was extremely high even though no heat treatment was performed.

The exposed porous layer 101 was selectively etched with a 1: 300 mixed solution of hydrofluoric acid / hydrogen peroxide. The etching rates of the solution used for selective etching with respect to single crystal silicon and SiO ₂ are as follows.

Silicon vs. 3 Å / min SiO ₂ = 6 Å / min As a result, a substrate having a single-crystal silicon film of about 0.2 μm on a transparent quartz substrate was completed.

(FIG. 2A) Subsequently, as in the first embodiment,
The other portions were etched except for the single crystal silicon film 202 in the transistor portion in the peripheral driver circuit region.

(FIG. 2B) The patterned single-crystal silicon thin film 202 was oxidized at 200 Å in a dry oxygen atmosphere at 1000 ° C. to further strengthen the bonding strength at the bonding interface.

Subsequently, an amorphous silicon thin film 203 was deposited at a temperature of 550 ° C. by LPCVD at 1000 Å. Further, the amorphous silicon film 20
3, silicon ions are implanted using an ion implanter,
The film was completely amorphized. Next, this substrate is
Annealing was performed in a nitrogen atmosphere at 0 ° C. for 50 hours to polycrystallize the amorphous. This polycrystalline silicon film is made of a usual L
It has a larger particle size than a film deposited by PCVD, and has excellent mobility and other characteristics when formed into a transistor.

2 (c) to 2 (e) were performed in the same manner as in the first embodiment, and an active matrix liquid crystal display device having a higher performance than that of the first embodiment was completed.

[0091]

As described above, the liquid crystal display device of the present invention has a single crystal semiconductor layer and a non-single crystal semiconductor layer formed on an insulating layer formed on a semiconductor substrate. By electrically connecting the semiconductor elements formed over the layer and the non-single-crystal semiconductor layer, semiconductor elements having different performances can be integrally formed over the same substrate. For this reason, the cost in the mounting process can be significantly reduced.

Further, in the liquid crystal display device according to the present invention, since the peripheral drive circuit (or control circuit) is an SOI element,
A peripheral drive circuit (or control circuit) that enables high-speed driving, high-speed operation, miniaturization of elements, high integration, and the like can be obtained. The effects described above increase as the definition of the liquid crystal display device increases.

Further, a single-crystal silicon film is formed on a transparent insulating substrate by making full use of a bonding technique using porous silicon, and a peripheral drive circuit requiring a high drive capability is formed on the single-crystal silicon. Obtainable. Further, by forming a non-single-crystal silicon transistor having switching characteristics excellent in light leakage in the pixel portion, a high-performance active matrix liquid crystal display device can be realized.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating a manufacturing process of a liquid crystal display device according to a first embodiment.

FIG. 2 is a sectional view illustrating a manufacturing process of the liquid crystal display device according to the first embodiment.

FIG. 3 is a diagram showing a step of anodizing.

FIG. 4 is a cross-sectional view illustrating a liquid crystal display device according to a second embodiment.

FIG. 5 is a sectional view illustrating a manufacturing process of the liquid crystal display device according to the second embodiment.

FIG. 6 is a sectional view illustrating a manufacturing process of the liquid crystal display device according to the second embodiment.

FIG. 7 is a cross-sectional view illustrating a liquid crystal display device according to a third embodiment.

FIG. 8 is a sectional view illustrating a manufacturing process of the liquid crystal display device according to the third embodiment.

FIG. 9 is a sectional view illustrating a manufacturing process of the liquid crystal display device of the third embodiment.

FIG. 10 is a sectional view illustrating a manufacturing process of the liquid crystal display device of the fourth embodiment.

FIG. 11 is a sectional view illustrating a manufacturing process of the liquid crystal display device of the fifth embodiment.

FIG. 12 is a sectional view illustrating a manufacturing process of the liquid crystal display device of the fifth embodiment.

FIG. 13 is a sectional view illustrating a manufacturing process of the liquid crystal display device according to the sixth embodiment.

FIG. 14 is a sectional view illustrating a manufacturing process of the liquid crystal display device according to the sixth embodiment.

FIG. 15 is a plan view of a conventional liquid crystal display device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Insulating layer 3 Amorphous silicon layer 4 Single crystal silicon layer 5 Amorphous silicon element 6 Single crystal silicon element 7 Opening 8 Cover glass 9 Sealant 10 Liquid crystal 11 Pixel electrode 12 Polycrystalline silicon layer 13 Many Crystal silicon element 14 SOI substrate 15 Insulator 16 First silicon substrate 17 High concentration impurity layer 18 Second silicon substrate 19 Mask material 21 Pixel switching element (TFT) 22 Buffer circuit 23 Horizontal scanning circuit 24 Vertical scanning circuit 25 Display pixel 26 substrate 100, 300 single-crystal silicon substrate 101 porous silicon substrate 102, 202 epitaxial growth layer 103 epi-oxide film 110, 210, 406 transparent insulating substrate 304, 304 'anodizing solution 305, 305' positive electrode 306, 306 '' Negative electrode 401 pixel switch Switch 402 shift register buffer section 403 horizontal shift register section 404 vertical shift register section 405 liquid crystal pixel section

Claims (6)

[Claims] 1. A pixel switch made of a non-single-crystal semiconductor is provided at a position where a data line and a scan line intersect in an image display unit, and a periphery made of a single-crystal semiconductor is driven around the image display unit by driving the pixel switch. In a liquid crystal display device having an active matrix substrate provided with a driving circuit, and a counter substrate facing the active matrix substrate with a liquid crystal material interposed therebetween, the pixel switch and the peripheral driving circuit are formed on a substrate at least a surface of which is insulative. A liquid crystal display device formed on a liquid crystal display. 2. The liquid crystal display device according to claim 1, wherein the substrate having at least a surface that is insulative is a quartz substrate. 3. The liquid crystal display device according to claim 1, wherein the substrate having at least a surface having an insulating property is a semiconductor substrate having an insulating layer on the surface. 4. A pixel switch made of a non-single-crystal semiconductor is provided at a position where a data line and a scan line intersect in an image display portion, and a periphery made of a single-crystal semiconductor is driven around the image display portion by driving the pixel switch. In a method for manufacturing a liquid crystal display device having an active matrix substrate provided with a driving circuit, and a counter substrate facing the active matrix substrate with a liquid crystal material interposed therebetween, the step of manufacturing the active matrix substrate includes forming a porous substrate on a surface of a semiconductor substrate. Forming a porous semiconductor layer, forming a non-porous semiconductor layer on the surface of the porous semiconductor layer, forming an insulating layer on the surface of the non-porous semiconductor layer, removing the semiconductor substrate and the porous semiconductor layer Forming the peripheral driving circuit on the non-porous semiconductor layer, removing the non-porous semiconductor layer of the image display unit, Forming the pixel switch on a layer. 5. The method for manufacturing a liquid crystal display device according to claim 4, wherein when an insulating layer is formed on the surface of the non-porous semiconductor layer, a quartz substrate is attached. 6. The method for manufacturing a liquid crystal display device according to claim 4, wherein when an insulating layer is formed on the surface of the non-porous semiconductor layer, a semiconductor substrate having an insulating layer on the surface is attached.