JPH09293875A - Semiconductor element substrate, manufacture thereof, and semiconductor device using its substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high precision, a uniform surface, miniaturization and prevention of deterioration in display picture quality, by recrystallizing an amorphous conductive film to form a transparent conductive film. SOLUTION: A through-hole for connection with a metal electrode 12 on a drain side of a pixel switching element is formed in a second nitride film 15, and a transparent conductive film 17 is formed as a pixel electrode. In this case, for example, an amorphous ITO film is etched to be patterned. With the amorphous ITO film, since the etching rate on the sidewall is lower than in the direction of thickness, the quantity of etching on the sidewall may be estimated to be small and patterning precision is improved, thus enabling realization of higher precision. Subsequently, heat treatment is performed to crystallize the amorphous ITO film. Thus, the optical transmittance of the ITO film may be improved. Also, in this case, the surface roughness of the ITO film may be reduced. After that, a display section is provided with optical transmittance by a process of removing a part of a silicon wafer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element substrate having a semiconductor element and a method for manufacturing the same, and further to a semiconductor device using the semiconductor element substrate.

[0002]

2. Description of the Related Art A liquid crystal display device, which is one of semiconductor devices, is used in home appliances such as small TVs, flat panel displays such as notebook personal computers, car navigation systems and viewfinders, and projection T displays.
It is used as various display devices such as V and HMD. The most widely used liquid crystal display device at present is of a type in which each pixel is driven in an active matrix, and an active matrix substrate in which thin film transistors (TFTs) are arranged in a matrix as switching elements is used.

FIG. 5 is a schematic structural diagram of an active matrix substrate used in a liquid crystal display device. In the figure, 51 is a pixel switching element TFT, 52 is a buffer circuit, 5
3 is a horizontal scanning circuit, 54 is a vertical scanning circuit, 55 is a pixel electrode, and 56 is a substrate.

In FIG. 5, a television luminance signal and a sound signal are compressed into a certain frequency band and sent to a buffer circuit 52 driven by a horizontal scanning circuit 53 having a driving capability capable of following the frequency. come. Subsequently, the vertical scanning circuit 54 transfers a signal to the pixel electrode 55 while the pixel switching element 51 is on. Considering application to high-definition TV, assuming that the frame frequency is 60 Hz, the number of scanning lines is about 1000, the horizontal scanning period is about 30 μsec (effective scanning period 27 μsec), and the number of horizontal pixels is about 1500, the frequency of the television signal is about 45 MHz. And is transferred to the buffer circuit 52. Therefore, the performance required for each circuit is as follows:
3 has a driving capacity of 45 MHz or more, a vertical scanning circuit 54 has a driving capacity of 500 kHz or more, a horizontal scanning circuit 53 drives a transfer switch for transferring a television signal to the buffer circuit 52, a driving capacity of 45 MHz or more, and a pixel switching element 51 The driving capacity is 500 kHz or more.

With respect to the driving capability described here, when the number of gradations N in a liquid crystal display pixel is output, the voltage that gives the maximum or minimum transmittance of the liquid crystal is calculated from the V _m and VT (voltage-transmittance) curves. When the threshold voltage of the resulting liquid crystal and V _t, in the scanning _{period, V m - (V m -V} t) / N [V] or more voltage means to be transferred. From this, the pixel switching element 51 and the vertical scanning circuit 54
Drive capacity may be relatively small, but the horizontal scanning circuit 5
3 and the buffer circuit 52 need to be driven at high speed.
Therefore, in a normal active matrix drive type liquid crystal display device, the pixel switching element 51 and the vertical scanning circuit 54 are provided on an amorphous silicon layer or a polycrystalline silicon layer deposited on a glass substrate, and other peripheral drive circuits are provided. IC
This has been dealt with by mounting the chip externally.

Recently, a prototype of a liquid crystal display device which is monolithically formed with a peripheral drive circuit by using polycrystalline silicon has been manufactured. However, since the peripheral drive circuit has a small driving capability of TFT, the transistor size is increased. , A complicated design is required on the circuit. From this, in order to improve the performance of the peripheral drive circuit, it is necessary to form the peripheral drive circuit on the semiconductor layer having excellent crystallinity. Therefore, the element forming the peripheral drive circuit is a single crystal semiconductor element. Can be said to be desirable.

Regarding the pixel switching element, for example, the total load of the TFT of the active matrix circuit is set to 50 f.
F, assuming that the voltage swing width for liquid crystal alignment is 10 V, it is necessary to flow charges of 50 × 10 ⁻¹⁵ × 10 = 5 × 10 ⁻¹³ [C] within a fixed time. When this is driven at 500 kHz as described above, the saturation current I _{sat of the} TFT is I _sat × 1 / (500 × 10 ³ )> 5 × 10 ⁻¹³ and I _sat > 2.5 × 10 ⁻⁷ [A ] Becomes This can be easily achieved with an amorphous silicon TFT or a polycrystalline silicon TFT.

The liquid crystal display device is roughly classified into a light transmission type liquid crystal display device and a light reflection type liquid crystal display device. In the former case, the substrate of the liquid crystal display unit needs to be light-transmissive in the visible light region, but in the latter case, it is not always necessary. Further, in any case, the peripheral driving circuit must be shielded from light.

From the above, in a liquid crystal display device having a built-in peripheral drive circuit, it is sufficient to use an amorphous semiconductor element or a polycrystalline semiconductor element as the pixel switching element, but an element which constitutes the peripheral drive circuit. It can be said that it is desirable to use a single crystal semiconductor element.

FIG. 2 shows a conventional liquid crystal display device using a polycrystalline semiconductor element as a pixel switching element and a single crystal semiconductor element for a peripheral driving circuit, FIG. 1 showing its active matrix substrate, and FIGS. 3 and 4 showing its manufacturing process. Show. The peripheral drive circuit shown in FIG. 1 has a CMOS structure with a single crystal silicon element, and the MOS transistor is a coplanar type with gate self-alignment.

In the figure, 1 is a silicon substrate, 2 is a first silicon oxide film (hereinafter referred to as a first oxide film), 3 is a first silicon nitride film (hereinafter referred to as a first nitride film), and 4 is a first silicon oxide film. 2 a silicon oxide film (hereinafter referred to as a second oxide film), 5 a polycrystalline silicon layer, 6 a gate insulating film, 7 a gate electrode, 8 a channel, 9 a high concentration source / drain, 10 a low concentration source -Drain, 11 is an interlayer insulating film, 12 is a metal electrode, 13
Is a third silicon oxide film (hereinafter, third oxide film), 14
Is a metal light-shielding film, 15 is a second silicon nitride film (hereinafter, second nitride film), 17 is a transparent conductive film, 18 is a polycrystalline silicon element, 19 is a single crystal silicon element, and 20 is a first insulating layer. , 21 is a glass substrate, 22 is a light-shielding film, 23 is a color filter, 24 is a transparent counter electrode, 25 is a liquid crystal, 26 is a sealing material, 27 is an opening, 28 is a fourth silicon oxide film (hereinafter, referred to as a fourth silicon oxide film). Oxide film), 29 is an alignment film, and 30 is a second insulating layer.

The manufacturing process will be briefly described below.

A first oxide film 2 is formed on a silicon substrate 1 (a). A first nitride film 3 and a second oxide film 4 are stacked on the first oxide film 2 and patterned (b). A polycrystalline silicon layer 5 is laminated on the second oxide film 4 and patterned (c). After forming the gate insulating film 6, stacking and patterning the gate electrode 7, a channel 8, a high concentration source / drain 9 and a low concentration source / drain 10 are formed by ion implantation (d). After laminating the interlayer insulating film 11, the metal electrode 12 is formed and patterned (e). After stacking the third oxide film 13, the metal light-shielding film 14 is formed and patterned (f). After forming the second nitride film 15, the transparent conductive film 17 is formed and patterned (g).

An alignment film 29 made of an organic material such as polyimide is formed on the active matrix substrate, while a light-shielding film 22 made of a metal such as Cr, or a color made of a pigment or dye is formed on the glass substrate 21. A counter substrate provided with a filter 23, a transparent counter electrode 24 using an ITO film or the like, and an alignment film 29 is prepared and arranged to face the active matrix substrate. Spacers (not shown) for maintaining a space between both substrates are dispersed to seal both substrates.
It is sealed with 6 and the liquid crystal 25 is filled between the substrates (FIG. 2). Finally, the single crystal silicon substrate 1 in the display region is removed by anisotropic etching using the fourth oxide film 28 as a mask and the second oxide film 4 as an etching stopper layer to make the region light-transmissive.

In the light transmission type liquid crystal display device, ITO (Indium Tin O) is used as the pixel electrode (transparent conductive film 17).
A transparent conductive film such as xide) is used. Usually, an ITO film is often formed at a temperature of 200 ° C. or higher. For example, the temperature is 225 ° C., the pressure is 1.8 Torr, the SiH ₄ flow rate is 200 sccm, the Ar flow rate is 120 sccm, and the O ₂ flow rate is 1.2 sccm. , 140 nm thick at a deposition rate of 4.8 nm / min.

[0016]

However, the liquid crystal display device manufactured by the above method has some problems as described below.

(1) When patterning the ITO film,
Etching proceeds not only in the film thickness direction but also in the side wall direction. For example, when the ITO film is patterned under the above conditions, the ratio of the etching rate in the film thickness direction to the etching rate in the side wall direction is about 0.47.
The pattern becomes small when the O film is etched. This means that the precision of the fine processing of the ITO film is low, which is a major obstacle to the high definition of the liquid crystal display device.

(2) Leaf-like unevenness is observed on the surface of the ITO film obtained under the above conditions. I and I
The surface roughness of the TO film is 10 nm or more, indicating that the surface is not uniform. In liquid crystal display devices, IT
An alignment film for aligning liquid crystals is formed on the O film.
If the film surface is not uniform, a uniform alignment film cannot be formed, and uniform alignment of the liquid crystal cannot be realized. In particular, the liquid crystal layer on the ITO film becomes a portion for displaying a screen, which causes deterioration of display image quality.

(3) Plasma damage during formation of the ITO film affects the TFT. More specifically, it is a decrease in on-current, a decrease in driving force due to an increase in S value, etc., and a decrease in TFT performance causes deterioration in image display quality.

The above (3) can be solved by performing heat treatment after forming the ITO film or after patterning, but if the heat treatment step is increased by one step, or if appropriate heat treatment conditions are not selected, oxygen is desorbed from the ITO film, The ITO film is discolored black, and there arises a problem that the light transmittance is lowered. These problems not only occur in the liquid crystal display device described above, but also in other semiconductor devices using an ITO film and an insulating film containing hydrogen.

It is an object of the present invention to provide a semiconductor device substrate that solves the above problems. That is, having a single crystal semiconductor element and an amorphous semiconductor element on a single crystal substrate,
In a semiconductor element substrate in which the region where the amorphous semiconductor element is formed is transparent, an ITO film is formed with high accuracy and uniform surface, and plasma damage to the TFT is prevented to reduce the size and display image quality. An object of the present invention is to provide a semiconductor device such as a liquid crystal display device, which is intended to prevent deterioration.

[0022]

First, the present invention provides at least a single crystal semiconductor element on a single crystal semiconductor substrate, a non-single crystal semiconductor element formed through a transparent film, and an amorphous material. A transparent conductive film obtained by recrystallizing the conductive film, wherein the single crystal semiconductor substrate directly below the translucent film is removed, and the single crystal semiconductor element and the non-single crystal semiconductor element and the non-single crystal semiconductor element are transparent. The conductive film and the conductive film are electrically connected to each other.

A second aspect of the present invention is a method of manufacturing a semiconductor element substrate as described above, which comprises a step of forming a transparent film on a single crystal semiconductor substrate, and a non-single crystal semiconductor element on the transparent film. The method is characterized by including a step of forming, a step of forming a single crystal semiconductor element, a step of forming an amorphous conductive film, and a step of recrystallizing the amorphous conductive film to make it transparent.

Thirdly, the present invention provides a semiconductor device using the above semiconductor element substrate.

The semiconductor device of the present invention is preferably applied to a liquid crystal display device. Hereinafter, the present invention will be described with reference to a case of forming a liquid crystal display device as an example.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION In the method for manufacturing a semiconductor element substrate of the present invention, in step (g) shown in FIG. 4, an amorphous conductive film is once formed, and then the amorphous conductive film is heat-treated to form the amorphous conductive film. The feature is that the transparent conductive film 17 is obtained by recrystallization.

In the present invention, the amorphous conductive film is etched and patterned. However, since the etching rate on the side wall of the amorphous conductive film is smaller than that in the film thickness direction, the side wall is etched. It can be estimated small, and the patterning accuracy can be improved to achieve higher definition.

Further, when the transparent conductive film is once made amorphous and then heat-treated to be crystallized, the uniformity of the surface is improved.

Further, according to the manufacturing method of the present invention, plasma damage of the polycrystalline silicon layer can be recovered by the heat treatment of the amorphous conductive film.

Regarding the method of manufacturing the semiconductor element substrate of the present invention, the other steps are the same as the conventional one as long as they have the above characteristics, and various methods and conditions can be applied.

The manufacturing method of the present invention will be specifically described with reference to FIGS.

First, as a method for laminating the polycrystalline silicon layer 5 on the single crystal silicon substrate 1, an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method, or the like can be used. In this case, for example, in the low pressure CVD method, the pressure is 0.1 to
SiH ₄ , S at 5.0 Torr and temperature 450-900 ° C.
It is possible to dilute i ₂ H ₆ , Si ₂ Cl ₂ or the like with hydrogen or nitrogen. When SiH ₄ is diluted with nitrogen, the SiH ₄ concentration can be in the range of 20 to 30%. In the case of laminating a polycrystalline silicon layer using the thermal decomposition of SiH ₄ is not necessary to dilute the SiH _4. If Si ₂ H ₆ is used as a source gas, Si 2
A film can be formed at a lower temperature than H ₄ . Further, the plasma CVD method can reduce the film forming temperature to about 300 ° C.

Besides, it is also possible to recrystallize the amorphous silicon layer to obtain a polycrystalline silicon layer. in this case,
The amorphous silicon layer is a low pressure CVD method, a glow discharge method, an arc discharge method, a reactive sputtering method, a thermal CVD method, a photo CVD method.
Method, plasma CVD method, vapor deposition method or the like. As the lamination conditions, for example, in the glow discharge method, it is possible to use SiH ₄ , Si ₂ H ₆ , SiCl _4, or the like. In this case, SiH ₄ has a pressure of 0.
It is possible to stack the amorphous silicon layer in the range of 5 to 2.0 Torr, the temperature of 250 to 350 ° C., and the glow oscillation frequency of 50 to 450 Hz.

As the recrystallization method, a laser annealing method using a pulse beam of an argon laser, a CW laser beam, a Q-switch pulse laser beam, an excimer laser beam of KrF or XeCl, an electron beam, or the like, and a heat treatment. It is possible to use the solid phase growth method by

In the laser annealing method, room temperature to 300 ° C.
It is possible to carry out recrystallization within the range. In the solid phase growth method, recrystallization can be performed by heating with an infrared lamp or a strip heater in hydrogen or nitrogen at a temperature of 500 to 800 ° C. for 10 to 20 hours.

As for the gate insulating film 6, in addition to the oxide film,
Nitride film, alumina (Al ₂ O ₃ ), tantalum oxide (Ta
₂ O ₅ ), ONO (Oxidized-Nitride)
It is possible to use a dOxide) film, a oxynitride film (SiON), and a laminated film thereof.

The oxide film is formed by the thermal oxidation method or atmospheric pressure CVD.
Method, low pressure CVD method, plasma CVD method, or sputtering method. For thermal oxidation, pyrogenic oxidation, dry oxidation, wet oxidation, steam oxidation,
It can be performed by halogen oxidation using hydrochloric acid or the like. In the CVD method, TEOS (tetraethox)
It is also possible to use Y.

As a method for forming the nitride film, a thermal nitriding method, an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method, or the like can be used. Alumina or tantalum oxide is produced by forming Al or Ta by a sputtering method and then performing anodic oxidation.

As the gate electrode 7, it is possible to use high-concentration doped polycrystalline silicon (for example, n-type polycrystalline silicon or p-type polycrystalline silicon) or a metal electrode described later. Regarding the doping of polycrystalline silicon, it is possible to perform ion implantation in the vapor phase or ion implantation. For example, B, B
Using ions such as F ₂ to convert p-type polycrystalline silicon into P,
N-type polycrystalline silicon can be obtained by using ions such as Sb and As. In addition, it is also possible to use an excimer laser doping method in which impurity doping is performed during formation of amorphous silicon or polycrystalline silicon and activation is performed by an excimer laser or the like (amorphous silicon is simultaneously polycrystallized).

As the interlayer insulating film 11, BPSG (Bo
Rono-Phospho Silicate Gla
ss) film, NSG (Non-doped Sili)
Cate Glass) film, BSG film, PSG film and the like can be used.

For the metal electrode 12, Al, W, T
It is possible to use a, Ti, Cu, Cr, Mo, TaN, TiN, or a silicide thereof alone or in combination.

For the metal light-shielding film 14, the metal electrode 12
It is possible to use the same material as.

Second nitride film 15 which is an insulating film containing hydrogen
Is formed by a plasma CVD method and can function as a hydrogen supply source if the thickness is 10 nm or more.

As the amorphous conductive film, for example, amorphous ITO
The film can be formed at room temperature (25 ° C) to 150 ° C. As the etching method for the amorphous ITO film, HI / H ₃ PO ₂ as well as HBr / H ₃ PO ₂ and HI can be used.
It is also possible to use a mixed solution of / FeCl ₃ or the like.

The amorphous conductive film is crystallized by oxygen, nitrogen and Ar.
And the like, and a mixed gas of any of these, at a temperature of 200 to 350 ° C. for a treatment time of 10
It can be performed in the range of up to 120 minutes. It should be noted that if the heat treatment is performed in a reducing gas such as hydrogen, the ITO film is reduced and blackened. Therefore, a large amount of oxygen should be contained in the amorphous ITO film or a small amount of oxygen should be added under the above conditions. Heat treatment is performed by mixing hydrogen.

The pixel switching element is a pMOS
Either a transistor or an nMOS transistor can be used. PMOS transistor and nMOS
It is also possible to mount transistors together.

The peripheral drive circuit may have a CMOS structure or a Bi-CMOS structure including a bipolar transistor for further improving the driving capability. The structure of the MOS transistor can be a coplanar type, an inverted coplanar type, a staggered type, or an inverted staggered type.

Further, in order to provide the TFT with redundancy, it has a dual gate structure in which gate electrodes are arranged in parallel,
It is also possible to adopt a double gate structure in which gate electrodes are provided above and below the channel portion in order to increase the on / off ratio.

Further, in the present invention, as a method of etching the single crystal silicon substrate 1, TMAH (tetramethylammonium hydroxide), EDP (ethylenediaminepyrocatechol), hydrazine aqueous solution, KO is used.
It is possible to use an alkaline solution such as H solution (KOH / isopropanol, KOH / hydrazine mixed solution, etc.).

Further, the display area shown in FIG. 2 remains the opening 27 formed on the silicon wafer, but in this portion, the light transmittance of silicon rubber, epoxy resin, silicon oxide film, silicon nitride film or the like is obtained. It is also possible to improve the mechanical strength of the liquid crystal display portion by filling or depositing an insulating material.

Here, the mechanical strength of the liquid crystal display portion will be described in more detail.

In the liquid crystal display device shown in FIG. 2, when the silicon substrate immediately below the liquid crystal display portion is removed, the first oxide film 2, the first nitride film 3 and the second oxide film 4 which are insulating films are formed. There must be some tensile stress. If excessive compressive stress is applied to the insulating films 2 to 4, when the silicon substrate directly below the liquid crystal display portion is removed, the insulating films 2 to 4 will be wrinkled, or the weight of the injected liquid crystal will cause the insulating film to grow. 2 to 4 are dripping, which causes problems such as nonuniform cell thickness. On the contrary, if an excessive tensile stress is applied to the insulating films 2 to 4, when the silicon substrate directly below the liquid crystal display portion is removed, the insulating film 2
This causes problems such as cracks in 4 to 4. Therefore, in the case of a liquid crystal display device to which the semiconductor device of the present invention is applied, it is very important to control the stress applied to the insulating films 2 to 4 on which the pixel switching elements and the like are formed.

In this embodiment, a laminated film of an oxide film and a nitride film is used as the insulating film, but in the above film structure,
The film having the largest compressive stress was the first oxide film 2, and when laminated to a silicon wafer having a diameter of 150 mm to a thickness of 600 nm, the amount of warpage was about 42 μm. The film having the largest tensile stress is the first nitride film 3, which has a diameter of 150 mm.
When a 270 nm thick layer is stacked on a silicon wafer of mm,
The amount of warpage was about 47 μm.

Display area is diagonal 0.7 inch, cell thickness 4μ
In the case of a liquid crystal display device of m, tensile stress is applied to the active matrix substrate, and the warp amount is 0 to 15
It may be in the range of μm. When the amount of warpage exceeds 15 μm, the film is cracked due to tensile strength. Therefore, in the laminated structure of the film, if the stress and the amount of warp satisfy the above range in the state where the TFT array is formed on the substrate and the opening is provided and the element characteristics are not deteriorated, the film type, the film Thickness, stacking order, etc. can be freely set. The amorphous ITO film has very small internal stress, and even if it is crystallized, this characteristic does not change, which is convenient in designing the film structure.

Regarding other detailed manufacturing conditions and methods, those which can satisfy the performance required for the manufactured liquid crystal display device can be freely adopted.
For example, as a liquid crystal material, a TN (Twisted Nematic) is used in a TFT active matrix liquid crystal display device.
c) Liquid crystal is often used, but STN (SuperT
Wisted Nematic liquid crystal, FLC (Fer)
roelectric Liquid Crystal
l, Ferroelectric liquid crystal), AFLC (Anti-Ferro)
electric Liquid Crystal, antiferroelectric liquid crystal), PDLC (Polymer-Diff)
It is also possible to use a used liquid crystal (polymer dispersed liquid crystal) or the like. TN, STN,
In FLC and AFLC, it is necessary to provide polarizing plates above and below the liquid crystal display device, but in PDLC, liquid crystal display can be performed by a Schlieren optical system.

[0056]

EXAMPLE As an example of the present invention, the liquid crystal display device shown in FIG. 2 was produced by the following steps.

On an n-type silicon wafer having a plane orientation of <100>, a diameter of 150 mm, a thickness of 625 μm, and a specific resistance of 2.0 Ωcm, an acceleration voltage of 60 keV and a dose of 9 × 10 ¹² cm ^-2.
After injecting B ions at, the oxygen / nitrogen mixed gas (O ₂ :
A heat treatment was performed at 1150 ° C. for 840 minutes in N ₂ = 1: 5) to form the channel region 8 of the nMOS transistor of the single crystal silicon element 19.

The first oxide film 2 was formed on the portion where the TFT is to be formed by thermal oxidation. Here, it was performed in an oxygen / hydrogen mixed gas (O ₂ : H ₂ = 4: 6) under conditions of a temperature of 1000 ° C. and an oxidation rate of 4.6 nm / min, and a thickness of 550 n.
m oxide film was formed (pyrogenic oxidation). This oxide film was also formed on a portion to be a peripheral circuit, and element isolation of the single crystal silicon element 19 was also performed.

Next, the first nitride film 3 is formed by the low pressure CVD method.
Were laminated. Here, temperature 780 ° C., pressure 23 Pa, S
iH ₂ Cl ₂ flow rate 63 sccm, NH ₃ flow rate 630 sc
cm, and the deposition rate was 27.5 nm / min, and a nitride film having a thickness of 0.3 μm was laminated.

Subsequently, the surface of the first nitride film 3 was oxidized to form a second oxide film 4 having a thickness of 30 nm. Here, at a temperature of 1 in an oxygen / hydrogen mixed gas (O ₂ : H ₂ = 4: 6).
It was performed under conditions of 000 ° C. and an oxidation rate of 1.3 nm / min.

Next, a polycrystalline silicon layer 5 to be a TFT was laminated. Here, temperature 610 ° C., pressure 18 Pa, SiH
_{4 A} 70-nm-thick polycrystalline silicon layer was laminated under the conditions of a flow rate of 600 sccm and a deposition rate of 4.8 nm / min.
Subsequently, the acceleration voltage is 35 keV and the dose is 1 × 10 ¹² cm ^-2.
BF ₂ ions were implanted at 950 ° C. in nitrogen for 10
The heat treatment for 1 minute was performed to form the channel region 8 of the polycrystalline silicon layer 18. Further, the polycrystalline silicon layer 5 was patterned by anisotropic dry etching.

The polycrystalline silicon layer constitutes an nMOS pixel switching element, and the peripheral drive circuit has a CMOS configuration having a single crystal silicon layer. Here, the MOS transistor constituting the CMOS is of a coplanar type with gate self-alignment.

The gate insulating film 6 was formed by dry oxidation under the conditions of a temperature of 1150 ° C. and an oxidation rate of 4.5 nm / min and a thickness of 85 nm.

Subsequently, the gate electrode 7 was formed. Here, the temperature is 610 ° C., the pressure is 18 Pa, and the SiH ₄ flow rate is 60.
After depositing a polycrystalline silicon layer having a thickness of 440 nm under conditions of 0 sccm and a deposition rate of 5.5 nm / min, P ions are implanted at an accelerating voltage of 70 keV and a dose amount of 1.5 × 10 ¹⁶ cm ^-2 , and oxygen is further added. / Nitrogen mixed gas (O ₂ : N ₂ =
After heat treatment at 950 ° C. for 10 minutes in 1:20), anisotropic dry etching was performed to form a gate electrode.

Next, the source / drain regions of the MOS transistor were formed by ion implantation. Here, for the polycrystalline silicon element 18, which is a pixel switching element, P with an acceleration voltage of 95 keV and a dose of 1 × 10 ¹³ cm ^-2 is used.
Ions were implanted to form the source / drain regions of the nMOS transistor. As for the peripheral driving circuit, P ions having an acceleration voltage of 95 keV and a dose amount of 5 × 10 ¹⁵ cm ⁻² are implanted to form source / drain regions of the nMOS transistor, and an acceleration voltage of 100 keV and a dose amount of 3 × 10 ¹⁵ are formed.
BF ₂ ions of cm ⁻² were implanted to form the source / drain regions of the pMOS transistor. After the ion implantation, heat treatment was performed in nitrogen at 1000 ° C. for 10 minutes.

Subsequently, the thickness of the interlayer insulating film 11 is 700n.
After laminating m BPSG films, anisotropic dry etching was performed to form contact holes. BPS
After stacking the G film, an oxygen / nitrogen mixed gas (O ₂ : N ₂ = 1:
In 20), reflow was performed by heat treatment at 1000 ° C. for 5 minutes.

A metal electrode material such as aluminum was deposited by a sputtering method, and a predetermined wiring shape was dry-etched to form a wiring portion. Here Ti / TiN
/ Al-Si / TiN in order of 10/200/350/1
It was formed by stacking layers with a thickness of 00 nm. After the Ti / TiN layer was laminated, heat treatment was performed in nitrogen at 450 ° C. for 30 minutes.

Subsequently, the third oxide film 1 is formed by the plasma CVD method.
3 was formed, and the metal light shielding film 14 made of Ti was formed thereon. The third oxide film 13 has a temperature of 400 ° C. and a pressure of 1.
8 Torr, SiH ₄ flow rate 200 sccm, N ₂ O flow rate 6000 sccm, N ₂ flow rate 3150sccm, 2 using the plasma frequency exciting deposition rate 49.5 nm / min
Was deposited to a thickness of 950 nm under the above conditions. In addition, Ti was formed by laminating 200 nm thick at 200 ° C. by a sputtering method. By this step, the fourth oxide film 28 serving as a mask material was formed and patterned on the back surface side of the silicon wafer.

Plasma CVD is used as an insulating film containing hydrogen.
The second nitride film 15 was formed by the method. Here, the temperature is 400 ° C., the pressure is 2.8 Torr, and the SiH ₄ flow rate is 290 s.
ccm, NH ₃ flow rate 1900 sccm, N ₂ flow rate 100
Deposition rate 2 using plasma of 0 sccm and 2 frequency excitation
A second nitride film 15 having a thickness of 270 nm was formed under the condition of 0.8 nm / min. The hydrogen content in this nitride film is 5
%Met.

Subsequently, heat treatment is performed in hydrogen at 400 ° C. for 120 minutes to diffuse hydrogen from the second nitride film into the polycrystalline silicon layer. This is done to improve the characteristics of the polycrystalline silicon element 18. That is, it is intended to increase the electric mobility of polycrystalline silicon by diffusing hydrogen and to realize a high-speed operation of a TFT which is required to write an electric charge in a pixel in several μsec.

A through hole connected to the metal electrode 12 on the drain side of the pixel switching element was formed in the second nitride film 15, and a transparent conductive film 17 was formed as a pixel electrode. Here, the temperature is 100 ° C., the pressure is 2 mTorr, and O ₂
An amorphous ITO film having a thickness of 140 nm was deposited by a sputtering method under the conditions of partial pressure of 3% and Sn partial pressure of 10%. In this state, the pixel electrode was black and the light transmittance was 70%. After that, patterning was performed using a mixed solution of HI / H ₃ PO ₂ at 40 ° C. The etching amount in the side wall direction could be suppressed to about 14 nm.

After that, heat treatment was carried out in nitrogen at 400 ° C. for 120 minutes to crystallize the amorphous ITO film. As a result, the light transmittance of the ITO film became 95%. The surface roughness of the ITO film at this time was about several nm.

Then, a known liquid crystal display device assembling process was performed to fabricate a liquid crystal cell. Finally TM at 90 ℃
Anisotropic etching with AH was performed to remove a part of the n-type silicon wafer. Here, the first oxide film 2 serves as an etching stopper layer. The display part became light transmissive by the said process.

The liquid crystal display device of this embodiment is a high-performance liquid crystal display device which has a switching element and a drive circuit having better electric characteristics than the conventional device, and which is highly precise and in which the liquid crystal is uniformly aligned. It was

[0075]

As described above, according to the present invention,
It is possible to obtain a semiconductor element substrate provided with a high-quality transparent conductive film having good etching characteristics and a semiconductor element that is stably driven at high speed.

In the liquid crystal display device to which the semiconductor device of the present invention using the above semiconductor element substrate is applied, the amount of etching in the side wall direction can be suppressed in the manufacturing process of the transparent conductive film which is the pixel electrode, so that the pattern is small. It is possible to realize high definition of the display unit without causing a problem, and it is preferably applied to a projector with a more realistic and fine image display or a magnifying optical system.

Further, since the surface of the transparent conductive film crystallized from the amorphous state is uniform, it is possible to form a uniform alignment film and the uniform alignment of the liquid crystal, thereby providing a uniform and high-quality image display. Will be realized, and the yield in lighting inspection will be improved.

Further, at the same time as crystallization of the amorphous conductive film,
Since the plasma damage of the semiconductor element can be recovered, the characteristic deterioration of the semiconductor element can be suppressed, the manufacturing yield can be improved, and the effect can be obtained without increasing the total number of steps. The manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of a semiconductor element substrate of the present invention.

FIG. 2 is a cross-sectional view showing a liquid crystal display device which is an embodiment of a semiconductor device of the present invention.

FIG. 3 is a diagram showing a manufacturing process of the semiconductor element substrate shown in FIG.

FIG. 4 is a diagram showing a manufacturing process of the semiconductor element substrate shown in FIG.

FIG. 5 is a schematic configuration diagram of an active matrix substrate of a liquid crystal display device.

[Explanation of symbols]

 1 silicon substrate 2 first silicon oxide film 3 first silicon nitride film 4 second silicon oxide film 5 polycrystalline silicon layer 6 gate insulating film 7 gate electrode 8 channel 9 high concentration source / drain 10 low concentration source / drain 11 Interlayer Insulating Film 12 Metal Electrode 13 Third Silicon Oxide Film 14 Metal Light Shielding Film 15 Second Silicon Nitride Film 17 Transparent Conductive Film 18 Polycrystalline Silicon Element 19 Single Crystal Silicon Element 20 First Insulating Layer 21 Glass Substrate 22 Light Shielding Film 23 Color filter 24 Transparent counter electrode 25 Liquid crystal 27 Encapsulant 27 Opening 28 Fourth silicon oxide film 29 Alignment film 30 Second insulating layer 51 Pixel switching element 52 Buffer circuit 53 Horizontal scanning circuit 54 Vertical scanning circuit 55 pixels Electrode 56 substrate

Claims (5)

[Claims] 1. A transparent conductive film obtained by recrystallizing an amorphous conductive film, and at least a single crystal semiconductor device, a non-single crystal semiconductor device formed through a translucent film, on a single crystal semiconductor substrate. And the single crystal semiconductor substrate directly below the translucent film is removed, and the single crystal semiconductor element and the non-single crystal semiconductor element and the non-single crystal semiconductor element and the transparent conductive film are electrically connected, respectively. A semiconductor element substrate characterized in that 2. The semiconductor element substrate according to claim 1, wherein the transparent conductive film is a film containing indium oxide as a main component. 3. The method for manufacturing a semiconductor element substrate according to claim 1, wherein the step of forming a light-transmitting film on the single crystal semiconductor substrate, and the non-single-crystal semiconductor on the light-transmitting film. A step of forming an element, a step of forming a single crystal semiconductor element,
A method of manufacturing a semiconductor device substrate, comprising: a step of forming an amorphous conductive film; and a step of recrystallizing the amorphous conductive film to make it transparent. 4. The method of manufacturing a semiconductor device substrate according to claim 3, wherein the amorphous conductive film is formed at 25 to 150 ° C. and then patterned. 5. A semiconductor device using the semiconductor element substrate according to claim 1.