JPH09293876A - Semiconductor element substrate, manufacture thereof, and semiconductor device using its substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high precision, a uniform surface, miniaturization and prevention of deterioration in display picture quality, by providing at least a semiconductor layer, and a transparent conductive film formed by recrystallizing an insulating film containing hydrogen and an amorphous conductive film, on a substrate. SOLUTION: Metal electrodes 19 are formed on high-density source and drain 15 of a polycrystalline silicon element 13, and a transparent conductive film 20 is formed on one of the metal electrodes 19. These are electrically insulated by an interlayer insulating film 21 formed on the gate electrodes 19, except with the high-density source and drain 15. A silicon oxide film 22 is stacked on the interlayer insulating film 21, and a metal shielding film 23 is formed thereon. A silicon nitride film 24 is formed on the metal shielding film 23. This nitride film 24 contains a large quantity of hydrogen. The transparent conductive film 20 is obtained by a process of recrystallizing the amorphous state so as to be transparent and simultaneously diffusing hydrogen from the nitride film 24 into the polycrystalline silicon element 13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element substrate having a semiconductor element and a method for manufacturing the same, and further to a semiconductor device using the semiconductor element substrate.

[0002]

2. Description of the Related Art A liquid crystal display device, which is one of semiconductor devices, is used in home appliances such as small TVs, flat panel displays such as notebook personal computers, car navigation systems and viewfinders, and projection T displays.
It is used as various display devices such as V and HMD. The most widely used liquid crystal display device at present is of a type in which each pixel is driven in an active matrix, and an active matrix substrate in which thin film transistors (TFTs) are arranged in a matrix as switching elements is used.

FIG. 12 is a schematic block diagram of an active matrix substrate used in a liquid crystal display device. In the figure, 60 is a TFT which is a pixel switching element, 61 is an image signal circuit,
62 is a synchronizing circuit, 63 is a horizontal scanning circuit, 64 is a vertical scanning circuit, 65 is a pixel electrode, and 66 is a substrate.

In FIG. 12, an image signal is sent to an image signal circuit 61 and then transferred to a pixel switching element 60 via a horizontal scanning circuit 63 and a vertical scanning circuit 64. As a result, a signal is written in the pixel electrode 65 and an image is displayed. The synchronizing circuit 62 is for timing the horizontal scanning circuit 63 and the vertical scanning circuit 64 which transfer the image signal.

In such an active matrix type liquid crystal display device, an amorphous silicon element or a polycrystalline silicon element is often used as a pixel switching element. Currently, in a large-screen panel with a diagonal size of 5 inches or more, a TFT is made of amorphous silicon that has good uniformity and low off-current characteristics, and can be formed on a large-area glass substrate at low temperature, and IC is used as a peripheral circuit. As externally connected. For a small panel with a diagonal of less than 5 inches, a TFT and a peripheral drive circuit are formed of polycrystalline silicon on the same substrate in order to reduce the size and cost of a liquid crystal display device by incorporating a peripheral drive circuit. There is.

FIG. 1 is a process chart showing a method of manufacturing an active matrix substrate in which a TFT is formed of polycrystalline silicon. Here, only the manufacturing process of the TFT in question will be schematically shown below. In FIG. 1, 1 is an insulating substrate, 2 is polycrystalline silicon, 3 is a gate insulating film, 4 is a gate electrode, 5 is a channel, 6 is a source, 7 is a drain, 8 is an insulating film containing hydrogen, and 9 is a metal. The electrodes 10 are transparent conductive films. The steps in FIG. 1 are as follows.

(A) After depositing the polycrystalline silicon layer 2 on the insulating substrate 1, patterning is performed.

(B) The gate insulating film 3 is laminated and patterned.

(C) The gate electrode 4 is formed and patterned.

(D) Ions are implanted into the polycrystalline silicon layer 2 to form a channel 5, a source 6 and a drain 7.
To form

(E) After forming the insulating film 8 containing hydrogen,
Patterning is performed to expose a part of the source 6 and the drain 7.

(F) The metal electrode 9 is laminated and patterned.

(G) The transparent conductive film 10 is stacked and patterned, and hydrogen is diffused from the insulating film 8 containing hydrogen into the polycrystalline silicon layer 2 by heat treatment.

After the above steps, an active matrix type polycrystalline silicon TFT is formed through the steps of forming an alignment film, alignment treatment, bonding with a counter substrate, and liquid crystal injection.
A liquid crystal display device was manufactured.

In the step (g), hydrogen is diffused into the polycrystalline silicon layer 2, but this is done to improve the characteristics of the TFT. That is,
By the hydrogenation method or the annealing method described above, it is intended to increase the electric mobility of the polycrystalline silicon and realize the high speed operation of the TFT which is required to write the electric charge in the pixel in several μs. As described above, in the hydrogenation method, after forming a film containing hydrogen on polycrystalline silicon, the hydrogen in the film is bonded to a carrier trap in a grain boundary of polycrystalline silicon by heat treatment, so that carrier transfer occurs. In the annealing method, the polycrystalline silicon is heat-treated at a temperature of 600 ° C. for 10 to 20 hours to increase the crystal grain size of the polycrystalline silicon to several μm so that the carrier mobility is increased. It is intended to improve.

In the above active matrix type liquid crystal display device, a transparent quartz glass is used as the insulating substrate 1, a silicon oxide film is used as the gate insulating film 3, an impurity-doped polycrystalline silicon electrode is used as the gate electrode 4, and an aluminum electrode is used as the metal electrode 9. , ITO as transparent conductive film
A silicon nitride film formed by a plasma CVD method is often used as the (Indium Tin Oxide) film and the insulating film 8 containing hydrogen. For the ITO film, for example, the temperature is 225 ° C., the pressure is 1.8 Torr, the SiH ₄ flow rate is 200 sccm, the Ar flow rate is 120 sccm, and the O ₂ flow rate is 1.2 sccm, and the deposition rate is 4.8 using the sputtering method.
There is a specific example of depositing a thickness of 140 nm under the condition of nm / min.

[0017]

However, the liquid crystal display device manufactured by the above method has some problems as described below.

(1) When patterning the ITO film,
Etching proceeds not only in the film thickness direction but also in the side wall direction. For example, when the ITO film is patterned under the above conditions, the ratio of the etching rate in the film thickness direction to the etching rate in the side wall direction is about 0.47.
The pattern becomes small when the O film is etched. This means that the precision of the fine processing of the ITO film is low, which is a major obstacle to the high definition of the liquid crystal display device.

(2) Leaf-like unevenness is observed on the surface of the ITO film obtained under the above conditions. I and I
The surface roughness of the TO film is 10 nm or more, indicating that the surface is not uniform. In liquid crystal display devices, IT
An alignment film for aligning liquid crystals is formed on the O film.
If the film surface is not uniform, a uniform alignment film cannot be formed, and uniform alignment of the liquid crystal cannot be realized. In particular, the liquid crystal layer on the ITO film becomes a portion for displaying a screen, which causes deterioration of display image quality.

(3) Plasma damage during formation of the ITO film affects the TFT. More specifically, it is a decrease in on-current, a decrease in driving force due to an increase in S value, etc., and a decrease in TFT performance causes deterioration in image display quality.

The above (3) can be solved by performing heat treatment after forming the ITO film or after patterning, but if the heat treatment step is increased by one step, or if appropriate heat treatment conditions are not selected, oxygen is desorbed from the ITO film, The ITO film is discolored black, and there arises a problem that the light transmittance is lowered. These problems not only occur in the liquid crystal display device described above, but also in other semiconductor element substrates using an ITO film and an insulating film containing hydrogen.

It is an object of the present invention to provide a semiconductor device substrate that solves the above problems. That is, in a semiconductor element substrate, a semiconductor device such as a liquid crystal display device, which is highly precise and has a uniform surface, further prevents plasma damage to a TFT, forms an ITO film, and is downsized and prevents deterioration of display image quality. The purpose is to provide.

[0023]

First, the present invention provides a semiconductor device substrate in which at least a semiconductor layer, an insulating film containing hydrogen, and an amorphous conductive film are recrystallized on the substrate. It is characterized by having a transparent conductive film which is formed.

A second aspect of the present invention provides a method for manufacturing a semiconductor device substrate, comprising the steps of forming an amorphous conductive film and recrystallizing the amorphous conductive film to make it transparent. And diffusing hydrogen from the insulating film containing hydrogen into the semiconductor layer.

Thirdly, the present invention provides a semiconductor device using the above semiconductor element substrate.

The semiconductor device of the present invention is preferably applied to a liquid crystal display device. Hereinafter, the present invention will be described with reference to a case of forming a liquid crystal display device as an example.

[0027]

BEST MODE FOR CARRYING OUT THE INVENTION In the method for manufacturing a semiconductor element substrate of the present invention, in the step (g) shown in FIG. 1, an amorphous conductive film is once formed and then the amorphous conductive film is heat-treated. The transparent conductive film 10 is obtained by recrystallization, and hydrogen is diffused from the insulating film 8 containing hydrogen into the polycrystalline silicon layer 2.

In the present invention, the amorphous conductive film is etched and patterned. However, since the etching rate on the side wall of the amorphous conductive film is smaller than that in the film thickness direction, the amount of side wall etching is reduced. It can be estimated small, and the patterning accuracy can be improved to achieve higher definition.

Further, when the transparent conductive film is once made amorphous and then heat-treated to be crystallized, the uniformity of the surface is enhanced.

Further, according to the manufacturing method of the present invention, plasma damage of the polycrystalline silicon layer can be recovered by the heat treatment of the amorphous conductive film.

The process shown in FIG. 1 is a schematic process, and when actually manufacturing a semiconductor element substrate, a more complicated structure and process are required. As a specific example thereof, an example of manufacturing a light transmissive liquid crystal display device incorporating a peripheral circuit will be shown below.

[First Embodiment] FIG. 2 is a cross-sectional view of a first embodiment of a semiconductor element substrate of the present invention.

In this embodiment, the transparent quartz glass 1
A polycrystalline silicon element 13 is formed on the surface 2. The polycrystalline silicon element 13 is provided with a channel 14, a high concentration source / drain 15 and a low concentration source / drain 16 in a polycrystalline silicon layer, and a gate electrode with a gate insulating film 17 sandwiched on the polycrystalline silicon layer. 18 is provided.

A metal electrode 19 is formed on the high-concentration source / drain 15 of the polycrystalline silicon element 13, and a transparent conductive film 20 is formed on one of the metal electrodes 19. These are electrically insulated from the layers other than the high-concentration source / drain 15 by the interlayer insulating film 21 formed on the gate electrode 19.

A silicon oxide film 22 is formed on the interlayer insulating film 21.
(Hereinafter referred to as an oxide film), and a metal light-shielding film 23 for preventing external light from entering the polycrystalline silicon element 13.
Are formed. The metal light shielding film 23 is electrically insulated from the metal electrode 19 and the transparent conductive film 20 by the oxide film 22. A silicon nitride film 24 is formed on the metal light-shielding film 23.
(Hereinafter, a nitride film) is formed.

The nitride film 24 contains a large amount of hydrogen in the film. After the transparent conductive film 20 is formed in an amorphous state,
It is obtained by crystallization in the step of diffusing hydrogen from the nitride film 24 into the polycrystalline silicon element 13.

27 and 28 are both polycrystalline silicon MO
S transistor, for example, 27 is p-type, 28 is n-type and is C
A peripheral drive circuit for driving the polycrystalline silicon element 13 is constituted by a MOS structure.

FIG. 3 is a sectional view of a liquid crystal display device manufactured using the semiconductor element substrate shown in FIG. Here, FIG.
The same reference numerals as in FIG.

In FIG. 3, a polycrystalline silicon element 13 as a pixel switching element and a polycrystalline silicon pMOS transistor 27 and a polycrystalline silicon nMOS transistor 28 as a peripheral driving circuit are formed on a transparent quartz glass 12 and a transparent pixel electrode. The transparent conductive film 20 is connected to the polycrystalline silicon element 13, and the polycrystalline silicon element 13 and the peripheral drive circuit are covered with the insulating layer 30.

The glass substrate 3 is opposed to the transparent conductive film 20.
1 is arranged on the glass substrate 31 and, for example, C
A light shielding film 32 made of a metal such as r, a color filter 33 made of a pigment or a dye, and a transparent counter electrode 34 are formed.

A liquid crystal alignment film 35 made of an organic material such as polyimide is formed on the transparent counter electrode 34 and the transparent conductive film 20. Liquid crystal 36 is filled between the liquid crystal alignment films 35, and the periphery thereof is sealed with a sealing material 37, and at the same time, the semiconductor element substrate and the glass substrate 31.
And are pasted together. Although not shown, a spacer is arranged inside in order to keep the space between both substrates.

The manufacturing method of the liquid crystal display device of this embodiment is not particularly limited as long as it includes the manufacturing method of the present invention, and various methods and conditions can be applied.

For example, although the transparent quartz glass 12 is used as the substrate in the above embodiment, other fused quartz glass,
High melting point glass, borosilicate glass, synthetic quartz glass or the like can be used.

As a method for laminating the polycrystalline silicon layer, an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method or the like can be used. In this case, for example, in the low pressure CVD method, the pressure is 0.1 to 5.0 Torr and the temperature is 450 to 900.
It is possible to dilute SiH ₄ , Si ₂ H ₆ , Si ₂ Cl _{2 and the} like with hydrogen or nitrogen at ℃. SiH ₄
Is diluted with nitrogen, the SiH ₄ concentration can be in the range of 20 to 30%. When a polycrystalline silicon layer is laminated by utilizing thermal decomposition of SiH ₄ ,
_No need to dilute ₄ . When Si ₂ H ₆ is used as the source gas, it is possible to form a film at a lower temperature than SiH ₄ . In the plasma CVD method, the film forming temperature is 30
It is possible to lower the temperature to about 0 ° C.

Besides, it is also possible to recrystallize the amorphous silicon layer to obtain a polycrystalline silicon layer. in this case,
The amorphous silicon layer is a low pressure CVD method, a glow discharge method, an arc discharge method, a reactive sputtering method, a thermal CVD method, a photo CVD method.
Method, plasma CVD method, vapor deposition method or the like. As the lamination conditions, for example, in the glow discharge method, it is possible to use SiH ₄ , Si ₂ H ₆ , SiCl _4, or the like. In this case, SiH ₄ has a pressure of 0.
It is possible to stack the amorphous silicon layer in the range of 5 to 2.0 Torr, the temperature of 250 to 350 ° C., and the glow oscillation frequency of 50 to 450 Hz.

As the recrystallization method, a laser annealing method using a pulse beam of an argon laser, a CW laser beam, a Q switch pulse laser beam, an excimer laser beam of KrF or XeCl, an electron beam or the like, and a heat treatment are used. It is possible to use the solid phase growth method by

In the laser annealing method, room temperature to 300 ° C.
It is possible to carry out recrystallization within the range. In the solid phase growth method, recrystallization can be performed by heating with an infrared lamp or a strip heater in hydrogen or nitrogen at a temperature of 500 to 800 ° C. for 10 to 20 hours.

For the gate insulating film 17, the above-mentioned acid is used.
In addition to oxide film, nitride film, alumina (Al _Two O_Three ), Tan oxide
Taru (Ta_Two O_Five ), ONO (Oxidized-Ni
trixed oxide film, oxynitride film (SiO)
N) and laminated films of these can be used.

The oxide film is formed by the thermal oxidation method or atmospheric pressure CVD.
Method, low pressure CVD method, plasma CVD method, or sputtering method. For thermal oxidation, pyrogenic oxidation, dry oxidation, wet oxidation, steam oxidation,
It can be performed by halogen oxidation using hydrochloric acid or the like. In the CVD method, TEOS (tetraethox)
It is also possible to use Y.

As a method of forming the nitride film, a thermal nitriding method, an atmospheric pressure CVD method, a low pressure CVD method, a plasma CVD method or the like can be used. Alumina or tantalum oxide is produced by forming Al or Ta by a sputtering method and then performing anodic oxidation.

As the gate electrode 18, it is possible to use a highly-doped polycrystalline silicon (for example, n-type polycrystalline silicon or p-type polycrystalline silicon) or a metal electrode described later. Regarding doping of polycrystalline silicon, in addition to ion doping in the vapor phase,
It can be performed by ion implantation or the like. For example, B,
P-type polycrystalline silicon using ions such as BF ₂
N-type polycrystalline silicon can be obtained by using ions such as P, Sb and As. In addition, it is also possible to use an excimer laser doping method in which impurity doping is performed during formation of amorphous silicon or polycrystalline silicon and activation is performed by an excimer laser or the like (amorphous silicon is simultaneously polycrystallized).

As the interlayer insulating film 21, BPSG (Bo
Rono-Phospho Silicate Gla
ss) film, NSG (Non-doped Sili)
Cate Glass) film, BSG film, PSG film and the like can be used.

For the metal electrode 19, Al, W, T
It is possible to use a, Ti, Cu, Cr, Mo, TaN, TiN, or a silicide thereof alone or in combination.

For the metal light-shielding film 23, the metal electrode 19
It is possible to use the same material as.

The nitride film 24 which is an insulating film containing hydrogen is C
If it is formed by the VD method and has a thickness of 10 nm or more, it can function as a hydrogen supply source.

As the amorphous conductive film, for example, amorphous ITO
The film can be formed at room temperature to 120 ° C. The etching method for the amorphous ITO film is HI /
In addition to H ₃ PO ₂ , HBr / H ₃ PO ₂ , HI / FeCl ₃
It is also possible to use a mixed solution such as.

Crystallization of the amorphous conductive film and diffusion of hydrogen into the polycrystalline silicon layer are carried out at a temperature of 350 to 500 ° C. in an inert gas such as oxygen, nitrogen, Ar or a mixed gas thereof. The processing time can be 10 to 120 minutes. When the heat treatment is performed in hydrogen, the ITO film is reduced and blackened. Therefore, the amorphous ITO film should be made to contain a large amount of oxygen, or a slight amount of hydrogen should be mixed under the above conditions to perform the heat treatment. Will be done.

The pixel switching element is a pMOS
Either a transistor or an nMOS transistor can be used. In addition, pMOS transistor and nMO
It is also possible to mount the S transistor together.

The peripheral driving circuit may have a CMOS structure or a Bi-CMOS structure including a bipolar transistor for further improving the driving capability. The MOS structure may be a coplanar type, an inverted coplanar type, a staggered type, or an inverted staggered type.

Further, in order to provide the TFT with redundancy, it has a dual gate structure in which gate electrodes are arranged in parallel,
It is also possible to adopt a double gate structure in which gate electrodes are provided above and below the channel portion in order to increase the on / off ratio.

In addition, when a low temperature process such as a plasma CVD method, a sputtering method, or a laser annealing method is adopted in the TFT array manufacturing process, the TFT or the periphery is formed on a transparent glass substrate (for example, non-alkali glass such as Corning 7059, 1733). A drive circuit can be manufactured. Regarding the positional relationship between the polycrystalline silicon layer, the insulating film containing hydrogen, and the transparent conductive film, it suffices to take a position where hydrogen is sufficiently supplied to the polycrystalline silicon layer, for example, between the transparent quartz glass and the polycrystalline silicon layer. It is also possible to provide an insulating film containing hydrogen. However, in this case, since the steps up to and including the temperature used for the crystallization of the amorphous conductive film and the diffusion treatment of hydrogen to the polycrystalline silicon layer must be performed, the film formation is performed by the plasma CVD method or the sputtering method. It is appropriate to use the method.

Regarding other detailed manufacturing conditions and methods, those which can satisfy the performance required for the manufactured liquid crystal display device can be freely adopted.
For example, as a liquid crystal material, a TN (Twisted Nematic) is used in a TFT active matrix liquid crystal display device.
c) Liquid crystal is often used, but STN (SuperT
Wisted Nematic liquid crystal, FLC (Fer)
roelectric Liquid Crystal,
Ferroelectric liquid crystal), AFLC (Anti-Ferroel)
electric Liquid Crystal, antiferroelectric liquid crystal), PDLC (Polymer-Diffus)
ed Liquid Crystal, polymer dispersed liquid crystal) or the like can also be used. TN, STN, F
In LC and AFLC, it is necessary to provide polarizing plates above and below a liquid crystal display device, but in PDLC, liquid crystal display can be performed by a Schlieren optical system.

[Embodiment 2] FIG. 4 shows a sectional view of a second embodiment of the semiconductor element substrate of the present invention. In the figure, the same members as those in FIG.

In this embodiment, the silicon substrate 38
A first silicon oxide film 39 (hereinafter,
First oxide film), first silicon nitride film 40 (hereinafter, first nitride film) and second silicon oxide film 41 (hereinafter,
A second oxide film) is formed, and the same polycrystalline silicon element 13 as that of the first embodiment is formed on the second oxide film 41. Reference numeral 42 is a third silicon oxide film (hereinafter, third oxide film), and 43 is a second silicon nitride film (hereinafter, second nitride film). The second nitride film contains a large amount of hydrogen in the film.

In the present embodiment, the peripheral drive circuit is made of a CMOS structure of single crystal silicon,
Is a pMOS transistor, and 46 is an nMOS transistor.

Further, a fourth silicon oxide film 47 (hereinafter, referred to as a fourth silicon oxide film 47, directly below the first oxide film 39, the first nitride film 40, and the second oxide film 41 on which the polycrystalline silicon element 13 is formed).
The opening 48 is provided using the fourth oxide film) as a mask material.

FIG. 5 is a sectional view of a liquid crystal display device constructed by using the semiconductor element substrate shown in FIG. Here, the same members as those in FIGS. 3 and 4 are designated by the same reference numerals, and the description thereof will be omitted.

Also in this embodiment, as in the first embodiment described above, the polycrystalline silicon element 13 connected to the transparent conductive film 20 is used as a pixel switching element, and a CM including a pMOS transistor 45 and an nMOS transistor 46.
The OS circuit is used as a peripheral drive circuit, the alignment film 35 is provided on the surface, and the liquid crystal is injected by being attached to the counter substrate similar to that in Embodiment 1.

The liquid crystal display device of the present embodiment is also a light transmission type, and external light can be incident from above to see the image displayed through the opening 48.

In the method of manufacturing the liquid crystal display device shown in FIG. 5, the same members as those in the liquid crystal display device of FIG. 3 are as described above.

In this embodiment, the etching method of the silicon substrate 38 is TMAH (tetramethylammonium hydroxide), EDP (ethylenediaminepyrocatechol), hydrazine aqueous solution, KOH solution (KOH / isopropanol, KOH / hydrazine mixed solution, etc.). It is possible to use an alkaline solution such as.

Further, in the present embodiment, the display portion remains the opening 48 formed on the silicon wafer, but in this portion, a light-transmissive insulating material such as silicon rubber, epoxy resin or silicon oxide film, silicon nitride film is formed. It is also possible to improve the mechanical strength of the liquid crystal display portion by filling or depositing the material.

Here, the mechanical strength of the liquid crystal display portion will be described in more detail.

In the liquid crystal display device shown in FIG. 5, when the silicon substrate directly below the liquid crystal display portion is removed, the first oxide film 39, the first nitride film 40 and the second oxide film 4 which are insulating films are formed.
1 must have some tensile stress. Here, if excessive compressive stress is applied to the insulating films 39 to 41, when the silicon substrate directly below the liquid crystal display portion is removed, the insulating films 39 to 41 may be wrinkled or the weight of the injected liquid crystal may cause the insulating films 39 to 41 to wrinkle. 39 to 41 are dripping, which causes a problem such as nonuniform cell thickness. On the contrary, if excessive tensile stress is applied to the insulating films 39 to 41, when the silicon substrate immediately below the liquid crystal display portion is removed, problems such as cracks in the insulating films 39 to 41 occur. . Therefore, in the case of the liquid crystal display device of this embodiment, it is very important to control the stress applied to the insulating films 39 to 41 in which the pixel switching elements and the like are formed.

In this embodiment, a laminated film of an oxide film and a nitride film is used as the insulating film, but in the above film structure,
The film having the largest compressive stress was the first oxide film 39, and when the silicon oxide wafer having a diameter of 150 mm was stacked to a thickness of 600 nm, the amount of warpage was about 42 μm. The film having the largest tensile stress is the first nitride film 40, which has a diameter of 1
When laminated 270 nm thick on a 50 mm silicon wafer, the amount of warpage was about 47 μm.

Display area is diagonal 0.7 inch, cell thickness 4 μ
In the case of a liquid crystal display device of m, tensile stress is applied to the active matrix substrate, and the warp amount is 0 to 15
It may be in the range of μm. When the amount of warpage exceeds 15 μm, the film is cracked due to tensile strength. Therefore, in the laminated structure of the film, if the stress and the amount of warp satisfy the above range in the state where the TFT array is formed on the substrate and the opening is provided and the element characteristics are not deteriorated, the film type, the film Thickness, stacking order, etc. can be freely set. The amorphous ITO film has very small internal stress, and even if it is crystallized, this characteristic does not change, which is convenient in designing the film structure.

[Third Embodiment] FIG. 6 shows a sectional view of a semiconductor element substrate according to a third embodiment of the present invention. Also in this figure,
The same members as those in FIGS. 2 and 4 are designated by the same reference numerals and the description thereof will be omitted.

The feature of this embodiment is that the peripheral drive circuit is
I element (Silicon on Insulator)
52 is a pMOS transistor, 5
3 is an nMOS transistor.

FIG. 7 shows a cross-sectional view of a liquid crystal display device in which a counter substrate is attached to the semiconductor element substrate of FIG. 6 in the same manner as in the first and second embodiments. This liquid crystal display device is also shown in FIG.
Similar to the liquid crystal display device shown in FIG. 3, the liquid crystal display device is a light transmissive liquid crystal display device having an opening 48 as a display portion.

The SOI used in the peripheral drive circuit in this embodiment
The element is a single crystal silicon element provided over an insulating layer or an insulator. The SOI element has (1) easy dielectric separation and high integration, and (2) excellent radiation resistance.
(3) Stray capacitance is reduced to enable high speed, (4) Well process can be omitted, (5) Latch-up can be prevented, (6) Full depletion type field effect transistor is possible by thinning, etc. It has many advantages over semiconductor devices manufactured on a single crystal silicon layer.

The liquid crystal display device of this embodiment is a high-performance liquid crystal display device which has a switching element and a drive circuit having good electric characteristics and has high definition and in which liquid crystals are uniformly aligned. Further, by forming the peripheral driving circuit with the SOI element, higher driving force and stability can be obtained, and the above-described advantages can be obtained.

The semiconductor element substrate of this embodiment is formed by removing the single crystal silicon layer of the display portion after each element is formed on the substrate having the SOI structure. As a method for manufacturing an SOI substrate, an ion implantation method, a direct bonding method, or the like can be used. The ion implantation method is a method of implanting ions into a silicon substrate to embed an insulating layer. Particularly, a method of implanting oxygen ions to manufacture an SOI substrate is SIM.
It is called the OX method and is widely used. The direct bonding method is a method in which two silicon substrates are bonded to each other with an insulating layer interposed therebetween, and one silicon substrate is thinned to be manufactured. Polishing or etching is used as a thinning method. Has been.

The SOI substrate used in this embodiment can be manufactured by any method. For example, when the ion implantation method is used, it is possible to implant oxygen ions into a silicon substrate to form an oxide film and nitrogen ions to implant a nitride film. , And their laminates can be used. At this time, for oxygen ions, for example, an acceleration voltage of 180 keV and a dose amount of 3.5 to 4.0 × 10 ^{17 are used.}
cm ⁻² and then 1350 in Ar / O ₂ gas mixture.
By heat treatment at 240 ° C. for 240 minutes, the dislocation density in the single crystal silicon layer can be reduced to 10 ⁻² cm or less.

When the direct bonding method is used in this embodiment, there is no limitation on the insulating layer, and the forming method, film thickness, etc. can be freely selected according to the purpose of the semiconductor element substrate to be manufactured. . The bonding conditions may be atmospheric air, oxygen, nitrogen, an inert gas such as Ar, a mixed gas with any of these, a vacuum, pure water, or the like. Regarding the heat treatment conditions after bonding, the temperature is 900 to 1 in oxygen, nitrogen, or oxygen / nitrogen mixed gas.
It is possible to freely select in the range of 200 ° C.

The present embodiment is the same as the second embodiment except that the peripheral drive circuit is formed by the SOI element. Therefore, for the details other than the above, the same conditions and methods shown in the second embodiment are applied. can do.

[Fourth Embodiment] FIG. 8 is a sectional view of a semiconductor element substrate according to a fourth embodiment of the present invention. 2 to 7 in the figure
The same members as those in FIG.

The feature of this embodiment is that the transparent quartz glass 12 is used.
On top, a polycrystalline silicon element 13 and an SOI element p
MOS transistor 52 and nMOS transistor 5
3 is provided. In this embodiment, the transparent quartz glass 12 and a single crystal silicon substrate are bonded together to form the single crystal S.
It is formed by thinning the i substrate from the back surface.

In this embodiment, the transparent quartz glass 12 is used as the substrate, but fused quartz glass, high melting point glass, borosilicate glass, synthetic quartz glass or the like can be used. The heat treatment conditions after bonding the glass and the single crystal Si substrate are as follows: melting point, strain point,
It can be determined in consideration of the coefficient of thermal expansion and the like. For example, in the case of transparent quartz glass and a silicon substrate in oxygen,
In nitrogen, mixed gas of oxygen and nitrogen, temperature 200-500
It can be freely selected within the range of ° C.

The present embodiment uses an SOI substrate manufactured by a direct bonding method of a single crystal silicon substrate and an insulator,
Further, it is manufactured by the same manufacturing method as that of the semiconductor element substrate shown in the third embodiment except that the silicon substrate is made a light transmissive type without being etched. Therefore, the conditions and method described in the third embodiment can be applied to the details of the present embodiment.

[Fifth Embodiment] FIG. 9 shows a sectional view of a semiconductor element substrate according to a fifth embodiment of the present invention. 2 to 8 in the figure
The same members as are denoted by the same reference numerals.

In this embodiment, an amorphous silicon element 55 and a pMOS transistor 27 and an nMOS transistor 28 which are polycrystalline silicon elements are formed on a glass substrate 54. In the amorphous silicon element 55, the channel 14 and the high-concentration source / drain 15 are provided in the amorphous silicon layer, and the amorphous silicon layer includes the gate electrode 18 provided on the glass substrate 54 and the gate insulating film. 1
It is located across 7.

A metal electrode 19 is formed on the high-concentration source / drain 15 of the amorphous silicon element 55, and one of the metal electrodes 19 is connected to the transparent conductive film 20 formed on the gate insulating film 17. ing. The metal electrode 19 is
The gate insulating film 17 and the nitride film 24 electrically insulate other than the high-concentration source / drain 15. The nitride film 24 contains a large amount of hydrogen in the film.

In addition, the MOS transistors 27 and 28, which are polycrystalline silicon elements, have channel 1 in the polycrystalline silicon layer.
4. The high-concentration source / drain 15 is provided, and the polycrystalline silicon layer is located between the gate electrode 18 provided on the glass substrate 54 and the gate insulating film 17. The metal electrode 1 is also formed on the high-concentration source / drain 15.
9 is formed, and the metal electrode 19 is the gate insulating film 1
7 and the nitride film 24 electrically insulate other than the high concentration source / drain 15.

The transparent conductive film 20 is obtained by being crystallized at the same time in the step of diffusing hydrogen from the nitride film 24 into the amorphous silicon element 55 and the polycrystalline silicon elements 27 and 28 after being formed in an amorphous state. It has been done.

FIG. 10 is a cross-sectional view of a light-transmissive liquid crystal display device using the semiconductor element substrate of FIG. 9 and adhering the same counter substrates as those of the first to third embodiments.

In this embodiment, the amorphous silicon layer is a low pressure CVD method, a glow discharge method, an arc discharge method, a reactive sputtering method, a thermal CVD method, a photo CVD method, a plasma CVD method.
It is possible to stack them by using a method, a vapor deposition method, or the like. The lamination conditions are, for example, SiH ₄ , S in the glow discharge method.
It is possible to use i ₂ H ₆ , SiCl _4, or the like.
In this case, the pressure of SiH ₄ is 0.5 to 2.0 Torr,
Temperature 250-350 ° C, glow oscillation frequency 50-450
It is possible to stack an amorphous silicon layer in the range of Hz.

The present embodiment is different from the first embodiment except that the pixel switching element is formed of an amorphous silicon element.
The same conditions and methods as in Embodiments 1 to 4 can be applied to the details. For example, the peripheral driver circuit can be formed using a single crystal silicon element or an SOI element. After forming an amorphous silicon element over a silicon substrate with an insulating layer interposed therebetween, the silicon substrate of the display portion is removed. It is also possible to make it. The structure of the transistor can be a coplanar type, an inverted coplanar type, a staggered type, or an inverted staggered type.

[Sixth Embodiment] FIG. 11 is a sectional view of a semiconductor element substrate according to a sixth embodiment of the present invention. In this figure, the same members as those in FIG.

In this embodiment, a thin film diode (Thin) is used instead of the amorphous silicon element 55 in the fifth embodiment.
This is a configuration in which a film diode (TFD) 56 is provided. 57 is a lower electrode, 59 is an upper electrode, and 58 is an inter-electrode insulating layer. TFD is usually such MIM
Since it has a (Metal-Insulator-Metal) structure, it is not necessary to form an amorphous silicon layer or a polycrystalline silicon layer.

Regarding the TFD used in this embodiment, Al, W, Ta, and T are used as the upper electrode 59 and the lower electrode 57.
It is possible to use metal electrodes such as i, Cu, Cr, Mo, TaN, and TiN, and the insulating layer between the electrodes is an oxide film, a nitride film, alumina, tantalum oxide, an ONO film, a nitrided oxide film, or the like. It is possible to use a laminated film. The TFD device structure may be a tandem structure in which TFD elements are arranged in parallel to improve characteristics as a switching element.

The details other than those described above are the same as in the fifth embodiment, and the same conditions and methods as in the fifth embodiment can be applied.

[0102]

【Example】

Example 1 The liquid crystal display device shown in FIG. 3 was manufactured by the following steps.

A polycrystalline silicon layer was laminated on a transparent quartz glass 12 having a diameter of 150 mm and a thickness of 625 μm. Here, temperature 610 ° C., pressure 18 Pa, SiH ₄ flow rate 600
sccm, with the addition of BH ₃ diluted to 10% in H _2,
A 50 nm-thick polycrystalline silicon layer was laminated under the condition of a deposition rate of 4.8 nm / min to form a TFT channel region. Further, the polycrystalline silicon layer is patterned by anisotropic dry etching. Then, a pixel switching element having an nMOS structure and a peripheral driving circuit having a CMOS structure were formed on the polycrystalline silicon layer. Here, the MOS transistor is a coplanar type with gate self-alignment.

The gate insulating film 17 was formed by sputtering at a temperature of 200 ° C. and had a thickness of 70 nm.

Subsequently, the gate electrode 18 was formed.
Here, the temperature is 610 ° C., the pressure is 18 Pa, and the SiH ₄ flow rate is 6
After depositing a polycrystalline silicon layer having a thickness of 440 nm under the conditions of 00 sccm and a deposition rate of 5.5 nm / min, P ions are implanted at an accelerating voltage of 70 kev and a dose amount of 1.5 × 10 ¹⁶ cm ^-2. Oxygen / nitrogen mixed gas (O ₂ : N
After heat treatment at 950 ° C. for 20 minutes in ₂ = 1: 20), anisotropic dry etching was performed to form the gate electrode 18.

Source / drain regions of the MOS transistor were formed by ion implantation. Here, for the pixel switching element 13, an acceleration voltage of 95 keV, P ions with a dose amount of 1 × 10 ¹³ cm ⁻² are implanted to form the source / drain regions of the nMOS transistor, and for the peripheral drive circuit, an acceleration voltage of 95 keV, a dose. Amount 5 × 10
Injecting ¹⁵ cm ^-2 P ions into the nMOS transistor 2
8 source / drain regions are formed, and the acceleration voltage is 100k.
BF ₂ ions having an eV and a dose of 3 × 10 ¹⁵ cm ⁻² were implanted to form the source / drain regions of the pMOS transistor 27. After ion implantation, in nitrogen at 900 ℃, 20
Heat treatment was performed for 1 minute.

Then, as the interlayer insulating film 21, a thickness of 700 is obtained.
After laminating a BPSG film of nm thickness, anisotropic dry etching was performed to form a contact hole. In addition, BP
After the SG film is laminated, an oxygen / nitrogen mixed gas (O ₂ : N ₂ =
Reflow was performed by heat treatment at 850 ° C. for 10 minutes in 1:20).

A metal electrode material such as aluminum was deposited by a sputtering method, and a predetermined wiring shape was dry-etched to form a wiring portion. Here, Ti / Ti
N / Al-Si / TiN sequentially 10/200/300 /
It was formed by laminating with a thickness of 100 nm. Also, Ti / TiN
After the lamination, the heat treatment was performed in nitrogen at 450 ° C. for 30 minutes.

Next, the metal light-shielding film 23 was formed via the silicon oxide film 22. The silicon oxide film 22 was formed by a plasma CVD method, and Ti was used as a metal light shielding film.
Silicon oxide film 22 has a temperature of 400 ° C. and a pressure of 1.8 Torr
r, SiH ₄ flow rate 200 sccm, N ₂ O flow rate 6000
It was deposited to a thickness of 950 nm under the conditions of a deposition rate of 49.5 nm / min using a plasma of sccm, N ₂ flow rate of 3150 sccm, and two-frequency excitation. Further, Ti was formed by stacking 200 nm thick at 200 ° C. by a sputtering method.

Subsequently, plasma C is formed as an insulating film containing hydrogen.
The silicon nitride film 24 was formed by the VD method. Here, the temperature is 400 ° C., the pressure is 2.8 Torr, and the SiH ₄ flow rate is 29.
0 sccm, NH ₃ flow rate 1900 sccm, N ₂ flow rate 1
A silicon nitride film 24 having a thickness of 270 nm was formed under the conditions of a deposition rate of 20.8 nm / min using plasma of 2,000 sccm and dual frequency excitation. The hydrogen content in this nitride film was 5%.

A contact hole connected to the metal electrode 19 on the drain side of the pixel switching element was formed in the nitride film, and a transparent conductive film 20 was formed as a pixel electrode. Here, the temperature is 120 ° C., the pressure is 2 mTorr, and the O ₂ partial pressure is 0.4.
%, Sn partial pressure 10%, thickness 8 by sputtering method
A 0 nm amorphous ITO film was deposited. In this state, the pixel electrode was black and the light transmittance was 75%. After that, the pixel electrode was patterned. HI / H at 40 ℃
_When a mixed solution of ₃ PO ₂ is used, the ratio of the etching rate in the film thickness direction to the etching rate in the side wall direction is 10
Becomes That is, here, the etching amount in the side wall direction is set to 8
It becomes possible to suppress to about nm.

Thereafter, heat treatment is performed in nitrogen at 350 ° C. for 120 minutes to crystallize the amorphous ITO film and at the same time hydrogen is diffused from the silicon nitride film 24 into the polycrystalline silicon layer. Crystallization of the amorphous ITO film resulted in a light transmittance of 90%. The surface roughness of the ITO film is several n.
m was about the same as when the amorphous ITO film was formed. After that, a liquid crystal cell was produced by a known liquid crystal display device assembling process to obtain a liquid crystal display device.

The light transmissive liquid crystal display device incorporating the peripheral drive circuit of this embodiment has a switching element and a drive circuit having better electric characteristics than before, and has a high definition and high performance in which liquid crystals are uniformly aligned. It was a liquid crystal display device.

[Embodiment 2] As a second embodiment of the present invention,
The liquid crystal display device shown in FIG. 5 was manufactured by the following steps.

On an n-type silicon wafer having a plane orientation of <100>, a diameter of 150 mm, a thickness of 625 μm and a specific resistance of 2.0 Ωcm, an acceleration voltage of 60 keV and a dose of 9 × 10 ¹² cm ^-2.
After injecting B ions at, the oxygen / nitrogen mixed gas (O ₂ :
The channel region 14 of the nMOS transistor 46 is formed by performing heat treatment at 1150 ° C. for 840 minutes in N ₂ = 1: 5).
Was formed.

The first oxide film 39 was formed by thermal oxidation on the portion where the TFT is to be formed. Here, it was performed in an oxygen / hydrogen mixed gas (O ₂ : H ₂ = 4: 6) under conditions of a temperature of 1000 ° C. and an oxidation rate of 4.6 nm / min, and a thickness of 550.
nm oxide film was formed (pyrogenic oxidation). This oxide film is also formed on the part that becomes the peripheral circuit, and the pMOS
Element isolation of the transistor 45 and the nMOS transistor 46 was also performed.

Next, the first nitride film 4 is formed by the low pressure CVD method.
0 was laminated. Here, the temperature is 780 ° C., the pressure is 23 Pa,
SiH ₂ Cl ₂ flow rate 63 sccm, NH ₃ flow rate 630 s
A nitride film having a thickness of 0.3 μm was laminated under the conditions of ccm and a deposition rate of 27.5 nm / min.

Then, the surface of the first nitride film 40 was oxidized to form a second oxide film 41 having a thickness of 30 nm. Here, it was performed in an oxygen / hydrogen mixed gas (O ₂ : H ₂ = 4: 6) under conditions of a temperature of 1000 ° C. and an oxidation rate of 1.3 nm / min.

Next, a polycrystalline silicon layer to be a TFT was laminated. Here, temperature 610 ° C., pressure 18 Pa, SiH ₄
A 70-nm-thick polycrystalline silicon layer was stacked under the conditions of a flow rate of 600 sccm and a deposition rate of 4.8 nm / min. Subsequently, BF ₂ ions were implanted at an accelerating voltage of 35 keV and a dose of 1 × 10 ¹² cm ^-2 , and then heat treatment was performed in nitrogen at 950 ° C. for 10 minutes to form a channel region 14 of the TFT. Further, the polycrystalline silicon layer was patterned by anisotropic dry etching.

A pixel switching element having an nMOS structure is constituted by the polycrystalline silicon layer, and a peripheral driving circuit has a CMOS structure having a single crystal silicon layer. Here, the MOS transistor constituting the CMOS is of a coplanar type with gate self-alignment.

The gate insulating film 17 was formed by dry oxidation under the conditions of a temperature of 1150 ° C. and an oxidation rate of 4.5 nm / min and a thickness of 85 nm.

Subsequently, the gate electrode 18 was formed.
Here, the temperature is 610 ° C., the pressure is 18 Pa, and the SiH ₄ flow rate is 6
After depositing a 440 nm-thick polycrystalline silicon layer under the conditions of 00 sccm and a deposition rate of 5.5 nm / min, P ions are implanted at an accelerating voltage of 70 keV and a dose amount of 1.5 × 10 ¹⁶ cm ^-2 , and oxygen is further added. / Nitrogen mixed gas (O ₂ : N ₂
= 1: 20), heat treatment was performed at 950 ° C. for 10 minutes, and then anisotropic dry etching was performed to form a gate electrode.

Next, the source / drain regions of the MOS transistor were formed by ion implantation. Here, with respect to the pixel switching element, P ions having an acceleration voltage of 95 keV and a dose amount of 1 × 10 ¹³ cm ⁻² were implanted to form the source / drain regions of the nMOS transistor. The peripheral drive circuit has an acceleration voltage of 95 keV and a dose of 5 × 1.
The source / drain regions of the nMOS transistor 46 are formed by implanting P ions of 0 ¹⁵ cm ^-2 , and the acceleration voltage is 100
BF ₂ ions having a keV and a dose of 3 × 10 ¹⁵ cm ⁻² were implanted to form the source / drain regions of the pMOS transistor 45. 1000 ° C in nitrogen after ion implantation,
Heat treatment was performed for 10 minutes.

Subsequently, an interlayer insulating film 21 having a thickness of 700 n is formed.
After laminating m BPSG films, anisotropic dry etching was performed to form contact holes. BPS
After stacking the G film, an oxygen / nitrogen mixed gas (O ₂ : N ₂ = 1:
In 20), reflow was performed by heat treatment at 1000 ° C. for 5 minutes.

A metal electrode material such as aluminum is deposited by a sputtering method, and a predetermined wiring shape is dry-etched to form a wiring portion. Here Ti / TiN
/ Al-Si / TiN in order of 10/200/350/1
It was formed by stacking layers with a thickness of 00 nm. After the Ti / TiN layer was laminated, heat treatment was performed in nitrogen at 450 ° C. for 30 minutes.

Then, the third oxide film 4 is formed by the plasma CVD method.
2 was formed, and the metal light-shielding film 23 made of Ti was formed thereon. The third oxide film 42 has a temperature of 400 ° C. and a pressure of 1.
8 Torr, SiH ₄ flow rate 200 sccm, N ₂ O flow rate 6000 sccm, N ₂ flow rate 3150sccm, 2 using the plasma frequency exciting deposition rate 49.5 nm / min
Was deposited to a thickness of 950 nm under the above conditions. In addition, Ti was formed by laminating 200 nm thick at 200 ° C. by a sputtering method. By this step, the fourth oxide film 47 serving as a mask material was formed and patterned on the back surface side of the silicon wafer.

Plasma CVD as an insulating film containing hydrogen
The second nitride film 43 was formed by the method. Here, the temperature is 400 ° C., the pressure is 2.8 Torr, and the SiH ₄ flow rate is 290 s.
ccm, NH ₃ flow rate 1900 sccm, N ₂ flow rate 100
Deposition rate 2 using plasma of 0 sccm and 2 frequency excitation
A second nitride film 43 having a thickness of 270 nm was formed under the condition of 0.8 nm / min. The hydrogen content in this nitride film is 5
%Met.

A contact hole connected to the metal electrode 19 on the drain side of the pixel switching element was formed in the second nitride film 43, and the transparent conductive film 20 was formed as the pixel electrode. Here, the temperature is 100 ° C., the pressure is 2 mTorr,
An amorphous ITO film having a thickness of 140 nm was deposited by a sputtering method under the conditions of O ₂ partial pressure of 3% and Sn partial pressure of 10%. In this state, the pixel electrode was black and the light transmittance was 70%. After that, patterning was performed using a mixed solution of HI / H ₃ PO ₂ at 40 ° C. The etching amount in the side wall direction could be suppressed to about 14 nm.

Thereafter, heat treatment was performed in nitrogen at 400 ° C. for 120 minutes to crystallize the amorphous ITO film, and at the same time, hydrogen was diffused from the second nitride film 43 into the polycrystalline silicon layer. The light transmittance of the ITO film was 90% due to crystallization, and the surface roughness was about several nm as in Example 1.

After that, a known liquid crystal display device assembling process was performed to fabricate a liquid crystal cell. Finally TM at 90 ℃
AH (tetramethylammonium hydroxide)
Anisotropic etching was performed to remove a part of the n-type silicon wafer. Here, the first oxide film 39 serves as an etching stopper layer. The display part became light transmissive by the said process.

The liquid crystal display device of this embodiment is a high-performance liquid crystal display device which has a switching element and a drive circuit having better electric characteristics than the conventional device, and which is highly precise and in which the liquid crystal is uniformly aligned. . Further, by forming the peripheral driving circuit with a single crystal silicon element, higher driving force and stability could be obtained.

[Embodiment 3] As a third embodiment of the present invention,
The liquid crystal display device shown in FIG. 7 was manufactured by the following steps.

A first oxide film 39 was formed by thermal oxidation on a p-type silicon wafer having a plane orientation of <100>, a diameter of 150 mm, a thickness of 625 μm, and a specific resistance of 0.1 Ωcm. Here, it was performed in an oxygen / hydrogen mixed gas (O ₂ : H ₂ = 4: 6) under the conditions of a temperature of 1000 ° C. and an oxidation rate of 4.6 nm / min to form an oxide film having a thickness of 550 nm.

Next, the first nitride film 4 is formed by the low pressure CVD method.
0 was laminated. Here, the temperature is 780 ° C., the pressure is 23 Pa,
SiH ₂ Cl ₂ flow rate 63 sccm, NH ₃ flow rate 630 s
A nitride film having a thickness of 0.3 μm was laminated under the conditions of ccm and a deposition rate of 27.5 nm / min.

Then, the surface of the first nitride film 40 was oxidized to form a second oxide film 41 having a thickness of 30 nm. Here, it was performed in an oxygen / hydrogen mixed gas (O ₂ : H ₂ = 4: 6) under conditions of a temperature of 1000 ° C. and an oxidation rate of 1.3 nm / min.

The second oxide film 41 and the plane orientation <10
0>, diameter 150 mm, thickness 625 μm, specific resistance 1.5
After bonding the n-type silicon wafer of Ωcm in nitrogen, heat treatment was performed in nitrogen at 1150 ° C. for 5 minutes to completely bond the both. Next, after thinning the n-type silicon wafer to a thickness of 0.3 μm, the single crystal silicon layer was patterned by RIE (reactive ion etching) to expose a part of the second oxide film 41. Here, an n-type silicon wafer was thinned to a thickness of 1.0 μm by grinding and polishing, and then plasma etching was performed at a pressure of Torr and an accelerating voltage of 1 eV or less to obtain a single crystal silicon layer having the above thickness.

Thereafter, the acceleration voltage is 60 keV and the dose amount is 9
After implanting B ions at × 10 ¹² cm ^-12 , the mixture was placed in an oxygen / nitrogen mixed gas (O ₂ : N ₂ = 1: 5) at 1150 ° C. and 84
A heat treatment for 0 minutes was performed to form a channel region of the nMOS transistor 53.

In this embodiment, the CMOS transistor is of a coplanar type with gate self-alignment.

Next, a polycrystalline silicon layer was laminated by the low pressure CVD method. Here, temperature 656 ℃, pressure 0.2
Si in a mixed gas of 5 Torr, SiH ₄ and H ₂
H ₄ partial pressure 0.15 Torr, deposition rate 300 nm / mi
A polycrystalline silicon layer having a thickness of 100 nm was laminated under the condition of n. Subsequently, the acceleration voltage is 35 keV and the dose amount is 1 × 10 ^12.
After implanting BF ₂ ions at cm ⁻² , 950 in nitrogen.
A heat treatment was performed at 10 ° C. for 10 minutes to form a channel region of the pixel switching element. Further, the polycrystalline silicon layer was patterned by anisotropic dry etching.

A liquid crystal display device was constructed in the same manner as in Example 2 below.

The liquid crystal display device of the present embodiment is a high-performance liquid crystal display device having a switching element and a drive circuit having good electric characteristics as compared with the conventional device, and having a high definition and in which the liquid crystal is uniformly aligned. . Further, by forming the peripheral driving circuit with a single crystal silicon element, higher driving force and stability could be obtained.

[Embodiment 4] As a fourth embodiment of the present invention,
A liquid crystal display device using the semiconductor element substrate shown in FIG. 8 was manufactured by the following steps.

A transparent quartz glass 12 having a diameter of 150 mm and a thickness of 625 μm, a plane orientation <100>, a diameter of 150 mm,
After bonding an n-type silicon wafer having a thickness of 625 μm and a specific resistance of 2.5 Ωcm in nitrogen, 450 ° C. in nitrogen,
Heat treatment was performed for 2 hours to completely bond the both.

Next, after thinning the n-type silicon wafer,
The single crystal silicon layer was patterned by RIE (reactive ion etching) to expose a part of the transparent quartz glass 12. After that, the same steps as in Example 2 were performed to obtain a liquid crystal display device. Since quartz glass is used in this embodiment, it is not necessary to etch the silicon substrate.

The liquid crystal display device of this embodiment is a high-performance liquid crystal display device having a switching element and a drive circuit having better electric characteristics than the conventional device, and having a high definition and in which liquid crystals are uniformly aligned. . Further, by forming the peripheral driving circuit with the SOI element, higher driving force and stability could be obtained. Further, in this embodiment, since etching from the back surface side for forming the opening in the active matrix substrate is not necessary, it is possible to relatively easily consider the process simplification and the film stress during device structure design.

[Embodiment 5] As a fifth embodiment of the present invention,
The liquid crystal display device shown in FIG. 10 was manufactured by the following manufacturing process.

The gate electrode 18 was formed on a transparent glass substrate 54 (here, Asahi Glass AN) having a diameter of 150 mm and a thickness of 625 μm. Here, it is 100 to 2 by the sputtering method.
The gate electrode 18 was formed by laminating aluminum having a thickness of 200 nm at 00 ° C.

Next, the surface of the gate electrode 18 is anodized to form alumina, which is further subjected to plasma CVD to form 2
A 350 nm-thick nitride film was formed at 50 to 350 ° C. to form the gate insulating film 17.

Then, a plasma CVD method is performed to 230-2.
An amorphous silicon layer having a thickness of 10 nm was stacked at 80 ° C.
Further, the energy intensity is 200 mJ / cm ² , the wavelength is 30
The amorphous silicon layer in the peripheral circuit portion was annealed with an 8 nm XeCl excimer laser beam to form a polycrystalline silicon layer.

A thickness of 100 n is provided on the peripheral circuit section and the display section.
m amorphous silicon layers are stacked, and n is used as a contact layer.
^{+ An} amorphous silicon layer was laminated. After patterning these silicon layers, an amorphous ITO film serving as a pixel electrode was formed by sputtering at 100 ° C. to a thickness of 80 nm. H
After patterning the amorphous ITO film using a mixed solution of I / H ₃ PO ₂ , a metal electrode 19 was formed.
Here, the thickness is 15 at 100 to 150 ° C. by the sputtering method.
Aluminum of 0 nm was laminated to form a metal electrode 19.

After that, a silicon nitride film 24 was formed as an insulating layer containing hydrogen by a plasma CVD method. Here, 230 to 28 using the dual frequency excitation plasma CVD method.
A 270 nm thick nitride film was formed at 0 ° C.

Next, heat treatment is performed in nitrogen at 350 ° C. for 120 minutes to crystallize the amorphous ITO film, and hydrogen is diffused from the silicon nitride film 24 into the amorphous silicon layer and the polycrystalline silicon layer. Let

The pixel switching element has an nMOS structure, the peripheral drive circuit has a CMOS structure, and each is composed of an inverted staggered MOS transistor.

After that, a liquid crystal cell was produced by a known liquid crystal display device assembling process to obtain a light transmission type liquid crystal display device.

The liquid crystal display device of the present embodiment is a high-performance liquid crystal display device having a switching element and a drive circuit having better electric characteristics than the conventional device, and having a high definition and in which the liquid crystal is uniformly aligned. .

[Embodiment 6] As a sixth embodiment of the present invention,
A liquid crystal display device using the semiconductor element substrate shown in FIG. 11 was manufactured by the following steps.

A TFD was formed on a transparent glass substrate 54 (here, NEG OA-2) having a diameter of 150 mm and a thickness of 625 μm.
The lower electrode 57 and the gate electrode 18 were formed. Here, the TFD lower electrode 57 and the gate electrode 18 were formed by stacking Ta having a thickness of 100 nm at 100 to 150 ° C. by the dual frequency excitation sputtering method.

Next, in a 5 wt% ammonium borate solution, a voltage of 54 V and a current density of 0.4 mA / cm ² were applied to anodic oxidation to make the surface of Ta ₂ O _{5 the} inter-electrode insulating layer 58 of the TFD.
Was formed. The insulating layer also serves as a gate insulating film.

Then, plasma C is formed on the inter-electrode insulating layer 58.
An amorphous silicon layer having a thickness of 50 nm was stacked at 230 to 280 ° C. by the VD method. Further, after implanting P or B ions into the source / drain regions, the energy intensity is 300
The amorphous silicon layer was annealed by irradiating it with a KrF excimer laser beam of mJ / cm ⁻² and a wavelength of 248 nm for 45 nsec to form a polycrystalline silicon layer.

After patterning the polycrystalline silicon layer, an amorphous ITO film serving as a pixel electrode was formed by sputtering at 100 ° C. to a thickness of 80 nm. After patterning the amorphous ITO film using a mixed solution of HI / H ₃ PO ₂ , a TFD upper electrode 59 and a metal electrode 19 were formed. Here, Ti having a thickness of 150 nm was laminated at 100 to 150 ° C. by the sputtering method to form the above electrode.

Thereafter, the nitride film 24 is formed in the same manner as in the fifth embodiment.
Was formed, and hydrogen was diffused from the nitride film 24 into the polycrystalline silicon layer by heat treatment, and at the same time, the amorphous ITO film was crystallized to be transparent.

Through the above steps, the pixel switching element has a TFD of MIM structure, and the peripheral drive circuit has a polycrystalline silicon CMOS structure. Then, a liquid crystal cell was produced by a known liquid crystal display device assembling process to obtain a light transmission type liquid crystal display device.

The liquid crystal display device of the present embodiment is a high-performance liquid crystal display device having a switching element and a drive circuit having better electric characteristics than the conventional device, and having a high definition and in which the liquid crystal is uniformly aligned. .

[0164]

As described above, according to the present invention,
It is possible to obtain a semiconductor element substrate provided with a high-quality transparent conductive film having good etching characteristics and a semiconductor element that is stably driven at high speed.

In the liquid crystal display device to which the semiconductor device of the present invention using the above semiconductor element substrate is applied, the amount of etching in the side wall direction can be suppressed in the manufacturing process of the transparent conductive film which is the pixel electrode, so that the pattern is small. It is possible to realize high definition of the display unit without causing the problem, and it is preferably applied to a projector with a more realistic and fine image display or a magnifying optical system.

Further, since the surface of the transparent conductive film crystallized from the amorphous state is uniform, it is possible to realize the formation of a uniform alignment film and the uniform alignment of the liquid crystal, thereby providing a uniform and high-quality image display. Will be realized, and the yield in lighting inspection will be improved.

Furthermore, the plasma damage of the semiconductor element can be recovered at the same time when the amorphous conductive film is crystallized and the hydrogen is diffused from the insulating film to the semiconductor layer.
It is possible to suppress the characteristic deterioration of the semiconductor element, improve the manufacturing yield, and obtain the effect without increasing the total number of steps, so that the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a manufacturing process of a semiconductor element substrate of the present invention.

FIG. 2 is a cross-sectional view of the semiconductor element substrate of the first embodiment of the present invention.

FIG. 3 is a cross-sectional view of the liquid crystal display device of the first embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor element substrate according to a second embodiment of the present invention.

FIG. 5 is a sectional view of a liquid crystal display device according to a second embodiment of the present invention.

FIG. 6 is a sectional view of a semiconductor element substrate according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a liquid crystal display device according to a third embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor element substrate according to a fourth embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor element substrate according to a fifth embodiment of the present invention.

FIG. 10 is a sectional view of a liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 11 is a sectional view of a semiconductor element substrate of a sixth embodiment of the present invention.

FIG. 12 is a schematic configuration diagram of an active matrix substrate of an active matrix type liquid crystal display device.

[Explanation of symbols]

 1 Insulating Substrate 2 Polycrystalline Silicon Layer 3 Gate Insulating Film 4 Gate Electrode 5 Channel 6 Source 7 Drain 8 Insulating Film Containing Hydrogen 9 Metal Electrode 10 Transparent Conductive Film 12 Transparent Quartz Glass 13 Polycrystalline Silicon Element 14 Channel 15 High Concentration Source・ Drain 16 Low concentration source / drain 17 Gate insulating film 18 Gate electrode 19 Metal electrode 20 Transparent conductive film 21 Interlayer insulating film 22 Silicon oxide film 23 Metal light-shielding film 24 Silicon nitride film 27 Polycrystalline silicon pMOS transistor 28 Polycrystalline silicon nMOS transistor 30 Insulating Layer 31 Glass Substrate 32 Light-shielding Film 33 Color Filter 34 Transparent Counter Electrode 35 Liquid Crystal Alignment Film 36 Liquid Crystal 37 Sealing Material 38 Silicon Substrate 39 First Silicon Oxide Film 40 First Silicon Nitride Film 41 Second Silicon Oxide Film2 Third Silicon Oxide Film 43 Second Silicon Nitride Film 45 pMOS Transistor 46 nMOS Transistor 47 Fourth Silicon Oxide Film 48 Opening 49 First Insulating Layer 50 Second Insulating Layer 51 SOI Element 52 SOI-pMOS Transistor 53 SOI-nMOS transistor 54 Glass substrate 55 Amorphous silicon element 56 Thin film diode (TFD) 57 Lower electrode 58 Inter-electrode insulating layer 59 Upper electrode 60 Pixel switching element (TFT) 61 Image signal circuit 62 Synchronous circuit 63 Horizontal scanning circuit 64 Vertical scanning circuit 65 Pixel electrode 66 Substrate

Claims (7)

[Claims] 1. A semiconductor device substrate comprising at least a semiconductor layer, an insulating film containing hydrogen, and a transparent conductive film formed by recrystallizing an amorphous conductive film on a substrate. 2. The semiconductor element substrate according to claim 1, wherein the semiconductor layer is made of an amorphous semiconductor or a polycrystalline semiconductor. 3. The semiconductor element substrate according to claim 1, wherein the insulating film containing hydrogen is a silicon nitride film. 4. The semiconductor element substrate according to claim 1, wherein the transparent conductive film is a film containing indium oxide as a main component. 5. The method of manufacturing a semiconductor device substrate according to claim 1, wherein the step of forming an amorphous conductive film and the step of recrystallizing the amorphous conductive film to make it transparent are performed simultaneously. And a step of diffusing hydrogen from an insulating film containing hydrogen into the semiconductor layer. 6. The method for manufacturing a semiconductor element substrate according to claim 5, wherein the insulating layer containing hydrogen is formed by a plasma CVD method. 7. A semiconductor device using the semiconductor element substrate according to claim 1 as an active matrix substrate.