JP2008124104A - Manufacturing method for semiconductor substrate, semiconductor substrate, semiconductor device, electrooptic device, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor substrate inhibiting the deterioration of the electrical characteristics of a semiconductor layer resulting from a substrate floating effect and displaying excellent electrical characteristics, to provide a semiconductor substrate, to provide a semiconductor device, to provide an electrooptic device, and to provide electronic equipment. <P>SOLUTION: A non-single-crystal semiconductor layer 210 is formed on one surface side of a single-crystal semiconductor substrate 200, and an insulating layer 211 is formed on the top face of the non-single-crystal semiconductor layer 210. Ions are implanted into the single-crystal semiconductor substrate 200 from the insulating layer 211 side to form an ion implanting layer 205. After the ions are implanted, a supporting substrate 500 is laminated on the insulating layer 211 side of the single-crystal semiconductor substrate 200. A surface layer section reverse to the non-single-crystal semiconductor layer 210 in the single-crystal semiconductor substrate 200 is separated by the ion implanting layer 205, and a single-crystal semiconductor layer 220 is formed on the supporting substrate 500. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, a semiconductor device, an electro-optical device, and an electronic apparatus.

  SOI (Silicon On Insulator) technology, in which a silicon film is formed on an insulating substrate and a semiconductor layer is formed on the silicon film, is widely researched because it has advantages of higher speed, lower power consumption and higher integration of the semiconductor layer Has been. As an example of this SOI technique, a technique for manufacturing an SOI substrate by bonding a single crystal silicon substrate is known. In this method, which is generally called a bonding method, a single crystal silicon substrate and a supporting substrate are bonded together by hydrogen bonding force, and then the bonding strength is enhanced by heat treatment. Next, the single crystal silicon substrate is polished or etched, whereby a single crystal silicon film is formed over the supporting substrate. In this method, since a single crystal silicon film is directly thinned, a high performance device with excellent crystallinity of the silicon film can be manufactured.

  As an application example of the above bonding method, there is a method in which hydrogen ions are implanted on a single crystal silicon substrate, bonded to a supporting substrate, and then a silicon thin film is separated from a hydrogen implanted region of the single crystal silicon substrate by heat treatment. It is known (see, for example, Patent Document 1). In addition, a single crystal silicon thin film is epitaxially grown on a silicon substrate having a porous surface, bonded to the support substrate, the silicon substrate is removed, and the porous silicon layer is etched, thereby epitaxially growing the single crystal silicon film on the support substrate. A technique for forming a crystalline silicon thin film is also known (see, for example, Patent Document 2). The SOI substrate based on the above bonding method is used for manufacturing various devices in the same way as an ordinary bulk semiconductor substrate. However, unlike a conventional bulk semiconductor substrate, various materials can be used as a supporting substrate. is there. That is, not only a normal silicon substrate but also a transparent quartz or glass substrate can be used as the support substrate. By forming a single crystal silicon film having excellent crystallinity on a transparent substrate, a high-performance semiconductor device can be formed in an electro-optical device that requires light transmission, such as a transmissive liquid crystal display device. Is possible.

In a MIS (Metal Insulator Semiconductor) type semiconductor device using a general bulk semiconductor substrate, a channel formation region can be held at a predetermined potential through the substrate. Therefore, the electrical characteristics of the semiconductor device are changed by a potential change in the channel portion. There is no change.
US Pat. No. 5,374,564 JP-A-4-346418

  However, in the MIS type semiconductor device using the SOI substrate, since the lower part of the channel formation region is completely separated by the base insulating film, the channel formation region cannot be held at a predetermined potential, and so-called substrate floating An effect occurs, and the channel formation region is in an electrically floating state. For this reason, when a high voltage is applied to the drain electrode, surplus carriers generated by impact ionization due to collision between carriers accelerated by a high electric field near the drain region and the crystal lattice accumulate in the lower portion of the channel. Then, the channel potential rises, and the source / channel / drain NPN structure (in the case of the N channel type) operates as an apparent bipolar semiconductor device (parasitic bipolar effect). Then, an abnormal current is generated, which causes problems such as deterioration of electrical characteristics such as deterioration of the breakdown voltage between the source and drain of the semiconductor device.

  The present invention has been made in view of such circumstances, and suppresses deterioration of the electrical characteristics of the semiconductor layer due to the substrate floating effect, and exhibits excellent electrical characteristics. It is an object to provide a substrate, a semiconductor device, an electro-optical device, and an electronic apparatus.

  The method for manufacturing a semiconductor substrate of the present invention includes a step of forming a non-single crystal semiconductor layer on one side of a single crystal semiconductor substrate, a step of providing an insulating layer on the upper surface of the non-single crystal semiconductor layer, and the insulating layer side. A step of implanting ions into the single crystal semiconductor substrate to form an ion implantation layer, a step of bonding a support substrate to the insulating layer side of the single crystal semiconductor substrate after the ion implantation, and the single crystal semiconductor And a step of separating a surface layer portion of the substrate opposite to the non-single-crystal semiconductor layer with the ion-implanted layer to form a single-crystal semiconductor layer on the support substrate.

  According to the method for manufacturing a semiconductor substrate of the present invention, a semiconductor substrate in which a non-single crystal semiconductor layer and a single crystal semiconductor layer are sequentially stacked on an insulating layer provided on one surface of a support substrate can be manufactured. The semiconductor layer having a stacked structure of the non-single crystal semiconductor layer and the single crystal semiconductor layer can be used as an active layer of a semiconductor device by providing a gate electrode over the semiconductor layer with a gate insulating film interposed therebetween, for example. At this time, even when surplus carriers are generated due to impact ionization in the vicinity of the drain region, the crystal defects included in the non-single-crystal semiconductor layer act as recombination centers of the surplus carriers and make it difficult to accumulate the surplus carriers in the lower portion of the channel. be able to. Accordingly, generation of a substrate floating effect such as a parasitic bipolar effect is suppressed, and a semiconductor substrate constituting a semiconductor device exhibiting excellent electrical characteristics can be manufactured. A crystal defect included in the non-single-crystal semiconductor layer may function as a recombination center of excess carriers. If there are too many crystal defects, the electrical characteristics of the semiconductor device may be adversely affected. As the non-single-crystal semiconductor layer, a polycrystalline semiconductor layer having a certain degree of crystallinity is preferable to an amorphous semiconductor layer.

  Alternatively, the method for manufacturing a semiconductor substrate of the present invention includes a step of performing ion implantation from one side of a single crystal semiconductor substrate to form an ion implantation layer, a step of providing an insulating layer on one side of the support substrate, A step of providing a non-single crystal semiconductor layer on an insulating layer, a step of bonding a surface of the support substrate on the non-single crystal semiconductor layer side, and a surface of the single crystal semiconductor substrate on the ion implantation side; And a step of separating the single crystal semiconductor substrate at a portion of the ion implantation layer after the aligning step.

  According to the method for manufacturing a semiconductor substrate of the present invention, a semiconductor substrate in which a non-single crystal semiconductor layer and a single crystal semiconductor layer are sequentially stacked on an insulating layer provided on one surface of a support substrate can be manufactured. The semiconductor layer having a stacked structure of the non-single crystal semiconductor layer and the single crystal semiconductor layer can be used as an active layer of a semiconductor device by providing a gate electrode over the semiconductor layer with a gate insulating film interposed therebetween, for example. At this time, even when surplus carriers are generated due to impact ionization in the vicinity of the drain region, the crystal defects included in the non-single-crystal semiconductor layer act as recombination centers of the surplus carriers and make it difficult to accumulate the surplus carriers in the lower portion of the channel. be able to. Accordingly, generation of a substrate floating effect such as a parasitic bipolar effect is suppressed, and a semiconductor substrate constituting a semiconductor device exhibiting excellent electrical characteristics can be manufactured.

  The semiconductor substrate of the present invention is characterized in that a semiconductor layer having a stacked structure of a non-single crystal semiconductor layer and a single crystal semiconductor layer is provided on an insulating layer provided on one side of a support substrate. .

  According to the semiconductor substrate of the present invention, on the insulating layer provided on one surface of the support substrate, since the semiconductor layer having a stacked structure of the non-single crystal semiconductor layer and the single crystal semiconductor layer is provided, for example, By providing a gate electrode over the semiconductor layer with a gate insulating film interposed therebetween, it can be used as an active layer of a semiconductor device. At this time, even if surplus carriers are generated due to impact ionization near the drain region, the crystal defects contained in the non-single-crystal semiconductor layer function as recombination centers of the surplus carriers, thereby accumulating the surplus carriers in the lower part of the channel. It can be made difficult to do. Therefore, generation of a substrate floating effect such as a parasitic bipolar effect is suppressed, and a semiconductor substrate capable of constituting a semiconductor device exhibiting excellent electrical characteristics is obtained.

  A semiconductor device of the present invention includes a semiconductor layer in which a non-single crystal semiconductor layer and a single crystal semiconductor layer are stacked over an insulating layer provided on one side of a support substrate, and the semiconductor layer serves as an active layer. It is used.

  According to the semiconductor device of the present invention, for example, a gate insulating film can be provided on a semiconductor layer to constitute a MIS type semiconductor device. Therefore, when surplus carriers are generated due to the impact ionization phenomenon, crystal defects included in the non-single-crystal semiconductor layer function as recombination centers of surplus carriers, and surplus carriers are difficult to accumulate in the lower portion of the channel. Therefore, the occurrence of a substrate floating effect such as a parasitic bipolar effect is suppressed, and the semiconductor device exhibits excellent electrical characteristics.

  An electro-optical device according to the present invention includes the above-described semiconductor device.

  According to the electro-optical device of the present invention, as described above, since the generation of the substrate floating effect such as the parasitic bipolar effect is suppressed and the semiconductor device having excellent electrical characteristics is provided, the electro-optical device itself is also electrically connected. High characteristic and high reliability. Further, when the semiconductor device is miniaturized, the above-described substrate floating effect becomes remarkable. Therefore, if the present invention is adopted, the substrate floating effect can be suppressed, and the semiconductor device can be favorably downsized. Therefore, for example, by using the semiconductor device as a switching element in each pixel region of the electro-optical device, the pixel can be miniaturized and the aperture ratio can be increased.

  According to another aspect of the present invention, there is provided an electronic apparatus including the above electro-optical device.

  According to the electronic apparatus of the present invention, as described above, since the electro-optical device having high electrical characteristics and reliability and having a fine pixel structure is provided, the electronic apparatus itself has high performance and high quality. It will be a thing.

(First embodiment)
Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In addition, embodiment described below shows the one part aspect of this invention, and does not limit this invention. Moreover, in each drawing used for the following description, the scale is appropriately changed for each layer and each member so that each layer and each member has a size that can be recognized on the drawing.

1 to 2 are process cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to the first embodiment of the present invention.
In this embodiment, first, as shown in FIG. 1A, a single crystal silicon substrate (single crystal semiconductor substrate) 200 having a thickness of, for example, 750 μm is prepared, and one side surface is formed by a low pressure chemical vapor deposition method (LPCVD method). Then, an amorphous silicon layer (non-single crystal semiconductor layer) 210 is formed. The film thickness of the amorphous silicon layer 210 is preferably set to about 30 to 100 nm, and a more preferable range is 40 to 60 nm. In this embodiment, the film thickness of the amorphous silicon layer 210 is 50 nm. After the amorphous silicon layer is formed, the amorphous silicon layer may be converted into a polycrystalline silicon layer by performing heat treatment in a nitrogen atmosphere at 600 ° C. or higher. Further, instead of forming the amorphous silicon layer, a polycrystalline silicon layer may be directly formed.

  Next, as shown in FIG. 1B, a silicon oxide film (insulating layer) 211 is formed on the upper surface of the amorphous silicon layer 210. As a method of forming the silicon oxide film 211, for example, the amorphous silicon layer 210 is formed by thermal oxidation in an oxygen atmosphere at about 1000 ° C. When thermal oxidation is performed at a high temperature of about 1000 ° C., the amorphous silicon layer 210 is polycrystallized and crystallinity is improved. Note that the silicon oxide film 211 may be formed by LPCVD or plasma enhanced chemical vapor deposition (PECVD) instead of the thermal oxidation.

Next, as shown in FIG. 1C, hydrogen ions (H ⁺ ) are implanted into the single crystal silicon substrate 200 from the silicon oxide film 211 side to form a hydrogen ion implanted layer (ion implanted layer) 205.
As a result, a hydrogen ion implantation layer 205 having a penetration depth distribution as shown by a broken line in FIG. 1C is formed inside the single crystal silicon substrate 200. The hydrogen ion implantation conditions at this time include, for example, an acceleration energy of 60 to 150 keV (in this embodiment, 100 keV) and a dose amount of 5 × 10 ¹⁶ atoms / cm ² to 15 × 10 ¹⁶ atoms / cm ² (this embodiment). Then, 10 × 10 ¹⁶ atoms / cm ² ). Note that a semiconductor substrate having single-crystal silicon layers with different thicknesses can be obtained by changing the acceleration voltage of hydrogen ions to change the implantation depth of hydrogen ions.

  Next, a support substrate 500 to be bonded to the silicon oxide film 211 of the single crystal silicon substrate 200 is prepared. A semiconductor substrate obtained by employing a substrate made of a light transmissive material such as glass or quartz as the support substrate 500 is a transmissive electro-optical device as described later, such as a transmissive liquid crystal device (light valve). It can be applied to. In this embodiment, a quartz substrate is used as the support substrate 500. Since the quartz substrate has higher heat resistance than a general glass substrate, a high temperature process of about 1000 ° C. can be employed by using the quartz substrate. Further, since the quartz substrate has a higher light transmittance than a general glass substrate, a bright transmissive liquid crystal device can be manufactured by using the quartz substrate.

Then, as shown in FIG. 2A, a support substrate 500 is bonded to the surface of the single crystal silicon substrate 200 on the silicon oxide film 211 side, and the single crystal silicon substrate 200 is placed on the support substrate 500 at room temperature to about 200 ° C. to paste together. In the present embodiment, since the quartz substrate mainly composed of SiO ₂ is used as the support substrate 500, the above bonding can be performed satisfactorily. When a material made of a material not mainly composed of SiO ₂ is used as a support substrate, an oxide film such as a silicon oxide film or NSG (non-doped silicate glass) is formed on the bonding surface of the support substrate by sputtering or CVD. It is desirable to form the substrate and polish it by a CMP method or the like. This oxide film is a film for ensuring the adhesion between the single crystal silicon substrate 200 and the support substrate 500, and the single crystal silicon substrate 200 and the support substrate 500 are connected via the insulating layer 213 by the action of the OH group on the substrate surface. Can be pasted together.

  Next, as illustrated in FIG. 2B, the single crystal silicon substrate 200 after bonding is thinned, and a single crystal silicon layer (single crystal semiconductor layer) 220 is formed. The film thickness of the single crystal silicon layer 220 is preferably set to 50 nm or more, and is set to 200 nm in this embodiment.

  This thinning is performed by subjecting the bonded single crystal silicon substrate 200 and the support substrate 500 to heat treatment at 350 ° C. to 700 ° C. in an inert gas atmosphere such as nitrogen or argon, thereby positioning the hydrogen ion implanted layer 205. The single crystal silicon substrate 200 is peeled off. Thus, the semiconductor substrate 600 including the semiconductor layer 250 having a stacked structure of the non-single-crystal silicon layer 210 and the single-crystal silicon layer 220 is formed over the support substrate 500.

  This peeling phenomenon occurs because a microcavity is generated by ions implanted in a defect layer region formed in the hydrogen ion implanted layer 205, and bonds between semiconductor crystals are broken. It becomes more prominent at the peak position of the concentration. Therefore, the position peeled off by the heat treatment substantially coincides with the peak position of the ion concentration, that is, the hydrogen ion implanted layer 205. Note that the single crystal silicon substrate 200 after separation can be used for manufacturing another semiconductor substrate as it is.

  Note that since the surface of the substrate after separation has unevenness of about several nm on the surface of the single crystal silicon layer 220, it is necessary to planarize the surface. For this reason, in this configuration example, a touch polish that polishes the substrate surface to a small amount (less than 10 nm of polishing amount) using the CMP method is used. As another planarization method, a hydrogen annealing method in which heat treatment is performed in a hydrogen atmosphere can also be used. According to the semiconductor substrate 600 manufactured as described above, a semiconductor layer having a stacked structure of the non-single-crystal silicon layer 210 and the single-crystal silicon layer 220 on the silicon oxide film 211 provided on one side of the support substrate 500. 250 is formed. Therefore, although details will be described later, for example, when the semiconductor layer 250 is used as an active layer of a semiconductor device, a crystal defect included in the non-single-crystal silicon layer 210 serves as a recombination center of surplus carriers, and a substrate floating effect is generated. Can be suppressed.

(Second Embodiment)
Next, a second embodiment of the semiconductor substrate of the present invention will be described with reference to FIG.
The manufacturing method of the semiconductor substrate in this embodiment is different from that of the first embodiment in that an insulating layer and a non-single crystal semiconductor layer are formed on the support substrate side, and only an ion implantation layer is formed on the single crystal semiconductor substrate side. ing. 3 and 4 are process cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to the second embodiment. Note that the same members as those in the first embodiment are described with the same reference numerals, and the peeling of the single crystal silicon substrate 200 in the bonding process and thinning is the same as that in the first embodiment, and thus the detailed description thereof will be omitted. The explanation is omitted.

First, in this embodiment, as shown in FIG. 3A, a single crystal silicon substrate 200 having a thickness of, for example, 750 μm is prepared, and hydrogen ions (H ⁺ ) are prepared from one surface side under the same conditions as in the above embodiment. Inject. As a result, a hydrogen ion implantation layer 205 having a penetration depth distribution as shown by a broken line in FIG. 3A is formed inside the single crystal silicon substrate 200.

  Next, as shown in FIG. 3B, a support substrate 500 made of a quartz substrate is prepared, and a silicon oxide film 211 as an insulating layer is provided on one side of the support substrate 500. As a method of forming this silicon oxide film 211, the LPCVD method can be adopted, and the silicon oxide film 211 is formed to a thickness of about several hundreds of nanometers.

  Next, an LPCVD method is used to form an amorphous silicon layer 210 with a thickness of about 50 nm on the silicon oxide film 211 as shown in FIG. Similar to the first embodiment, a polycrystalline silicon layer may be formed instead of the amorphous silicon layer. Next, as shown in FIG. 4A, the non-single crystal silicon layer 210 side surface of the support substrate 500 and the ion implantation side surface of the single crystal silicon substrate 200 are bonded together. For the bonding step, a method of directly bonding two substrates by heat treatment can be employed.

  Subsequently, as shown in FIG. 4B, the single crystal silicon substrate 200 after bonding is subjected to heat treatment in the same manner as in the above embodiment, so that the single crystal silicon substrate 200 is peeled off at the position of the hydrogen ion implantation layer 205. The single crystal silicon layer 220 is formed. As a result, the semiconductor substrate 600 including the semiconductor layer 250 is formed on the support substrate 500. By using the semiconductor substrate 600 manufactured as described above, a semiconductor device exhibiting excellent electrical characteristics can be provided by preventing the substrate floating effect as in the first embodiment.

(Semiconductor device)
FIG. 5 is a cross-sectional view showing a schematic configuration of an embodiment of a semiconductor device of the present invention. The semiconductor device according to this embodiment is mainly composed of the semiconductor substrate 600 obtained by the first and second embodiments, and the semiconductor layer 250 is used as an active layer.

  As a method for forming the semiconductor device 700 shown in FIG. 5, first, the semiconductor substrate 600 is prepared, and the semiconductor layer 250 including the non-single-crystal silicon layer 210 and the single-crystal silicon layer 220 is formed by photolithography. Pattern. Then, the gate insulating film 300 made of a silicon oxide film is formed to a thickness of about 20 nm by thermal oxidation in an oxygen atmosphere of about 900 ° C. to 1000 ° C., for example, covering the surface of the semiconductor layer 250. At this time, when the non-single-crystal silicon film 210 is exposed to a high temperature atmosphere, the non-single-crystal silicon film 210 becomes a polycrystalline silicon film 210a, and crystallinity can be improved. Then, a gate electrode 310 is formed on the gate insulating film 300. The gate length is preferably 2 μm or less.

  Impurity ions serving as donors or acceptors are implanted into the semiconductor layer 250 using a photoresist or the gate electrode 310 as a mask, thereby forming a source region 250a and a drain region 250b. A channel region 250c is formed. If necessary, an LDD (Lightly Doped Drain) structure as described later may be adopted. Then, an interlayer insulating film 260 made of a silicon oxide film is formed so as to cover the semiconductor layer 250 and the gate electrode 310. Further, contact holes H1 and H2 that penetrate the interlayer insulating film 260 and the gate insulating film 300 are formed, and the source electrode 270 and the drain electrode that are connected to the source region 250a and the drain region 250b through the contact holes H1 and H2. 280 is formed. In this way, the semiconductor device 700 according to the present embodiment can be obtained.

  Here, in order to explain the special effects of the semiconductor device of the present invention, a conventional semiconductor device will be described as a comparison. In the conventional semiconductor device, since the active layer in the semiconductor layer is formed only of the single crystal semiconductor layer (single crystal silicon layer), the impact ionization phenomenon caused by the collision between the carrier accelerated by the electric field near the drain region and the crystal lattice. The excess carriers generated by the above are easily accumulated in the lower part of the channel. As a result, the channel potential rises and the electrical characteristics of the semiconductor device deteriorate due to the so-called parasitic bipolar effect in which the source / channel / drain NPN structure operates as an apparent bipolar semiconductor device. There was a problem such as.

  On the other hand, in the semiconductor device 700 according to the present embodiment, the upper side of the semiconductor layer 250 is constituted by the single crystal silicon film 220 and the lower side is constituted by the polycrystalline silicon film 210a. According to this configuration, when surplus carriers are generated due to the impact ionization phenomenon, crystal defects contained in the polycrystalline silicon film (non-single crystal semiconductor layer) 210a provided on the lower layer side on the semiconductor layer 250 side are regenerated as surplus carriers. It acts as a bonding center and makes it difficult for excess carriers to accumulate at the bottom of the channel. Therefore, the occurrence of a substrate floating effect such as a parasitic bipolar effect is suppressed, and excellent electrical characteristics are exhibited.

(Electro-optical device)
Next, as an embodiment of the electro-optical device of the present invention, an example of a liquid crystal light valve (liquid crystal device) used as light modulation means of a projection display device will be described. The liquid crystal light valve of the present embodiment is an active matrix type liquid crystal panel, in which a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate. The switching element (TFT element) provided on the TFT array substrate is configured by using the semiconductor device of the present invention as an active layer.

  6 is a schematic configuration diagram of a liquid crystal light valve as an example of the electro-optical device of the present invention, FIG. 7 is a cross-sectional view taken along the line HH ′ of FIG. 6, and FIG. 9 is an equivalent circuit diagram of a plurality of pixels, FIG. 9 is a plan view of a plurality of pixel groups, and FIG. 10 is a cross-sectional view taken along the line AA ′ of FIG.

(Overall configuration of liquid crystal light valve)
As shown in FIGS. 6 and 7, the configuration of the liquid crystal light valve 1 of the present embodiment is such that a sealing material 52 is provided on the TFT array substrate 10 along the edge of the counter substrate 20. In parallel with this, a light shielding film 53 (peripheral parting) is provided as a frame. A data line driving circuit 201 and an external circuit connection terminal 202 are provided along one side of the TFT array substrate 10 in a region outside the sealing material 52, and the scanning line driving circuit 104 is provided on two sides adjacent to the one side. It is provided along.

  Furthermore, a plurality of wirings 105 are provided on the remaining one side of the TFT array substrate 10 for connecting the scanning line driving circuits 104 provided on both sides of the image display area. Further, at least one corner portion of the counter substrate 20 is provided with a vertical conductive material 106 for electrical conduction between the TFT array substrate 10 and the counter substrate 20. As shown in FIG. 7, the counter substrate 20 having substantially the same outline as the seal material 52 shown in FIG. 6 is fixed to the TFT array substrate 10 by the seal material 52, and the TFT array substrate 10, the counter substrate 20, A liquid crystal layer 50 is sealed between the two. Further, the opening provided in the sealing material 52 shown in FIG. 6 is a liquid crystal injection port 52 a and is sealed by the sealing material 25.

(Configuration of TFT array substrate)
In FIG. 8, each of a plurality of pixels formed in a matrix that forms the image display area of the liquid crystal light valve 1 in the present embodiment has a pixel electrode 9 and a TFT 30 for switching control of the pixel electrode 9. The data line 6 a formed and supplied with an image signal is electrically connected to the source region of the TFT 30. The TFT 30 is configured by using the semiconductor device according to the present invention as an active layer. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group to a plurality of adjacent data lines 6a. Good.

  The scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signals G1, G2,..., Gm are applied to the scanning line 3a in a pulse-sequential manner in this order at a predetermined timing. Has been. The pixel electrode 9 is electrically connected to the drain of the TFT 30, and the image signal S1, S2,... Sn supplied from the data line 6a is obtained by turning on the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9 are held for a certain period with a common electrode (described later) formed on the counter substrate 20. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is provided in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode.

  As shown in FIG. 9, a plurality of rectangular pixel electrodes 9 (outlined by dotted line portions 9 </ b> A) are provided in a matrix on the TFT array substrate 10, and the vertical and horizontal boundaries of the pixel electrodes 9 are provided. A data line 6a and a scanning line 3a are provided along each line. In addition, the scanning line 3a is arranged so as to face the channel region 1a ′ shown by the oblique line region rising to the right in FIG. 9 in the semiconductor layer 1a constituting the TFT 30, and the scanning line 3a is directly used as the gate of the TFT 30. Functions as an electrode. The detailed structure of the TFT 30 will be described later.

  As shown in FIGS. 9 and 10, in this embodiment, the storage capacitor 70 is a relay conductive film as a pixel potential side capacitor electrode electrically connected to the high concentration drain region 1 e of the TFT 30 and the pixel electrode 9. 71 a and a part of the capacitor line 300 as the fixed potential side capacitor electrode are formed so as to face each other with the dielectric film 75 interposed therebetween.

  The storage capacitor 70 also has a function as a light shielding film. The relay conductive film 71 a is made of a conductive polysilicon film or the like, has a higher light absorption than the second film 73 that constitutes the capacitor line 300, and is disposed between the second film 73 and the TFT 30. It functions as an absorption layer. Further, the relay conductive film 71 a functions to relay conduction between the pixel electrode 9 and the TFT 30.

  The capacitor line 300 is formed of a multilayer film in which the first film 72 and the second film 73 are laminated, and itself functions as a light shielding film. The first film 72 has a function as a light absorption layer disposed between the second film 73 and the TFT 30. For example, a conductive polysilicon film or an amorphous silicon film having a thickness of about 50 nm to 150 nm, It is composed of a single crystal silicon film or the like. The second film 73 has a function as a light shielding layer that shields the TFT 30 from incident light on the upper side of the TFT 30. For example, a high melting point metal such as Ti, Cr, W, Ta, Mo, Pb having a thickness of about 150 nm is used. These are made of a simple metal, an alloy, a metal silicide, a polysilicide, a laminate of these, or a metal that is not a refractory metal such as Al. Note that the second film 73 does not need to have conductivity, but if formed of a material having conductivity, the resistance of the capacitor line 300 can be further reduced.

  In addition, a dielectric film 75 is disposed between the relay conductive film 71a and the capacitor line 300 as shown in FIG. The dielectric film 75 is made of, for example, a relatively thin silicon oxide film having a thickness of about 5 to 200 nm, a silicon nitride film, a nitrided oxide film, or a laminated film thereof. From the viewpoint of increasing the storage capacitor 70, the dielectric film 75 is preferably as thin as the film reliability is sufficiently obtained.

  Further, the capacitor line 300 includes a main line portion extending in a stripe shape along the scanning line 3a in plan view, and a portion overlapping the TFT 30 from the main line portion protrudes up and down in FIG. In FIG. 9, the TFTs 30 on the TFT array substrate 10 are arranged in regions where the data lines 6a extending in the vertical direction and the capacitor lines 300 extending in the horizontal direction intersect. That is, the TFT 30 is double-covered by the data line 6a and the capacitor line 300 when viewed from the counter substrate 20 side. The data lines 6a and the capacitor lines 300 that intersect each other form a lattice-shaped light-shielding layer as viewed in plan, and define an opening area of each pixel.

  Further, below the TFT 30 on the TFT array substrate 10, a lower light-shielding film 11 a made of the same material as the second film 73 described above is provided in a lattice shape. This prevents light (return light) from the lower side of the TFT array substrate 10 from entering the TFT 30. The lower light-shielding film 11a is formed to be narrower than the width of the capacitor line 300 and the data line 6a, and is slightly smaller than the capacitor line 300 and the data line 6a. The channel region 1a of the TFT 30 is located in the intersecting region of the lower light shielding film 11a including the junction between the low concentration source region 1b and the low concentration drain region 1c. A light absorption layer may be provided on the inner surface of the lower light shielding film 11a.

  The capacitor line 300 extends from the image display area where the pixel electrode 9 is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. Further, the lower light-shielding film 11a also extends from the image display region to the periphery thereof and is connected to a constant potential source, similarly to the capacitor line 300, in order to avoid the potential fluctuation from adversely affecting the TFT 30. Good.

  As shown in FIG. 9 and FIG. 10, the data line 6a is connected to a relay conductive film 71b for relay connection through a contact hole 81. The relay conductive film 71b is made of, for example, a polysilicon film through a contact hole 82. The semiconductor layer 1a is electrically connected to the high concentration source region 1d. Further, the pixel electrode 9 is electrically connected to the high-concentration drain region 1e in the semiconductor layer 1a through the contact hole 83 and the contact hole 8 by relaying the relay conductive film 71a. Note that the relay conductive film 71b is formed simultaneously from the same film as the relay conductive film 71a.

  On the scanning line 3a, a first interlayer insulating film 41 is formed in which a contact hole 82 leading to the high concentration source region 1d and a contact hole 83 leading to the high concentration drain region 1e are opened. Relay conductive films 71a and 71b and a capacitor line 300 are formed on the first interlayer insulating film 41, and a contact hole 81 and a contact hole 8 respectively leading to the relay conductive films 71a and 71b are opened on these. A holed second interlayer insulating film 42 is formed. Further, the data line 6a is formed on the second interlayer insulating film 42, and the third interlayer insulating film 43 in which the contact hole 8 leading to the relay conductive film 71a is formed is formed thereon. Yes. The pixel electrode 9 is provided on the upper surface of the third interlayer insulating film 43 thus configured.

  As shown in FIGS. 9 and 10, the liquid crystal light valve 1 according to the present embodiment includes a TFT array substrate 10 having a transparent quartz substrate as a substrate body 10A, and a transparent counter substrate 20 disposed to face the TFT array substrate. I have. The TFT array substrate 10 is provided with a pixel electrode 9 made of a transparent conductive film such as indium tin oxide (hereinafter abbreviated as ITO). A predetermined alignment process such as a rubbing process is provided above the pixel electrode 9. An alignment film 16 is provided. The alignment film 16 is made of an organic film such as a polyimide film, for example. A polarizer 17 is provided on the side of the TFT array substrate 10 opposite to the liquid crystal layer 50 of the substrate body 10A.

  On the other hand, the counter substrate 20 is provided with a common electrode 21 over the entire surface of the substrate body 20A, and an alignment film 22 that has been subjected to a predetermined alignment process such as a rubbing process is provided below the common electrode 21. Yes. Similarly to the pixel electrode 9, the common electrode 21 is also made of a transparent conductive film such as an ITO film. The alignment film 22 is made of an organic film such as a polyimide film. A polarizer 24 is formed on the opposite side of the substrate body 20 </ b> A of the counter substrate 20 from the liquid crystal layer 50.

  Between the TFT array substrate 10 and the counter substrate 20, which are configured in this manner and arranged so that the pixel electrode 9 and the common electrode 21 face each other, liquid crystal is sealed in a space surrounded by a sealing material 52, A liquid crystal layer 50 is formed. The liquid crystal layer 50 assumes a predetermined alignment state by the alignment films 16 and 22 in a state where an electric field from the pixel electrode 9 is not applied. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one kind or several kinds of nematic liquid crystals are mixed. Further, a base insulating film 12 is provided under the TFT 30. In addition to the function of insulating the TFT 30 from the lower light-shielding film 11a, the base insulating film 12 is formed on the entire surface of the TFT array substrate 10 so that the surface of the TFT array substrate 10 becomes rough during polishing or remains after cleaning. For example, the TFT 30 has a function of preventing a change in characteristics of the TFT 30.

(Configuration of TFT)
As shown in FIG. 10, in this embodiment, the TFT 30 is configured by using the semiconductor device of the present invention as an active layer. That is, the semiconductor layer 1a is configured by a stacked structure of a non-single crystal silicon layer 210 and a single crystal silicon layer 220 (see FIGS. 2 and 4). The TFT 30 has an LDD structure, and insulates the scanning line 3a, the channel region 1a ′ of the semiconductor layer 1a where a channel is formed by the electric field from the scanning line 3a, and the scanning line 3a from the semiconductor layer 1a. An insulating thin film 2 including a gate insulating film, a low concentration source region 1b and a low concentration drain region 1c of the semiconductor layer 1a, a high concentration source region 1d and a high concentration drain region 1e of the semiconductor layer 1a are provided.

  FIG. 11 is a diagram showing a manufacturing process of the TFT array substrate 10. First, as shown in FIG. 11A, a substrate body 10A made of a transparent quartz substrate is prepared, and the light shielding layer 11 is formed. Next, as shown in FIG. 11B, a photoresist pattern 113 is formed on the light shielding layer 11. Next, as shown in FIG. 11C, the light shielding layer 11 is etched using the photoresist pattern 113 as a mask, and the light shielding layer 11 other than the transistor formation region is removed by dry etching. The lower light shielding film 11a is formed by peeling 113. Next, as shown in FIG. 11D, the base insulating film 12 is deposited in order to ensure insulation between the lower light-shielding film 11a and the semiconductor layer 250 formed thereon. A silicon oxide film was used for the base insulating film 12. This silicon oxide film can be formed, for example, by sputtering or plasma CVD using TEOS (tetraethylorthosilicate).

  As will be described later, the base insulating film 12 preferably has a thickness that can ensure sufficient insulation from the semiconductor layer 250 even if the coating step of the lower light-shielding film 11a is planarized by polishing. Specifically, the base insulating film 12 is preferably deposited to be about 500 to 1000 nm thicker than the film thickness of the lower light shielding film 11a. In this configuration example, a silicon oxide film was deposited by 1000 nm by TEOS plasma CVD with respect to the film thickness of 400 nm of the lower light-shielding film 11a. Since the substrate with the light-shielding layer thus obtained has irregularities in accordance with the presence or absence of the lower light-shielding film 11a, bonding to the single crystal silicon substrate in this state causes voids (voids) ) Is formed and bonding strength becomes non-uniform when bonded.

  For this reason, as shown in FIG. 11E, the surface of the substrate on which the lower light-shielding film 11a is formed is globally polished and flattened. A CMP (chemical mechanical polishing) method was used as a planarization method by polishing. By performing the CMP process, the step at the end of the light shielding layer pattern can be reduced, and even when the single crystal silicon substrate is bonded, the bonding strength can be obtained uniformly over the entire surface of the substrate. Thereafter, the TFT array substrate 10 is obtained by forming the semiconductor layer 1a on the substrate body 10A provided with the lower light-shielding film 11a by the semiconductor substrate manufacturing method according to the present invention. Description of the following steps for forming the semiconductor layer is omitted.

(Electronics)
Next, a projection type liquid crystal display device which is an example of an electronic apparatus including the electro-optical device will be described with reference to FIG.
In the projection type liquid crystal display device (electronic device) 1100 shown in FIG. 12, the liquid crystal module including the liquid crystal light valve 1 described above is employed as the RGB light valves 100R, 100G, and 100B.
In this liquid crystal projector 1100, when light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light corresponding to the three primary colors R, G, and B is emitted by three mirrors 1106 and two dichroic mirrors 1108. The light components are separated into components R, G, and B (light separating means) and led to the corresponding light valves 100R, 100G, and 100B (liquid crystal light valve 1). At this time, since the optical component B has a long optical path, the light component B is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss. Then, the light components R, G, and B corresponding to the three primary colors respectively modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 1112 (light combining unit) from three directions and are combined again, and then the projection lens. A color image is projected on a screen 1120 or the like via 1114.

  According to the above configuration, since the RGB light valves 100R, 100G, and 100B including the liquid crystal light valve 1 formed from the semiconductor substrate 600 of the present invention are provided, the projection type liquid crystal display device can display more images to be displayed. High quality can be achieved.

  The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, the present invention uses various electro-optical elements using a reflective liquid crystal display device, electroluminescence (EL), a digital micromirror device (DMD, registered trademark), or fluorescence by plasma emission or electron emission. Needless to say, the present invention can also be applied to an electro-optical device and an electronic apparatus including the electro-optical device.

It is process sectional drawing which shows the manufacturing method of the semiconductor substrate which concerns on 1st Embodiment. FIG. 2 is a process cross-sectional view illustrating the manufacturing method of the semiconductor substrate following FIG. 1. It is process sectional drawing which shows the manufacturing method of the semiconductor substrate which concerns on 2nd Embodiment. FIG. 4 is a process cross-sectional view illustrating the manufacturing method of the semiconductor substrate following FIG. 3. It is sectional drawing which shows schematic structure of one Embodiment of a semiconductor device. It is a schematic block diagram of the liquid crystal light valve which shows one Example of an electro-optical apparatus. It is sectional drawing which follows the HH 'line of FIG. It is an equivalent circuit diagram of a plurality of pixels constituting a liquid crystal light valve. It is a top view of a plurality of pixel groups. It is sectional drawing of the liquid crystal light valve by the AA 'line arrow of FIG. It is a figure which shows the manufacturing process of a TFT array substrate. It is a figure which shows the structure of the projection type liquid crystal display device which is an example of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal light valve (electro-optical apparatus), 200 ... Single crystal silicon substrate (single crystal semiconductor substrate), 205 ... Hydrogen ion implantation layer (ion implantation layer), 210 ... Amorphous silicon layer (non-single crystal semiconductor layer) 211 ... Silicon oxide film (insulating layer) 220 ... Single crystal silicon layer (single crystal semiconductor layer) 250 ... Semiconductor layer 500 ... Support substrate 600 ... Semiconductor substrate 700 ... Semiconductor device 1100 ... Projection type liquid crystal display Equipment (electronic equipment)

Claims (6)

Forming a non-single-crystal semiconductor layer on one side of the single-crystal semiconductor substrate;
Providing an insulating layer on the top surface of the non-single-crystal semiconductor layer;
Performing ion implantation into the single crystal semiconductor substrate from the insulating layer side to form an ion implantation layer;
A step of bonding a support substrate to the insulating layer side of the single crystal semiconductor substrate after the ion implantation;
Separating the surface layer portion of the single crystal semiconductor substrate opposite to the non-single crystal semiconductor layer with the ion implantation layer, and forming a single crystal semiconductor layer on the support substrate. A method of manufacturing a semiconductor substrate. Performing ion implantation from one side of the single crystal semiconductor substrate to form an ion implantation layer;
Providing an insulating layer on one side of the support substrate;
Providing a non-single-crystal semiconductor layer on the insulating layer;
Bonding the non-single crystal semiconductor layer side surface of the support substrate and the ion implantation side surface of the single crystal semiconductor substrate; and
And a step of separating the single crystal semiconductor substrate at the ion implantation layer after the bonding step.   A semiconductor substrate, wherein a semiconductor layer having a stacked structure of a non-single crystal semiconductor layer and a single crystal semiconductor layer is provided over an insulating layer provided on one side of the support substrate.   A semiconductor layer in which a non-single crystal semiconductor layer and a single crystal semiconductor layer are stacked is provided over an insulating layer provided on one side of a support substrate, and the semiconductor layer is used as an active layer Semiconductor device.   An electro-optical device comprising the semiconductor device according to claim 4.   An electronic apparatus comprising the electro-optical device according to claim 5.

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