JP4677727B2 - Semiconductor device, electro-optical device and electronic apparatus - Google Patents

Description

  The present invention relates to a semiconductor device, an electro-optical device, and an electronic apparatus.

  2. Description of the Related Art Conventionally, a technique is known in which an active matrix liquid crystal device driven by a thin film transistor (hereinafter abbreviated as TFT) is used as, for example, a light valve of a projection display device. In order to improve the quality of the display image of the projection display device, the following technique is employed.

As described above, when a liquid crystal device is used as a light valve, generally, projection light is incident from the side of the counter substrate that is disposed opposite to the liquid crystal device substrate with the liquid crystal layer interposed therebetween. Here, when the projection light is incident on a channel formation region composed of a silicon film of the TFT (for example, an amorphous silicon film or a polysilicon film), a photocurrent due to the photoelectric conversion effect is generated in this region, and the TFT The transistor characteristics deteriorate.
For this reason, a light shielding film called a black matrix or a black mask is generally formed on a counter substrate from a metal material such as chromium (Cr) or resin black at a position facing each TFT (for example, (See Patent Document 1).
JP 2003-186049 A

In addition to the technique of forming the silicon film shown in Patent Document 1 with an amorphous silicon film or a polysilicon film, there is a technique of using single crystal silicon as a silicon film from the viewpoint of speeding up, low power consumption, high integration, and the like. Are known. Conventionally, SOI (Silicon On Insulator) technology has been used as a technology for forming such single crystal silicon on an insulating substrate such as glass or quartz.
In order to further increase the speed, a technique is also known in which a TFT gate electrode and a light-shielding film are electrically connected and a light-shielding film having a small electrical resistance is used for gate signal input.

  Here, the SOI technology includes a step of etching the single crystal silicon so that the bonded single crystal silicon has a predetermined thickness. For example, when a 200 nm-thick single crystal silicon film is formed to a 50 nm film thickness, first, the 200 nm single crystal silicon film is oxidized into a 50 nm single crystal silicon film and a 300 nm silicon oxide film. Thereafter, the 300 nm silicon oxide is removed by etching, leaving 50 nm single crystal silicon.

  In this etching process, for example, if there is a defect such as a hole in the single crystal silicon layer, the insulating substrate is also etched through the defect when the silicon oxide is etched, and the light shielding film is exposed. There is a risk of causing problems such as contamination by components (for example, Cr) forming the film. In order to prevent the occurrence of this problem, the thickness from the silicon layer to the light-shielding film is thicker than the thickness of the silicon oxide (for example, 300 nm), and preferably twice the thickness (for example, 600 nm). It was.

  However, as described above, when the thickness from the silicon layer to the light shielding film is increased (the distance is increased), the light shielding region of the light shielding film with respect to the channel formation region becomes narrow, and the projection light easily enters the channel formation region. As a result, in the channel formation region, a photocurrent is likely to be generated, the transistor characteristics of the TFT are degraded, and the quality of the displayed image may be degraded.

  In addition, when the thickness from the silicon layer to the light shielding film is increased, the aspect ratio of the electrical connection portion between the gate electrode and the light shielding film is increased (the shape of the electrical connection portion is elongated). The electrical resistance between the film increases. As a result, the delay of the gate signal cannot be prevented, and there is a possibility that the display quality such as a decrease in contrast due to insufficient writing to the TFT and a luminance gradient due to the application of a DC voltage component to the liquid crystal material may occur.

  SUMMARY An advantage of some aspects of the invention is that it provides a semiconductor device, an electro-optical device, and an electronic apparatus that can prevent deterioration in display image quality.

  In order to achieve the above object, a semiconductor device of the present invention includes a supporting substrate and a semiconductor substrate having a semiconductor layer which are bonded to each other to form a thin film transistor using the semiconductor layer as an active layer. In addition, a light-shielding layer that has conductivity and shields light incident on the thin film transistor from the support substrate side is formed, and a relay layer that electrically connects the gate electrode of the thin film transistor and the light-shielding layer is formed. It is characterized by.

In other words, since the semiconductor device of the present invention electrically connects the gate electrode and the light shielding layer using the relay layer, the light shielding layer can be used for gate signal input, and delay of the gate signal is prevented. Can do.
Furthermore, by using the relay layer, the electrical connection between the gate electrode and the light shielding layer is divided into an electrical connection between the gate electrode and the relay layer, and an electrical connection between the relay layer and the light shielding layer. The aspect ratio of the electrical connection is reduced (the electrical connection is thicker and shorter). Then, it is possible to reduce the electrical resistance of the electrical connection portion and to reduce variation in the electrical resistance. As a result, the delay of the gate signal can be prevented and the on-current of the thin film transistor can be increased and stabilized (less variation in on-current).
For example, if this semiconductor device is used in a liquid crystal display device, it is possible to prevent a decrease in contrast due to insufficient writing to the thin film transistor, a luminance gradient due to application of a DC voltage component to the liquid crystal material, and the like by preventing delay of the gate signal, Display quality degradation can be prevented. In addition, by increasing and stabilizing the on-state current, it is possible to improve brightness unevenness of the display image and to increase the number of gradations.

More specifically, in order to realize the above configuration, it is desirable that the relay layer be formed between the light shielding film and the semiconductor layer.
According to this configuration, the aspect ratio of the electrical connection portion between the gate electrode and the relay layer and the electrical connection portion between the relay layer and the light shielding layer can be reliably reduced. As a result, the electrical resistance of the electrical connection portion can be reduced more reliably and the delay of the gate signal can be prevented.

In order to realize the above configuration, more specifically, it is desirable that the relay layer is formed of a material that blocks light and is formed in a region that blocks light incident on the thin film transistor from the support substrate side.
According to this configuration, since the relay layer is formed in a layer closer to the semiconductor layer than the light shielding layer,
The relay layer can block light incident on the thin film transistor from a wider angle than the light blocking layer. Therefore, it is easy to prevent generation of photocurrent in the channel formation region of the thin film transistor, and deterioration of transistor characteristics of the thin film transistor can be prevented.
For example, when this semiconductor device is used in a liquid crystal display device, deterioration of transistor characteristics of a thin film transistor can be prevented, so that deterioration in display image quality can be prevented.

In order to realize the above-described configuration, more specifically, it is desirable that the relay layer and the light shielding layer are electrically connected by contact.
In order to realize the above configuration, more specifically, it is desirable that the gate electrode and the relay layer are brought into conduction by being in contact with each other.
According to this configuration, since the relay layer and the light shielding layer are in contact with the gate electrode and the relay layer, the contact resistance between the relay layer and the light shielding layer and the contact resistance between the gate electrode and the relay layer are Variations can be suppressed and the values of both contact resistances can be reduced. As a result, the on-current of the thin film transistor can be increased and stabilized (less variation in on-current).

More specifically, in order to realize the above-described configuration, it is desirable that the relay layer be formed from a high melting point material.
According to this configuration, even if a process having a high processing temperature, for example, a process of forming a thermal oxide film on the semiconductor layer is performed after the relay layer is formed, the relay layer can be prevented from being damaged. Since the relay layer is not damaged by the high temperature, the delay of the gate signal can be prevented, and the on-current of the thin film transistor can be increased and stabilized.
Examples of the refractory material include doped Si, and examples of the refractory metal include Cr, Ti, W, Ta, and Mo. More preferably, the relay layer is formed as a metal silicide film of the refractory metal. It is desirable.

In order to realize the above configuration, more specifically, it is desirable that the light shielding layer is electrically independent between gate electrodes to which different gate signals are input.
According to this configuration, it is possible to prevent a gate signal to be transmitted to a predetermined gate electrode from being transmitted to another gate electrode via the light shielding layer. Therefore, it is possible to prevent the semiconductor device from operating unintentionally. For example, when this semiconductor device is used for a liquid crystal display device, it is possible to prevent erroneous display of an image and to prevent deterioration in the quality of a display image.

In order to realize the above configuration, more specifically, it is desirable that the support substrate is a transparent substrate. More preferably, the support substrate is a glass substrate, and the support substrate is preferably a quartz substrate.
According to this configuration, by using a transparent substrate (preferably a glass substrate, more preferably a quartz substrate) as the support substrate, the semiconductor device can be provided with translucency. Therefore, the semiconductor device can be used for a light transmission type electro-optical device.

In order to realize the above configuration, more specifically, the thin film transistor may be formed of one type of conductive transistor.
According to this configuration, since the plurality of thin film transistors are formed of one type of conductive transistor, the manufacturing process of the thin film transistor can be simplified as compared with the case of forming from a plurality of conductive type transistors. . Therefore, the manufacturing process of the semiconductor device can be simplified and the manufacturing efficiency can be improved.

An electro-optical device according to the present invention includes the semiconductor device according to the present invention.
That is, since the electro-optical device of the present invention includes the semiconductor device of the present invention, it is possible to prevent a decrease in contrast due to insufficient writing to the thin film transistor and a luminance gradient due to application of a DC voltage component to the liquid crystal material. A decrease can be prevented. In addition, by increasing and stabilizing the on-state current, it is possible to improve brightness unevenness of the display image and to increase the number of gradations.

An electronic apparatus according to the present invention includes the electro-optical device according to the present invention.
That is, since the electronic apparatus of the present invention includes the electro-optical device of the present invention, it is possible to prevent a decrease in contrast due to insufficient writing to the thin film transistor and a luminance gradient due to application of a DC voltage component to the liquid crystal material. A decrease can be prevented. In addition, by increasing and stabilizing the on-state current, it is possible to improve brightness unevenness of the display image and to increase the number of gradations.

[First Embodiment]
A liquid crystal device that is a first embodiment of an electro-optical device using a semiconductor device according to the present invention will be described below with reference to FIGS. The liquid crystal device according to the present embodiment is an active matrix transmissive liquid crystal device using a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) type TFT as a switching element TFT. Moreover, in this embodiment, the case where TN mode is employ | adopted as a display mode is illustrated.

FIG. 1 is an equivalent circuit diagram of switching elements, signal lines, and the like in a plurality of pixels arranged in a matrix that constitutes an image display region of the transmissive liquid crystal device of this embodiment.
In the drawings shown in the present specification, the scales of the respective layers and members are different in order to make each layer and each member recognizable on the drawing.

  In the transmissive liquid crystal device according to the present embodiment, as shown in FIG. 1, a plurality of pixels arranged in a matrix constituting an image display region includes a pixel electrode 9 and a switching element for controlling the pixel electrode 9. TFTs (thin film transistors) 30 are respectively formed, and a data line 6 a for supplying an image signal output from an X driver (data line driving circuit) 201 to the TFT 30 is electrically connected to the source of the TFT 30. ing. Image signals S1, S2,..., Sn written from the X driver 201 to the data line 6a are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 6a. The

  A scanning line 3a for supplying a scanning signal output from the Y driver (scanning line driving circuit) 204 to the TFT 30 is electrically connected to the gate of the TFT 30, and the Y driver 204 supplies a plurality of scanning lines 3a to the gate. Scan signals G1, G2,..., Gm are applied in a line-sequential manner in a pulse manner at a predetermined timing. The pixel electrode 9 is electrically connected to the drain of the TFT 30, and the image signal S1, S2,... Supplied via the data line 6a is turned on by turning on the TFT 30 as a switching element for a certain period. , Sn is written at a predetermined timing.

  Image signals S1, S2,..., Sn written at a predetermined level on the liquid crystal via the pixel electrode 9 are held for a certain period with a common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode. The storage capacitor 70 is connected to a capacitor line 300 extending alongside the scanning line 3a. The capacitor line 300 is connected to a Y driver 204, and an arbitrary voltage or electric signal can be applied by the Y driver 204. It is configured.

FIG. 2 is a plan view showing the structure of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed.
Next, the planar structure of the transmissive liquid crystal device of this embodiment will be described with reference to FIG.
As shown in FIG. 2, a plurality of planar rectangular pixel electrodes 9 are arranged in a matrix on the TFT array substrate, and the data lines 6a and the scanning lines 3a are arranged along the vertical and horizontal boundaries of the pixel electrodes 9, respectively. And the capacity line 300 is extended. In this embodiment, an area where one pixel electrode 9 and a data line 6a, a scanning line 3a, a capacitor line 300, and the like arranged so as to surround the pixel electrode 9 are formed is a pixel and arranged in a matrix. Thus, the display can be performed for each pixel. A TFT 30 is formed in a region where the data line 6a and the scanning line 3a intersect.

The data line 6a is electrically connected to a source region, which will be described later, through contact holes 82 and 83 in the semiconductor layer 1a (a hatched region rising to the right in the figure) that constitutes the TFT 30, for example, made of a single crystal silicon film. The first source relay layer 3c and the second source relay layer 71b described later are connected via a contact hole 81.
On the other hand, the pixel electrode 9 has a contact hole 8 formed in a first drain relay layer 3b, which will be described later, which is electrically connected to a drain region which will be described later in the semiconductor layer 1a via contact holes 84, 85, and a capacitor electrode 71a. Is electrically connected.

The scanning line 3a includes a main line portion extending substantially linearly along the left-right boundary in FIG. 2 of the pixel electrode 9, and the data line 6a extending from the location where the main line portion intersects the data line 6a in FIG. And a protruding portion protruding in the vertical direction. Further, the scanning lines 3a adjacent in the vertical direction are formed electrically independently.
The scanning line 3a also functions as a light shielding film and is formed so as to cover the TFT 30 including the channel region of the semiconductor layer 1a when viewed from the TFT array substrate side. Therefore, hereinafter, the scanning line 3a is referred to as a light shielding scanning line (light shielding layer) 3a.
Further, the semiconductor layer 1a and the light-shielding scanning line 3a are arranged so as to cross each other so as to face each other in a channel region (a hatched region in the left-upward direction in the figure) described later of the semiconductor layer 1a.

A gate electrode 3g electrically connected to the light-shielding scanning line 3a is disposed to face the channel region and functions as a gate electrode layer. The gate electrode 3g is formed independently for each TFT 30, and extends substantially linearly in the left-right direction on the channel region, and functions as a gate electrode layer, and is formed above and below the electrode portions formed at both ends of the electrode portion. And a connecting portion having a wide width in the direction. The gate electrode 3g is electrically connected to the light-shielding scanning line 3a at the connection portion.
As described above, the gate electrode 3g may be formed independently for each TFT 30, or as shown in FIG. 3, the gate electrode 3g electrically connected to the same light-shielding scanning line 3a. You may connect between by a connection part.

As shown in FIG. 2, the relay layer 4 is formed in substantially the same region as the light-shielding scanning line 3a and between the semiconductor layer 1a and the light-shielding scanning line 3a (see FIG. 2). 4).
The relay layer 4 electrically connects the light-shielding scanning line 3a and the gate electrode 3g and functions as a light-shielding film so as to cover the TFT 30 including the channel region of the semiconductor layer 1a when viewed from the TFT array substrate side. Is formed.

  The capacitor line 300 has a main line portion that extends substantially linearly along the light-shielding scanning line 3a, and a protrusion that protrudes forward (upward in the figure) along the data line 6a from a location where the main line portion intersects the data line 6a. Part.

FIG. 4 is a cross-sectional view showing the structure of the transmissive liquid crystal device of this embodiment, and is a cross-sectional view taken along the line AA ′ of FIG.
Next, a cross-sectional structure of the transmissive liquid crystal device of the present embodiment will be described with reference to FIG.
As shown in FIG. 4, the transmissive liquid crystal device of this embodiment includes a TFT array substrate (semiconductor substrate) 10, a counter substrate 20 disposed opposite thereto, and a liquid crystal sandwiched between the substrates 10 and 20. Layer 50. The TFT array substrate 10 is mainly composed of a substrate body (support substrate, transparent substrate, glass substrate, quartz substrate) 10A made of a light-transmitting material such as quartz, the pixel electrode 9 formed on the liquid crystal layer 50 side surface, the TFT 30, and the like. The counter substrate 20 is mainly composed of a substrate body 20A made of a translucent material such as glass or quartz and a common electrode 21 formed on the surface of the liquid crystal layer 50 side. By using a substrate made of a light-transmitting material such as quartz for the substrate main bodies 10A and 20A, the liquid crystal device of this embodiment has light transmittance and can be a transmissive liquid crystal device.

In the TFT array substrate 10, a pixel electrode 9 is provided on the surface of the substrate body 10 </ b> A on the liquid crystal layer 50 side, and a pixel switching TFT 30 that performs switching control of each pixel electrode 9 is provided at a position adjacent to each pixel electrode 9. ing.
The TFT 30 has an LDD (Lightly Doped Drain) structure as shown in FIG. 4, and includes a gate electrode 3g, a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the gate electrode 3g, and a gate electrode 3g. A first gate insulating film 2a, a second gate insulating film 2b, a data line 6a, a low concentration source region 1b and a low concentration drain region 1c of the semiconductor layer 1a, and a high concentration source region of the semiconductor layer 1a. 1d and a high concentration drain region 1e.

On the surface of the substrate body 10A on the liquid crystal layer 50 side, the light incident from the substrate body 10A side enters the channel region 1a ′ and the low-concentration source / drain regions 1b and 1c of the semiconductor layer 1a. A light-shielding scanning line 3 a that functions as a light-shielding film for preventing incidence is provided.
Between the light-shielding scanning line 3a and the TFT 30, there is an underlying insulating film 12 composed of an insulating film 12a, a protective layer 12b, an insulating film 12c, and a bonded insulating film 12d, which are sequentially stacked from the substrate body 10A side. Is provided. The base insulating film 12 has a function of electrically insulating the semiconductor layer 1a constituting the TFT 30 and the light-shielding scanning line 3a. In addition, the light-shielding scanning line 3a is oxidized in a subsequent process, or the light-shielding scanning line. It is possible to prevent the component 3a from diffusing and contaminating the semiconductor layer 1a.

FIG. 5 is a cross-sectional view showing the structure of the transmissive liquid crystal device of this embodiment, and is a partial cross-sectional view taken along the line BB ′ of FIG.
The relay layer 4 is formed between the insulating film 12c and the bonded insulating film 12d, and the relay layer 4 scans light through a relay contact hole 86 that penetrates the insulating film 12a, the protective layer 12b, and the insulating film 12c. It is electrically connected to the line 3a. As shown in FIG. 5, the relay layer 4 is electrically connected to the gate electrode 3g through a gate contact hole 87 that penetrates the second gate insulating film 2b and the bonded insulating film 12d.

  Thus, as shown in FIG. 4, the TFT array substrate 10 according to the present embodiment uses a composite substrate (SOI substrate) in which the semiconductor layer 1a is formed on the substrate body 10A with the base insulating film 12 interposed therebetween. In the active matrix substrate thus configured, the bonding insulating film 12d of the base insulating film 12 is an insulating film having a bonding interface bonded using an SOI technique.

  A first source contact hole 83 leading to the high concentration source region 1d and a first drain contact hole 85 leading to the high concentration drain region 1e are formed in the first gate insulating film 2a and the second gate insulating film 2b of the TFT 30. Yes. On the second gate insulating film 2b, a first source relay layer 3c and a first drain made of a conductive material (for example, a doped polysilicon film), preferably made of the same material as the gate electrode 3g. The relay layer 3b is formed. The first source relay layer 3c and the first drain relay layer 3b may be formed of a doped polysilicon film as described above, or may be formed of a highly conductive metal film.

A first interlayer insulating film 41 is formed on the gate electrode 3g and the second gate insulating film 2b, and a second source contact hole 82 leading to the first source relay layer 3c is formed in the first interlayer insulating film 41. , And a second drain contact hole 84 leading to the first drain relay layer 3b. A capacitor electrode 71a and a second source relay layer 71b are formed on the first interlayer insulating film 41.
In the plan view shown in FIG. 2, the capacitor electrode 71a is formed in a substantially L shape extending along the light shielding scanning line 3a and the data line 6a with the position where the light shielding scanning line 3a and the data line 6a intersect as a base point. Yes.
As shown in FIG. 4, the capacitor electrode 71a is connected to the high concentration drain region 1e of the semiconductor layer 1a via the first drain relay layer 3b formed in the second drain contact hole 84 and the first drain contact hole 85. Is electrically connected. The second source relay layer 71b is electrically connected to the high concentration source region 1d through the first source contact hole 83.

A capacitor insulating film 75 is formed so as to cover the capacitor electrode 71a and the second source relay layer 71b on the first interlayer insulating film 41. The capacitor line 300 is formed so as to face the capacitor electrode 71a with the capacitor insulating film 75 interposed therebetween. In the present embodiment, the capacitor electrode 71a as the pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9 and a part of the capacitor line 300 as the fixed potential side capacitor electrode are capacitively insulated. The storage capacitor 70 is formed by being opposed to each other via the film 75.
The capacitor electrode 71a as the pixel potential side capacitor electrode is made of a doped polysilicon film having conductivity. The capacitor line 300 as a fixed potential side capacitor electrode includes a doped polysilicon film having conductivity, a first film 72 made of an amorphous or single crystal silicon film, a metal silicide film containing a refractory metal, etc. The second film 73 is made of a multilayer film formed by laminating.

In the liquid crystal device according to the present embodiment, the light-shielding scanning line 3a that functions as the light-shielding film of the TFT 30, the relay layer 4, and the second film 73 of the capacitor line 300 are high in, for example, Cr, Ti, W, Ta, Mo, Pb, and the like. It is preferable to use a melting point metal, or a metal silicide containing these metals, a polysilicide, or a laminate of these metals. In some cases, it may be made of Al or the like.
The capacitor insulating film 75 constituting the storage capacitor 70 interposed between the capacitor electrode 71a and the capacitor line 300 is, for example, a relatively thin HTO film having a film thickness of about 5 to 200 nm, a silicon oxide film such as an LTO film, It is composed of a silicon nitride film, a nitrided oxide film, or a laminated film thereof. From the viewpoint of increasing the storage capacity, it is better that the capacitor insulating film 75 is thinner as long as the reliability of the film is sufficiently obtained.

The first film 72 that not only functions as a light absorption layer but also constitutes a part of the capacitor line 300 is made of, for example, a polysilicon film with a film thickness of 50 to 150 nm or a silicon film made of amorphous or single crystal. Further, the second film 73 that not only functions as a light shielding film but also constitutes a part of the capacitor line 300 is made of, for example, a tungsten silicide film having a thickness of about 150 nm. Further, the capacitor electrode 71 a is composed of a polysilicon film similar to the first film 72.
As described above, the first film 72 and the capacitor electrode 71a disposed on the side in contact with the capacitor insulating film 75 are formed of the polysilicon film, thereby preventing the capacitor insulating film 75 from being deteriorated and improving the reliability of the liquid crystal device. Can be made.

A third interlayer insulating film 42 is formed on the capacitor insulating film 75 and on the substrate body 10 </ b> A including the capacitor line 300. In the third interlayer insulating film 42, a pixel contact hole 8 leading to the capacitor electrode 71a, a third source contact hole 81 leading to the second source relay layer 71b, and a contact hole 93 leading to the capacitor line 300 are opened. .
On the third interlayer insulating film 42, data lines 6a extending in a direction perpendicular to the light-shielding scanning lines 3a and signal wirings 6b are formed.
The data line 6a is electrically connected to the second source relay layer 71b via the third source contact hole 81, and is electrically connected to the high concentration source region 1d of the semiconductor layer 1a via the second source relay layer 71b. ing.

  The capacitor line 300 extends in a plan view from the image display region in which the pixel electrode 9 is disposed, and is connected to the signal line 6b through a contact hole 93 provided through the second interlayer insulating film 42. Conductive connection. The signal wiring 6b is actually electrically connected to the constant potential source of the Y driver 204 disposed outside the image display area, and holds the capacitor line 300 at an arbitrary potential. .

  As a constant potential source conductively connected to the capacitor line 300, not only a Y driver (scanning line driving circuit) 204 for supplying the scanning signal of the TFT 30 to the light-shielding scanning line 3a but also an image signal is supplied to the data line 6a. Therefore, it is also possible to use a constant power source such as a positive power source or a negative power source supplied to an X driver (data line driving circuit) 201 that controls the sampling circuit. Further, a constant potential source that supplies a constant potential to the electrode 21 of the counter substrate 20 may be used.

A third interlayer insulating film 43 is formed on the second interlayer insulating film 42 and on the substrate body 10A including the data line 6a. A pixel contact hole 8 leading to the capacitor electrode 71a is opened in the third interlayer insulating film 43. Has been. That is, the pixel contact hole 8 is a contact hole that passes through the third interlayer insulating film 43 and the second interlayer insulating film 42 and reaches the capacitor electrode 71a.
A pixel electrode 9 is formed on the third interlayer insulating film 43, and the pixel electrode 9 is conductively connected to the capacitor electrode 71 a through the pixel contact hole 8. With this conductive connection structure, the pixel electrode 9 is electrically connected to the high-concentration drain region 1e of the semiconductor layer 1a through the capacitance electrode 71a. In addition, the pixel electrode 9 is formed in a rectangular shape in a region including the image display region as shown in FIG.

  As described above, the capacitor electrode 71a functions as a pixel potential side capacitor electrode of the storage capacitor 70 and a function as a light absorption layer, and also functions to relay the electrical connection between the pixel electrode 9 and the high concentration drain region 1e. have. By providing such a capacitive electrode 71a, even when the interlayer distance is as long as 1000 to 2000 nm, for example, a series of relatively small diameters is avoided while avoiding the technical difficulty of connecting the two with a single contact hole. The contact holes can be satisfactorily connected to each other, and the pixel aperture ratio can be improved by reducing the contact hole diameter. In addition, since the depth of the opening is relatively small even when the contact hole is opened, there is an effect that penetration during etching hardly occurs.

  On the outermost surface of the TFT array substrate 10 on the liquid crystal layer 50 side, that is, on the third interlayer insulating film 43 including the pixel electrode 9, an alignment film for regulating the alignment of liquid crystal molecules in the liquid crystal layer 50 when no voltage is applied. 16 is formed. A polarizer 17 is provided on the surface of the TFT array substrate 10 opposite to the liquid crystal layer 50.

  On the other hand, in the counter substrate 20, a common electrode 21 made of indium tin oxide (ITO) or the like is formed over the entire surface of the substrate body 20 </ b> A on the liquid crystal layer 50 side. An alignment film 22 for regulating the alignment of liquid crystal molecules in the liquid crystal layer 50 when no voltage is applied is formed. A polarizer 24 is also provided on the surface of the counter substrate 20 opposite to the liquid crystal layer 50.

  The surface of the substrate body 10A of the TFT array substrate 10 on the liquid crystal layer 50 side can also be provided with a groove in a lattice pattern in plan view. In this groove, wiring such as the light-shielding scanning line 3a, the data line 6a, the TFT 30, By forming the element, it is possible to alleviate the formation of a step between the region where the wiring or the element is formed and the region where these are not formed. The advantage that alignment failure etc. can be prevented is obtained.

According to the above configuration, by using the relay layer 4, the contact hole that electrically connects the gate electrode 3 g and the light-shielding scanning line 3 a becomes the gate contact that electrically connects the gate electrode 3 g and the relay layer 4. The hole 87 is divided into a relay contact hole 86 that electrically connects the relay layer 4 and the light-shielding scanning line 3a, and the aspect ratio of the contact hole is reduced (the contact hole becomes thicker and shorter). As a result, the electrical resistance of the connecting portion in the contact hole can be lowered, and variation in the electrical resistance can be reduced. As a result, the delay of the gate signal can be prevented, and the on-current of the TFT 30 can be increased and stabilized (less variation in on-current).
Therefore, since the liquid crystal device of the present invention can prevent the delay of the gate signal, it can prevent a decrease in contrast due to insufficient writing to the TFT 30 and a luminance gradient due to application of a DC voltage component to the liquid crystal material, thereby preventing a deterioration in display quality. be able to. In addition, by increasing and stabilizing the on-state current, it is possible to improve brightness unevenness of the display image and to increase the number of gradations.

  Since the relay layer 4 is formed in a layer closer to the TFT 30 than the light shielding scanning line 3a, the relay layer 4 can shield light incident on the TFT 30 from a wider angle than the light shielding scanning line 3a. Therefore, it becomes easy to prevent generation of photocurrent in the channel formation region of the TFT 30, and deterioration of transistor characteristics of the TFT 30 can be prevented.

  Since the relay layer 4 and the light-shielding scanning line 3a are in contact with the gate electrode 3g and the relay layer 4, the contact resistance between the relay layer 4 and the light-shielding scanning line 3a and the gate electrode 3g and the relay layer 4 are Variations in contact resistance can be suppressed and the values of both contact resistances can be reduced. As a result, the on-current of the TFT 30 can be increased and stabilized (less variation in on-current).

  Since adjacent light-shielding scanning lines 3a are formed electrically independently, a gate signal to be transmitted to a predetermined gate electrode 3g is transmitted to another gate electrode 3g via the light-shielding scanning line 3a. Can be prevented. Therefore, the liquid crystal device can prevent erroneous display of images, and can prevent deterioration in the quality of displayed images.

<Method for manufacturing active matrix substrate>
Hereinafter, an active matrix substrate manufacturing method including a semiconductor device manufacturing method according to the present invention will be described with reference to the drawings. In the present embodiment, a process of manufacturing the TFT array substrate 10 provided in the liquid crystal device of the previous embodiment will be described in detail with reference to cross-sectional process diagrams shown in FIGS.

First, as shown in FIG. 6A, a substrate body 10A made of glass, quartz or the like is prepared. The substrate body 10A is preferably annealed at a temperature equal to or higher than the heating temperature in the subsequent steps. Specifically, annealing is preferably performed by heating to about 850 ° C. to 1300 ° C. in an inert gas atmosphere such as N ₂ . By performing the annealing process, it is possible to reduce the distortion of the substrate that occurs when the substrate main body 10A is subjected to a high-temperature process in a subsequent process.

Next, a light-shielding scanning line 3a that functions as a light-shielding film is formed on the entire surface of the substrate body 10A thus treated. The light-shielding scanning line 3a is made of a single metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pb, and is formed by a sputtering method, a CVD method, an electron beam heating vapor deposition method, or the like. It is deposited and patterned into a predetermined planar shape using a known photolithography technique. More preferably, the light-shielding scanning line 3a is formed from tungsten silicide (WSi).
Further, the film thickness of the light-shielding scanning line 3a is desirably formed to, for example, approximately 150 nm to approximately 200 nm, and more preferably approximately 200 nm.

Next, as shown in FIG. 6B, an insulating film 12a, a protective layer 12b, an insulating film 12c, and the like are formed on the surface of the substrate body 10A on which the light-shielding scanning lines 3a are formed by sputtering, CVD, or the like. , Form.
As the constituent material of the insulating films 12a and 12c, highly insulating glass such as silicon oxide, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorous silicate glass), etc. Etc. can be illustrated. Preferably, the insulating film 12a is made of high temperature silicon oxide (hereinafter referred to as HTO) HTO, and the insulating film 12c is made of TEOS (tetraethoxysilane) -NSG.
The film thickness of the insulating film 12a is preferably about 50 nm, and the film thickness of the insulating film 12c is preferably about 600 nm, but the film thickness is not particularly limited. Further, as the protective layer 12b, for example, a silicon nitride (SiN) film having a thickness of about 10 nm to 50 nm, preferably 15 nm can be used, and can be formed by a low pressure CVD method or a plasma CVD method using dichlorosilane and ammonia. .

At this time, a convex portion that follows the light-shielding scanning line 3a is formed on the surface of the insulating film 12c on the region where the light-shielding scanning line 3a is formed. Further, by providing the protective layer 12b, diffusion of the metal material constituting the light-shielding scanning line 3a and diffusion of impurities from the substrate body 10A can be suppressed, and the reliability of the semiconductor device can be improved. .
As described above, the protrusions may be left on the surface of the insulating film 12c, or the surface of the insulating film 12c may be polished using a method such as CMP (chemical mechanical polishing). The surface of the insulating film 12c may be planarized.

  Then, as shown in FIG. 6C, a relay contact hole 86 that penetrates the insulating film 12a, the protective layer 12b, and the insulating film 12c is formed using a known photolithography method or the like. At this time, since the film thickness of the insulating film 12a, the protective layer 12b, and the insulating film 12c is, for example, about 50 nm, about 15 nm, and about 600 nm, the depth of the relay contact hole 86 becomes shallow, and the depth is controlled. It becomes easy.

  When the relay contact hole 86 is formed, as shown in FIG. 6D, a doped polysilicon film into which phosphorus ions are introduced simultaneously with the film formation is formed. Alternatively, a metal simple substance, an alloy, or a metal silicide film including at least one of Ti, Cr, W, Ta, Mo, and Pb is formed. Then, the relay layer 4 is formed by forming a pattern in a predetermined planar shape using a known photolithography technique.

Next, as shown in FIG. 6E, an insulating film 12d1 is formed over the insulating film 12c and the relay layer 4 by a sputtering method, a CVD method, or the like.
As a constituent material of the insulating film 12d1, highly insulating glass such as silicon oxide, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), or the like is used. It can be illustrated. Preferably, the insulating film 12d1 is formed of TEOS (tetraethoxysilane) -NSG.
At this time, on the region where the relay layer 4 is formed, a convex portion that follows the relay layer 4 is formed on the surface of the insulating film 12d1.
After that, the surface of the insulating film 12d1 is polished using a method such as CMP to planarize the surface of the insulating film 12d1.

Next, as shown in FIG. 7A, the substrate body 10A that has undergone the above steps is bonded to a separately prepared single crystal silicon substrate.
As the single crystal silicon substrate used for bonding, a single crystal silicon substrate having a plate thickness of, for example, about 600 μm composed of the single crystal silicon layer 1 and the oxide film 12d2 formed on one surface thereof is used. For example, hydrogen ions are implanted into the single crystal silicon layer 1 at an acceleration voltage of 100 keV and a dose of 10 × 10 ¹⁶ / cm ² . The oxide film 12d2 can be formed by oxidizing the single crystal silicon layer of the single crystal silicon substrate 1 by about 50 nm to 800 nm. For the bonding step, a method of directly bonding two substrates can be adopted by performing heat treatment at about 300 ° C. to 350 ° C. for 2 hours in a state where the single crystal silicon substrate and the substrate body 10A are in contact with each other. By this bonding step, a bonding insulating film 12d having a bonding interface s is formed between the single crystal silicon layer (semiconductor layer) and the insulating layer 12c.

In order to further increase the bonding strength, a method of raising the heat treatment temperature to about 450 ° C. can be applied. However, the thermal expansion coefficient of the substrate body 10A made of quartz or the like and the thermal expansion coefficient of the single crystal silicon substrate 1 are Since there is a large difference between them, if the heating is continued as it is, defects such as cracks are generated in the single crystal silicon layer, and the quality of the manufactured TFT array substrate 10 may be deteriorated.
In order to suppress the occurrence of such defects such as cracks, the single crystal silicon substrate 1 once subjected to heat treatment for bonding at 300 ° C. is thinned to about 100 to 150 μm by wet etching or CMP, Thereafter, it is desirable to perform heat treatment at a higher temperature. For example, etching is performed using a KOH aqueous solution at 80 ° C. so that the thickness of the single crystal silicon substrate 1 becomes 150 μm, and then bonding is performed with the substrate body 10A, followed by heat treatment again at 450 ° C. It is desirable to increase the bonding strength.

  Next, the bonded single crystal silicon layer 1 is partially peeled off. This separation of the single crystal silicon layer utilizes an action in which silicon bonds are separated in the vicinity of the surface of the single crystal silicon layer 1 on the side of the bonded insulating film 12c by hydrogen ions introduced into the single crystal silicon layer 1. To do. The heat treatment here can be performed, for example, by heating the two bonded substrates to 600 ° C. at a temperature increase rate of 20 ° C. per minute. By this heat treatment, the bonded single crystal silicon layer 1 is partially separated from the substrate body 10A, and a single crystal silicon layer of about 200 nm ± 5 nm is obtained on the surface of the substrate body 10A. About the film thickness of the single crystal silicon layer 1 after peeling, it can adjust arbitrarily in the range of 10 nm-3000 nm, for example by changing the acceleration voltage of the hydrogen ion implantation performed with respect to the single crystal silicon substrate mentioned above.

  In addition to the method described here, the thinned single crystal silicon layer 1 is polished by a PACE (Plasma Assisted Chemical Etching) method after polishing the surface of the single crystal silicon substrate to a thickness of 3 to 5 μm. An ELTRAN (Epitaxial Layer) method in which the film thickness is etched to about 0.05 to 0.8 μm and the epitaxial silicon layer formed on the porous silicon is transferred onto the bonded substrate by selective etching of the porous silicon layer. It can also be obtained by the Transfer method.

  Furthermore, in order to improve the adhesion between the bonding insulating film 12d and the single crystal silicon layer 1 and increase the bonding strength, the substrate body 10A and the single crystal silicon layer 1 are bonded together, and then a rapid thermal processing method ( It is desirable to perform a heat treatment such as RTA). The heating temperature at that time is preferably 600 ° C. to 1200 ° C., preferably 1050 ° C. to 1200 ° C. in order to lower the viscosity of the insulating film and increase the atomic adhesion.

Next, as shown in FIG. 7B, a semiconductor layer 1a having a predetermined pattern is formed with a film thickness of, for example, approximately 40 nm to approximately 60 nm by a mesa-type separation method using a photolithography process, an etching process, or the like. For the element isolation step, a well-known LOCOS isolation method or trench isolation method can also be used.
Thereafter, the semiconductor layer 1a is thermally oxidized at a temperature of about 750 ° C. to 1050 ° C. to form a first gate oxide film (gate insulating film) 2a. The thickness of the first gate oxide film 2a is preferably about 5 to 50 nm, more preferably about 20 nm. As the thermal oxidation method here, dry thermal oxidation treatment or wet thermal oxidation treatment is appropriately selected and used according to the thickness of the first gate oxide film 2a to be specifically formed as described above.
Thereafter, the second gate insulating film 2b made of HTO is formed on the first gate oxide film 2a and the bonded insulating film 12d by sputtering, CVD, or the like. The second gate insulating film 2b is preferably formed with a film thickness of approximately 60 nm, but may be formed with a film thickness other than that.

Next, as shown in FIG. 8A, when the first gate insulating film 2a and the second gate insulating film 2b are formed, ion implantation is performed on the semiconductor layer 1a.
In this embodiment, the case where an N-channel thin film transistor is formed as the TFT 30 will be described. However, the TFT 30 may be a P-channel transistor, or a part thereof may be a P-channel transistor.
In order to form the N-channel TFT 30, first, the semiconductor layer 1a is doped with a dopant of a group III element such as boron at a low concentration (for example, an acceleration voltage of 35 keV and a dose of about 1 × 10 ¹² / cm ² ). Thereafter, a group III element such as boron is doped with a dose of 1 to 10 times that of the above-described process while further coating the photoresist on the semiconductor layer 1a and the gate insulating film 2. Subsequently, in order to form the N-channel high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, phosphorus or the like is formed in a state where a resist layer is formed with a mask wider than a light-shielding scanning line 3a described later. The dopant of the group V element is doped at a high concentration (for example, P ions are accelerated at an acceleration voltage of 70 keV and a dose of 4 × 10 ¹⁵ / cm ² ).
When forming a P-channel TFT, a group V element dopant such as phosphorus may be used instead of the group III element dopant, and a group III element such as boron may be used instead of the group V element dopant. Use a dopant. In the drawings referred to below,
The high concentration source region 1d and the high concentration drain region 1e, and the low concentration source region 1b and the low concentration drain region 1c, which will be described later, are omitted as appropriate.

  Next, as shown in FIG. 8B, the first source penetrating the first gate insulating film 2a and the second gate insulating film 2b in the region corresponding to the high concentration source region 1d and the high concentration drain region 1e. The contact hole 83 and the first drain contact hole 85 are formed using a known photolithography method or the like. At this time, since the film thicknesses of the first gate insulating film 2a and the second gate insulating film 2b are, for example, about 20 nm and about 60 nm, the depths of the first source contact hole 83 and the first drain contact hole 85 become shallow. , It becomes easier to control the depth.

Next, as shown in FIG. 8C, a doped polysilicon film into which phosphorus ions are introduced simultaneously with film formation is formed. Alternatively, a film obtained by depositing a polysilicon film with a thickness of about 350 nm by a low pressure CVD method or the like and then thermally diffusing phosphorus (P) to make the polysilicon film conductive can be used. Furthermore, a single metal, an alloy, a metal silicide, or the like containing at least one of Ti, W, Co, and Mo on the doped polysilicon film is formed by sputtering, CVD, electron beam heating deposition, or the like. For example, it is good also as a layered structure deposited in the film thickness of 150-200 nm. By employing such a layer structure, the conductivity of the layer including the doped polysilicon film can be improved.
A gate electrode 3g having a predetermined pattern, a first source relay layer 3c, and a first drain relay layer 3b are formed by a photolithography process, an etching process, or the like using a resist mask.
Thereafter, in order to form an N-channel LDD region in the semiconductor layer 1a, a dopant of a group V element such as phosphorus is first doped at a low concentration using the gate electrode 3g as a mask. Specifically, P ions are doped at an acceleration voltage of 70 keV and a dose of 6 × 10 ¹² / cm ² to form the low concentration source region 1b and the low concentration drain region 1c shown in FIG.

FIGS. 9A to 9C are process diagrams viewed from a cross section taken along the line BB ′ in FIG. 2, and are diagrams illustrating the same processes as those in FIGS. 8A to 8C.
FIG. 9A is a diagram showing a step of performing ion implantation into the semiconductor layer 1a.
Next, as shown in FIG. 9B, a gate contact hole 87 that penetrates the first gate insulating film 2b and the bonded insulating film 12d is formed by using a known photolithography method or the like (see FIG. 2). . At this time, the depth of the gate contact hole 87 is shallower than that of the contact hole penetrating to the light-shielding scanning line 3a. Therefore, the ratio (aspect ratio) between the cross-sectional area and the depth of the contact hole is reduced, and the gate contact hole 87 is easily formed. Further, since the depth of the gate contact hole 87 becomes shallow, it becomes easy to control the depth during formation.

After the gate contact hole 87 is formed, a doped polysilicon film into which phosphorus ions are introduced at the same time as the film formation is formed as shown in FIG. 9C. Alternatively, a film obtained by depositing a polysilicon film by a low pressure CVD method or the like and thermally diffusing phosphorus (P) to make the polysilicon film conductive can be used. Further, a single metal, an alloy, a metal silicide, or the like containing at least one of Ti, W, Co, and Mo is deposited on the doped polysilicon film by a sputtering method, a CVD method, an electron beam heating evaporation method, or the like. A layered structure may be used.
A gate electrode 3g having a predetermined pattern, a first source relay layer 3c, and a first drain relay layer 3b are formed by a photolithography process, an etching process, or the like using a resist mask.

Next, as shown in FIG. 10A, NSG, PSG, BSG, BPSG is formed by, for example, atmospheric pressure or low pressure CVD so as to cover the gate electrode 3g, the first source relay layer 3c, and the first drain relay layer 3b. A first interlayer insulating film 41 made of a silicate glass film such as silicon nitride film or silicon oxide film is formed.
The film thickness of the first interlayer insulating film 41 is preferably about 500 to 1500 nm, and more preferably 800 nm. Thereafter, in order to activate the high concentration source region 1d and the high concentration drain region 1e, an annealing process at about 850 ° C. is performed for about 20 minutes.

Next, the second source contact hole 82 that reaches the first source relay layer 3c through the first interlayer insulating film 41 and the second drain contact hole 84 that reaches the first drain relay layer 3b are subjected to reactive etching and reaction. It is formed by dry etching such as reactive ion beam etching or wet etching.
Thereafter, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film is formed on the first interlayer insulating film 41. Alternatively, a polysilicon film may be deposited with a thickness of about 350 nm by a low pressure CVD method or the like, and then phosphorus (P) may be thermally diffused to make the polysilicon film conductive.
After forming the doped polysilicon film, the doped polysilicon film is patterned by a photolithography process, an etching process, or the like to form the capacitor electrode 71a and the second source relay layer 71b. Thereafter, a silicon oxide, silicon nitride, or silicon oxynitride film is formed by a vapor phase synthesis method such as atmospheric pressure or low pressure CVD method, vapor deposition method, etc., so that the first interlayer insulating film 41 and the capacitor electrode 71a are formed. Then, a capacitor insulating film 75 is formed to cover the second source relay layer 71b.

  Next, a laminated film of a first film 72 made of a doped polysilicon film or a single crystal silicon film and a second film 73 made of a metal silicide film containing a refractory metal or the like is formed, and a photolithography process and etching are performed. The capacitance line 300 having a predetermined planar shape shown in FIG. 2 is formed by patterning through a process or the like. Since the capacitor line 300 is connected to the Y driver 204 as shown in FIG. 1, it extends to the outside of the image display area in the left-right direction of FIG.

Next, as shown in FIG. 10B, NSG, PSG, BSG, and the like are used by using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas so as to cover the capacitor line 300 and the first interlayer insulating film 41. A second interlayer insulating film 42 made of a silicate glass film such as BPSG, a nitride semiconductor film, an oxide semiconductor film, or the like is formed. The film thickness of the second interlayer insulating film 42 is preferably about 500 to 1500 nm, more preferably about 800 nm.
Subsequently, a third source contact hole 81 that reaches the second source relay layer 71b through the second interlayer insulating film 42 and the capacitor insulating film 75 is formed.

Next, as shown in FIG. 10C, a light-shielding low-resistance metal such as Al or metal silicide is formed on the second interlayer insulating film 42 by sputtering or the like to a thickness of about 100 to 700 nm. Preferably, after depositing to about 350 nm, patterning is performed by a photolithography process, an etching process, or the like to form data lines 6a, signal wirings 6c, and wirings 6d.
The data line 6a is electrically connected to the second source relay layer 71b through the third source contact hole 81.

Next, as shown in FIG. 10D, NSG, PSG, BSG are used to cover the data line 6a and the second interlayer insulating film 42 using, for example, atmospheric pressure or reduced pressure CVD method, TEOS gas, or the like. A third interlayer insulating film 43 made of a silicate glass film such as BPSG, a nitride semiconductor film or an oxide semiconductor film is formed. The film thickness of the third interlayer insulating film 43 is preferably about 500 to 1500 nm, and more preferably 800 nm.
Next, in the TFT 30, in order to electrically connect the pixel electrode 9 and the capacitor electrode 71a, the pixel contact hole 8 penetrating the second interlayer insulating film 42 and the third interlayer insulating film 43 is subjected to reactive etching and reaction. It is formed by dry etching such as reactive ion beam etching.

Then, after depositing a transparent conductive thin film 9 such as ITO on the third interlayer insulating film 43 to a thickness of about 50 to 200 nm by sputtering or the like, patterning is performed by a photolithography process, an etching process, etc. The pixel electrode 9 having a rectangular shape in plan view shown in FIG. 2 is formed. Note that when the electro-optical device of the present embodiment is a reflective electro-optical device, the pixel electrode 9 may be formed from an opaque material having a high reflectance such as Al.
Thereafter, if the alignment film 16 made of polyimide or the like is applied and formed so as to cover the pixel electrode 9 and the third interlayer insulating film 43, the TFT array substrate 10 provided in the liquid crystal device of the previous embodiment is obtained.

  In the manufacturing method of the present embodiment including the above steps, since the plurality of TFTs 30 are configured by one type of conductive type transistor, the manufacturing process of the TFT 30 is compared with the case of forming from a plurality of conductive type transistors. Can be simplified. Therefore, the manufacturing process of the electro-optical device substrate can be simplified, and the manufacturing efficiency can be improved.

  Since the relay layer 4 is made of a doped polysilicon film or a single metal, alloy, or metal silicide film containing at least one of Ti, Cr, W, Ta, Mo, and Pb, the relay layer 4 Even if a process with a high processing temperature, for example, a process of forming a thermal oxide film on the semiconductor layer 1a, is performed after the formation of, the relay layer 4 can be prevented from being damaged. Since the relay layer 4 is not damaged by the high temperature, the delay of the gate signal can be prevented, and the on-current of the TFT 30 can be increased and stabilized.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG.
The basic configuration of the liquid crystal device in the present embodiment is the same as that in the first embodiment, but the TFT array substrate is different from the first embodiment. Therefore, in this embodiment, only the periphery of the insulating film of the TFT array substrate will be described with reference to FIG. 11, and description of the TFT and the like will be omitted.
Next, a cross-sectional structure of the transmissive liquid crystal device of this embodiment will be described with reference to FIG.
As shown in FIG. 11, on the substrate main body 10A, a light shielding scanning line 3a, an insulating film 12a, a relay layer 4, and a bonded insulating film 12d, which are sequentially stacked from the substrate main body 10A side, are provided. . The bonded insulating film 12d functions to electrically insulate the semiconductor layer 1a constituting the TFT 30 from the light-shielding scanning line 3a. In addition, the light-shielding scanning line 3a is oxidized in the subsequent process, or the light-shielding scanning is performed. It is possible to prevent the component of the line 3a from diffusing and contaminating the semiconductor layer 1a.
As described above, the TFT array substrate 10 according to the present embodiment is an active matrix substrate configured using a composite substrate (SOI substrate) in which the semiconductor layer 1a is formed on the substrate main body 10A via the bonded insulating film 12d. The bonded insulating film 12d is an insulating film having a bonded interface bonded using the SOI technology.

  According to said structure, the total film thickness of the insulating film 12a on the light-shielding scanning line 3a, the relay layer 4, and the bonding insulating film 12d can be made thin. Thereby, the light-shielding property by the light-shielding scanning line 3a and the relay layer 4 is improved, and the contrast of the display image by the liquid crystal device can be improved.

(Electronics)
As an electronic apparatus using the liquid crystal device having such a configuration, a projection display device (liquid crystal projector) illustrated in FIG. 12 can be given.
In the projection type liquid crystal display device 1100 shown in FIG. 12, a liquid crystal module including the above-described liquid crystal device 100 is employed as the RGB light valves 100R, 100G, and 100B.

In this liquid crystal projector 1100, when light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light corresponding to the three primary colors R, G, and B is emitted by three mirrors 1106 and two dichroic mirrors 1108. The light components are separated into components R, G, and B (light separating means) and led to the corresponding light valves 100R, 100G, and 100B (liquid crystal device 100 / liquid crystal light valve). At this time, since the optical component B has a long optical path, the light component B is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss.
The light components R, G, and B corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 1112 (light combining unit) from three directions and are combined again, and then the projection lens. A color image is projected on a screen 1120 or the like via 1114.

  According to the above configuration, since the liquid crystal device of the present invention is provided, unevenness in brightness of a display image displayed by the projection display device can be improved, and multi-gradation can be achieved.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, the liquid crystal device according to the present invention has been described as being adapted to a projection display device. However, the present invention is not limited to adaptation to a projection display device, and a portable device using a liquid crystal device is used. The present invention can be applied to electronic devices including various other liquid crystal devices such as telephones and PDAs.

1 is an equivalent circuit diagram of a liquid crystal device according to a first embodiment of the present invention. FIG. 3 is a plan configuration diagram of a pixel region. FIG. 6 is a plan configuration diagram of another example in the pixel region. FIG. 3 is a cross-sectional configuration diagram taken along line A-A ′ of FIG. 2. FIG. 3 is a partial cross-sectional configuration diagram taken along line B-B ′ of FIG. 2. It is a section manufacturing process figure of a TFT array substrate. It is a section manufacturing process figure of a TFT array substrate. It is a section manufacturing process figure of a TFT array substrate. It is a section manufacturing process figure of a TFT array substrate. It is a section manufacturing process figure of a TFT array substrate. It is a cross-sectional block diagram in 2nd Embodiment of the liquid crystal device by this invention. It is a schematic block diagram which shows one form of an electronic device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 3a ... Light-shielding scanning line (light-shielding layer), 3g ... Gate electrode, 4 ... Relay layer, 10 ... TFT array substrate (semiconductor substrate), 10A ... Substrate Main body (support substrate, transparent substrate, glass substrate, quartz substrate) 30 ... TFT (Thin Film Transistor)

Claims (12)

A support substrate and a semiconductor substrate having a semiconductor layer are bonded together,
A thin film transistor having the semiconductor layer as an active layer is formed,
Between the support substrate and the semiconductor layer, a light shielding layer is formed that has conductivity and blocks light incident on the thin film transistor from the support substrate side,
Between the light shielding layer and the thin film transistor, a relay layer that electrically connects the light shielding layer and the gate electrode of the thin film transistor, and a plurality of insulating films are laminated,
The relay layer is electrically connected to the light shielding layer through a contact hole penetrating an insulating film formed on the substrate so as to cover the light shielding film, and covers the relay layer. wherein the insulating another insulating film formed on the film via a contact hole passing through the are electrically connected to the gate electrode Te wherein a. The connection portion between the gate electrode and the light shielding layer is electrically connected when the relay layer and the light shielding layer are brought into contact with each other and the gate electrode and the relay layer are brought into contact with each other. The semiconductor device according to claim 1, further comprising a connecting portion.   The insulating film covering the light shielding film has a protective layer made of a nitride film and a plurality of insulating films made of oxide films respectively formed on upper and lower layers of the protective layer. Semiconductor device.   The said relay layer is formed from the material which shields light, and is formed in the area | region which shields the light which injects into the said thin-film transistor from the said support substrate side, It is any one of Claim 1 to 3 characterized by the above-mentioned. Semiconductor device.   The semiconductor device according to claim 1, wherein the relay layer is made of a high melting point material. The light-shielding layer, a semiconductor device according to any one of claims 1, characterized in that are electrically independent between different gate signal is a gate electrode which is input five. A semiconductor device according to any one of 6 claim 1 wherein the supporting substrate is a transparent substrate. The semiconductor device according to claim 7, wherein the support substrate is a glass substrate. The semiconductor device according to claim 7, wherein the support substrate is a quartz substrate. The thin film transistor is one kind of semiconductor device according to any one of claims 1 to 9, characterized by being composed of a conductive type of the transistor. Electro-optical apparatus comprising the semiconductor device according to any one of claims 1 to 10. An electronic apparatus comprising the electro-optical device according to claim 11 .

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