JP4507546B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, an active matrix substrate, an electro-optical device, and an electronic apparatus.

  2. Description of the Related Art Conventionally, in electro-optical devices such as liquid crystal display devices, thin film transistors (hereinafter abbreviated as TFTs) constituting peripheral drive circuits and pixel switching elements from the viewpoints of speeding up, low power consumption, high integration, and the like. A technique using single crystal silicon for the active layer is known, and an SOI (Silicon On Insulator) technique has been conventionally used as a technique for forming such single crystal silicon on an insulating substrate such as glass or quartz. .

By the way, when the SOI technology is applied to an electro-optical device or the like, reliability at the bonding interface of the insulating film between the insulating substrate and the single crystal silicon may be a problem. Specifically, when opening a contact hole that conductively connects conductive layers (for example, a light shielding film and a capacitor line) provided on both sides across the bonding interface, an etchant enters the bonding interface, Cracks and peeling may occur at such interfaces. Therefore, in Patent Document 1 described below, a method of penetrating the bonding interface by dry etching when the contact hole is opened is used to prevent contact between the bonding interface and the etching solution.
JP 2002-353424 A

  According to the manufacturing method described in Patent Document 1, defects such as cracks and peeling at the bonding interface can surely be prevented. However, in an active matrix substrate used for an electro-optical device or the like, a relatively complicated structure has an SOI substrate. Since the contact hole penetrating the bonding interface is formed not only on the insulating film between the semiconductor thin film and the insulating substrate of the SOI substrate, but also on a plurality of other insulating films provided on the semiconductor thin film Often provided through. Thus, when opening a contact hole penetrating a plurality of insulating films, the dry process alone takes a long time to open, and the capacitor insulating film and the semiconductor thin film constituting the pixel storage capacitor are damaged by the plasma. There is a risk of causing a capacity leak and a reduction in device capability.

  The present invention has been made in view of the above-described problems of the prior art, and eliminates problems such as peeling caused by the bonding interface of the SOI substrate, and has high reliability and high element performance. And a method for manufacturing the same. Another object of the present invention is to provide an active matrix substrate, an electro-optical device, and an electronic apparatus that are excellent in reliability and high performance.

And supporting lifting the substrate, a semiconductor substrate having a semiconductor layer, comprising a composite substrate formed by bonding with an insulating film provided on each of the the support substrate side of the first insulating film having a bonding interface 1 A conductive layer is provided, and a second conductive layer is provided on the semiconductor layer via a second insulating film, and the first conductive layer and the second conductive layer penetrate the first insulating film. Conductively connected through a first contact hole provided through the second insulating film, a second contact hole provided through the second insulating film, and a relay conductive layer provided between the contact holes. A semiconductor device.
According to this configuration, the conductive connection structure between the first conductive layer and the second conductive layer provided on both sides of the semiconductor layer of the composite substrate has the plurality of contact holes and the relay conductive structure provided therebetween. Since the contact holes are mounted via the layers, the aspect ratio of each contact hole can be reduced, and the contact area of the conductive film inside the contact hole is improved. As a result, the contact resistance can be reduced. In particular, since the contact hole that penetrates the insulating film having the bonding interface can be made shallow, the etching time can be shortened, and even if dry etching is used, which may cause damage to the semiconductor layer due to plasma when forming the contact hole, the semiconductor is used. The damage to the layer is small, so that a high-performance semiconductor device can be provided. In addition, since dry etching is used, the etching solution does not naturally enter the bonding interface, and there is no possibility of peeling or cracking at the bonding interface.

Before Symbol first contact hole, the second contact hole, can be configured to provided in a position overlapping in a plan view. According to this configuration, the area occupied by both the contact holes can be reduced, and when used in an electro-optical device or the like, the configuration can contribute to an improvement in the aperture ratio of the pixel.

Opening diameter of the front Stories second contact hole is preferably larger than the opening diameter of the first contact hole. According to this configuration, when the conductive connection structure between the two contact holes arranged in a plan view is formed, the contact between the second conductive layer and the relay conductive layer at the bottom of the second contact hole can be more reliably and reliably performed. You can do it.

Before Symbol a first contact hole and the second contact hole may be configured provided at different positions in plan view. According to this configuration, since the conductive connection region between the second conductive layer and the relay conductive layer at the bottom of the second contact hole is outside the region where the first contact hole is formed, the reliability of the conductive connection can be improved. it can.

Can be a thin film transistor provided in front Symbol semiconductor layer, a structure comprising a plurality of electrode wirings which is conductively connected to the thin film transistor to. According to this configuration, a semiconductor device suitable for use in an active matrix substrate including a thin film transistor as a switching element is provided.

Before SL relay conductive layer, the conductive member constituting the thin film transistor, or it is preferable that the electrode wiring and the same material. According to this configuration, the conductive connection structure between the first conductive layer and the second conductive layer can be formed in the same process as the constituent members of the transistor, and a semiconductor device that can be efficiently manufactured is provided. The

Before SL relay conductive layer is preferably an electrode wire of the same material which is connected to the gate electrode or the gate electrode of the thin film transistor. According to this configuration, the relay conductive layer can be formed in the same process together with the gate electrode and the electrode wiring provided in the upper layer or the lower layer of the semiconductor layer constituting the main component of the thin film transistor. Since the distance to one conductive layer is reduced, the first contact hole can be formed in a short time by dry etching.

Further comprising a storage capacitor which is connected in front Symbol TFT, the second conductive layer may be configured to include a capacitor lines constituting the storage capacitor. According to this configuration, it is possible to provide a semiconductor device in which the capacitor line and the first conductive layer are electrically connected.

Before Stories second conductive layer, it can be configured to extend in a planar region comprising a channel region of the thin film transistor. According to this configuration, the channel region of the thin film transistor can be planarly covered with the second conductive layer, and can function as a light shielding film.

Before Stories second conductive layer comprises a structure formed by stacking a plurality of conductive films, it is preferred that one of the plurality of conductive films has a light shielding property. With such a configuration, the second conductive layer can be configured to have both light shielding properties and excellent conductivity, and the components of the conductive film made of the light shielding material can be diffused. The advantage that it can prevent with another electrically conductive film is acquired.

A drain contact hole that penetrates the front Stories second insulating film reaches the drain region of the thin film transistor, and a capacitor electrode connected to the thin film transistor through the drain contact hole capacitor insulating provided on the capacitive electrode The capacitor line may be formed on the capacitor insulating film so as to have a region overlapping with the capacitor electrode in a plane.
According to this configuration, a semiconductor device is provided in which a storage capacitor composed of a capacitor electrode, a capacitor line, and a capacitor insulating film is formed on the second insulating film. In this configuration, since the semiconductor layer and the storage capacitor can be arranged in a planar manner, if the semiconductor device of this configuration is applied to an active matrix substrate such as an electro-optical device, the aperture ratio of the pixel can be improved. Can do.

A source contact hole that reaches the source region of the thin film transistor through the pre-Symbol second insulating film, a second relay conductive layer connected to the thin film transistor via the source contact hole, on the second conductive layer A second source contact hole extending through the third insulating film and reaching the second relay conductive layer. It can be set as the structure electrically connected with the said relay conductive layer via. According to this configuration, the source region of the semiconductor layer and the electrode wiring (data line) which are separated by interposing a plurality of insulating films are conductively connected through the plurality of contact holes, so that the aspect ratio of each contact hole The contact resistance can be reduced. Further, the contact hole can be easily downsized.

A third insulating film formed on the front Stories second conductive layer, the third and a provided signal lines on the insulating film, the signal wiring, the third said through an insulating film second A configuration may be adopted in which the second conductive layer is connected to the conductive layer through a contact hole. According to this configuration, the conductive connection between the second conductive layer and another circuit can be implemented by the signal wiring provided on the third insulating film. For example, this is a useful configuration for mounting a conductive connection structure between a capacitor line and an external constant potential source. In addition, since the electrode wiring connected to the previous source region is provided on the third insulating film, the signal wiring can be formed together with this electrode wiring, and the structure can be efficiently manufactured.

Before Symbol first conductive layer may be configured to include a light shielding film of the thin film transistor. According to this configuration, the channel region of the thin film transistor can be shielded from the support substrate side. In addition, since the first conductive layer and the second conductive layer are conductively connected, it is easy to hold the light shielding film disposed opposite to the channel region at a constant potential, so that the potential variation of the light shielding film is reduced. The operation of the thin film transistor can be prevented from being affected.
Also, the first conductive layer provided on the lower side of the semi-conductor layer (supporting substrate side) can also function as a back gate electrode of the thin film transistor. Also in this case, since an arbitrary electric signal can be supplied to the back gate electrode via the second conductive layer, the drive control thereof becomes easy.

Between the front Symbol first conductive layer and the semiconductor layer may be a configuration in which an insulating protective layer is provided. According to this configuration, it is possible to effectively prevent the component of the first conductive layer from contaminating the semiconductor layer or oxidizing the first conductive layer by an etching process or the like.

Next, in order to solve the above-described problems, the present invention includes a composite substrate in which a supporting substrate and a semiconductor substrate having a semiconductor layer are bonded to each other through respective insulating films, and the first substrate having the bonded interface. A method of manufacturing a semiconductor device comprising: a first conductive layer provided between one insulating film and the support substrate; and a second conductive layer provided on the semiconductor layer via a second insulating film. Forming a first contact hole penetrating through the first insulating film and reaching the first conductive layer; forming a relay conductive layer in a planar region including the first contact hole; and Forming a second insulating film on the layer; forming a second contact hole penetrating the second insulating film and reaching the relay conductive layer; and in a planar region including the second contact hole. Forming the second conductive layer. To provide a method of manufacturing a semiconductor device, characterized in that.
According to this configuration, when forming the conductive connection structure between the first conductive layer and the second conductive layer penetrating the plurality of insulating films, a plurality of contact holes are used, so the aspect ratio of each contact hole can be reduced, Therefore, the contact area of the conductive film in the contact hole can be improved and the contact resistance can be reduced.

In the method of manufacturing a semiconductor device according to the present invention, it is preferable that the first contact hole is formed by a dry etching process.
The manufacturing method according to the present invention is effective in that the formation time of the first contact hole penetrating the insulating film having the bonding interface can be shortened. That is, since the etching time is shortened, it is possible to suppress an increase in the number of defects in the semiconductor layer even when dry etching in which damage to the semiconductor layer due to plasma is concerned is used. In addition, since there is no need to use wet etching, there is no possibility of causing peeling or cracking due to the penetration of the etching solution into the bonding interface.

In the method for manufacturing a semiconductor device of the present invention, the step of forming the second contact hole by an etching process includes a step of partially removing the second insulating film by a wet etching process, and a recess formed by the process. On the other hand, it is preferable to further include a step of opening a contact hole reaching the relay conductive layer by performing a dry etching process.
According to this manufacturing method, when the second contact hole is formed, a combination of wet etching and dry etching is used, so that the dry etching time is shortened and the constituent members (insulating film and semiconductor) of the semiconductor device by etching plasma are used. Damage to the layer etc.). In addition, the use of dry etching improves the contact hole manufacturing accuracy.

  In the method for manufacturing a semiconductor device of the present invention, the second contact hole can be formed by dry etching. According to this manufacturing method, a process can be simplified and manufacturing efficiency can be improved. In addition, the accuracy of the contact hole can be improved.

  The method for manufacturing a semiconductor device of the present invention further includes a step of forming a thin film transistor in the semiconductor layer, and in the step of forming the relay conductive layer, the relay conductive layer, the gate electrode of the thin film transistor, and / or the gate electrode The signal wiring connected to can be formed of the same material. According to this manufacturing method, the relay conductive layer can be efficiently formed, and the simplicity and efficiency of the process can be improved.

The method of manufacturing a semiconductor device according to the present invention further includes a step of forming a thin film transistor in the semiconductor layer, and the step of forming the second insulating film and the step of forming the second contact hole A step of forming a drain contact hole penetrating the insulating film and reaching the drain region of the thin film transistor; a step of forming a capacitor electrode in a planar region including the drain contact hole; and a capacitor insulating film covering the capacitor electrode In the step of forming the second conductive layer, a capacitor line facing the capacitor electrode through the capacitor insulating film can be formed.
According to this configuration, the storage capacitor and the semiconductor layer can be arranged to overlap in a planar manner, and a semiconductor device suitable for use in an active matrix substrate such as an electro-optical device can be manufactured. In the semiconductor device, the second contact hole is provided through the capacitor insulating film and the second insulating film. However, as described above, in the present invention, the second contact hole is relatively shallow. The capacitor insulating film is not damaged by the plasma during the dry etching process. Therefore, according to this manufacturing method, it is possible to manufacture a highly reliable and relatively high performance semiconductor device with reduced capacitance leakage.

The method of manufacturing a semiconductor device according to the present invention further includes a step of forming a thin film transistor in the semiconductor layer, and a step of forming a plurality of electrode wirings electrically connected to the thin film transistor, wherein the second insulating film is formed. And a step of forming a source contact hole penetrating the second insulating film and reaching a source region of the thin film transistor between the step of forming the second contact hole and a plane including the source contact hole Forming a second relay conductive layer in the region, forming a third insulating film on the second conductive layer, and reaching the second relay conductive layer through the third insulating film A step of forming a second source contact hole and a step of forming the electrode wiring in a planar region including the second source contact hole can also be included.
According to this manufacturing method, since the conductive connection structure between the electrode wiring and the source region of the thin film transistor is performed through the plurality of contact holes and the relay conductive layer, the contact resistance can be reduced by reducing the aspect ratio of each contact hole. A reduction effect is obtained.

  In the method of manufacturing a semiconductor device of the present invention, in the step of forming the second source contact hole, in the step of forming a contact hole that penetrates the third insulating film and reaches the capacitor line, and subsequently forming the electrode wiring A signal wiring that is conductively connected to the capacitor line may be formed. According to this configuration, the signal wiring that conductively connects the capacitor line and, for example, an external constant potential source can be formed together with the electrode wiring, and the manufacturing can be efficiently performed.

Next, an active matrix substrate according to the present invention includes the semiconductor device according to the present invention described above. According to this configuration, an active matrix substrate that is excellent in reliability, excellent in driving capability of the switching element, and suitable for use in a high-definition electro-optical device is provided.
Further, according to the manufacturing method of the active matrix substrate including the manufacturing method of the semiconductor device according to the present invention, it is possible to easily and efficiently manufacture the active matrix substrate having excellent reliability and excellent driving ability of the switching element. Can do.

  Next, an electro-optical device according to the present invention includes the active matrix substrate according to the present invention described above. According to this configuration, an electro-optical device having excellent reliability, high performance, and excellent display quality is provided.

  Next, an electronic apparatus according to the invention includes the electro-optical device according to the invention described above. According to this configuration, an electronic device having an excellent reliability and a high-performance display unit is provided.

Next, an embodiment according to the present invention will be described in detail.
<Liquid crystal device>
Hereinafter, a configuration of a liquid crystal device which is an embodiment of an electro-optical device according to the present invention will be described with reference to FIGS. The liquid crystal device of this embodiment is an active matrix transmissive liquid crystal device using TFTs (Thin-Film Transistors) as switching elements. Moreover, in this embodiment, the case where TN mode is employ | adopted as a display mode is illustrated.

  FIG. 1 is an equivalent circuit diagram of switching elements, signal lines, etc. in a plurality of pixels arranged in a matrix constituting the image display region of the transmissive liquid crystal device of this embodiment, and FIG. 2 is a data line, a scanning line, and a pixel electrode. FIG. 3 is a cross-sectional view showing the structure of the transmissive liquid crystal device of the present embodiment, and is a cross-sectional view taken along line AA of FIG. It is sectional drawing which follows a line. In each figure, the scales are different for each layer and each member so that each layer and each member can be recognized in the drawing.

  In the transmissive liquid crystal device according to the present embodiment, as shown in FIG. 1, a plurality of pixels arranged in a matrix constituting an image display region includes a pixel electrode 9 and a switching element for controlling the pixel electrode 9. Each of the TFTs 30 is formed, and a data line 6 a that supplies an image signal output from the X driver (data line driving circuit) 201 to the TFT 30 is electrically connected to the source of the TFT 30. The image signals S1, S2,..., Sn written from the X driver 201 to the data line 6a are supplied line-sequentially in this order, or are supplied for each group to a plurality of adjacent data lines 6a.

  A scanning line 3a for supplying an operation signal output from the Y driver (scanning line driving circuit) 204 to the TFT 30 is electrically connected to the gate of the TFT 30, and the Y driver 204 supplies a plurality of scanning lines 3a to the gate. Scan signals G1, G2,..., Gm are applied in a line-sequential manner in a pulse manner at a predetermined timing. The pixel electrode 9 is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied via the data line 6a is turned on by turning on the TFT 30 as a switching element for a certain period. Is written at a predetermined timing.

  Image signals S1, S2,..., Sn written at a predetermined level on the liquid crystal via the pixel electrode 9 are held for a certain period with a common electrode described later. The liquid crystal modulates light by changing the orientation and order of the molecular assembly according to the applied voltage level, thereby enabling gradation display. Here, in order to prevent the held image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9 and the common electrode. The storage capacitor 70 is connected to a capacitor line 300 extending alongside the scanning line 3a. The capacitor line 300 is connected to a Y driver 204, and an arbitrary voltage or electric signal can be applied by the Y driver 204. It is configured.

Next, the planar structure of the transmissive liquid crystal device of this embodiment will be described with reference to FIG.
As shown in FIG. 2, a plurality of planar rectangular pixel electrodes 9 are arranged in a matrix on the TFT array substrate, and the data lines 6a and the scanning lines 3a are arranged along the vertical and horizontal boundaries of the pixel electrodes 9, respectively. And the capacity line 300 is extended. In this embodiment, an area where one pixel electrode 9 and a data line 6a, a scanning line 3a, a capacitor line 300, and the like arranged so as to surround the pixel electrode 9 are formed is a pixel and arranged in a matrix. In this structure, display can be performed for each pixel. A TFT 30 is formed in a region where the data line 6a and the scanning line 3a intersect.

The data line 6a is a relay conductor electrically connected to a source region, which will be described later, through a contact hole 82 in the semiconductor layer 1a (a hatched region rising to the right in the figure) made of, for example, a single crystal silicon film constituting the TFT 30. It is connected to the layer 71b through a contact hole 81. On the other hand, the pixel electrode 9 is electrically connected through a contact hole 8 to a capacitor electrode 71a of the semiconductor layer 1a that is electrically connected through a contact hole 83 to a drain region described later.
In addition, the semiconductor layer 1a and the scanning line 3a are arranged so as to cross each other so as to face each other in a channel region (a hatched region in the left upward direction in the drawing) described later of the semiconductor layer 1a. The scanning line 3a functions as a gate electrode at a portion facing the channel region. The scanning line 3a can be formed of a silicon film such as polysilicon, amorphous silicon, or a single crystal silicon film, or a polycide or silicide thereof.

The capacitor line 300 has a main line portion extending substantially linearly along the scanning line 3a, and a protruding portion that protrudes forward (upward in the drawing) along the data line 6a from a location where the main line portion intersects the data line 6a. And have.
Further, a light shielding film 11a is provided in a lattice shape in plan view along both the data line 6a and the scanning line 3a. The light shielding film 11a is formed so as to cover the TFT 30 including the channel region of the semiconductor layer 1a when viewed from the TFT array substrate side. The light shielding film 11a and the capacitor line 300 are conductively connected to each other through contact holes 91 and 92 provided in a region between two semiconductor layers 1a and 1a adjacent in the extending direction of the data line 6a. .

Next, a cross-sectional structure of the transmissive liquid crystal device of the present embodiment will be described based on FIG.
As shown in FIG. 3, the transmissive liquid crystal device of this embodiment is sandwiched between a TFT array substrate (active matrix substrate) 10, a counter substrate 20 disposed opposite thereto, and both the substrates 10 and 20. The liquid crystal layer 50 is provided. The TFT array substrate 10 is mainly composed of a substrate body (supporting substrate) 10A made of a translucent material such as quartz, the pixel electrode 9 formed on the surface of the liquid crystal layer 50, the TFT 30, and the like, and the counter substrate 20 Is mainly composed of a substrate body 20A made of a translucent material such as glass or quartz and a common electrode 21 formed on the surface of the liquid crystal layer 50 side.

  In the TFT array substrate 10, a pixel electrode 9 is provided on the surface of the substrate body 10 </ b> A on the liquid crystal layer 50 side, and a pixel switching TFT 30 that performs switching control of each pixel electrode 9 is provided at a position adjacent to each pixel electrode 9. ing. The TFT 30 has an LDD (Lightly Doped Drain) structure as shown in FIG. 3, and includes a scanning line (gate electrode) 3a and a channel region 1a ′ of the semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a. The gate insulating film 2 that insulates the scanning line 3a from the semiconductor layer 1a, the data line 6a, the low concentration source region 1b and the low concentration drain region 1c of the semiconductor layer 1a, the high concentration source region 1d and the high concentration drain of the semiconductor layer 1a. A region 1e is provided.

On the surface of the substrate main body 10A on the liquid crystal layer 50 side, light incident from the substrate main body 10A side enters the channel region 1a ′ and the low concentration source / drain regions (LDD regions) of the semiconductor layer 1a. A light shielding film 11a is provided to prevent the light from entering 1b and 1c. Between the light shielding film 11a and the TFT 30, a base insulating film (first insulating film) 12 including an insulating film 12a, a protective layer 12b, and a bonding insulating film 12c, which are sequentially stacked from the substrate body 10A side, is provided. Is provided. The base insulating film 12 functions to electrically insulate the semiconductor layer 1a constituting the TFT 30 from the light shielding film 11a, and in addition, the light shielding film 11a is oxidized in a subsequent process, or a component of the light shielding film 11a. Can be prevented from diffusing and contaminating the semiconductor layer 1a.
As described above, the TFT array substrate 10 according to the present embodiment is an active matrix substrate configured using a composite substrate (SOI substrate) in which the semiconductor layer 1a is formed on the substrate body 10A via the base insulating film 12. In addition, the bonding insulating film 12c of the base insulating film 12 is an insulating film having a bonding interface bonded by using SOI technology.

  A contact hole (first contact hole) 92 reaching the light shielding film 11 a is formed in the base insulating film 12, and the first relay conductive layer 3 b conductively connected to the light shielding film 11 a through the contact hole 92 includes: It is provided in the same layer as the semiconductor layer 1a. The first relay conductive layer 3b is made of the same material as the scanning line 3a, and can be formed in the same process as the scanning line 3a in the manufacturing process.

  A source contact hole 82 leading to the high concentration source region 1d and a drain contact hole 83 leading to the high concentration drain region 1e are opened on the substrate body 10A including the scanning line 3a and the gate insulating film 2. An interlayer insulating film 41 is formed. A capacitor electrode 71a and a second relay conductive layer 71b are formed on the first interlayer insulating film 41, and the capacitor electrode 71a is connected to the scanning line 3a and the data line 6a in the plan view shown in FIG. Are formed in a substantially L shape extending along the scanning line 3a and the data line 6a with the position where the crossing points are defined as a base point. Although not shown in FIG. 2, the relay conductive layer 71 b is formed at substantially the same position as the contact holes 81 and 82 that are arranged so as to overlap in plan view. The capacitor electrode 71a is electrically connected to the high concentration drain region 1e of the semiconductor layer 1a through the drain contact hole 83, and the second relay conductive layer 71b is connected to the high concentration source region through the source contact hole 82. It is electrically connected to 1d.

  A capacitor insulating film 75 is formed so as to cover the capacitor electrode 71a and the second relay conductive layer 71b formed on the first interlayer insulating film 41. A capacitor line 300 is formed so as to face the capacitor electrode 71a with the capacitor insulating film 75 interposed therebetween. In this embodiment, the capacitor electrode 71a as the pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9 and a part of the capacitor line 300 as the fixed potential side capacitor electrode are capacitively insulated. The storage capacitor 70 is formed by being opposed to each other via the film 75. The capacitor electrode 71a as the pixel potential side capacitor electrode is made of a doped polysilicon film having conductivity. The capacitor line 300 as a fixed potential side capacitor electrode includes a doped polysilicon film having conductivity, a first film 72 made of an amorphous or single crystal silicon film, a metal silicide film containing a refractory metal, etc. The second film 73 is made of a multilayer film formed by laminating.

The capacitor line 300 is provided in the tip region of the protrusion shown in FIG. 2 and is connected to the first through a contact hole (second contact hole) 91 that penetrates the capacitor insulating film 75 and the first interlayer insulating film 41. One relay conductive layer 3b is connected. That is, the capacitor line 300, the first relay conductive layer 3b, and the light shielding film 11a are conductively connected through the contact holes 91 and 92.
As described above, in the liquid crystal device of the present embodiment, the conductive connection structure between the conductive layers (the light shielding film 11a and the capacitor line 300) disposed on both sides of the semiconductor layer 1a is provided between the plurality of contact holes. In addition, high reliability can be obtained by using the intermediate conductive layer. That is, since the contact holes penetrating the plurality of insulating films 12 and 41 are formed in a plurality of stages, each contact hole can be shallowed (the aspect ratio is reduced). Thereby, the surroundings of the conductive film (capacitor line 300 and relay conductive layer 3b) embedded therein can be improved, and the contact resistance can be reduced.

  In particular, reducing the aspect ratio of the contact hole 92 penetrating the base insulating film 12 having the bonding interface of the SOI substrate in the film is effective in improving the reliability and manufacturing yield of the liquid crystal device. When this type of contact hole is formed, a dry etching process or a wet etching process can be selected. However, in the wet etching process, the etchant enters the bonded interface of the composite substrate, and the interface is peeled off or cracked. On the other hand, in the dry etching process, there is a concern that the semiconductor layer 1a may be damaged by plasma. In contrast, in the liquid crystal device of this embodiment, the aspect ratio of the contact hole 92 that penetrates the base insulating film 12 is small, so that the etching process time can be shortened, and even when dry etching process is used, The semiconductor layer 1a can be prevented from being damaged by the etching plasma. And since the wet etching process which penetrates a bonding interface is not performed, peeling and a crack of a bonding interface by an etching liquid do not occur naturally.

The storage capacitor 70 also functions as a second light shielding film in the present liquid crystal device. That is, the capacitor electrode 71 a made of a doped polysilicon film has a higher light absorption than the second film 73 of the capacitor line 300, and serves as a light absorption layer disposed between the second film 73 and the TFT 30. It has a function. Further, the capacitor line 300 functions as a light shielding film by itself, and the first film 72 made of a polysilicon film or the like has a function as a light absorption layer disposed between the second film 73 and the TFT 30, and has a high function. The second film 73 made of a metal silicide film containing a melting point metal or the like functions as a light shielding layer that shields the TFT 30 from light incident from the upper side of the TFT 30 in the figure. That is, the light incident from the opposite substrate body 20A side is shielded by the second film 73, and the light entering between the second film 73 and the TFT 30 is effectively absorbed by the capacitor electrode 71a and the first film 72. It has come to be.
In the capacitor line 300 having the above laminated structure, since the first film 72 is made of a conductive polysilicon film, the second film 73 functioning as a light-shielding film is not a conductive material. However, if the second film 73 is made of a conductive material, the resistance of the capacitor line 300 can be further reduced.

In the liquid crystal device of this embodiment, the light shielding film 11a functioning as the light shielding film of the TFT 30 and the second film 73 of the capacitor line 300 are, for example, refractory metals such as Cr, Ti, W, Ta, Mo, Pb, or the like. It is preferable to use a metal silicide, a polysilicide containing these metals, or a laminate of these, or a structure made of Al or the like.
The capacitor insulating film 75 constituting the storage capacitor 70 interposed between the capacitor electrode 71a and the capacitor line 300 is a silicon oxide film such as a relatively thin HTO film or LTO film having a film thickness of about 5 to 200 nm, for example. , A silicon nitride film, a nitrided oxide film, and a laminated film thereof. From the viewpoint of increasing the storage capacity, it is better that the capacitor insulating film 75 is thinner as long as the reliability of the film is sufficiently obtained.

  The first film 72 that not only functions as a light absorption layer but also constitutes a part of the capacitor line 300 is made of, for example, a polysilicon film having a film thickness of 50 to 150 nm or an amorphous or single crystal silicon film, and is a light shielding film. The second film 73 that not only functions as a part of the capacitor line 300 but also includes, for example, a tungsten silicide film having a thickness of about 150 nm. Further, the capacitor electrode 71 a is composed of a polysilicon film similar to the first film 72. As described above, the first film 72 and the capacitor electrode 71a disposed on the side in contact with the capacitor insulating film 75 are made of the polysilicon film, thereby preventing the capacitor insulating film 75 from being deteriorated and improving the reliability of the liquid crystal device. Can be made. If a storage capacitor is formed, if the capacitor insulating film 75 and the metal silicide film are in contact with each other, the metal component contained in the metal silicide film is diffused into the capacitor insulating film 75, so that the insulating property of the capacitor insulating film 75 is increased. May deteriorate.

  On the capacitor insulating film 75 and the substrate body 10A including the capacitor line 300, the pixel contact hole 8 leading to the capacitor electrode 71a, the second source contact hole 81 leading to the second relay conductive layer 71b, and the capacitor line 300 are formed. A third interlayer insulating film 42 having a contact hole 91 leading to it is formed. On the third interlayer insulating film 42, data lines 6a extending in a direction perpendicular to the scanning lines 3a and signal wirings 6b are formed. The data line 6a is electrically connected to the second relay conductive layer 71b via the second source contact hole 81, and is electrically connected to the high concentration source region 1d of the semiconductor layer 1a via the second relay conductive layer 71b. It is connected.

  The capacitor line 300 extends in a plan view from the image display region in which the pixel electrode 9 is disposed, and is connected to the signal line 6b through a contact hole 91 provided through the second interlayer insulating film 42. And conductively connected. The signal wiring 6b is actually electrically connected to the constant potential source of the Y driver 204 disposed outside the image display area, and holds the capacitor line 300 at an arbitrary potential. . In the present embodiment, since the capacitor line 300 and the light shielding film 11a are conductively connected via the contact holes 91 and 92 and the first relay conductive layer 3b, the capacitor line 300 can be held at a constant potential similarly to the capacitor line 300. Thus, it is possible to avoid the potential fluctuation from adversely affecting the TFT 30.

  As a constant potential source conductively connected to the capacitor line 300 (and the light shielding film 11a), not only the Y driver (scanning line driving circuit) 204 for supplying the scanning signal of the TFT 30 to the scanning line 3a but also the image signal as data. A constant potential source such as a positive power source or a negative power source supplied to an X driver (data line driving circuit) 201 that controls a sampling circuit to be supplied to the line 6a can also be used. Further, a constant potential source that supplies a constant potential to the electrode 21 of the counter substrate 20 may be used.

  A third interlayer insulating film 43 having a pixel contact hole 8 leading to the capacitor electrode 71a is formed on the second interlayer insulating film 42 and the substrate body 10A including the data line 6a. That is, the pixel contact hole 8 is a contact hole that passes through the third interlayer insulating film 43 and the second interlayer insulating film 42 and reaches the capacitor electrode 71a. On the third interlayer insulating film 43, the pixel electrode 9 that is conductively connected to the capacitor electrode 71 a through the pixel contact hole 8 is formed. With this conductive connection structure, the pixel electrode 9 is electrically connected to the high-concentration drain region 1e of the semiconductor layer 1a through the capacitance electrode 71a. In addition, the pixel electrode 9 is formed in a rectangular shape in a region including the image display region as shown in FIG.

  As described above, the capacitor electrode 71a functions as a pixel potential side capacitor electrode of the storage capacitor 70 and a function as a light absorption layer, and also functions to relay electrical connection between the pixel electrode 9 and the high concentration drain region 1e. have. By providing such a capacitor electrode 71a, even when the interlayer distance is as long as 1000 to 2000 nm, for example, a series of relatively small diameters is avoided while avoiding the technical difficulty of connecting the two with a single contact hole. The contact holes can be satisfactorily connected to each other, and the pixel aperture ratio can be improved by reducing the contact hole diameter. Moreover, since the opening depth is relatively small even when the contact hole is opened, there is an effect that penetration during etching hardly occurs.

  An alignment film for regulating the alignment of the liquid crystal molecules in the liquid crystal layer 50 when no voltage is applied on the outermost surface of the TFT array substrate 10 on the liquid crystal layer 50 side, that is, on the third interlayer insulating film 43 including the pixel electrode 9. 16 is formed. A polarizer 17 is provided on the surface of the TFT array substrate 10 opposite to the liquid crystal layer 50.

  On the other hand, in the counter substrate 20, a common electrode 21 made of indium tin oxide (ITO) or the like is formed over the entire surface of the substrate body 20 </ b> A on the liquid crystal layer 50 side. An alignment film 22 for regulating the alignment of liquid crystal molecules in the liquid crystal layer 50 when no voltage is applied is formed. A polarizer 24 is also provided on the surface of the counter substrate 20 opposite to the liquid crystal layer 50.

  The surface of the TFT array substrate 10 on the side of the liquid crystal layer 50 of the substrate body 10A can be provided with grooves in a plan view. Wiring and elements such as the scanning lines 3a, the data lines 6a, and the TFTs 30 are provided in these grooves. By forming the step, it is possible to alleviate the formation of a step between a region where a wiring or an element is formed and a region where these are not formed. There is an advantage that defects and the like can be prevented.

<Method for manufacturing active matrix substrate>
Hereinafter, a method for manufacturing an active matrix substrate including a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. In the present embodiment, a process of manufacturing the TFT array substrate (active matrix substrate) 10 provided in the liquid crystal device of the previous embodiment will be described in detail with reference to cross-sectional process diagrams shown in FIGS.

First, as shown in FIG. 4A, a substrate body 10A made of glass, quartz or the like is prepared. The substrate body 10A is preferably annealed at a temperature equal to or higher than the heating temperature in the subsequent steps. Specifically, annealing is preferably performed by heating to about 850 ° C. to 1300 ° C. in an inert gas atmosphere such as N ₂ . By performing the annealing process, it is possible to reduce the distortion of the substrate that occurs when the substrate main body 10A is subjected to a high-temperature process in a subsequent process.

  Next, a single metal, alloy, metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pb is sputtered on the entire surface of the substrate body 10A thus treated. For example, the film is deposited to a thickness of 150 to 200 nm by a CVD method, an electron beam heating vapor deposition method, or the like. Thereafter, a light shielding film (first conductive layer) 11a is formed by patterning in a predetermined planar shape using a known photolithography technique.

  Next, as shown in FIG. 4B, a lower-layer-side insulating film 12a, a protective layer 12b, and a lower-layer-side insulating film are formed on the surface of the substrate body 10A on which the light-shielding film 11a is formed by sputtering, CVD, or the like. An upper-layer insulating film 12c3 having a two-layer structure including the film 12c1 and the upper-layer insulating film 12c2 is formed. At this time, a convex portion that follows the light shielding film 11a is formed on the surface of the upper insulating film 12c3 on the region where the light shielding film 11a is formed. In addition, by providing the protective layer 12b, diffusion of the metal material constituting the light shielding film 11a and diffusion of impurities from the substrate body 10A can be suppressed, and the reliability of the semiconductor device can be improved.

  As a constituent material of the insulating films 12a, 12c1, and 12c2, high insulation such as silicon oxide, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), and BPSG (boron phosphorus silicate glass) are used. Examples thereof include glass. The lower insulating film 12a has a thickness of about 50 nm, and the insulating films 12c1 and 12c2 constituting the upper insulating film 12c3 both have a thickness of about 800 nm. As the protective layer 12b, for example, a silicon nitride film having a thickness of about 10 nm to 50 nm, preferably 15 nm can be used, and can be formed by a low pressure CVD method or a plasma CVD method using dichlorosilane and ammonia.

  Next, as shown in FIG. 4C, the surface of the upper insulating film 12c3 is polished using a method such as a CMP (Chemical Mechanical Polishing) method to remove the convex portion that follows the light shielding film 11a. To flatten the surface. The thickness of the upper insulating film 12c3 after the planarization is about 120 nm in the formation region of the light shielding film 11a.

Next, as shown in FIG. 4D, the substrate body 10A that has undergone the above-described steps is bonded to a separately prepared single crystal silicon substrate. As the single crystal silicon substrate used for bonding, a single crystal silicon substrate having a thickness of, for example, about 600 μm composed of the single crystal silicon layer 1 and the oxide film 12c4 formed on one surface thereof is used. For example, hydrogen ions are implanted into the single crystal silicon layer 1 at an acceleration voltage of 100 keV and a dose of 10 × 10 ¹⁶ / cm ² . The oxide film 12c4 can be formed by oxidizing the single crystal silicon layer of the single crystal silicon substrate 1 by about 50 nm to 800 nm. For the bonding step, a method of directly bonding two substrates can be adopted by performing heat treatment at about 300 ° C. to 350 ° C. for 2 hours in a state where the single crystal silicon substrate and the substrate body 10A are in contact with each other. By this bonding step, a bonding insulating film 12c having a bonding interface s is formed between the single crystal silicon layer (semiconductor layer) and the protective layer 12b.

  In order to further increase the bonding strength, a method of raising the heat treatment temperature to about 450 ° C. can be applied. However, the thermal expansion coefficient of the substrate body 10A made of quartz or the like and the thermal expansion coefficient of the single crystal silicon substrate 1 are Since there is a large difference between them, if the heating is continued as it is, defects such as cracks are generated in the single crystal silicon layer, and the quality of the manufactured TFT array substrate 10 may be deteriorated. In order to suppress the occurrence of such defects such as cracks, the single crystal silicon substrate 1 once subjected to heat treatment for bonding at 300 ° C. is thinned to about 100 to 150 μm by wet etching or CMP, Thereafter, it is desirable to perform heat treatment at a higher temperature. For example, etching is performed using a KOH aqueous solution at 80 ° C. so that the thickness of the single crystal silicon substrate 1 becomes 150 μm, and then bonding is performed with the substrate body 10A, followed by heat treatment again at 450 ° C. It is desirable to increase the bonding strength.

  Next, the bonded single crystal silicon layer 1 is partially peeled off. This separation of the single crystal silicon layer utilizes an action in which silicon bonds are separated in the vicinity of the surface of the single crystal silicon layer 1 on the side of the bonded insulating film 12c by hydrogen ions introduced into the single crystal silicon layer 1. To do. The heat treatment here can be performed, for example, by heating the two bonded substrates to 600 ° C. at a rate of temperature increase of 20 ° C. per minute. By this heat treatment, the bonded single crystal silicon layer 1 is partially separated from the substrate body 10A, and a single crystal silicon layer of about 200 nm ± 5 nm is obtained on the surface of the substrate body 10A. About the film thickness of the single crystal silicon layer 1 after peeling, it can adjust arbitrarily in the range of 10 nm-3000 nm, for example by changing the acceleration voltage of the hydrogen ion implantation performed with respect to the single crystal silicon substrate mentioned above.

  In addition to the method described here, the thinned single crystal silicon layer 1 is polished by a PACE (Plasma Assisted Chemical Etching) method after polishing the surface of the single crystal silicon substrate to a thickness of 3 to 5 μm. An ELTRAN (Epitaxial Layer) that transfers the film onto the bonded substrate by selective etching of the porous silicon layer by etching the film to a thickness of about 0.05 to 0.8 μm. It can also be obtained by the Transfer method.

  Furthermore, in order to improve the adhesion between the bonding insulating film 12c and the single crystal silicon layer 1 and increase the bonding strength, the substrate body 10A and the single crystal silicon layer 1 are bonded together, and then a rapid thermal processing method ( It is desirable to perform a heat treatment such as RTA). The heating temperature at that time is preferably 600 ° C. to 1200 ° C., preferably 1050 ° C. to 1200 ° C. in order to lower the viscosity of the insulating film and increase the atomic adhesion.

Next, as shown in FIG. 4E, a semiconductor layer 1a having a predetermined pattern is formed with a film thickness of, for example, 50 nm by a mesa-type separation method using a photolithography process, an etching process, or the like. For the element isolation step, a well-known LOCOS isolation method or trench isolation method can also be used. Further, when the X driver 201 and the Y driver 204 shown in FIG. 1 are mounted on the TFT array substrate 10, a semiconductor layer of a switching element used for these driver circuits may be formed together with the semiconductor layer 1a. Further, a semiconductor layer for a driver circuit having a layer thickness (for example, about 200 nm) different from that of the semiconductor layer 1a can be formed.
Thereafter, the semiconductor layer 1a is thermally oxidized at a temperature of about 750 to 1050 ° C. to form a thermal oxide film (gate insulating film) 2 having a thickness of about 5 to 50 nm. As the thermal oxidation method here, dry thermal oxidation treatment or wet thermal oxidation treatment is appropriately selected and used according to the thickness of the thermal oxide film 2 to be specifically formed as described above.

  In the above description, the gate oxide film 2 is made of only a thermal oxide film. However, the gate oxide film 2 is formed by forming a thermal oxide film and then using a vapor phase synthesis method such as atmospheric pressure or reduced pressure CVD method, vapor deposition. By a method or the like, a laminated structure with a vapor phase synthetic insulating film in which silicon oxide, silicon nitride, or silicon oxynitride is formed can also be formed. By forming the vapor phase synthetic insulating film on the thermal oxide film in this way, it is possible to effectively prevent the insulating film from being thinned at the upper corner of the semiconductor layer 1a, and to improve the breakdown voltage of the gate insulating film 2. Can do. The vapor phase synthetic insulating film may be formed as a single layer or may be a laminated film including a plurality of films selected from the insulating materials. The thickness of the vapor-phase synthetic insulating film is preferably 10 nm or more in order to obtain an insulating film with good film quality. In addition, after the formation of the vapor phase synthetic insulating film, it is preferable to perform annealing by heating to about 900 to 1050 ° C. in an inert gas atmosphere such as nitrogen or argon.

When the gate insulating film 2 is formed, ion implantation is performed on the semiconductor layer 1a. In this embodiment, a case where an N-channel thin film transistor is formed as the TFT 30 will be described, but the TFT 30 may be a P-channel transistor.
In order to form an N-channel TFT 30 for pixel switching, first, a dopant of a group III element such as boron is applied to the semiconductor layer 1a at a low concentration (for example, an acceleration voltage of 35 keV and a dose of about 1 × 10 ¹² / cm ² ). Dope. Thereafter, in a state where the semiconductor layer 1a and the gate insulating film 2 are coated with a photoresist, a group III element such as boron is doped at a dose 1 to 10 times that of the previous step. In the case of forming a P-channel TFT, a dopant of a group V element such as phosphorus may be used instead of the group III element dopant.

  Next, as shown in FIG. 4F, a contact hole (first contact hole) 92 that passes through the lower insulating film 12a, the protective layer 12b, and the bonded insulating film 12c and reaches the light shielding layer 11a is made reactive. It is formed by dry etching such as etching or reactive ion beam etching. At this time, since the contact hole 13 and the like are opened by anisotropic etching such as reactive etching and reactive ion beam etching, the bonded insulating film 12c is formed as in the case of forming the contact hole 92 by wet etching. The occurrence of cracks and peeling due to the etching solution entering the bonding interface s existing therein is prevented. Then, since the contact hole 92 is formed in the lower insulating layer 12a, the protective layer 12b, and the bonded insulating film 12c (total film thickness of about 350 to 400 nm) having a relatively thin layer thickness, The gate insulating film 2 and the semiconductor layer 1a are not damaged. Further, there is an advantage that the aperture shape can be made substantially the same as the mask shape.

  Next, as shown in FIG. 5G, a doped polysilicon film 3 into which phosphorus ions are introduced simultaneously with film formation is formed. Alternatively, a film obtained by depositing a polysilicon film with a thickness of about 350 nm by a low pressure CVD method or the like and then thermally diffusing phosphorus (P) to make the polysilicon film conductive can be used. Further, a single metal, an alloy, a metal silicide, or the like containing at least one of Ti, W, Co, and Mo is formed on the doped polysilicon film 3 by a sputtering method, a CVD method, an electron beam heating evaporation method, or the like. For example, it is good also as a layered structure deposited in the film thickness of 150-200 nm. By employing such a layer structure, the conductivity of the layer including the doped polysilicon film can be improved.

Next, as shown in FIG. 5H, the scanning lines 3a having the predetermined pattern shown in FIGS. 2 and 3, the first relay conductive layer 3b, and the like are formed by a photolithography process, an etching process, and the like using a resist mask. Form.
Thereafter, in order to form an N-channel LDD region in the semiconductor layer 1a, a dopant of a group V element such as phosphorus is first doped at a low concentration using the scanning line 3a as a mask. Specifically, P ions are doped at an acceleration voltage of 70 keV and a dose of 6 × 10 ¹² / cm ² to form the low concentration source region 1b and the low concentration drain region 1c shown in FIG. Subsequently, in order to form the N-channel high concentration source region 1d and the high concentration drain region 1e in the semiconductor layer 1a, a resist layer is formed on the scanning line 3a with a mask wider than the scanning line 3a. Similarly, a dopant of a group V element such as phosphorus is doped at a high concentration (for example, P ions are applied at an acceleration voltage of 70 keV and a dose of 4 × 10 ¹⁵ / cm ² ).
When a P-channel TFT is formed, a group III element dopant such as boron is used instead of the group V element dopant. In the drawings referred to below, the low concentration source region 1b, the high concentration source region 1d, the low concentration drain region 1c, and the high concentration drain region 1e are omitted as appropriate.

  Next, as shown in FIG. 5I, a silicate glass film such as NSG, PSG, BSG, BPSG, or the like is nitrided by, for example, atmospheric pressure or reduced pressure CVD so as to cover the scanning line 3a and the first relay conductive layer 3b. A first interlayer insulating film (second insulating film) 41 made of a silicon film, a silicon oxide film, or the like is formed. The film thickness of the first interlayer insulating film 41 is preferably about 500 to 1500 nm, and more preferably 800 nm. Thereafter, in order to activate the high concentration source region 1d and the high concentration drain region 1e, an annealing process at about 850 ° C. is performed for about 20 minutes.

  Next, as shown in FIG. 5J, the source contact hole 82 and the drain contact hole 83 that reach the semiconductor layer 1a through the first interlayer insulating film 41 are formed by reactive etching, reactive ion beam etching, or the like. It is formed by dry etching or wet etching.

Next, as shown in FIG. 5K, a doped silicon film 71 is formed on the first interlayer insulating film 41 by introducing P ions simultaneously with the formation of the polysilicon film. Alternatively, a polysilicon film may be deposited with a thickness of about 350 nm by a low pressure CVD method or the like, and then phosphorus (P) may be thermally diffused to make the polysilicon film conductive.
Thereafter, as shown in FIG. 6L, the doped polysilicon film 71 is patterned by a photolithography process, an etching process, or the like to form a capacitor electrode 71a and a second relay conductive layer 71b. Thereafter, a silicon oxide, silicon nitride, or silicon oxynitride film is formed by a vapor phase synthesis method such as atmospheric pressure or low pressure CVD method, vapor deposition method, etc., so that the first interlayer insulating film 41 and the capacitor electrode 71a are formed. And a capacitor insulating film 75 covering the second relay conductive layer 71b.

  Next, as shown in FIG. 6M, the first interlayer insulating film 41 on the first relay conductive layer 3b is partially etched by wet etching in a state where a mask (not shown) having a predetermined shape is formed with a photoresist or the like. The recess 91a is formed by removing the target. Then, in a subsequent step shown in FIG. 6N, a contact hole reaching the first relay conductive layer 3b through the first interlayer insulating film 41 by dry etching the planar region corresponding to the recess 91a. (Second contact hole) 91 is formed.

  Thereafter, as shown in FIG. 6O, a laminated film of a first film 72 made of a doped polysilicon film or a single crystal silicon film and a second film 73 made of a metal silicide film containing a refractory metal or the like is formed. The capacitor line 300 having a predetermined planar shape shown in FIG. 2 is formed by forming a film and patterning it by a photolithography process and an etching process. Since the capacitor line 300 is connected to the Y driver 204 as shown in FIG. 1, it extends to the outside of the image display area in the left-right direction of FIG.

  Next, as shown in FIG. 7 (P), NSG, PSG, BSG, and the like are used to cover the capacitor line 300 and the first interlayer insulating film 41 by using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas. A second interlayer insulating film 42 made of a silicate glass film such as BPSG, a nitride semiconductor film, an oxide semiconductor film, or the like is formed. The film thickness of the second interlayer insulating film 42 is preferably about 500 to 1500 nm, more preferably about 800 nm.

Subsequently, a second source contact hole 81 that penetrates the second interlayer insulating film 42 and reaches the second relay conductive layer 71b is formed, and a low-resistance metal such as light-shielding Al, metal silicide, or the like is formed by sputtering or the like. Then, after depositing to a thickness of about 100 to 700 nm, preferably about 350 nm, the data line 6a is formed by patterning by a photolithography process, an etching process or the like.
Further, when the second source contact hole 81 is opened, a contact hole 93 reaching the capacitor line 300 extending outside the image display region is simultaneously formed. In the formation region of the contact hole 93, a signal wiring 6b for conductively connecting the capacitor line 300 and the Y driver 204 shown in FIG. 1 is formed together with the data line 6a in the subsequent formation process of the data line 6a. .

Next, as shown in FIG. 7Q, the NSG is formed using, for example, atmospheric pressure or reduced pressure CVD method, TEOS gas, or the like so as to cover the data line 6a, the signal wiring 6b, and the second interlayer insulating film. A third interlayer insulating film 43 made of a silicate glass film such as PSG, BSG, or BPSG, a nitride semiconductor film, an oxide semiconductor film, or the like is formed. The thickness of the third interlayer insulating film 43 is preferably about 500 to 1500 nm, and more preferably 800 nm.
Next, in the TFT 30, in order to electrically connect the pixel electrode 9 and the capacitor electrode 71a, the pixel contact hole 8 penetrating the second interlayer insulating film 42 and the third interlayer insulating film 43 is subjected to reactive etching and reaction. It is formed by dry etching such as reactive ion beam etching.

Then, after depositing a transparent conductive thin film 9 such as ITO on the third interlayer insulating film 43 to a thickness of about 50 to 200 nm by sputtering or the like, patterning is performed by a photolithography process, an etching process, etc. The pixel electrode 9 having a rectangular shape in plan view shown in FIG. 2 is formed. Note that when the electro-optical device of the present embodiment is a reflective electro-optical device, the pixel electrode 9 may be formed from an opaque material having a high reflectance such as Al.
After that, if the alignment film 16 made of polyimide or the like is applied and formed so as to cover the pixel electrode 9 and the third interlayer insulating film 43, the TFT array substrate 10 provided in the liquid crystal device of the previous embodiment is obtained.

In the manufacturing method of the present embodiment including the above-described steps, a contact hole for conductively connecting the relay conductive layer 3b and the light shielding film 11a in order to conductively connect the light shielding film 11a and the capacitor line 300 via the relay conductive layer 3b. 92 is formed only by a dry etching process, and a contact hole 91 for conductively connecting the first relay conductive layer 3b and the capacitor line 300 is formed by a combination of a wet etching process and a dry etching process.
That is, as shown in FIG. 5F, since the contact hole 92 penetrating the bonded insulating film 12c having the bonded interface s is formed only by dry etching processing, there is a problem when using wet etching processing. Thus, the etching solution does not enter the bonding interface s, so that peeling or cracking at the bonding interface s does not occur. Further, since the contact hole 91 has a small aspect ratio and is shallow, the time during which the substrate is exposed to the plasma of the dry etching process can be shortened. Therefore, damage to the semiconductor layer 1a due to the plasma is reduced, and excellent device capability is achieved. It is possible to form the TFT 30 having the above.

  Then, by partially forming the contact hole 91 by wet etching, it is possible to reduce the time during which the capacitor insulating film 75 is exposed to the plasma of the dry etching process. Damage can be reduced and capacity leakage can be effectively prevented. Therefore, according to this manufacturing method, a highly reliable and high performance TFT array substrate 10 can be obtained.

  Further, since the light shielding film 11a and the capacitor line 300 are conductively connected by the relatively shallow contact holes 91 and 92 via the relay conductive layer 3b, the relay conductive layer 3b and the capacitor on the inner wall surface of each contact hole 91 and 92 are connected. The area around the line 300 is improved, and the contact resistance can be reduced. Furthermore, as shown in FIGS. 5G and 5H, the first relay conductive layer 3b that relays between the capacitor line 300 and the light shielding film 11a is formed together with the scan line 3a in the process of forming the scan line 3a. Therefore, efficient production is possible.

<Other forms of liquid crystal device>
Hereinafter, another embodiment of the liquid crystal device according to the present invention will be described with reference to FIG. The liquid crystal device according to this embodiment whose cross-sectional structure is shown in FIG. 8 has the same basic configuration as the liquid crystal device of the previous embodiment shown in FIGS. 9 and a conductive connection structure between the capacitor electrode 71a and a conductive connection structure between the capacitor line 300 and the light shielding film 11a. Hereinafter, only these two conductive connection structures will be described in detail, and the same components as those in FIGS. 1 to 3 are denoted by the same reference numerals and description thereof is omitted.

As shown in FIG. 8, in the liquid crystal device of this embodiment, the conductive connection structure between the pixel electrode 9 and the capacitor electrode 71a has a contact hole 84 that penetrates the second interlayer insulating film 42 and reaches the capacitor electrode 71a. A third relay conductive layer 6c formed in a planar region including the contact hole 84 and a contact hole 83 that penetrates the third interlayer insulating film 43 and reaches the third relay conductive layer 6c. The third relay conductive layer 6c is formed in the same layer as the data line 6a and the signal wiring 6b, and can be formed together with these components in the same process (process (P) shown in FIG. 7).
Since the pixel electrode 9 and the capacitor electrode 71a are thus connected via the relay conductive layer 6c, the aspect ratio of each contact hole 83, 84 is larger than that of the pixel contact hole 8 shown in FIG. The ratio can be reduced, and the contact of the conductive film on the inner wall surface and the bottom surface becomes good. As a result, the contact resistance in the conductive connection structure can be reduced.

Furthermore, in the case of this embodiment, it has a stack type structure in which the contact holes 83 and 84 are provided at positions where they overlap in a plan view, and the area occupied by the contact holes 83 and 84 is reduced. Therefore, such a configuration contributes to an improvement in the aperture ratio of the pixel and is suitable for a high-definition liquid crystal device.
Further, the conductive connection structure can be formed in almost the same manufacturing process as the liquid crystal device of the previous embodiment. Compared with the liquid crystal device of the previous embodiment, a contact hole 84 and a relay conductive layer 6c are newly added. The contact hole 84 is different from the contact hole 81 connecting the relay conductive layer 71b and the data line 6a. Since the relay conductive layer 6c can be formed in the same process as the data line 6a, a conductive connection structure having a low contact resistance can be formed without increasing the number of steps.

  Next, a conductive connection structure between the capacitor line 300 and the light shielding film 11a will be described. In the present embodiment, the contact holes 91 and 92 that conductively connect the capacitor line 300 and the light shielding film 11a are of a stacked type provided at positions where they overlap in a plan view. With such a configuration, the area occupied by the contact holes 91 and 92 provided in the peripheral region of the pixel electrode 9 can be reduced, thereby contributing to the improvement of the pixel aperture ratio.

<Electronic equipment>
An example of an electronic device including a liquid crystal panel obtained by the manufacturing method of the embodiment will be described.
FIG. 9 is a perspective view showing an example of a mobile phone as another example of an electronic apparatus using the electro-optical device (liquid crystal device) of the embodiment. In FIG. 9, a mobile phone 1300 includes a display unit 1301 including the liquid crystal device of the above embodiment, an operation unit 1302, a receiver 1303, and a transmitter 1304. The electronic apparatus (mobile phone) shown in FIG. 9 includes the liquid crystal device according to each of the embodiments described above, and therefore includes a display unit that has high reliability and high performance display quality. It has become.

In addition to the mobile phone, the electronic device of the present invention includes, for example, a projector (projection type display device), a wristwatch type electronic device having a liquid crystal display unit using the liquid crystal display device, a word processor, a personal computer, etc. The present invention can also be applied to other portable information processing apparatuses.
It should be noted that the technical scope of the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

FIG. 1 is an equivalent circuit diagram of a liquid crystal device according to an embodiment. FIG. 2 is a plan view of the pixel area. FIG. 3 is a cross-sectional configuration diagram taken along the line A-A ′ of FIG. 2. FIG. 4 is a cross-sectional manufacturing process diagram of the TFT array substrate. FIG. 5 is a cross-sectional manufacturing process diagram of the TFT array substrate. FIG. 6 is a cross-sectional manufacturing process diagram of the TFT array substrate. FIG. 7 is a cross-sectional manufacturing process diagram of the TFT array substrate. FIG. 8 is a cross-sectional configuration diagram illustrating another embodiment of the liquid crystal device. FIG. 9 is a perspective configuration diagram illustrating one embodiment of an electronic apparatus.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... TFT array substrate (active matrix substrate), 20 ... Counter substrate, 10A, 20A ... Substrate body (support substrate), 1a ... Semiconductor layer, 3b ... First relay conductive layer, 16, 22 ... Alignment film, 11a ... Light shielding Membrane (first conductive layer), 70 ... Storage capacitor, 71a ... Capacitive electrode, 71b ... Second relay conductive layer, 300 ... Capacitor line, 72 ... First film (capacitor line), 73 ... Second film (capacitor line) , 9 ... Pixel electrode, 21 ... Common electrode, 6a ... Data line, 3a ... Scan line, 12 ... Underlying insulating film (first insulating film), 12c ... Bonding insulating film, 41 ... First interlayer insulating film (second Insulating film), 42 ... Second interlayer insulating film (third insulating film), 43 ... Third interlayer insulating film, 30 ... TFT, 50 ... Liquid crystal layer

Claims (7)

A composite substrate in which a supporting substrate and a semiconductor substrate having a semiconductor layer are bonded to each other through respective insulating films, and a first insulating film provided between the first insulating film having the bonding interface and the supporting substrate is provided. A method for manufacturing a semiconductor device, comprising: a conductive layer; and a second conductive layer provided on the semiconductor layer via a second insulating film,
Forming a first contact hole penetrating through the first insulating film and reaching the first conductive layer by a dry etching process ;
Forming a relay conductive layer in a planar region including the first contact hole;
Forming the second insulating film on the relay conductive layer;
Forming a second contact hole penetrating the second insulating film and reaching the relay conductive layer;
Forming the second conductive layer in a planar region including the second contact hole. A method for manufacturing a semiconductor device, comprising: Forming the second contact hole by an etching process;
A step of partially removing the second insulating film by a wet etching process, and a contact hole reaching the relay conductive layer is formed by further performing a dry etching process on the recess formed in the process. The method for manufacturing a semiconductor device according to claim 1 , further comprising a step. The method of manufacturing a semiconductor device according to claim 2 , wherein the second contact hole is formed by a dry etching process. Further comprising forming a thin film transistor in the semiconductor layer;
In the step of forming the relay conductive layer, according to claim 1, characterized in that forming said relay conductive layer, and the signal line connected to the gate electrode and / or the gate electrode of the thin film transistor, the at same material 4. A method for manufacturing a semiconductor device according to any one of items 1 to 3 . Further comprising forming a thin film transistor in the semiconductor layer;
Between the step of forming the second insulating film and the step of forming the second contact hole,
Forming a drain contact hole penetrating through the second insulating film and reaching a drain region of the thin film transistor;
Forming a capacitive electrode in a planar region including the drain contact hole;
Forming a capacitive insulating film covering the capacitive electrode,
5. The semiconductor device according to claim 1 , wherein in the step of forming the second conductive layer, a capacitor line is formed to face the capacitor electrode with the capacitor insulating film interposed therebetween. Production method. Forming a thin film transistor in the semiconductor layer; and forming a plurality of electrode wirings conductively connected to the thin film transistor;
Between the step of forming the second insulating film and the step of forming the second contact hole,
Forming a source contact hole penetrating the second insulating film and reaching a source region of the thin film transistor;
Forming a second relay conductive layer in a planar region including the source contact hole,
Forming a third insulating film on the second conductive layer;
Forming a second source contact hole penetrating the third insulating film and reaching the second relay conductive layer;
5. The method of manufacturing a semiconductor device according to claim 1 , further comprising: forming the electrode wiring in a planar region including the second source contact hole. In the step of forming the second source contact hole, a contact hole penetrating the third insulating film to reach the capacitor line is formed, and in the subsequent step of forming the electrode wiring, a signal conductively connected to the capacitor line 7. The method of manufacturing a semiconductor device according to claim 6 , wherein wiring is formed.

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