JP2005217288A - Method of manufacturing electro-optical apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing an electro-optical apparatus with which the defective article generation rate of an element formed on a monocrystal silicon layer can be reduced by preventing a defect from occurring in the monocrystal silicon layer. <P>SOLUTION: The method of manufacturing the electro-optical apparatus includes a substrate forming step for sticking a monocrystal semiconductor layer 1a on an insulated supporting substrate 10, a gate insulating film forming step for forming a gate insulating film 2 of a thin film transistor on the monocrystal semiconductor layer 1a, and a gate electrode forming step for forming a gate electrode 3a on the gate insulating film 2. A temperature of heat treatment that is performed after the step for forming the gate electrode 3a is made lower than or equal with 950°C. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing an electro-optical device.

  Conventionally, an SOI (Silicon On Insulator) substrate having a structure in which a buried silicon oxide film and a single crystal silicon layer are sequentially stacked on a single crystal silicon substrate (or quartz substrate) is known. In the case where a transistor integrated circuit is formed in a single crystal silicon layer using an SOI substrate having such a structure, there is a mesa type separation method as one of methods for insulating and isolating transistors from each other. This isolation method is a method of removing all of the single crystal silicon layer in a region excluding a region where a transistor is to be formed, and is widely used because it has a feature that it can be easily manufactured and the isolation region can be narrowed. In addition, a transistor using the single crystal silicon layer separated and formed in this manner is suitably used as a switching element or the like in various electro-optical devices.

When a transistor is formed using the single crystal silicon layer, normally, the single crystal silicon layer is thermally oxidized, and a thermal oxide film made of a silicon oxide film is formed on the surface, which is used as a gate insulating film. (For example, refer to Patent Documents 1 and 2.)
JP-A-5-82789 JP-A-8-172198

However, in the case of a substrate having a structure in which a buried silicon oxide film and a single crystal silicon layer are sequentially laminated on an insulating substrate having a thermal expansion coefficient that is significantly different from that of a single crystal silicon layer, such as a quartz substrate, the disclosure is disclosed in Patent Documents 1 and 2. As described above, when a thermal oxide film is formed by high-temperature heat treatment, a large defect such as lattice slip occurs in the single crystal silicon layer due to the difference in thermal expansion coefficient between the insulating substrate and the single crystal silicon layer. The probability was high.
Further, the occurrence of such defects is not limited to the formation of a thermal oxide film, and any process can be used as long as it is a process in which high-temperature heat treatment is performed after the insulating substrate and the single crystal silicon layer are bonded to each other. There was a risk of occurrence.

  An element formed using the single-crystal silicon layer having the defect has a problem that it cannot exhibit a predetermined performance. For example, when a transistor is taken as an example of an element, there is a problem that a defect occurs and the switch function cannot be exhibited (the off-current is significantly increased and the on-current is decreased).

  The present invention has been made to solve the above-described problems, and reduces the occurrence rate of defective products of elements formed in a single crystal silicon layer by preventing the occurrence of defects in the single crystal silicon layer. An object of the present invention is to provide a method for manufacturing an electro-optical device.

  In order to achieve the above object, a method of manufacturing an electro-optical device according to the present invention includes a substrate forming step in which a single crystal semiconductor layer is bonded to an insulating support substrate, and a gate insulating film of a thin film transistor is formed on the single crystal semiconductor layer. And a gate electrode forming step of forming a gate electrode on the gate insulating film, and a heat treatment temperature performed after the gate electrode forming step is 950 ° C. or lower.

  More specifically, in order to realize the above-described configuration, it is desirable that the heat treatment temperature performed after the gate electrode formation step is 850 ° C. or lower.

That is, according to the method for manufacturing an electro-optical device of the present invention, after the gate electrode is formed, heat treatment that applies a temperature higher than 950 ° C. is not performed, and therefore, due to a difference in thermal expansion coefficient between the support substrate and the single crystal semiconductor layer. The stress acting on the single crystal semiconductor layer is reduced, and the occurrence of defects such as lattice slip in the single crystal semiconductor layer can be prevented. As a result, the incidence of defective products (switch function failures) of thin film transistors using a single crystal semiconductor layer can be reduced.
Here, according to the results of experiments by the inventors, a thin film transistor was formed using a quartz substrate and a single crystal silicon layer as a supporting substrate and a single crystal semiconductor layer and changing only the heat treatment temperature conditions after the gate electrode was formed. When the heat treatment temperature of the conventional heat treatment temperature is approximately 1000 ° C. and the case of 950 ° C., the defective product occurrence rate (defect occurrence rate in the single crystal semiconductor layer) of the thin film transistor is higher when the heat treatment temperature is 950 ° C. It is clear that it will decrease. Further, comparing the case where the heat treatment temperature after the formation of the gate electrode is 950 ° C. with the case where the heat treatment temperature is 850 ° C., the defective product occurrence rate of the thin film transistor is reduced by an order of magnitude when the heat treatment temperature is 850 ° C.

In order to realize the above structure, more specifically, in the gate insulating film formation step, the gate insulating film may be formed by performing heat treatment on the single crystal semiconductor layer, and the temperature of the heat treatment may be 850 ° C. or lower.
According to this configuration, since the heat treatment temperature when forming the gate insulating film is 850 ° C. or less, the stress acting on the single crystal semiconductor layer due to the difference in thermal expansion coefficient between the support substrate and the single crystal semiconductor layer is reduced, Generation of defects such as lattice slip in the single crystal semiconductor layer can be prevented. As a result, the incidence of defective products (switch function failures) of thin film transistors using a single crystal semiconductor layer can be reduced.

In order to realize the above-described configuration, more specifically, an introduction step of introducing an impurity that makes the single crystal semiconductor layer a predetermined conductivity type semiconductor layer into a predetermined region of the single crystal semiconductor layer; An activation step of performing activation by heat treatment, and the heat treatment temperature in the activation step may be 850 ° C. or lower.
According to this configuration, since the heat treatment temperature in the activation process is 850 ° C. or lower, the stress acting on the single crystal semiconductor layer due to the difference in thermal expansion coefficient between the support substrate and the single crystal semiconductor layer is reduced, and the single crystal semiconductor Generation of defects such as lattice slip in the layer can be prevented.

In order to realize the above-described configuration, more specifically, after the gate electrode formation step, a capacitor electrode electrically connected to the thin film transistor, a capacitor line formed of a conductive material, a capacitor electrode and a capacitor line are provided. A capacitor forming step for forming a storage capacitor comprising a capacitor insulating film to be insulated may be provided, and the firing temperature at the time of forming the capacitor insulating film in the capacitor forming step may be 850 ° C. or lower.
According to this configuration, since the firing temperature at the time of forming the capacitive insulating film is 850 ° C. or lower, the stress acting on the single crystal semiconductor layer due to the difference in thermal expansion coefficient between the support substrate and the single crystal semiconductor layer is reduced. Generation of defects such as lattice slip in the crystalline semiconductor layer can be prevented.

  In order to realize the above structure, more specifically, a source region, a channel region, and a drain region are formed in the single crystal semiconductor layer, and the impurity concentration is relative to each of the source region and the drain region. Highly high concentration regions and relatively low low concentration regions may be formed, and the sheet resistance of the low concentration regions may be 60 kΩ / □ or less.

In order to realize the above structure, more specifically, a source region, a channel region, and a drain region are formed in the single crystal semiconductor layer, and the impurity concentration is relative to each of the source region and the drain region. It is desirable that a high concentration region and a relatively low low concentration region are formed, and the sheet resistance of the low concentration region is 40 kΩ / □ or less.
According to this configuration, since the sheet resistance in the low-concentration region is formed to be 60 kΩ / □ or less, it is possible to reduce the incidence of defective thin film transistors (switch function failures).
Here, according to an experiment result of the inventor who uses a single crystal silicon layer with a film thickness of 50 nm as a single crystal semiconductor layer and forms a thin film transistor by changing only the sheet resistance in the low concentration region, the sheet resistance in the low concentration region is Comparing the case where it is larger than the conventional case of 60 kΩ / □ and the case of 60 kΩ / □ or less, the case where the sheet resistance in the low-concentration region is 60 kΩ / □ or less is the defective product occurrence rate of the thin film transistor It has been clarified that the defect occurrence rate) is reduced. Further, when the sheet resistance in the low concentration region is 60 kΩ / □ and the case in which the sheet resistance in the low concentration region is 40 kΩ / □, the defective product occurrence rate of the thin film transistor is substantially lower when the sheet resistance in the low concentration region is 40 kΩ / □. It is half.

Hereinafter, a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS.
FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display area of a liquid crystal display device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. 3 is a cross-sectional view taken along line AA ′ of FIG. Moreover, in each figure, in order to make each layer and each member large enough to be recognized on the drawing, the scale is varied for each layer and each member.
In FIG. 1, each of a plurality of pixels formed in a matrix that forms an image display area of a liquid crystal display device includes a pixel electrode 9a and a TFT (Thin Film Transistor) 30 for switching control of the pixel electrode 9a. Are formed, and the data line 6 a to which the image signal is supplied is electrically connected to the source of the TFT 30.

The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group of a plurality of adjacent data lines 6a. It may be.
Further, a scanning line (gate electrode) 3a is electrically connected to the gate of the TFT 30, and scanning signals G1, G2,..., Gm are applied to the scanning line 3a in this order in the order of lines. It is configured as follows.
The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the TFT 30 as a switching element for a certain period, the image signals S1, S2,..., Sn are transmitted from the data line 6a to the pixel electrode 9a. Is written on.

Image signals S1, S2,..., Sn written to the pixel electrode 9a are held for a certain period between the counter electrodes formed on the counter substrate. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly according to the voltage level applied to the pixel electrode 9a. Therefore, light (image) having a contrast corresponding to the image signal is emitted from the liquid crystal display device.
If this liquid crystal display device adopts a normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each pixel, and a normally black mode is adopted. In this case, the transmittance for incident light is increased in accordance with the voltage applied in units of pixels.

  A storage capacitor 70 is formed in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided side by side with the scanning line 3a, and is configured to include a fixed potential side capacitor electrode and a capacitor line 300 fixed to a constant potential, as will be described later.

Hereinafter, a configuration of a liquid crystal display device that realizes the above-described circuit operation using the data line 6a, the scanning line 3a, the TFT 30, and the like will be described with reference to FIGS.
As shown in FIG. 3, the liquid crystal display device includes a TFT array substrate (supporting substrate) 10 on which data lines 6a, scanning lines 3a, TFTs 30 and the like are formed, a counter substrate 20 disposed opposite thereto, a TFT array, The liquid crystal layer sandwiched between the substrate 10 and the counter substrate 20 is generally configured.
The TFT array substrate 10 is formed from, for example, a quartz substrate, a glass substrate, or a silicon substrate, and the counter substrate 20 is formed from a light-transmitting material such as a glass substrate or a quartz substrate.

  On the TFT array substrate 10, as shown in FIG. 3, a base insulating film 12, a first interlayer insulating film 41, a second interlayer insulating film 42, and a third interlayer insulating film 43 are provided in order from the bottom. A lower light-shielding film 11 a is provided between the TFT array substrate 10 and the base insulating film 12, and a TFT 30 and a scanning line 3 a are provided between the base insulating film 12 and the first interlayer insulating film 41. Yes. A storage capacitor 70 is provided between the first interlayer insulating film 41 and the second interlayer insulating film 42, and a data line 6 a is formed between the second interlayer insulating film 42 and the third interlayer insulating film 43. Yes.

As shown in FIG. 3, the pixel electrode 9 a is provided on the third interlayer insulating film 43, and the alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9 a. ing.
The pixel electrode 9a is formed of a transparent conductive film such as an ITO (Indium Tin Oxide) film, and the alignment film 16 is formed of a transparent organic film such as a polyimide film. Further, as shown in FIG. 2, a plurality of the pixel electrodes 9a are provided in a matrix form on the TFT array substrate 10 (the outline is indicated by a dotted line portion 9a ′), and the vertical and horizontal boundaries of the pixel electrodes 9a are provided. A data line 6a and a scanning line 3a are provided along each line.
The data line 6a is formed from a metal film such as an aluminum film or an alloy film. The scanning line 3a is disposed so as to face the channel region 1a ′ indicated by the hatched region rising to the right in the drawing in the semiconductor layer (single crystal semiconductor layer) 1a, and the scanning line 3a functions as a gate electrode. That is, each of the intersections between the scanning lines 3a and the data lines 6a is provided with a pixel switching TFT 30 in which the main line portion of the scanning line 3a is disposed opposite to the channel region 1a ′ as a gate electrode.

As shown in FIG. 3, the TFT 30 has an LDD (Lightly Doped Drain) structure. As the constituent elements, as described above, the scanning line 3a functioning as a gate electrode, the channel region 1a ′ of the semiconductor layer 1a formed of a single crystal silicon layer and having a channel formed by the electric field from the scanning line 3a, the scanning line A gate insulating film 2 that insulates the semiconductor layer 1a, a lightly doped source region (source region, lightly doped region) 1b, a lightly doped drain region (drain region, lightly doped region) 1c, A concentration source region (source region, high concentration region) 1d and a high concentration drain region (drain region, high concentration region) 1e are provided.
Here, the low-concentration source region 1b and the low-concentration drain region 1c of the TFT 30 have a sheet resistance of at least 60 kΩ / □ or less, preferably 40 kΩ / □ or less when the film thickness of the single crystal silicon layer is 50 nm. Is formed.

Further, as shown in FIG. 3, the storage capacitor 70 includes a relay layer (capacitance electrode) 71 that functions as a pixel potential side capacitance electrode and a part of a capacitance line 300 that functions as a fixed potential side capacitance electrode. (Capacitance insulating film) 75 is disposed so as to face each other.
The relay layer 71 is formed so as to be electrically connected to the high-concentration drain region 1e of the TFT 30 and the pixel electrode 9a via contact holes 83 and 85, which will be described later, and a conductive material such as a polysilicon film, for example. And functions as a pixel potential side capacitor electrode as described above. Note that the relay layer 71 may be formed of a polysilicon film as described above, or may be formed of a single layer film or a multilayer film containing a metal or an alloy, like the capacitor line 300 described later.

The capacitor line 300 is made of a conductive film containing, for example, a metal or an alloy, and functions as a fixed potential side capacitor electrode as described above. The capacitance line 300 is formed so as to overlap with the formation region of the scanning line 3a when viewed in plan as shown in FIG.
More specifically, the capacitor line 300 includes a main line portion extending along the scanning line 3a, a protruding portion protruding upward along the data line 6a from each portion intersecting the data line 6a in the drawing, and a contact hole. A portion corresponding to 85 is provided with a recessed portion that is slightly recessed.
The capacitor line 300 is preferably formed from a conductive light-shielding film containing a refractory metal. In addition to the function as a fixed-potential-side capacitor electrode of the storage capacitor 70, the light-shielding layer that shields the TFT 30 from incident light above the TFT 30. As a function.

Further, the capacitor line 300 preferably extends from the image display region 10a (see FIG. 4) in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. . As such a constant potential source, a constant potential source of a positive power source or a negative power source supplied to the data line driving circuit 101 or a constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used.
As shown in FIG. 3, the dielectric film 75 is made of a silicon oxide film such as a relatively thin HTO (High Temperature Oxide) film having a thickness of about 5 to 200 nm, a silicon nitride film, or the like.

As shown in FIG. 3, a contact hole 85 is formed in the second interlayer insulating film 42 and the third interlayer insulating film 43 so as to penetrate the second interlayer insulating film 42 and the third interlayer insulating film 43. .
In the first interlayer insulating film 41 and the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the TFT 30 and the data line 6a is formed.
The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high concentration drain region 1 e and the relay layer 71 of the storage capacitor 70.
The first interlayer insulating film 41, the second interlayer insulating film 42, and the third interlayer insulating film 43 are made of an insulating material such as a silicate glass film, a silicon nitride film, or a silicon oxide film.

In the lower region of the TFT 30, as shown in FIGS. 2 and 3, a lower light-shielding film 11a is provided. The lower light-shielding film 11a is patterned in a lattice shape, thereby defining an opening area of each pixel.
Note that the opening region is also defined by forming the data line 6a extending in the vertical direction in FIG. 2 and the capacitor line 300 extending in the horizontal direction in FIG.
Similarly to the case of the capacitance line 300, the lower light-shielding film 11a is also extended from the image display area to the periphery thereof in order to prevent the potential fluctuation from adversely affecting the TFT 30. It may be connected to a potential source.

  A counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is formed of a transparent conductive film such as an ITO film, for example, like the pixel electrode 9a described above, and the alignment film 22 is formed of a transparent organic film such as a polyimide film.

(Overall configuration of liquid crystal display device)
The overall configuration of the electro-optical device in each embodiment configured as described above will be described with reference to FIGS. 4 and 5. 4 is a plan view of the TFT array substrate as viewed from the counter substrate 20 side together with the components formed thereon, and FIG. 5 is a cross-sectional view taken along the line HH ′ of FIG.
In the liquid crystal display device, as shown in FIGS. 4 and 5, the TFT array substrate 10 and the counter substrate 20 are arranged to face each other. Liquid crystal 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material provided in a seal region located around the image display region 10a. 52 are bonded to each other.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like, and is cured by ultraviolet rays, heating, or the like in order to bond the two substrates together. Further, in this sealing material 52, if the liquid crystal display device is a small liquid crystal device that performs enlarged display like a projector, a glass fiber for setting the distance between the two substrates (inter-substrate gap) to a predetermined value is used. Alternatively, a gap material (spacer) such as glass beads is dispersed. Alternatively, such a gap material may be included in the liquid crystal layer 50 as long as the liquid crystal display device is a large-sized liquid crystal device that performs the same magnification display as a liquid crystal display or a liquid crystal television.

  In an area outside the sealing material 52, a data line driving circuit 101 and an external circuit connection terminal 102 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing are provided on one side of the TFT array substrate 10. A scanning line driving circuit 104 for driving the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing is provided along two sides adjacent to the one side. . Needless to say, if the delay of the scanning signal supplied to the scanning line 3a is not a problem, the scanning line driving circuit 104 may be provided on only one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a.

  On the remaining side of the TFT array substrate 10, a plurality of wirings 105 are provided for connecting the scanning line driving circuits 104 provided on both sides of the image display region 10a. Further, at least one corner portion of the counter substrate 20 is provided with a conductive material 106 for electrical connection between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, as shown in FIG. 5, an alignment film is formed on the pixel electrode 9a. On the other hand, in addition to the counter electrode 21, an alignment film is formed on the uppermost layer portion on the counter substrate 20. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  According to the above configuration, the sheet resistance of the low concentration source region 1b and the low concentration drain region 1c is formed to be at least 60 kΩ / □ or less, preferably 40 kΩ / □ or less. The malfunction rate can be reduced.

(Manufacturing method of liquid crystal display device)
Below, the manufacturing method of the liquid crystal display device mentioned above is demonstrated, referring FIGS. 6-8.
First, in FIG. 6A, a substrate such as a silicon substrate, a quartz substrate, or a glass substrate (that is, a TFT array substrate 10 is prepared. Here, preferably in an inert gas atmosphere such as N ₂ (nitrogen), about 850 to Annealing is performed at a high temperature of 1300 ° C., more preferably 1000 ° C., and pre-processing is performed so as to reduce distortion generated in the TFT array substrate 10 in a high-temperature process performed later.

On the entire surface of the TFT array substrate 10 thus treated, a metal simple substance, alloy, metal silicide or the like containing at least one of Ti, Cr, W, Ta, Mo and Pd is formed by sputtering or the like. A light-shielding layer having a thickness of about ˜500 nm, preferably about 200 nm is formed. Thereafter, the lower light-shielding film 11a is formed in a predetermined pattern by photolithography and etching.
Subsequently, on the lower light-shielding film 11a, for example, TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl boatate) gas, TMOP (tetramethylmethyl) by atmospheric pressure or reduced pressure CVD method or the like.・ Silicate glass films such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride film, using oxy-phosphorate gas, etc. Then, a base insulating film 12 made of a silicon oxide film or the like is formed.
Next, the surface of the base insulating film 12 is polished using a method such as CMP (Chemical Mechanical Polishing), and the surface of the base insulating film 12 is planarized as shown in FIG. The film thickness of the base insulating film 12 is about 400 to 1000 nm, more preferably about 800 nm.

Next, a method for manufacturing the TFT 30 and the like on the TFT array substrate 10 on which the base insulating film 12 is formed will be described with reference to FIGS. 7 to 8 are process diagrams showing a part of the TFT array substrate in each process corresponding to the cross-sectional view of the liquid crystal panel shown in FIG.
Fig.7 (a) is a figure which takes out a part of FIG.6 (b), and shows it on a different scale. As shown in FIG. 7B, the TFT array substrate 10 having the base insulating film 12 having a planarized surface shown in FIG. 7A and the single crystal silicon substrate 206a are bonded to each other.

The thickness of the single crystal silicon substrate 206a used for bonding is, for example, 600 μm. An oxide film layer 206b is formed on the surface of the single crystal silicon substrate 206a on the side to be bonded to the TFT array substrate 10 in advance, and hydrogen Ions (H ⁺ ) are implanted, for example, at an acceleration voltage of 100 keV and a dose of 10 × 10 ¹⁶ / cm ² . The oxide film layer 206b is formed by oxidizing the surface of the single crystal silicon substrate 206a by about 0.05 to 0.8 μm.
For the bonding step, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours can be employed.

  Further, in order to further increase the bonding strength, it is necessary to increase the heat treatment temperature to about 450 ° C. However, the thermal expansion coefficient of the TFT array substrate 10 made of quartz or the like and the thermal expansion coefficient of the single crystal silicon substrate 206a Since there is a large difference between them, defects such as cracks occur in the single crystal silicon layer when heated as they are, and the quality of the manufactured TFT array substrate 10 may be deteriorated. In order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 206a once subjected to heat treatment for bonding at 300 ° C. is thinned to about 100 to 150 μm by wet etching or CMP, and then further It is desirable to perform a high temperature heat treatment. For example, by etching using a 80 ° C. aqueous KOH solution so that the thickness of the single crystal silicon substrate 206a is 150 μm, bonding to the TFT array substrate 10 is performed, and then heat treatment is performed again at 450 ° C. It is desirable to increase the bonding strength.

Next, as shown in FIG. 7C, the single crystal silicon substrate 206a is removed from the TFT array substrate while leaving the oxide film 206b and the single crystal silicon layer 206 on the bonded surface side of the bonded single crystal silicon substrate 206a. Heat treatment for peeling (separating) from 10 is performed.
This substrate peeling phenomenon is caused by the fact that silicon bonds are broken at a certain layer near the surface of the single crystal silicon substrate 206a by hydrogen ions introduced into the single crystal silicon substrate 206a. The heat treatment here can be performed, for example, by heating the two bonded substrates to 600 ° C. at a rate of temperature increase of 20 ° C. per minute. By this heat treatment, the bonded single crystal silicon substrate 206 a is separated from the TFT array substrate 10, and a single crystal silicon layer 206 of about 200 nm ± 5 nm is formed on the surface of the TFT array substrate 10.

The film thickness of the single crystal silicon layer 206 can be arbitrarily formed in the range of, for example, 10 nm to 3000 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 206a described above.
Note that the thinned single crystal silicon layer 206 is not limited to the method and process described here, and after polishing the surface of the single crystal silicon substrate to a thickness of 3 to 5 μm, the PACE (Plasma A method in which the film thickness is etched to about 0.05 to 0.8 μm by the Assisted Chemical Etching method, or an epitaxial silicon layer formed on the porous silicon is bonded to the bonded substrate by selective etching of the porous silicon layer. It can also be obtained by other general methods for manufacturing SOI substrates such as ELTRAN (Epitaxial Layer Transfer) method.

Further, in order to improve the adhesion between the base insulating film 12 and the single crystal silicon layer 206 and increase the bonding strength, after the TFT array substrate 10 and the single crystal silicon layer 206 are bonded together, a rapid thermal processing method (RTA). It is desirable to heat by, for example. The heating temperature is 600 ° C. to 1200 ° C., and it is desirable to heat at 1050 ° C. to 1200 ° C. to lower the viscosity of the oxide film and to improve the atomic adhesion.
Next, as shown in FIG. 7D, a semiconductor layer 1a having a predetermined pattern is formed by a mesa-type separation method using a photolithography process, an etching process, or the like. For the element isolation step, a well-known LOCOS isolation method or trench isolation method may be used.

Next, as shown in FIG. 8A, the gate insulating film 2 is formed by thermally oxidizing the semiconductor layer 1a. Here, the heat treatment temperature when forming the gate insulating film 2 by thermally oxidizing the semiconductor layer 1a is controlled to be 950 ° C. or lower, desirably 850 ° C. or lower.
As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 50 nm, and the gate insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to The thickness is 100 nm.

Next, as shown in FIG. 8B, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and P (phosphorus) is further thermally diffused to make the polysilicon film conductive. Then, the scanning lines 3a having a predetermined pattern are formed in the image display region 10a by a photolithography process, an etching process, or the like.
Next, by doping impurity ions in two steps of low concentration and high concentration, a low concentration source region 1b, a low concentration drain region 1c, a high concentration source region 1d, and a high concentration drain region 1e (see FIG. 3) are included. The semiconductor layer 1a of the pixel switching TFT 30 having the LDD structure is formed in the image display region.

For example, when forming a P-channel LDD region in the semiconductor layer 1a, first, a dopant (impurity) of a group III element such as B is used at a low concentration (for example, BF ₂ ions are accelerated by 90 keV, 3 × 10 Doping is performed (with a dose of ¹³ / cm ² ) to form a low concentration source region and a low concentration drain region of the P channel. Thereafter, a dopant of a group III element such as B is doped at a high concentration (for example, BF ₂ ions are accelerated at a pressure of 90 keV and a dose of 2 × 10 ¹⁵ / cm ² ) to form a high concentration source region of the P channel. And a high concentration drain region is formed. Alternatively, when forming a P-channel LDD region, first, a dopant (impurity) of a group V element such as P is used at a low concentration (for example, P ions are accelerated at 70 keV, 6 × 10 ¹² / cm ² . Doping is performed to form an N channel low concentration source region and a low concentration drain region. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions are applied at an acceleration voltage of 70 keV and a dose of 4 × 10 ¹⁵ / cm ² ), and an N-channel high concentration source region and A high concentration drain region is formed.

Next, as shown in FIG. 8C, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, using atmospheric pressure or reduced pressure CVD, TEOS gas, or the like. A first interlayer insulating film 41 made of is formed.
Subsequently, a polysilicon film is deposited by a low pressure CVD method or the like, phosphorus (P) is further thermally diffused, and the polysilicon film is made conductive to form a relay layer 71. Then, after depositing a dielectric film 75 made of a high temperature silicon oxide film (HTO film) or silicon nitride film to a relatively thin thickness of about 50 nm by low pressure CVD method, plasma CVD method or the like, Ti, Cr, W, Capacitor lines 300 are formed by sputtering a metal alloy film such as a metal such as Ta, Mo and Pd or a metal silicide. As a result, the storage capacitor 70 is formed in the image display area 10a.

Thereafter, the second interlayer insulating film 42 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using, for example, atmospheric pressure or low pressure CVD method, TEOS gas, or the like. .
Subsequently, after a contact hole is formed by dry etching such as reactive ion etching or reactive ion beam etching for the second interlayer insulating film 42, the entire surface on the second interlayer insulating film 42 is shielded from light by sputtering or the like. A low-resistance metal such as Al or metal silicide is deposited as a metal film to a thickness of about 100 to 500 nm, preferably about 300 nm. Then, the data line 6a having a predetermined pattern is formed in the image display area 10a by photolithography and etching.

  Here, the first interlayer insulating film 41, the second interlayer insulating film 42, and the dielectric film 75 that have already been formed are baked at 950 ° C. or lower, preferably 850 ° C. or lower, thereby forming the semiconductor layer 1a. Activation of ions implanted into the substrate may be achieved. In addition, this baking may be performed collectively as mentioned above, and may be performed separately, and is not specifically limited.

Next, as shown in FIG. 8D, the silicon oxide film is formed on the surface of the second interlayer insulating film 42 located in the opening region of each pixel and the data line 6a using, for example, atmospheric pressure or low pressure CVD. A third interlayer insulating film 43 is formed thereon.
Next, as shown in FIG. 8E, a contact hole 85 is formed by dry etching such as reactive ion etching or reactive ion beam etching for the third interlayer insulating film 43.

Thereafter, an ITO film is formed on the third interlayer insulating film 43 by sputtering or the like. Then, the pixel electrode 9a is formed by performing photolithography and etching on the ITO film. After that, the alignment film 16 is formed by applying a polyimide alignment film coating solution thereon and further performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.
As described above, the TFT 30, the storage capacitor 70, and the like are manufactured on the TFT array substrate 10.

Next, a manufacturing method of the counter substrate 20 and a method of manufacturing a liquid crystal panel from the TFT array substrate 10 and the counter substrate 20 will be described.
3 and 5, a light-transmitting substrate such as a glass substrate is prepared as the counter substrate 20, and a light shielding film 53 is formed on the surface of the counter substrate 20 as a peripheral parting. The light shielding film 53 serving as a peripheral parting is formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, and Al. These light shielding films 53 may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist in addition to the above metal material.

Thereafter, a transparent conductive thin film such as ITO is deposited to a thickness of about 50 to 200 nm on the entire surface of the counter substrate 20 by sputtering or the like to form the counter electrode 21. Further, the alignment film 22 is applied to the entire surface of the counter electrode 21 by applying a coating solution of an alignment film such as polyimide, and then performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. Form.
The counter substrate 20 is manufactured as described above.

  Finally, the TFT array substrate 10 and the counter substrate 20 manufactured as described above are bonded together by the sealing material 52 so that the alignment films 16 and 22 face each other. Then, a liquid crystal layer 50 having a predetermined thickness is formed by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystal into the space between both substrates by a method such as a vacuum suction method. As a result, a liquid crystal panel having the above structure is obtained.

  According to the manufacturing method described above, after the formation of the scanning line 3a, such as the heat treatment temperature for activating the ions implanted into the semiconductor layer 1a and the firing temperature of the dielectric film 75, the heat treatment for applying a temperature higher than 950 ° C. is performed. Therefore, the stress acting on the semiconductor layer 1a due to the difference in thermal expansion coefficient between the TFT array substrate 10 and the semiconductor layer 1a is reduced, and the occurrence of defects such as lattice slip in the semiconductor layer 1a can be prevented. As a result, the incidence of defective products (switch function failures) of the TFT 30 using the semiconductor layer 1a can be reduced.

  In addition, since the heat treatment temperature at the time of forming the gate insulating film 2 is 850 ° C. or lower, defects such as lattice slip in the semiconductor layer 1a due to the difference in thermal expansion coefficient between the TFT array substrate 10 and the semiconductor layer 1a are further generated. It can be surely prevented. As a result, the incidence of defective products (switch function failures) of the TFT 30 using the semiconductor layer 1a can be reduced.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, the present invention has been described as being applied to a liquid crystal display device. However, the present invention is not limited to a liquid crystal display device, and an SOQ (Silicon On) in which an element such as an organic EL device is formed. The present invention can be applied to all apparatuses using a (Quartz) substrate.

FIG. 3 is a circuit diagram illustrating an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix-like pixels that form an image display region in the electro-optical device of the invention. 2 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate on which data lines, scanning lines, pixel electrodes and the like are formed. FIG. FIG. 3 is a cross-sectional view taken along line AA ′ in FIG. 2. 2 is a plan view of a liquid crystal display device which is an example of the electro-optical device. FIG. FIG. 5 is a cross-sectional view taken along line HH ′ in FIG. 4. (A)-(b) is a manufacturing-process figure of an electro-optical apparatus. (A)-(d) is a manufacturing-process figure of an electro-optical apparatus. (A)-(e) is a manufacturing-process figure of an electro-optical apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer (single crystal semiconductor layer), 1a '... Channel region, 1b ... Low concentration source region (source region, low concentration region), 1c ... Low concentration drain region (drain region, Low concentration region), 1d ... High concentration source region (source region, high concentration region), 1e ... High concentration drain region (drain region, high concentration 0 degree region), 2 ... Gate insulating film, 3a ... Scanning line (gate electrode), 10 ... TFT array substrate (supporting substrate), 30 ... TFT (thin film transistor), 70 ... Storage capacitor, 71 ... Relay layer (capacitor electrode), 75 ... Dielectric film (capacitive insulating film), 300 ... Capacitor line

Claims (7)

A substrate forming step of attaching a single crystal semiconductor layer to an insulating support substrate;
Forming a gate insulating film of a thin film transistor on the single crystal semiconductor layer; and
Forming a gate electrode on the gate insulating film; and
Have
A method of manufacturing an electro-optical device, wherein a heat treatment temperature performed after the gate electrode forming step is 950 ° C. or lower.   2. The method of manufacturing an electro-optical device according to claim 1, wherein a heat treatment temperature performed after the gate electrode forming step is 850 [deg.] C. or lower. In the gate insulating film forming step, the gate insulating film is formed by subjecting the single crystal semiconductor layer to a heat treatment,
The method of manufacturing an electro-optical device according to claim 1, wherein a temperature of the heat treatment is set to 850 ° C. or less. Introducing an impurity that makes the single crystal semiconductor layer a predetermined conductivity type semiconductor layer into a predetermined region of the single crystal semiconductor layer;
An activation step of activating the introduced impurities by heat treatment,
The method of manufacturing an electro-optical device according to claim 1, wherein a heat treatment temperature in the activation step is set to 850 ° C. or less. After the gate electrode forming step,
A capacitance forming step of forming a storage capacitor comprising a capacitor electrode electrically connected to the thin film transistor, a capacitor line formed of a conductive material, and a capacitor insulating film that insulates the capacitor electrode and the capacitor line; Have
5. The method of manufacturing an electro-optical device according to claim 1, wherein a firing temperature at the time of forming the capacitor insulating film in the capacitor forming step is 850 ° C. or lower. In the single crystal semiconductor layer, a source region, a channel region, and a drain region are formed. In the source region and the drain region, a high concentration region with a relatively high impurity concentration and a low concentration with a relatively low concentration, respectively. A concentration region is formed,
6. The method of manufacturing an electro-optical device according to claim 1, wherein the sheet resistance in the low concentration region is 60 kΩ / □ or less. In the single crystal semiconductor layer, a source region, a channel region, and a drain region are formed. In the source region and the drain region, a high concentration region with a relatively high impurity concentration and a low concentration with a relatively low concentration, respectively. A concentration region is formed,
7. The method of manufacturing an electro-optical device according to claim 1, wherein the sheet resistance in the low-concentration region is 40 kΩ / □ or less.

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