JP2007242723A - Process for fabricating electro-optical device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a process for fabricating an electro-optical device in which a high performance switching element enabling high speed drive can be formed on a supporting substrate. <P>SOLUTION: A sticking film 210 is formed on one surface of a single crystal silicon substrate 200 and the side where the sticking film 210 is formed is stuck to a supporting substrate 10A. A semiconductor layer consisting of the single crystal silicon substrate 200 is formed by etching and patterning the single crystal silicon substrate 200 using mixture liquid of hydrofluoric acid and ozone water. A switching element is formed by using the semiconductor layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing an electro-optical device.

  2. Description of the Related Art Conventionally, a substrate for an electro-optical device that constitutes an electro-optical device such as a liquid crystal display device includes a thin film transistor (Thin Film Transistor) made of amorphous silicon or polysilicon formed on a glass substrate. Such a thin film transistor has a larger number of defects and a higher interface state than a MOS transistor formed on, for example, single crystal silicon, so that sufficient electron mobility cannot be obtained, and leakage current when the transistor is OFF Becomes larger.

  Therefore, in recent years, a semiconductor layer made of a single crystal silicon layer is formed on a glass substrate, and a semiconductor device such as a switching element is formed from this semiconductor layer, thereby increasing the speed of the element, lowering power consumption, and increasing integration. An SOI (Silicon on Insulator) technique that can be used is known, and is used for a substrate for forming a switching element in an electro-optical device such as the above-described liquid crystal display device.

In an electro-optical device to which such SOI technology is applied, a thin film single crystal semiconductor layer is formed by bonding a semiconductor substrate having a single crystal semiconductor layer made of single crystal silicon or the like to a supporting substrate, and polishing the thin film single crystal semiconductor layer. A switching element for driving a liquid crystal is formed from the crystalline semiconductor layer.
As a method of forming such a thin film single crystal semiconductor layer, for example, after forming a single crystal silicon layer by epitaxial growth on a porous silicon single crystal substrate, the single crystal silicon layer side is bonded to a support substrate, and the porous There is a technique in which a silicon single crystal substrate portion is entirely removed by etching and a thin single crystal silicon layer is formed on a support substrate (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 5-41505

  However, when the switching element of the electro-optical device is formed from the single crystal silicon layer, since the patterning is generally performed by dry etching such as RIE (reactive ion etching), the formed single crystal silicon layer (semiconductor The layer) is damaged by etching such as plasma. A switching element formed from such a single crystal silicon layer has a large leakage current and low transistor characteristics, and the electro-optical device cannot be driven at high speed.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device manufacturing method capable of forming a high-performance switching element capable of high-speed driving on a support substrate.

  The method for manufacturing an electro-optical device according to the present invention includes a step of forming an adhesive film on one surface of a single crystal silicon substrate, and bonding the side on which the adhesive film is formed to a support substrate; and the single crystal silicon substrate Etching and patterning using a mixed solution of hydrofluoric acid and ozone water to form a semiconductor layer made of the single crystal silicon substrate, and forming a switching element using the semiconductor layer. It is characterized by having.

According to the method for manufacturing an electro-optical device of the present invention, since the single crystal silicon substrate is patterned by wet etching using a mixed solution of hydrofluoric acid and ozone water, generation of by-products and surface roughness during etching are performed. Thus, a semiconductor layer having low defects and low interface states can be formed on the supporting substrate. By using such a semiconductor layer, a high-performance switching element with little leakage current can be manufactured.
Accordingly, it is possible to provide an electro-optical device that is capable of high-speed driving including a high-performance switching element.

In the method of manufacturing the electro-optical device, it is preferable to use a single crystal silicon substrate having a plane orientation (100).
In this case, the mixed solution of hydrofluoric acid and ozone water increases the etching rate with respect to the single crystal silicon substrate, so that a large selection ratio can be obtained with respect to the mask. Further, since the etching proceeds anisotropically so that the (110) plane is exposed, the side surface portion of the semiconductor layer to be patterned can be inclined, and the surface area of the semiconductor layer can be increased.
Therefore, for example, when a gate electrode is formed over a semiconductor layer via an insulating film, the gate width becomes large and a large amount of current can flow between the source and the drain, so that a high-performance switching element can be provided.

In the electro-optical device manufacturing method, it is preferable that the single crystal silicon substrate is thermally oxidized to form the adhesive film made of silicon oxide.
In this way, it is possible to easily and reliably form an adhesive film required when the single crystal silicon substrate and the support substrate are bonded together.

In the method of manufacturing the electro-optical device, it is preferable to use a substrate in which a semiconductor device is formed in advance as the single crystal silicon substrate.
In this way, as a peripheral circuit in the electro-optical device, for example, by forming a semiconductor device such as a CMOS on a single crystal silicon substrate in advance, a circuit design for forming the semiconductor layer from the single crystal silicon substrate can be achieved. The degree of freedom can be improved.

In the method for manufacturing the electro-optical device, the semiconductor device is preferably a CMOS.
In this way, a peripheral circuit that enables high-speed driving can be formed on the same substrate, and a high-performance electro-optical device can be provided.

  Hereinafter, a case of manufacturing a liquid crystal display device (electro-optical device) will be described as an embodiment of a method for manufacturing an electro-optical device of the present invention. Prior to describing the manufacturing method of the liquid crystal display device, the configuration of the liquid crystal display device obtained by this manufacturing method will be described with reference to FIGS.

  FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image display area of a liquid crystal display device. FIG. 2 is a plan view of a plurality of pixel groups adjacent to each other on an element substrate on which data lines, scanning lines, pixel electrodes and the like are formed. 3 is a cross-sectional view taken along line AA ′ of FIG. Moreover, in each figure, in order to make each layer and each member large enough to be recognized on the drawing, the scale is varied for each layer and each member.

  In FIG. 1, a pixel electrode 9a and a transistor (switching element) 30 for controlling the switching of the pixel electrode 9a are formed in each of a plurality of pixels formed in a matrix that forms an image display area of the liquid crystal display device. The data line 6a to which the image signal is supplied is electrically connected to the source of the transistor 30. Note that the method of manufacturing the electro-optical device according to the present invention is characterized in the process of forming the transistor 30.

  The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each group of a plurality of adjacent data lines 6a. It may be. Further, a scanning line (gate electrode) 3a is electrically connected to the gate of the transistor 30, and scanning signals G1, G2,..., Gm are sequentially applied to the scanning line 3a in this order. It is comprised so that. The pixel electrode 9a is electrically connected to the drain of the transistor 30. By turning on the transistor 30 serving as a switching element for a certain period, the image signals S1, S2,. It is written in the pixel electrode 9a.

  Image signals S1, S2,..., Sn written to the pixel electrode 9a are held for a certain period between the counter electrodes formed on the counter substrate. The liquid crystal modulates light and enables gradation display by changing the orientation and order of the molecular assembly according to the voltage level applied to the pixel electrode 9a. Therefore, light (image) having a contrast corresponding to the image signal is emitted from the liquid crystal display device. If this liquid crystal display device adopts a normally white mode, the transmittance for incident light decreases according to the voltage applied in units of each pixel, and a normally black mode is adopted. In this case, the transmittance for incident light is increased in accordance with the voltage applied in units of pixels.

  A storage capacitor 70 is formed in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the counter electrode. The storage capacitor 70 is provided side by side with the scanning line 3a, and is configured to include a fixed potential side capacitor electrode and a capacitor line 300 fixed to a constant potential, as will be described later.

  Hereinafter, a configuration of a liquid crystal display device in which the above-described circuit operation is realized by the data line 6a, the scanning line 3a, the transistor 30, and the like will be described with reference to FIGS. As shown in FIG. 3, the liquid crystal device according to the present embodiment includes an element substrate 10 on which data lines 6a, scanning lines 3a, transistors 30 and the like are formed, a counter substrate 20 disposed opposite thereto, and both the substrates. And a liquid crystal layer 50 sandwiched between 10 and 20.

  The element substrate 10 is mainly composed of a substrate body (support substrate) 10A made of a light-transmitting material such as quartz, a pixel electrode 9a formed on the surface of the liquid crystal layer 50, a transistor 30, and the like. Is mainly composed of a substrate body 20A made of a translucent material such as glass or quartz and a counter electrode 21 formed on the surface of the liquid crystal layer 50 side. In the present embodiment, glass substrates are used as the substrate bodies 10A and 20A.

  As shown in FIG. 3, an insulating layer 15, a first interlayer insulating film 41, a second interlayer insulating film 42, and a third interlayer insulating film 43 are provided in order from the bottom on the substrate body 10 </ b> A constituting the element substrate 10. ing. A lower light-shielding film 11a is provided between the substrate body 10A and the insulating layer 15, and a transistor 30 and a scanning line 3a are provided between the insulating layer 15 and the first interlayer insulating film 41. A storage capacitor 70 is provided between the first interlayer insulating film 41 and the second interlayer insulating film 42, and a data line 6 a is formed between the second interlayer insulating film 42 and the third interlayer insulating film 43. Yes.

As shown in FIG. 3, the pixel electrode 9 a is provided on the third interlayer insulating film 43, and the alignment film 16 subjected to a predetermined alignment process such as a rubbing process is provided above the pixel electrode 9 a. ing.
The pixel electrode 9a is formed of a transparent conductive film such as an ITO (Indium Tin Oxide) film, and the alignment film 16 is formed of a transparent organic film such as a polyimide film. Further, as shown in FIG. 2, a plurality of the pixel electrodes 9a are provided in a matrix on the substrate body 10A (the outline is indicated by a dotted line portion 9a ′), and the vertical and horizontal boundaries of the pixel electrodes 9a are provided. A data line 6a and a scanning line 3a are provided along each.

  The data line 6a is formed from a metal film such as an aluminum film or an alloy film. The scanning line 3a is disposed so as to face the channel region 1a ′ indicated by the hatched region in the semiconductor layer (single crystal semiconductor layer) 1a in the lower right direction in the drawing, and the scanning line 3a functions as a gate electrode. In other words, each of the intersections of the scanning line 3a and the data line 6a is provided with a pixel switching transistor 30 in which the main line portion of the scanning line 3a is opposed to the channel region 1a ′ as a gate electrode.

  As shown in FIG. 3, the transistor 30 has an LDD (Lightly Doped Drain) structure. As the constituent elements, as described above, the scanning line 3a functioning as a gate electrode, the channel region 1a ′ of the semiconductor layer 1a formed of a single crystal silicon layer and having a channel formed by the electric field from the scanning line 3a, the scanning line A gate insulating film 2 that insulates the semiconductor layer 1a, a lightly doped source region (source region, lightly doped region) 1b, a lightly doped drain region (drain region, lightly doped region) 1c, A concentration source region (source region, high concentration region) 1d and a high concentration drain region (drain region, high concentration region) 1e are provided.

Here, a schematic configuration of the transistor 30 will be described.
As shown in FIG. 4, the gate insulating film 2 extends along a direction orthogonal to the semiconductor layer 1 a formed on the substrate body 10 </ b> A via the insulating layer 15 (in the direction of the arrow BB ′ in FIG. 3). A gate electrode 3a is formed via the. As the gate insulating film 2, it is preferable to use a material having a high dielectric constant. The gate electrode 3a is not limited to poly-Si, and may be a metal gate electrode.

  Source / drain regions (1b, 1c, 1d, 1e) are formed in the semiconductor layer 1a with the gate electrode 3a interposed therebetween. The side surface of the semiconductor layer 1a has an inclined surface 35 with the (110) plane exposed by an anisotropic etching process described later.

  That is, since the gate electrode 3a is formed on the inclined surface 35 with the gate insulating film 2 interposed therebetween, the gate width when viewed in plan (when viewed from the side perpendicular to the element substrate 10) is substantially the same. Only a portion formed along the inclined surface 35 can have a substantial length. With such a configuration, the current flowing between the source and the drain can be increased, so that high performance is achieved that enables high-speed driving.

  In addition, since the anisotropic etching process uses a mixed solution of hydrofluoric acid and ozone water as an etching solution as will be described later, the surface roughness of the etched surface is reduced (FIG. 10). reference). Therefore, defects due to surface roughness due to etching are prevented, and the semiconductor layer 1a has a low interface state density.

Further, as shown in FIG. 3, the storage capacitor 70 includes a relay layer (capacitance electrode) 71 that functions as a pixel potential side capacitance electrode and a part of a capacitance line 300 that functions as a fixed potential side capacitance electrode. (Capacitance insulating film) 75 is disposed so as to face each other.
The relay layer 71 is formed so as to be electrically connected to the high-concentration drain region 1e of the transistor 30 and the pixel electrode 9a through contact holes 83 and 85, which will be described later, and is made of a conductive material such as a polysilicon film. It is made of a material and functions as a pixel potential side capacitor electrode as described above. The relay layer 71 may be formed of a polysilicon film, or may be formed of a single layer film or a multilayer film containing a metal or an alloy.

The capacitor line 300 is made of a conductive film containing, for example, a metal or an alloy, and functions as a fixed potential side capacitor electrode as described above. The capacitance line 300 is formed so as to overlap with the formation region of the scanning line 3a when viewed in plan as shown in FIG. More specifically, the capacitor line 300 includes a main line portion extending along the scanning line 3a, a protruding portion protruding upward along the data line 6a from each portion intersecting the data line 6a in the drawing, and a contact hole. A portion corresponding to 85 is provided with a recessed portion that is slightly recessed.
The capacitor line 300 is preferably formed of a conductive light-shielding film containing a refractory metal, and functions as a fixed potential side capacitor electrode of the storage capacitor 70 and shields the transistor 30 from incident light above the transistor 30. It functions as a light shielding layer.

Further, the capacitor line 300 preferably extends from the image display region 10a (see FIG. 4) in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to be a fixed potential. . As such a constant potential source, a constant potential source of a positive power source or a negative power source supplied to the data line driving circuit 101 or a constant potential supplied to the counter electrode 21 of the counter substrate 20 may be used.
As shown in FIG. 3, the dielectric film 75 is composed of a silicon oxide film such as a relatively thin HTO (High Temperature Oxide) film having a thickness of about 5 to 200 nm, a silicon nitride film, or the like.

As shown in FIG. 3, a contact hole 85 is formed in the second interlayer insulating film 42 and the third interlayer insulating film 43 so as to penetrate the second interlayer insulating film 42 and the third interlayer insulating film 43. .
In the first interlayer insulating film 41 and the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the transistor 30 and the data line 6a is formed.
The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high concentration drain region 1 e and the relay layer 71 of the storage capacitor 70.
The first interlayer insulating film 41, the second interlayer insulating film 42, and the third interlayer insulating film 43 are made of an insulating material such as a silicate glass film, a silicon nitride film, or a silicon oxide film.

In the lower region of the transistor 30, as shown in FIGS. 2 and 3, a lower light-shielding film 11a is provided. The lower light-shielding film 11a is patterned in a lattice pattern, thereby defining an opening area of each pixel.
Note that the opening region is defined by the intersection of the data line 6a extending in the vertical direction in FIG. 2 and the capacitor line 300 extending in the horizontal direction in FIG.
Similarly to the case of the capacitance line 300, the lower light-shielding film 11a is also extended from the image display region to the periphery thereof in order to prevent the potential fluctuation from adversely affecting the transistor 30. Connect to a constant potential source.

  A counter electrode 21 is provided on the entire surface of the counter substrate 20, and an alignment film 22 subjected to a predetermined alignment process such as a rubbing process is provided below the counter electrode 21. The counter electrode 21 is formed of a transparent conductive film such as an ITO film, for example, like the pixel electrode 9a described above, and the alignment film 22 is formed of a transparent organic film such as a polyimide film. The liquid crystal layer 50 sandwiched between the substrates 10 and 20 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films 16 and 22.

(Overall configuration of liquid crystal display device)
The overall configuration of the liquid crystal display device configured as described above will be described with reference to FIG. 5A is a plan view of the liquid crystal display device as viewed from the counter substrate 20 side, and FIG. 5B is a liquid crystal display device taken along the line HH ′ shown in FIG. 5A. FIG.

  In the liquid crystal display device, as shown in FIGS. 5A and 5B, the element substrate 10 and the counter substrate 20 are arranged to face each other. A liquid crystal layer 50 is sealed between the element substrate 10 and the counter substrate 20, and the element substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region located around the image display region 10a. Are bonded to each other. Further, in the sealing material 52, a gap material (spacer) such as glass fiber or glass beads for dispersing the distance between the two substrates (inter-substrate gap) to a predetermined value is dispersed.

  In a region outside the sealing material 52, a data line driving circuit 101 and an external circuit connection terminal 102 for driving the data line 6a by supplying an image signal to the data line 6a at a predetermined timing along one side of the element substrate 10. A scanning line driving circuit 104 that drives the scanning line 3a by supplying a scanning signal to the scanning line 3a at a predetermined timing is provided along two sides adjacent to the one side.

  On the remaining side of the element substrate 10, a plurality of wirings 105 are provided for connecting between the scanning line driving circuits 104 provided on both sides of the image display area 10a. Further, at least one corner portion of the counter substrate 20 is provided with a conductive material 106 for electrical connection between the element substrate 10 and the counter substrate 20.

(Manufacturing method of liquid crystal display device)
Next, a method for manufacturing the liquid crystal display device will be described.
First, in FIG. 6A, a substrate body (supporting substrate) 10 </ b> A made of a glass substrate is prepared as a substrate material constituting the element substrate 10. Here, preferably, annealing is performed at a high temperature of about 850 to 1300 ° C., more preferably 1000 ° C. in an inert gas atmosphere such as N ₂ (nitrogen), and distortion generated in the element substrate 10 in a high-temperature process to be performed later is performed. Pre-processing to reduce is performed.

  On the entire surface of the substrate main body 10A thus treated, a single metal, an alloy, a metal silicide, or the like containing at least one of Ti, Cr, W, Ta, Mo, and Pd is formed by sputtering or the like. A light shielding layer having a thickness of about 500 nm, preferably about 200 nm is formed. Thereafter, the lower light-shielding film 11a is formed in a predetermined pattern by photolithography and etching.

Subsequently, on the lower light-shielding film 11a, for example, TEOS (tetraethyl orthosilicate) gas, TEB (tetraethyl boatate) gas, TMOP (tetramethylmethyl) by atmospheric pressure or reduced pressure CVD method or the like.・ Silicate glass films such as NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride film, using oxy-phosphorate gas, etc. Then, a base oxide film 12 made of a silicon oxide film or the like is formed.
Next, the surface of the base oxide film 12 is polished using a method such as CMP (Chemical Mechanical Polishing), and the surface of the base oxide film 12 is planarized as shown in FIG. The thickness of the base oxide film 12 is about 400 to 1000 nm, more preferably about 800 nm.

  Subsequently, the substrate main body 10A and the single crystal silicon substrate 200 having the plane orientation (100) are bonded to each other. First, the single crystal silicon substrate 200 is prepared. Here, the single crystal silicon substrate 200 has a bonded surface (referred to as a back surface side in the following description) for polishing, and has a thickness of about 5 to 150 μm. The substrate body 10A shown in FIGS. 7A to 7D is a part of FIG. 6B taken out and shown at a different scale, and the illustration of the lower light shielding film 11a is omitted. Yes.

  As shown in FIG. 7A, a silicon oxide film (adhesion film) 210 is formed by thermally oxidizing the back surface side of the single crystal silicon substrate 200. Here, the base oxide film 12 and the silicon oxide film 210 described above are formed to ensure adhesion between the single crystal silicon substrate 200 and the substrate body 10A. The thickness of the silicon oxide film 210 may be equal to or greater than the thickness at which the bonding surface becomes hydrophilic in a bonding process described later, but specifically, in this embodiment, the silicon oxide film 210 is formed to have a thickness of about 200 nm.

In addition, hydrogen ions (H ⁺ ) are implanted into the single crystal silicon substrate 200 at, for example, an acceleration voltage of 100 keV and a dose of 10 × 10 ¹⁶ / cm ² . This ion implantation process is for controlling the film thickness of the single crystal silicon layer that is generated from the single crystal silicon substrate 200 and forms the semiconductor layer. The hydrogen ion acceleration voltage is changed to change the hydrogen ion implantation depth. Thus, a single crystal silicon layer having a desired film thickness can be formed on the substrate body 10A. 7A to 7C indicate the position of the hydrogen ion implantation layer 205 in the ion implantation process.

  Next, as shown in FIG. 7B, the surface on the oxide film 210 side of the single crystal silicon substrate 200 and the surface on the base oxide film 12 side of the substrate body 10A are joined together, and the oxide films 210 and 12 are bonded. Then, the single crystal silicon substrate 200 is bonded. As a specific bonding process, for example, a method of directly bonding two substrates by heat treatment at 300 ° C. for 2 hours was adopted. Therefore, due to the action of the OH group on the substrate surface, the single crystal silicon substrate 200 and the substrate body 10A are bonded together via the insulating layers (oxide films 210 and 12) 15 as shown in FIG. Thereafter, it is desirable to further increase the bonding strength by performing heat treatment again at 450 ° C.

Next, the single crystal silicon substrate 200 bonded to the substrate body 10A is thinned to about 200 nm, for example, to form a single crystal silicon layer.
This thinning is performed by subjecting the bonded single crystal silicon substrate 200 and the substrate body 10A to a heat treatment at 350 ° C. to 700 ° C. in an inert gas atmosphere such as nitrogen or argon, whereby the position of the hydrogen ion implanted layer 205 is changed. A part of the single crystal silicon substrate 200 is peeled off. Note that the single crystal silicon substrate 200 after peeling can be used as it is for manufacturing other single crystal silicon layers.

This exfoliation phenomenon occurs because a microcavity is generated by ions implanted in the defect layer region formed in the hydrogen ion implantation layer 205 and the bonding of the semiconductor crystal is broken, and the ion concentration in the hydrogen ion implantation layer 205 is reduced. The peak position becomes more prominent. That is, the position peeled off by the heat treatment substantially coincides with the peak position of the ion concentration, that is, the hydrogen ion implanted layer 205.
Through the above steps, a single crystal silicon layer 201 of about 200 nm ± 5 nm is formed on the substrate body 10A via the insulating layer 15.

  By the way, the film thickness of the single crystal silicon layer 201 can be arbitrarily formed in the range of, for example, 10 nm to 3000 nm by changing the acceleration voltage of hydrogen ion implantation performed on the single crystal silicon substrate 200 described above. Note that the method of obtaining the thinned single crystal silicon layer 201 is not limited to the above-described method and process, and after polishing the surface of the single crystal silicon substrate 200 to a film thickness of 3 to 5 μm, A method in which the film thickness is etched to about 0.05 to 0.8 μm by the PACE (Plasma Assisted Chemical Etching) method or an epitaxial silicon layer formed on the porous silicon is pasted by selective etching of the porous silicon layer. It can also be obtained by other general manufacturing methods for SOI substrates such as ELTRAN (Epitaxial Layer Transfer) method for transferring onto a laminated substrate.

Next, the single crystal silicon layer 201 is etched to form a semiconductor layer 1a constituting a transistor.
First, as shown in FIG. 8A, after the surface of the single crystal silicon layer 201 is thermally oxidized to form a thermal oxide film (SiO ₂ film), the mask M is formed by patterning the thermal oxide film. Form. A SiO ₂ film or a Si ₃ N ₄ film is formed on the single crystal silicon layer 201 by a known method such as a sputtering method or a CVD method, and a mask M patterned into a shape corresponding to the switching element is formed. .

  Next, as shown in FIG. 8B, the single crystal silicon layer 201 is etched using the mask M using a mixed solution having a hydrofluoric acid concentration of 0.05% to 2% and an ozone concentration of 3 to 50 ppm as an etchant. To do. Note that “%” for the above-mentioned concentration regulation means weight percent (wt%).

  Here, FIG. 9 shows data of the etching rate of the thermal oxide film and the etching rate of the Si substrate by the mixed liquid of hydrofluoric acid and ozone water. As shown in FIG. 9, when a mixed solution of hydrofluoric acid and ozone is used, the etching rate of Si (silicon), that is, the single crystal silicon layer 201 depends on the ozone concentration. Accordingly, the etching rate of the thermal oxide film and the etching rate of the Si substrate can be arbitrarily set by appropriately selecting the hydrofluoric acid and ozone concentrations.

The practical range of the mixing ratio is 0.05 to 2% hydrogen fluoride and 3 to 50 ppm ozone. At this time, the etching rate of the mask M composed of the thermal oxide film (SiO ₂ film) is 0.5 to 13 nm / min, and the etching rate of the single crystal silicon layer 201 is about 15 to 100 nm / min. In this embodiment, a mixed solution of 0.05% hydrogen fluoride and 50 ppm of ozone is used as an etching solution, and an etching selectivity between the mask (thermal oxide film) 13 and the single crystal silicon substrate 200 is sufficiently ensured.

  In the present embodiment, since the single crystal silicon substrate 200 with the plane orientation (100) is etched as described above, the trapezoidal semiconductor layer 1a whose side surface becomes the inclined surface 35 as shown in FIG. 8B. Is formed. This is because, when the single crystal silicon substrate 200 is etched, the (110) plane, which has a slower etching rate than the (100) plane, precipitates to form an inclined plane.

By the way, the roughened surface of the etching surface using the above-mentioned mixed liquid can be reduced. FIG. 10 shows a measurement result in a state of surface roughness of the semiconductor layer 1a after the etching process using the above mixed solution.
As shown in FIG. 10, for example, when the etching process is performed with a mixed solution (APM) of ammonia and hydrogen peroxide, Ra = 2 or more, and the surface roughness of the single crystal silicon layer 201 becomes severe.

  On the other hand, if the present invention is adopted, the surface roughness Ra = 0.18 in bare Si (single crystal silicon substrate 200) before etching with a mixed solution of hydrofluoric acid and ozone water. When etched with the mixed solution, Ra = 0.14, and it was confirmed that the surface roughness was reduced. That is, the semiconductor layer 1a with less surface roughness can be formed by etching the single crystal silicon layer 201 using a mixed liquid of hydrofluoric acid and ozone water as in this embodiment. Further, no by-product due to etching is formed on the surface etched using the above mixed solution.

Therefore, when the single crystal silicon layer 201 is etched, a liquid mixture of hydrofluoric acid and ozone water is used, so that defects due to surface roughness due to etching can be prevented and the semiconductor layer 1a having a low interface state density can be obtained. The semiconductor layer 1a is for constituting the transistor 30 which is a switching element of the liquid crystal display device described above.
After etching with a mixture of hydrofluoric acid and ozone water, it is washed with water and dried in a dryer. Then, after removing the mask M, the process proceeds to the next step.

  The treatment method using a mixed solution of hydrofluoric acid and ozone water described above may be a batch method in which the mixed solution is immersed in a mixed solution, or a single wafer method in which the mixed solution is discharged from a nozzle and processed one by one. If the hydrofluoric acid concentration range and the ozone concentration range are the above-described concentration ranges, a sequence in which ozone is continuously generated and the chemical solution is discarded may be used, or a circulation system that dissolves ozone gas into the circulating hydrofluoric acid solution may be used.

  Next, as shown in FIG. 11A, the semiconductor layer 1a is thermally oxidized to form the gate insulating film 2. Here, the temperature at which the gate insulating film 2 is formed by thermal oxidation is controlled to be 950 ° C. or lower, preferably 850 ° C. or lower. Here, the thickness of the gate insulating film 2 is about 2 to 150 nm, preferably about 30 to 100 nm.

  Next, as shown in FIG. 11B, a polysilicon film is deposited to a thickness of about 100 to 500 nm by a low pressure CVD method or the like, and P (phosphorus) is further thermally diffused to make the polysilicon film conductive. Then, a scanning line 3a having a predetermined pattern and including the gate electrode 3a (see FIG. 3) is formed in the image display region 10a by a photolithography process, an etching process, or the like.

  Since the gate electrode 3a has a substantial gate width as described above, a large amount of current can flow between the source and the drain, and a high-performance switching element can be configured.

  Next, by doping impurity ions in two steps of low concentration and high concentration, a low concentration source region 1b, a low concentration drain region 1c, a high concentration source region 1d, and a high concentration drain region 1e (see FIG. 3) are included. Then, a pixel switching semiconductor layer 1a having an LDD structure is formed in the image display region.

For example, when a P-channel LDD region is formed in the semiconductor layer 1a, first, a dopant (impurity) of a group III element such as B is formed at a low concentration (for example, an acceleration voltage of 90 keV for BF ₂ ions, 3 × 10 3 Doping is performed (with a dose of ¹³ / cm ² ) to form a low concentration source region and a low concentration drain region of the P channel. Thereafter, a dopant of a Group III element such as B is doped at a high concentration (for example, BF ₂ ions are accelerated at a voltage of 90 keV and a dose of 2 × 10 ¹⁵ / cm ² ) to form a high concentration source region of the P channel. And a high concentration drain region is formed.

Alternatively, when an N-channel LDD region is formed, first, a dopant (impurity) of a group V element such as P is formed at a low concentration (for example, P ions are accelerated at 70 keV, 6 × 10 ¹² / cm ² ). Doping is performed to form an N channel low concentration source region and a low concentration drain region. Thereafter, a dopant of a group V element such as P is doped at a high concentration (for example, P ions are applied at an acceleration voltage of 70 keV and a dose of 4 × 10 ¹⁵ / cm ² ), and an N-channel high concentration source region and A high concentration drain region is formed.

  Next, as shown in FIG. 11C, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like using atmospheric pressure or reduced pressure CVD, TEOS gas, or the like. A first interlayer insulating film 41 made of is formed.

  Subsequently, a polysilicon film is deposited by a low pressure CVD method or the like, and phosphorus (P) is further thermally diffused, and this polysilicon film is made conductive to form a relay layer 71. Then, after depositing a dielectric film 75 made of a high temperature silicon oxide film (HTO film) or silicon nitride film to a relatively thin thickness of about 50 nm by low pressure CVD method, plasma CVD method or the like, Ti, Cr, W, The capacitor line 300 is formed by sputtering a metal alloy film such as a metal such as Ta, Mo, and Pd or a metal silicide. As a result, the storage capacitor 70 is formed in the image display area 10a.

  Thereafter, the second interlayer insulating film 42 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed using, for example, atmospheric pressure or low pressure CVD method, TEOS gas, or the like. .

  Subsequently, after a contact hole is formed by dry etching such as reactive ion etching or reactive ion beam etching for the second interlayer insulating film 42, the entire surface on the second interlayer insulating film 42 is shielded from light by sputtering or the like. A low-resistance metal such as Al or metal silicide is deposited as a metal film to a thickness of about 100 to 500 nm, preferably about 300 nm. Then, the data line 6a having a predetermined pattern is formed in the image display area 10a by photolithography and etching.

  Here, the first interlayer insulating film 41, the second interlayer insulating film 42, and the dielectric film 75 that have already been formed are baked at 950 ° C. or lower, preferably 850 ° C. or lower, thereby forming the semiconductor layer 1a. Activation of ions implanted into the substrate may be achieved. In addition, this baking may be performed collectively as mentioned above, and may be performed separately, and is not specifically limited.

Next, as shown in FIG. 8D, the silicon oxide film is formed on the surface of the second interlayer insulating film 42 located in the opening region of each pixel and the data line 6a using, for example, atmospheric pressure or low pressure CVD. A third interlayer insulating film 43 is formed thereon.
Next, as shown in FIG. 8E, a contact hole 85 is formed by dry etching such as reactive ion etching or reactive ion beam etching for the third interlayer insulating film 43.

Thereafter, an ITO film is formed on the third interlayer insulating film 43 by sputtering or the like. Then, the pixel electrode 9a is formed by performing photolithography and etching on the ITO film. Thereafter, an alignment film 16 is formed by applying a polyimide-based alignment film coating solution thereon and further performing a rubbing treatment in a predetermined direction so as to have a predetermined pretilt angle (see FIG. 3). .
Through the above steps, the active matrix substrate 10 configured using the substrate for the electro-optical device in which the semiconductor layer 1a is formed on the substrate body 10A via the insulating layer 15 is formed.

  Then, a substrate body 20A made of a glass substrate constituting the counter substrate 20 is prepared, and a light-shielding film 53 as a peripheral parting is formed on the surface of the substrate body 20A. The light shielding film 53 serving as a peripheral parting is formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, and Al. These light shielding films 53 may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist in addition to the metal material.

  Thereafter, a transparent conductive thin film such as ITO is deposited to a thickness of about 50 to 200 nm on the entire surface of the counter substrate 20 by sputtering or the like to form the counter electrode 21. Further, the alignment film 22 is applied to the entire surface of the counter electrode 21 by applying a coating solution of an alignment film such as polyimide, and then performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. Form. The counter substrate 20 is manufactured as described above.

  Finally, the element substrate 10 and the counter substrate 20 manufactured as described above are bonded together by the sealing material 52 so that the alignment films 16 and 22 face each other. Then, a liquid crystal layer 50 having a predetermined thickness is formed by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystal into the space between both substrates by a method such as a vacuum suction method. Thereby, the liquid crystal display device mentioned above can be manufactured.

  Further, the thin film formed on the Si substrate is not necessarily limited to the oxide film, and any material can be used as long as the etching selectivity with respect to the substrate Si can be obtained with respect to the mixed liquid of hydrofluoric acid and ozone water. Further, the concentration of each material in the mixed solution of hydrofluoric acid and ozone water may be appropriately changed according to the etching selectivity required for the thin film used as the mask and the substrate. Further, for example, the cleaning liquid may be switched from hydrofluoric acid and ozone water to a hydrofluoric acid solution to remove the oxide film used as a mask material.

According to the manufacturing method of the liquid crystal display device according to the present embodiment, since the single crystal silicon substrate 200 is patterned by wet etching using a mixed liquid of hydrofluoric acid and ozone water, generation of by-products during etching is generated. By preventing damage such as surface roughness, the semiconductor layer 1a having low defects and low interface states can be formed on the supporting substrate 10A. By using such a semiconductor layer 1a, a high-performance transistor 30 with little leakage current can be manufactured.
Therefore, it is possible to provide a liquid crystal device that is capable of high-speed driving with the high-performance transistor 30.

  Next, another embodiment of the above-described electro-optical device will be described. A semiconductor device having a CMOS (complementary metal oxide semiconductor) structure that forms a peripheral circuit in a liquid crystal display device is formed in advance on the single crystal silicon substrate 200 used in the above embodiment.

Below, this embodiment is described with reference to FIG. In the single crystal silicon substrate 200 according to the present embodiment, a CMOS portion 200 cmos is formed in advance. The CMOS portion 200 cmos is formed by a conventionally known method. As shown in FIG. 12A, the n-well region 203 n and the p-well region 203 p are interposed via an element isolation region 204 made of, for example, SiO _2. The pMOS portion 200p and the nMOS portion 200n are formed in the respective well regions 203n and 203p.

The CMOS portion 200 cmos is covered with a protective film 207 for protecting the p-MOS and n-MOS from contamination and humidity. This protective film 207 is made of, for example, SiO ₂ or Si ₃ N _4, and SiO ₂ is used in this embodiment. In addition to protecting the CMOS portion 200 cmos, the protective film 207 is used as a mask when forming the semiconductor layer 1 a as described later.

  First, as shown in FIG. 12B, the back surface of the single crystal silicon substrate 200 (the side where the protective film 207 is not formed) is polished to form a single crystal silicon layer 201 having a thickness of 5 to 150 μm. Form. Then, after forming a thermal oxide film on the polished surface as in the above embodiment, as shown in FIG. 12C, a single crystal silicon layer 201 covered with a protective film 207, a substrate body 10A made of a glass plate, Paste together.

  Subsequently, by using a conventionally known photolithography process, the protective film 207 covers a portion corresponding to the region where the semiconductor layer 1a is formed and the CMOS portion 200cmos as shown in FIG. Separate into parts.

  Similarly to the above-described embodiment, the single crystal silicon layer 201 in which the CMOS portion 200 cmos is formed is etched using a mixed solution of hydrofluoric acid and ozone water as an etching solution. A high performance semiconductor layer 1a can be obtained. Thereafter, the transistor 30 can be formed from the semiconductor layer 1a as in the above embodiment.

  According to the manufacturing method of the liquid crystal display device according to the present embodiment, by forming the peripheral circuit including the CMOS portion 200 cmos in advance on the single crystal silicon substrate 10 as described above, the degree of freedom in circuit design is increased and the density is increased. A liquid crystal display device capable of designing various high-performance circuits can be provided.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention.
For example, in the above-described embodiment, the present invention has been described as being applied to a liquid crystal display device. However, the present invention is not limited to a liquid crystal display device, and other electro-optical devices, for example, an SOI substrate such as a plasma display device may be used. It can be applied to all devices used.

It is a figure which shows the equivalent circuit in a liquid crystal display device. It is a top view of an element substrate. It is a sectional side view in the AA 'arrow of FIG. It is a perspective view which shows schematic structure of a transistor. (A), (b) is a figure which shows the whole structure of a liquid crystal display device. It is a figure explaining the manufacturing process of a liquid crystal display device. FIG. 7 is a diagram for explaining a manufacturing process for the liquid crystal display device following FIG. 6. FIG. 8 is a diagram for explaining a manufacturing process for the liquid crystal display device following FIG. 7. It is a figure which shows the etching rate of Si substrate by a liquid mixture. It is a figure which shows the measurement result of the state of the surface roughness of Si substrate. FIG. 9 is a diagram for explaining a manufacturing process for the liquid crystal display device following FIG. 8. It is a figure which shows the manufacturing process of the liquid crystal display device which concerns on other embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1a ... Semiconductor layer, 30 ... Transistor (switching element), 10A ... Support substrate, 200 ... Single crystal silicon substrate, 200 cmos ... CMOS part (semiconductor device), 210 ... Silicon oxide film (adhesion film)

Claims (5)

Forming an adhesive film on one surface of the single crystal silicon substrate, and bonding the side on which the adhesive film is formed to a support substrate;
Forming a semiconductor layer comprising the single crystal silicon substrate by etching and patterning the single crystal silicon substrate using a mixed solution of hydrofluoric acid and ozone water; and
And a step of forming a switching element by using the semiconductor layer.   2. The method of manufacturing an electro-optical device according to claim 1, wherein the single crystal silicon substrate has a plane orientation (100).   3. The method of manufacturing an electro-optical device according to claim 1, wherein the adhesive film made of silicon oxide is formed by thermally oxidizing the single crystal silicon substrate.   The method for manufacturing an electro-optical device according to claim 1, wherein the single crystal silicon substrate is a substrate on which a semiconductor device is formed in advance. The method of manufacturing an electro-optical device according to claim 4, wherein the semiconductor device is a CMOS.

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