JP2001102322A - Method for manufacturing semiconductor device and electro-optical device, and devices manufactured thereby - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a semiconductor device without adversely affecting a gate oxide film and a dielectric layer, and the semiconductor device and the electro-optical device manufactured by the method. SOLUTION: A semiconductor layer 201 is disposed on a substrate 200, a first insulating film 202 is formed to coat the semiconductor layer 201, and then impurity ions are implanted into the semiconductor layer 201. Subsequent to the process, a second insulating film is formed to coat the first insulating film to obtain a semiconductor device 204 with a gate-insulated film laminated with the first and the second insulating films. As a result, the gate-insulated film can be manufactured with high breakdown voltage, without defects such as pin holes, and the like.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and a method for manufacturing an electro-optical device, and more particularly to a method for implanting ions into a semiconductor layer through an insulating film formed over the semiconductor layer. It belongs to the technical field of the manufacturing method of the semiconductor device and the manufacturing method of the electro-optical device.

[0002]

2. Description of the Related Art In order to improve a conductive layer of a semiconductor layer of a thin film transistor (hereinafter, appropriately referred to as a TFT) formed on a substrate of an electro-optical device, a technique of implanting impurity ions such as phosphorus and boron into the semiconductor layer. It has been known. In addition, T as a switching element formed for each pixel
A structure in which the FT and the storage capacitor are formed simultaneously is known. In this case, the number of manufacturing steps can be reduced by using the semiconductor layer of the thin film transistor as one of the electrodes of the storage capacitor and using the gate oxide film provided on the semiconductor layer as the dielectric film. In this case, by implanting impurity ions into the region of the semiconductor layer forming the electrode of the storage capacitor, the resistance of this region can be reduced.

[0005] The above-described ion implantation is performed via a gate insulating film formed in advance on a semiconductor layer. By implanting through the gate insulating film, the implantation concentration can be made uniform in the thickness direction of the semiconductor layer.

[0004]

However, when impurity ions are implanted through a gate insulating film which also serves as a part of a dielectric film, the ion implantation damages the gate oxide film and causes defects such as pinholes. Can occur,
Deterioration of the withstand voltage characteristic in a region facing the gate electrode or a region serving as a dielectric layer of the storage capacitor may cause a problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems. Even if a gate insulating film is damaged, a short circuit failure due to a defect such as a pinhole originally caused by a foreign substance or the like at the time of film formation may occur. It is an object of the present invention to provide a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, and a semiconductor device and an electro-optical device manufactured by these methods, which prevent the problem and improve the breakdown voltage characteristics of the gate insulating film.

[0006]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor layer on a substrate; forming a first insulating film on the semiconductor layer; A step of implanting impurity ions into the semiconductor layer through a film; and a step of forming a second insulating film on the first insulating film.

In the present invention, by adopting such a structure, even if a defect occurs in the first insulating film due to the impurity ion implantation step, the second insulating film is formed to cover the first insulating film. Defects can be buried by the insulating film, which has an effect of preventing occurrence of defects. In addition, the formation of the second insulating film has an effect of improving the withstand voltage characteristics of the entire insulating film.

Further, the first insulating film is made of a silicon oxide film. By using an oxide film as the first insulating film in this manner, compared to the case of using a nitride film, the effect of reducing damage to the insulating film due to impurity ion implantation and reducing the incidence of defects in the first insulating film can be obtained. Have. When impurity ions are implanted into a semiconductor layer through an insulating film, when a silicon oxide film is used as an insulating film and when a silicon nitride film is used, the same is applied to the semiconductor layer through an insulating film having the same thickness. In order to implant a large amount of impurity ions, a larger amount of energy is required when a silicon nitride film is used than when a silicon oxide film is used. Therefore, in the case of using a silicon nitride film, the required amount of energy is larger than in the case of using a silicon oxide film, so that the insulating film is more damaged by impurity ion implantation. It is effective to use.

Further, the second insulating film is made of a silicon nitride film. With such a structure, the nitride film has a higher relative dielectric constant than the oxide film. Therefore, when a film having the same dielectric constant and the same area is formed, the nitride film should be thicker than the oxide film. Therefore, there is an effect that defects such as pinholes generated in the first insulating film can be reliably filled.

[0010] The method further comprises the step of forming a third insulating film on the second insulating film. With such a configuration, there is an effect that defects such as pinholes generated in the first insulating film can be more reliably filled with the second insulating film and the third insulating film.

Further, the third insulating film is made of a silicon oxide film. Here, a semiconductor layer is used as a storage capacitor electrode, and a structure is formed in the data line on the second insulating film, and an image signal having both positive and negative electrodes with respect to the potential of the storage capacitor electrode is supplied to the data line. In such a case, a nitride film, an oxide film,
The use of a nitride film results in a structure in which the nitride film is sandwiched between two oxide films, which makes it possible to suppress the pool-Frenkel current caused by holes in the nitride film and reduce the leakage current. Have.

According to the method of manufacturing an electro-optical device of the present invention, a step of forming a semiconductor layer partially serving as a storage capacitor electrode on a substrate; a step of forming a first insulating film so as to cover the semiconductor layer; Implanting impurity ions into the semiconductor layer serving as the storage capacitor electrode via the first insulating film; forming a second insulating film on the first insulating film; (2) forming a conductive layer on the insulating film;
It is characterized by having.

According to the present invention, the second insulating film is formed to cover the first insulating film even if a defect occurs in the first insulating film due to the impurity ion implantation step. Defects can be embedded with the insulating film. Accordingly, there is an effect that an electro-optical device in which a conductive layer and a semiconductor layer formed over the second insulating film do not short-circuit and have no short-circuit defect is obtained. In addition, the formation of the second insulating film has an effect of improving the withstand voltage characteristics of the entire insulating film.

In the method of manufacturing an electro-optical device according to the present invention, a step of forming a region to be a channel and a region to be one electrode for a storage capacitor on a substrate by a semiconductor layer; Forming a first insulating film on the region to be the first electrode; selectively implanting impurity ions into the region to be the first electrode through the first insulating film; Forming a second insulating film on the insulating film, forming a conductive layer on the second insulating film, patterning the conductive layer, and forming a gate electrode on a region to be the channel; Forming a region to be the other electrode for the storage capacitor on the region to be an electrode.

According to this structure, the gate electrode and the other electrode for the storage capacitor can be formed at the same time, and the effect is that the production efficiency is good. Further, even if a defect occurs in the first insulating film due to the impurity ion implantation step, the second insulating film is formed to cover the first insulating film, so that the defect can be embedded by the second insulating film. Accordingly, there is an effect that an electro-optical device in which a conductive layer and a semiconductor layer formed over the second insulating film do not short-circuit and have no short-circuit defect is obtained. In addition, the formation of the second insulating film has an effect of improving the withstand voltage characteristics of the entire insulating film. In particular, one electrode for the storage capacitor often has a higher impurity concentration than implantation of impurity ions for forming the source / drain regions. There is a high possibility that film defects will occur. Even in such a case, a defect can be filled with the second insulating film because the second insulating film is formed after the step of implanting impurity ions into a region to be one electrode. Further, since impurity ions are implanted into the semiconductor layer after the formation of the first insulating film, damage to the semiconductor layer due to the impurity ion implantation step can be reduced.

Further, the first insulating film is made of a silicon oxide film. By using an oxide film as the first insulating film in this manner, as compared with the case of using a nitride film, damage to the insulating film due to impurity ion implantation is reduced, the incidence of defects in the first insulating film is reduced, and the conductivity is further reduced. This has the effect of reducing the rate of occurrence of short circuits between the semiconductor layer and the semiconductor layer. When impurity ions are implanted into a semiconductor layer through an insulating film, when a silicon oxide film is used as an insulating film and when a silicon nitride film is used, the same is applied to the semiconductor layer through an insulating film having the same thickness. In order to implant a large amount of impurity ions, a larger amount of energy is required when a silicon nitride film is used than when a silicon oxide film is used. Therefore, in the case of using a silicon nitride film, compared with the case of using a silicon oxide film,
The greater the amount of energy required, the greater the damage to the insulating film due to the impurity ion implantation, so that it is effective to use an oxide film as the first insulating film.

Further, the second insulating film is made of a silicon nitride film. With such a structure, the nitride film has a higher relative dielectric constant than the oxide film. Therefore, when a film having the same dielectric constant and the same area is formed, the nitride film should be thicker than the oxide film. Therefore, there is an effect that defects such as pinholes generated in the first insulating film can be reliably filled.

A semiconductor device according to the present invention is manufactured by the above-described manufacturing method. With such a structure, the insulating property of the insulating film covering the semiconductor layer is improved, and an effect of obtaining a semiconductor device free from a short circuit due to a defect in the insulating film is obtained.

An electro-optical device according to the present invention is manufactured by the above-described method for manufacturing an electro-optical device. With such a configuration, there is an effect that an electro-optical device with excellent display quality without display defects is obtained.

Here, a semiconductor layer constituting the switching element and a semiconductor layer functioning as a storage capacitor electrode are formed so as to be electrically connected to each other, a storage capacitor line is arranged as a conductive layer, and the semiconductor layer is connected through a drain electrode. In the case of an electro-optical device having a structure electrically connected to a pixel electrode, a constant voltage is always applied to the storage capacitor line, so that the storage capacitor line and the storage capacitor electrode are short-circuited due to a defect in the insulating film. In such a case, a voltage is always applied to the pixel electrode, and there is a problem that an arbitrary display cannot be performed on the corresponding pixel. On the other hand, in the present invention, since there is no defect defect in the insulating film covering the semiconductor layer, such a display defect can be prevented.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device having a substrate on which a semiconductor layer is arranged according to the present invention will be described below with reference to FIG. FIG. 1 is a process diagram showing a manufacturing process of a semiconductor substrate.

As shown in FIG. 1C, the semiconductor device 20
4 is a substrate 200 such as a quartz substrate or a hard glass.
A semiconductor layer 201 made of a polysilicon film is disposed thereon, and a gate insulating layer is formed by sequentially stacking a silicon oxide film 202 as a first insulating film and a silicon nitride film 203 as a second insulating film so as to cover the semiconductor layer 201. A membrane is located.

A method for manufacturing a semiconductor device will be described below.

First, as shown in FIG. 1A, a quartz substrate 200 is prepared. Here, when a high-temperature process is included in the post-process, preferably, the quartz substrate is previously annealed in an inert gas atmosphere such as nitrogen and at a high temperature of about 900 to 1300 ° C., so that the distortion generated in the substrate due to the heat treatment is reduced. Pre-process as follows.

On such a quartz substrate 200, 450 to
In a relatively low-temperature environment of 550 ° C., preferably about 500 ° C., a reduced pressure C using monosilane gas, disilane gas, etc.
Amorphous silicon is formed by VD (for example, CVD at a pressure of about 20 to 40 Pa). Thereafter, the semiconductor layer 201 made of a polysilicon film is solid-phase grown to a thickness of about 50 to 200 nm by performing an annealing process at about 600 to 700 ° C. for about 1 to 10 hours in a nitrogen atmosphere.

Next, as shown in FIG. 1B, a mixed gas of TEOS (tetraethylorthosilicate) and oxygen gas is formed on the semiconductor layer 201 made of a polysilicon film by a plasma CVD method. ~ 50 nm,
Here, a silicon oxide film 202 with a thickness of 20 nm was formed. After that, P (phosphorus) as an impurity ion is added to the semiconductor layer 201 through the silicon oxide film 202, for example.
The implantation is performed at a dose of about 3 × 10 ¹⁵ / cm ² . Here, the thickness of the first insulating film formed before the impurity ion implantation step is desirably 10 nm or more, whereby the impurity ion concentration in the thickness direction of the semiconductor layer can be made uniform. When the thickness is 50 nm or less, the acceleration energy at the time of ion implantation can be reduced, damage to the polysilicon film can be reduced, and amorphousization can be prevented. In the case of using a resist mask, it is possible to prevent the resist from hardening after the implantation and to prevent the resist from remaining.

Next, as shown in FIG. 1C, a silicon nitride film 203 having a thickness of 20 to 100 nm, here 30 nm, is formed on the silicon oxide film 202 by a plasma CVD method using a monosilane gas and an ammonia gas. Was formed to obtain a gate insulating film in which a silicon oxide film 202 and a silicon nitride film 203 were stacked.

In the present embodiment, since impurity ions are implanted into the semiconductor layer via the first insulating film and then the second insulating film is formed, defects such as pinholes generated in the first insulating film due to the impurity ion implantation are eliminated. A gate insulating film which can be filled with the second insulating film and has no defect can be obtained. In addition, the formation of the second insulating film has an effect of improving the breakdown voltage characteristics of the gate insulating film. Here, it is desirable that the thickness of the second insulating film formed after the impurity ion implantation step be 20 nm or more, whereby defects such as pinholes generated in the first insulating film can be reliably filled. It is better to make the second insulating film thicker than the first insulating film.

In this embodiment, the gate insulating film has a two-layer structure, but may have a multilayer structure of three or more layers, such as a three-layer structure in which a silicon oxide film is formed on a second insulating film. In this case, a step of forming an insulating film at least once before and after the impurity ion implantation step is sufficient.

In this embodiment, a silicon oxide film is used as the first insulating film and a silicon nitride film is used as the second insulating film. However, the first insulating film is a silicon nitride film, the second insulating film is a silicon oxide film, Alternatively, both may be the same insulating film, and are not limited to this embodiment.

However, by using an oxide film as an insulating film formed before the impurity ion implantation step as in this embodiment, damage due to impurity ion implantation can be reduced as compared with the case where a nitride film is used. Therefore, it is effective to use an oxide film as the first insulating film. Here, for example, in the case of using the case where phosphorous ions 1 to 5 15 ^/ cm ² dose to the semiconductor layer via an insulating film having a film thickness of 75nm is injected, an oxide film as an insulating film 50k
While energy of eV is required, energy of 60 to 70 keV is required when a nitride film is used, and less energy is required when an oxide film is used. Therefore, when an oxide film is also used as an insulating film, damage due to impurity ion implantation can be reduced. When a resist is still used, it is possible to prevent the resist from hardening after the implantation and to prevent the resist from remaining.

Further, by using a nitride film as an insulating film formed after the impurity ion implantation step, it is possible to make the film thickness thicker when the same dielectric constant is used than when an oxide film is used. Therefore, a thick second insulating film can be formed, and defects such as pinholes generated in the first insulating film can be reliably filled.

Next, an embodiment in which the present invention is applied to a liquid crystal device as an electro-optical device will be described with reference to the drawings.

The structure of the liquid crystal device according to the present invention will be described with reference to FIGS. FIG. 2 is a plan view showing a pixel display area of the liquid crystal device and a peripheral drive circuit area which is arranged around the pixel display area and has a peripheral drive circuit for driving the pixel display area. FIG. 3 is a plan view of a plurality of pixel groups in a pixel display area of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 4 is a longitudinal sectional view of a pixel display region and a peripheral driving circuit region of the liquid crystal device, and the longitudinal sectional view of the pixel region is a sectional view taken along line AA ′ of FIG. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

In FIG. 2, the liquid crystal device has a pixel display area having a scanning line 3 and a data line 6 which intersect each other, and a scanning line for supplying a drive signal to each of the scanning line 3 and the data line 6. The driving circuit 104 includes a peripheral driving circuit area in which the data line driving circuit 101 is arranged.

The image display area includes a capacitor line 3b and a scanning line 3, which are arranged in parallel, a data line 6 which intersects with the scanning line 3, and an intersection of the scanning line 3 and the data line 6. Pixel electrodes 9a arranged in a matrix, and thin film transistors (hereinafter, TFTs) for controlling the pixel electrodes 9a.
30). The source of the TFT 30 is electrically connected to the data line 6 to which the image signal is supplied, and the gate of the TFT 30 is electrically connected to the scanning line 3 to which the scanning signal is supplied. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and by closing the switch of the TFT 30, which is a switching element, for a certain period, the image signal S1 supplied from the data line 6,
.., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the liquid crystal via the pixel electrodes 9a are held for a certain period between the counter electrodes (described later) formed on the counter substrate (described later). .

On the other hand, the peripheral drive circuit area includes a scan line drive circuit 104, a data line drive circuit 101, a sampling circuit 301, and a precharge circuit 201. The scanning line driving circuit 104 supplies the scanning signals G1, G2,..., G to the scanning line 3 at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY and its inverted clock, and the like.
m is applied in a pulsed manner in a line-sequential manner. Data line drive circuit 1
01 is the data line 6 based on the power supplied from the external control circuit, the reference clock CLX and its inverted clock, etc., in accordance with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2,. Transfer signal X from the shift register as a sampling circuit drive signal every time
, Xn are supplied to the sampling circuit 301 at a predetermined timing via the sampling circuit drive signal line 306. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6, a precharge signal line 204 is connected to the drain or source electrode of the TFT 202, and a precharge circuit drive signal line 206 is connected to the TFT 202. Is connected to the gate electrode of

In the present embodiment, since the semiconductor layer of the TFT 30 in the display pixel region is made of polysilicon, the peripheral driving circuit can be replaced by the TFT 30 in the display pixel region.
Can be formed in the same step on the same substrate as the above, but it is also possible to form a part of the peripheral drive circuit on another substrate and attach it externally.

In FIG. 4, the liquid crystal device 100 is a TFT.
The liquid crystal 50 is sandwiched between the array substrate 10 and the opposing substrate 80.

As shown in FIG. 3, the TFT array substrate 10
In this embodiment, a plurality of transparent pixel electrodes 9a are provided in a matrix on a glass substrate 60, and the data lines 6, the scanning lines 3, and the capacitance lines 3b are respectively provided along the vertical and horizontal boundaries of the pixel electrodes 9a.
Is provided. The data line 6 is formed in a shape extending in the vertical direction, and a source electrode 6a, which is a part of the data line 6, is connected to a source region to be described later in the semiconductor layer 1 (hatched portion) made of polysilicon through a contact hole 5a. The data line 6 is electrically connected near the source electrode 6a.
It is formed so that its width becomes wide. A drain electrode 6b formed in the same layer as the data line 6 is electrically connected to a later-described drain region of the semiconductor layer 1 through a contact hole 5b, and the drain electrode 6b is further connected through a contact hole 8. It is electrically connected to the pixel electrode 9a. In addition, the scanning line 3 is arranged to face the channel region in the semiconductor layer 1, and a part of the scanning line 3 functions as a gate electrode. In the present embodiment, the semiconductor layer 1 and the scanning line 3 overlap. There are two places, and it has a double gate structure. The capacitance line 3b is the scanning line 3
, And has a protruding portion protruding along the data line 6 from a portion intersecting the data line 6, and a part of the semiconductor layer is disposed substantially corresponding to the protruding portion.
The capacitance line 3b overlaps a part of the pixel electrode 9a in a plane, and forms a capacitance in this region. The semiconductor layer 1 extends below the data line 6 and the scanning line 3, and a part of the semiconductor layer functions as a storage capacitor electrode. This storage capacitor electrode is disposed to cover the semiconductor layer, which will be described later. Using the gate insulating film 18 as a dielectric layer, a capacitance is formed with a part of the capacitance line 3b.

As shown in FIG. 4, the TFT array substrate 10
In the pixel display area, a base film 12 made of silicon oxide and a semiconductor layer 1 made of polysilicon are arranged on a glass substrate 60. On the semiconductor layer 1, a gate insulating film 18 is arranged. The gate insulating film 18 is formed by stacking the silicon nitride film 17 on the silicon oxide film 2.
It has a layer structure. On the gate insulating film 18, a scanning line 3 (not shown) having a multilayer structure in which aluminum is a lower layer and titanium nitride is an upper layer, a gate electrode 3a which is a part of the scanning line, and a capacitance line 3b are arranged. ing. An insulating film 4 is disposed so as to cover the scanning line 3, the gate electrode 3a, and the capacitor line 3b. On the insulating film 4, a data line 6 formed in the same layer and a source which is a part of the data line 6 are formed. The electrode 6a and the drain electrode 6b are arranged. The source electrode 6a is electrically connected to a source region of the semiconductor layer 1 described later by a contact hole 5a formed in the gate insulating film 18 and the insulating film 4, and the drain electrode 6b is
Through a contact hole 5b formed in the insulating film 4, it is electrically connected to a drain region of the semiconductor layer 1 described later. Further, an interlayer insulating film 7 is arranged to cover the data line 6, the source electrode 6a, and the drain electrode 6b, and the drain electrode 6b is arranged on the interlayer insulating film 7 by a contact hole 8 formed in the interlayer insulating film 7. ITO (Indium
It is electrically connected to the pixel electrode 9a made of a Tin Oxide) film. Finally, an alignment film 16 made of polyimide is disposed so as to cover the pixel electrode. Here, the semiconductor layer 1 of the TFT in the display pixel region is lightly doped draid (LDD).
n) It has a structure, and details will be described later.

In the peripheral drive circuit area of the TFT array substrate 10, a complementary transistor structure is employed. As shown in FIG. 4, the complementary transistor structure includes an N-channel TFT 130a and a P-channel TFT
An N-channel type semiconductor layer 1 and a P-channel type semiconductor layer 1 are disposed on an underlayer 12 disposed on a glass substrate 60, and a gate insulating film 18 is disposed so as to cover these. Have been. The gate insulating film 18 has a two-layer structure in which the silicon nitride film 17 is stacked on the silicon oxide film 2. A gate electrode 103 is arranged on the gate insulating film 18 at a position corresponding to a channel region of the semiconductor layer. Further, the insulating film 4 is disposed to cover the gate electrode 103, and the source electrode 106 disposed on the insulating film 4 is provided.
a, 107a and the drain electrodes 106b, 107b are electrically connected to the corresponding source region or drain region of the semiconductor layer 1, respectively. Then, an interlayer insulating film 7 is disposed on the TFT having the complementary transistor structure. The semiconductor layer of the N-channel TFT is LDD.
It has a structure.

On the other hand, the opposing substrate 80 is composed of a light-shielding film 23 formed in a matrix on the glass substrate 20, an opposing electrode 21 made of an ITO film and formed over the same, and an alignment film 16 made of polyimide. Have been.

Next, a method of manufacturing a TFT array substrate will be described with reference to FIGS.

First, as shown in FIG. 5A, a SiO ₂ film is formed on a glass substrate 60 as a base film 12 by a PE (plasma enhanced) CVD method or an ECR (electron cyclotron resonance) CVD method. 500
It is formed with a thickness of about nm. This base film is formed by removing impurities such as dirt on the surface of the glass substrate 60 and impurities contained in the glass substrate.
It has a function of preventing the characteristics of the FT 30 from deteriorating.

Next, as shown in FIG. 5B, an a-Si film 401a is formed on the underlying film by a thickness of 30 to 100 nm by a plasma CVD method or an LP (low pressure) CVD method.
Laminate with a thickness of about.

Next, as shown in FIG.
Excimer laser light such as KrF or XeCl
Irradiation of 100 to 600 mJ / cm ² results in a-S
The i-film is crystallized to obtain a p-Si film 401b. The irradiation intensity, irradiation time, and the like of the excimer laser light are appropriately adjusted depending on the thickness, film quality, and the like of the a-Si film. In the present embodiment, since the polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is less expensive than a silicon substrate can be used as the substrate.

Next, as shown in FIG. 5D, a photoresist film 402 is formed in a shape corresponding to the semiconductor layer of each TFT in the display pixel region and the peripheral drive circuit region.

Next, as shown in FIG. 6A, using the photoresist film 402 as a mask, the p-Si film 401b is etched by RIE (reactive ion etching) using a chlorine-based gas. The layer 1 is formed. Note that R
In addition to dry etching such as IE, wet etching using a chemical such as etching using hydrofluoric nitric acid can also be used.

Next, as shown in FIG. 6B, after removing the photoresist film 402, as shown in FIG. 6C, a mixed gas of TEOS (tetraethylorthosilicate) and oxygen gas is formed by a plasma CVD method. Is used as a source gas, 2
A silicon dioxide film or a silicon oxide film 2 as a first insulating film is formed to a thickness of 20 nm, here 20 nm. Here, SiH ₄ and oxygen gas may be used as the source gas.

Next, as shown in FIG. 6D, of the semiconductor layer 1 in the display pixel region, a photoresist film 4 having a shape in which a portion corresponding to a region functioning as a capacitor electrode is removed.
03 is formed. Then, this photoresist film 403
Is used as a mask, phosphorus ions as impurities are implanted into the semiconductor layer 1 at a dose of 5 × 10 ¹⁴ to 10 ¹⁶ / cm ² to form the capacitor electrode 1f.
After the implantation, the photoresist film 403 is peeled off.

Next, as shown in FIG. 6E, a mixed gas of TEOS and oxygen gas is used as a source gas on the silicon oxide film 2 by a plasma CVD method for 2 to 100 n.
m, here, a silicon nitride film 17 as a second insulating film is formed with a thickness of 20 nm. Thus, a gate insulating film 18 in which the silicon oxide film 2 and the silicon nitride film 17 are stacked is formed.

Next, as shown in FIG. 7A, a PVD (physical vapor deposition)
Method, a film thickness of 200 to 600 nm, here 400
An aluminum film 405a having a thickness of 100 nm and a titanium nitride film 405b having a thickness of 100 nm are formed.

Next, as shown in FIG.
A photoresist film 404 having a shape corresponding to the gate electrode and the capacitor line is formed. Using this as a mask, RIE using a fluorine-based or chlorine-based gas as shown in FIG.
The aluminum film 405a and the titanium nitride film 405b are etched by the method.

After the etching, the photoresist film 404 is peeled off, and as shown in FIG. 7D, a scanning line having a multilayer structure composed of a lower layer made of aluminum and an upper layer made of titanium nitride, a gate electrode 3a, 103, a capacitance line 3b is obtained.

Next, as shown in FIG. 8A, the semiconductor layer 1 serving as a P-channel type TFT 130b in the peripheral circuit region is formed.
A photoresist film 405 is formed in a shape in which the resist at the position corresponding to is removed. Thereafter, the photoresist film 405 and the gate electrode 1 corresponding to the P-channel type TFT are formed.
03 as a mask, 5 × 10 ¹⁴ to 10
¹⁶ / cm ² boron ions are implanted by an ion implantation method to obtain a semiconductor layer 1 having a channel region 1a, a source region 1g, and a drain region 1h self-aligned with the gate electrode 103.

Next, as shown in FIG. 8B, after the photoresist film 405 is peeled off, as shown in FIG. 8C, the semiconductor layer 1 serving as the P-channel TFT 130b in the peripheral circuit region is formed.
A photoresist film 406 corresponding to is formed. Using the photoresist film 406, the gate electrode 3a, the gate electrode 103 corresponding to the N-channel type TFT, and the capacitor line 3b as a mask, 1 × 10 ¹³ to 2 × 10 ¹⁴
Ions / cm 2 of phosphorus ions are implanted by an ion implantation method. Thereby, in the peripheral circuit region, the gate electrode 103
Semiconductor corresponding to an N-channel type TFT having a channel region 1a self-aligned with a high-concentration source region, a low-concentration source region 1b having a lower impurity concentration than the high-concentration drain region, and a low-concentration drain region 1c. Tier 1
Get. In the pixel display region, two channel regions 1a (only one is shown) are formed so as to sandwich the two channel regions, and have a higher impurity concentration than the later-formed high-concentration source region and high-concentration drain region. A semiconductor 1 having a low-concentration source region 1b and a low-concentration drain region 1c is obtained.

Next, as shown in FIG. 9A, the gate electrode 10 of the N-channel TFT 130a has a pattern covering the semiconductor layer of the P-channel TFT 130b.
3 and a photoresist film 407 having a shape covering the periphery of the gate electrode 3a of the TFT in the display pixel region. Using this as a mask, 5 × 10 ^14-
10 ¹⁶ phosphorus ions / cm ² are implanted by an ion implantation method. After that, the photoresist 407 is peeled off by a peeling liquid. Thus, as shown in FIG. 9B, a semiconductor layer having an LDD structure having a high-concentration source region 1d and a high-concentration drain region 1e having a higher impurity concentration than the low-concentration source region 1b and the low-concentration drain region 1c. Can be obtained. Therefore, the TFT in the pixel display region and the N-channel TFT in the peripheral drive circuit region have a semiconductor layer having an LDD structure.

Next, as shown in FIG. 9C, the plasma C is applied so as to cover the gate electrodes 103 and 3a and the capacitance line 3b.
An insulating film 4 made of SiO _{2 having} a thickness of 1500 nm is formed by VD using TEOS and ozone gas as source gases. After that, activation heat treatment (activation annealing treatment) is performed at a temperature of 400 ° C. in order to activate the impurity ions.

Next, as shown in FIG. 9D, a contact hole for connecting the source / drain region of each TFT in the peripheral circuit region to a source / drain formed later, and a TFT in the display pixel region. A photoresist patterned into a shape corresponding to a contact hole for connecting a source region of the TFT and a source formed later, and a contact hole for connecting a drain region of a TFT in a display pixel region and a drain formed later. A film 409 is formed.

As shown in FIG. 10A, the insulating film 4 is etched using the photoresist film 409 as a mask.
Contact holes 5, 5a, 5b are formed. afterwards,
The structure of FIG. 10B is obtained by removing the photoresist film 409.

Next, as shown in FIG. 10C, an aluminum / titanium multilayer film 410 having a thickness of 300 to 1000 nm is formed on the insulating film 4 by a PVD method. Further, as shown in FIG. 10D, a photoresist film 41 having a shape in which portions corresponding to data lines, sources, and drains are removed is formed on the aluminum-titanium multilayer film 410.
Form one.

Next, as shown in FIG. 11A, using the photoresist film 411 as a mask, the aluminum / titanium film 410 is etched by a RIE method using a chlorine-based gas, and then the photoresist film 411 is peeled off. Thereby, as shown in FIG. 11B, in the peripheral circuit region,
Source electrodes 106a and 107 electrically connected to the source regions 1d and 1g and the drain regions 1e and 1h of the semiconductor layers of the N-channel TFT and the P-channel TFT, respectively.
a, drain electrodes 106b and 107b are obtained. In the display pixel region, a source electrode 6a electrically connected to the source region 1d and the drain region 1e of the semiconductor layer, respectively.
To obtain the data line 6 and the drain electrode 6b also serving as

Next, as shown in FIG.
Plasma CVD using a mixed gas of TEOS and oxygen gas as a source gas to cover the interlayer insulating film 7 covering the drain and the data line.
It is formed by a method. Here, a normal pressure CVD method may be used as a method for forming the interlayer insulating film 7, and a mixed gas of TEOS and ozone gas or Si gas is used as a source gas.
A mixed gas of H ₄ and oxygen gas may be used. Further, not only an inorganic film but also an organic film such as an acrylic film can be used. In this case, a film having a larger thickness can be easily obtained as compared with the inorganic film, and thus can be used as a flattening film.

Next, as shown in FIG. 11D, a photoresist film in which a resist corresponding to a contact hole connecting the drain electrode 6b and a pixel electrode to be formed later is removed on the interlayer insulating film 7. 413 is formed. Thereafter, as shown in FIG.
3 is used as a mask, the interlayer insulating film 7 is etched by the RIE method or the wet etching method, and the photoresist film 413 is stripped to obtain the interlayer insulating film 7 having the contact holes 8 as shown in FIG. .

Next, as shown in FIG. 12C, an ITO film 414 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by a sputtering method. Then, FIG.
As shown in (a), a photoresist film 415 corresponding to the shape of a pixel electrode is formed on an ITO film 414, and the ITO film 414 is wet-etched with aqua regia or HBr using this as a mask, or CH _{4 is used.} Alternatively, by performing dry etching by a RIE method using a gas such as HI, the pixel electrode 9a is formed as shown in FIG.
Get.

The electro-optical device manufactured as described above is
Since there is no defect in the gate insulating film, the storage capacitor line and the storage capacitor electrode to which a constant voltage is always applied are short-circuited due to the defect in the gate insulating film, and the voltage is always applied to the pixel electrode. There is no problem that the corresponding pixel cannot perform any display, and a liquid crystal device with high display quality can be obtained. Further, since the withstand voltage characteristics of the gate insulating film are improved, the switching characteristics of the TFT are not deteriorated.

In this embodiment, the gate insulating film has a two-layer structure, but may have a multilayer structure of three or more layers, such as a three-layer structure in which a silicon oxide film is formed on the second insulating film. In this case, a step of forming an insulating film at least once before and after the impurity ion implantation step is sufficient. Here, an image signal having both positive and negative poles with respect to the potential of the storage capacitor electrode is supplied to the data line. In such driving, by forming the gate insulating film into a three-layer structure of a nitride film, an oxide film, and a nitride film, it becomes possible to suppress the pool-Frenkel current caused by holes in the nitride film and to reduce the leak current. be able to.

In this embodiment, a silicon oxide film is used as the first insulating film and a silicon nitride film is used as the second insulating film. However, the first insulating film is a silicon nitride film, the second insulating film is a silicon oxide film, Alternatively, both may be the same insulating film, and are not limited to this embodiment. However, by using an oxide film as the insulating film formed before the impurity ion implantation step as in this embodiment, damage due to impurity ion implantation can be reduced as compared with the case where a nitride film is used. It is effective to use an oxide film as one insulating film.

Further, by using a nitride film as the insulating film formed after the impurity ion implantation step, it is possible to make the film thickness thicker when the same dielectric constant is used than when an oxide film is used. Therefore, a thick second insulating film can be formed, and defects such as pinholes generated in the first insulating film can be reliably filled.

[Brief description of the drawings]

FIG. 1 is a manufacturing process diagram of a semiconductor device according to an embodiment.

FIG. 2 is a plan view of a display pixel region and a peripheral driving circuit region of the liquid crystal device according to the embodiment.

FIG. 3 is a plan view of a TFT array substrate on which data lines, scanning lines, and pixel electrodes are formed in a display pixel region of the liquid crystal device according to the embodiment.

FIG. 4 is a longitudinal sectional view of a peripheral circuit region and a display pixel region of the liquid crystal device according to the embodiment, and the longitudinal sectional view of the display pixel region is a sectional view taken along line AA ′ of FIG. .

FIG. 5 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 6 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 7 is a process diagram (part 3) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 8 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 9 is a process diagram (part 5) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 10 is a process view (part 6) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 11 is a process view (part 7) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 12 is a process view (part 8) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 13 is a process diagram (part 9) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 201 ... Semiconductor layer 1f ... Storage capacitor electrode 2 ... First insulating film 3b ... Storage capacitor line 17 ... Second insulating film 18 ... Gate insulating film 30, 130a, 130b ... TFT 60, 200 ... Substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/336 F term (Reference) 2H092 HA28 JA34 JA37 JB22 JB31 JB67 KB25 MA07 MA19 MA29 NA27 NA29 5F038 AC05 DF20 EZ20 5F110 AA12 AA18 BB02 BB04 DD02 DD03 DD13 DD24 DD25 EE01 EE03 EE14 EE37 EE42 FF02 FF03 FF10 FF30 GG02 GG12 GG24 GG25 GG32 GG34 GG45 GG47 GG52 HJ01 HJ04 HJ13 HJ23 HL03 NN03 NN03 NN03 NN04 NN04

Claims (11)

[Claims] A step of forming a semiconductor layer on a substrate; a step of forming a first insulating film so as to cover the semiconductor layer; and implanting impurity ions into the semiconductor layer via the first insulating film. A method of manufacturing a semiconductor device, comprising: a step of forming a second insulating film on the first insulating film. 2. The method according to claim 1, wherein the first insulating film is made of a silicon oxide film. 3. The method according to claim 1, wherein the second insulating film is made of a silicon nitride film. 4. The method according to claim 1, further comprising a step of forming a third insulating film on the second insulating film. 5. The method according to claim 4, wherein the third insulating film is made of a silicon oxide film. 6. A step of forming a semiconductor layer partly serving as a storage capacitor electrode on a substrate; a step of forming a first insulating film on the semiconductor layer; and a step of forming the storage layer via the first insulating film. A step of implanting impurity ions into a semiconductor layer serving as a capacitor electrode; a step of forming a second insulating film on the first insulating film; and forming a conductive layer on a second insulating film facing the storage capacitor electrode And a method for manufacturing an electro-optical device. 7. A step of forming, on a substrate, a region to be a channel and a region to be one electrode for a storage capacitor by using a semiconductor layer; and forming a first region on the region to be a channel and the first electrode. Forming an insulating film; selectively implanting impurity ions into a region to be the first electrode through the first insulating film; forming a second insulating film on the first insulating film Forming a conductive layer on the second insulating film; patterning the conductive layer to form a gate electrode on the channel region and the storage capacitor on the one electrode region. Forming a region to be the other electrode of the electro-optical device. 8. The method according to claim 6, wherein the first insulating film is formed of a silicon oxide film. 9. The method according to claim 6, wherein the second insulating film is made of a silicon nitride film. 10. A semiconductor device manufactured by the method of manufacturing a semiconductor device according to claim 1. Description: 11. An electro-optical device manufactured by the method for manufacturing an electro-optical device according to claim 6. Description: