JP4062825B2 - Manufacturing method of electro-optical device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, and a semiconductor device and an electro-optical device manufactured by these manufacturing methods. In particular, the scanning line is formed before forming a resist film used as a mask during ion implantation. The present invention belongs to a technical field of a semiconductor device manufacturing method, an electro-optical device manufacturing method, and a semiconductor device and an electro-optical device manufactured by these manufacturing methods.
[0002]
[Prior art]
In general, in an active matrix liquid crystal device having a thin film transistor (hereinafter referred to as TFT) as a switching element, an electro-optical material such as a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate.
[0003]
Such a TFT array substrate is electrically connected to a plurality of scanning lines and a plurality of data lines arranged intersecting each other on the substrate, and a scanning line and a data line arranged at each intersection of the scanning lines and the data lines. It is composed of a thin film transistor to be connected and a pixel electrode electrically connected to the thin film transistor. The thin film transistor is configured by disposing a gate electrode on the semiconductor layer in the same layer as the scanning line and electrically connected via a gate insulating film. Then, a data line is formed thereon via an insulating film.
[0004]
The TFT array substrate as described above is formed through the following formation process, for example.
[0005]
First, a semiconductor layer made of polysilicon is formed on a glass substrate, and a gate insulating film is formed so as to cover the semiconductor layer. Next, a scan line having a gate electrode is formed over the gate insulating film at a position facing the channel region of the semiconductor layer. After forming the scanning line, ion implantation is performed in an arbitrary region of the semiconductor layer using the resist film as a mask. Next, after removing the resist film, an insulating film is formed on the gate insulating film so as to cover the scanning lines and the gate electrode, and a source electrode, a drain electrode, and a data line are formed on the insulating film. Further, an interlayer insulating film is formed on this upper layer, and a pixel electrode connected to the drain electrode through a contact hole is formed on this interlayer insulating film, thereby completing the TFT array substrate. The resist film is formed by applying a resist on a substrate, exposing to light, and developing the resist film so as to be patterned into a predetermined shape.
[0006]
[Problems to be solved by the invention]
When such a liquid crystal device is used in a device such as a portable information terminal, there has been a strong demand in recent years to reduce power consumption as much as possible. To reduce the power consumption of the TFT array substrate constituting the liquid crystal device, it is necessary to reduce the resistance of the scanning line, and instead of the conventionally used materials such as Cr and Ta, a manufacturing method using aluminum is attracting attention. . Further, when a metal containing aluminum is used for the scanning line, a multilayer structure in which a refractory metal such as titanium is stacked on a metal layer containing aluminum is used in order to prevent generation of protrusions called hillocks.
[0007]
However, when forming a resist film used as a mask in the ion implantation process, there is a problem that the aluminum layer of the scanning line is etched by the developer. Hereinafter, this will be described in detail with reference to FIG. FIG. 15 is a longitudinal sectional view in the vicinity of the intersection between the data line and the scanning line.
[0008]
FIG. 15A shows a state in which the scanning line 3 before the ion implantation process is formed. The semiconductor layer 1 is disposed on the TFT array substrate 60, and the scanning line 3 is disposed on the semiconductor layer via the gate insulating film 2. The scanning line has a two-layer structure, the lower layer is made of aluminum and the upper layer is made of titanium.
[0009]
FIG. 15B shows a state in which a resist film is arranged. The resist film is formed by applying a resist on the substrate, exposing the resist so that only a portion corresponding to the region of the semiconductor layer where ions are not implanted remains, and developing the resist. Therefore, as shown in the drawing, no resist film is formed in the vicinity of the intersection between the scanning line 3 and the data line. When the resist film is formed in such a shape, the side portion of the lower layer made of the aluminum layer of the scanning line is etched by the developer used for developing the resist as shown in the figure, and the vertical section of the scanning line has an overhang shape. It becomes a shape.
[0010]
Next, after implanting impurity ions into the semiconductor layer 1 using the resist film as a mask, the resist film is peeled off.
[0011]
Next, when the insulating film 4 is formed on the substrate so as to cover the overhanging scanning line as described above, a crack 4 ′ is generated in the insulating film 4 as shown in FIG. Therefore, when the data line 6 is formed on the insulating film 4 as shown in FIG. 15D, the scanning line 3 and the data line 6 are short-circuited by the crack 4 '. As a result, the pixel electrodes electrically connected to the shorted scanning lines 3 and data lines 6 cannot perform arbitrary display, resulting in line defects in the scanning lines and the data lines, and the display quality is significantly reduced. There is. Even if a short circuit does not occur, the data line 6 may be disconnected in the vicinity of the occurrence of a crack in the insulating film 4, which causes a display defect.
[0012]
The present invention has been made in view of the above-described problems, and prevents the scanning line from being etched by a developer used when forming a resist film. The scanning line and a data line formed thereon via an insulating film are provided. An object of the present invention is to provide a method for manufacturing a semiconductor device, a method for manufacturing an electro-optical device, and a semiconductor device and an electro-optical device manufactured by these manufacturing methods, which can prevent a short circuit failure between them.
[0013]
[Means for Solving the Problems]
The method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a region where a first wiring and a second wiring intersect, and a step of forming a semiconductor layer and a step of forming the first wiring Forming a resist film on a predetermined region of the first wiring; implanting impurity ions into the semiconductor layer using the resist film as a mask; and the first wiring on the predetermined region of the first wiring. Forming the second wiring so as to intersect one wiring.
[0014]
According to such a configuration, in the method of manufacturing a semiconductor device having a step of implanting impurity ions into the semiconductor layer, the resist film is formed so as to cover a region where the first wiring and the second wiring intersect. The first wiring in the intersection region between the first wiring and the second wiring is not etched by the developer used at the time of film formation, for example, a TMAH aqueous solution. As a result, it is possible to prevent the occurrence of cracks in the insulating film disposed in the vicinity of the first wiring and the second wiring, which are generated in the vicinity of the region where the first wiring and the second wiring intersect, There is an effect that a short circuit between the first wiring and the second wiring or the second disconnection can be prevented, and a defect-free semiconductor device can be obtained.
[0015]
Further, the present invention is a method for manufacturing a semiconductor device having a region where the first wiring and the second wiring intersect, wherein a step of forming a semiconductor layer, a step of forming the first wiring,
Forming a resist film on a predetermined region of the first wiring and on a predetermined region of the semiconductor layer; implanting impurity ions into the semiconductor layer using the resist film as a mask; and the first wiring Forming the second wiring so as to intersect the first wiring on the predetermined region.
[0016]
According to such a configuration, the resist film is formed so as to cover the region where the first wiring and the second wiring intersect at the same time as the formation of the mask used when implanting impurity ions into the semiconductor layer. The first wiring in the intersecting region between the first wiring and the second wiring is not etched by a developer used at the time of formation, for example, a TMAH aqueous solution. As a result, it is possible to prevent the occurrence of cracks in the insulating film disposed in the vicinity of the first wiring and the second wiring, which are generated in the vicinity of the region where the first wiring and the second wiring intersect, There is an effect that a short circuit between the first wiring and the second wiring or the second disconnection can be prevented, and a defect-free semiconductor device can be obtained.
[0017]
Further, the step of forming the resist film includes a step of applying a resist on the substrate and a step of forming the resist film by exposing and developing the resist. . According to such a configuration, since the resist is applied onto the substrate, a resist having a uniform film thickness can be obtained, and as a result, a resist film having a uniform film thickness distribution within the substrate surface can be obtained. it can. Thereby, ion implantation is performed uniformly in the plane, and for example, even when a plurality of thin film transistors having a semiconductor layer is formed on the substrate, there is an effect that variations in characteristics of the thin film transistors do not occur in the plane. Here, as a resist coating method, a spin coat method, a roll coater method, or the like can be used.
[0018]
Further, the first wiring contains aluminum. According to such a configuration, since low-resistance aluminum is used, the wiring width can be reduced, a high-definition semiconductor device can be obtained, and the wiring capacity is reduced, so that the semiconductor device with low power consumption can be obtained. Can be obtained. In addition, when a material containing aluminum is used as the electrode material, it is very effective to cover aluminum with a resist film because aluminum has a problem of etching with a developer as compared with other metals. The first wiring may be aluminum, an alloy containing aluminum as a main component, or a multilayer metal including at least one layer thereof.
[0019]
The first wiring has a multilayer structure including a lower layer containing aluminum and an upper layer containing a refractory metal. Furthermore, the upper layer is characterized by comprising a layer containing molybdenum or titanium. According to such a configuration, since the layer containing a refractory metal such as molybdenum or titanium is formed on the layer containing aluminum, no hillock is generated in the aluminum, and the first wiring and the second wiring due to the hillock are short-circuited. Occurrence can be prevented, and there is an effect that a high-quality semiconductor device is obtained. In the case of a multilayer structure in which a layer containing a refractory metal is disposed on such a layer containing aluminum, the layer containing the refractory metal has higher etching resistance to the developer than the layer containing aluminum. When the development is performed in a state where the resist film is not formed on the gate electrode, only the lower layer is etched by the developer, and the first wiring having an overhang-like cross section is formed. As a result, a crack is generated in the insulating film formed so as to cover the first wiring, and there is a problem that the second wiring and the first wiring formed on the insulating film are short-circuited through the crack. However, in the present invention, even when the first wiring having the multilayer structure is used, the first wiring corresponding to the intersection between the first wiring and the second wiring is covered with the resist film, so that the first wiring at the intersection is formed. However, the first wiring having an overhang-like cross section is not etched by the developing solution, and a problem that a crack occurs in the insulating film covering the first wiring can be avoided. As a result, a short circuit between the first wiring and the second wiring or disconnection of the second wiring is prevented, and an effect is obtained in that a high-quality semiconductor device is obtained.
[0020]
The method of manufacturing the electro-optical device according to the aspect of the invention includes a plurality of scanning lines, a plurality of data lines, and the scanning lines and the transistors connected to the data lines. Is a method of manufacturing an electro-optical device having intersecting regions, the step of forming the scanning line, the step of forming a resist film on a predetermined region of the scanning line, and the resist film as a mask, The method includes a step of implanting impurity ions into a semiconductor layer constituting a transistor, and a step of forming the data line on a predetermined region of the scanning line so as to intersect the scanning line.
[0021]
According to such a configuration, in the electro-optical device formed through the step of implanting impurity ions using the resist film as a mask, for example, simultaneously with the formation of the mask used when implanting impurity ions into the semiconductor layer, the scanning lines and Since the resist film is formed so as to cover the region where the data line intersects, it is possible to suppress the etching of the scanning line at the intersection of the scanning line and the data line line by the developer used at the time of forming the resist film. it can. As a result, it is possible to prevent the occurrence of cracks in the insulating film interposed between the scanning line and the data line near the area where the scanning line and the data line intersect. This has the effect of preventing a short circuit or disconnection of the data line and obtaining an electro-optical device free from display defects.
[0022]
In the electro-optical device manufacturing method of the present invention, the step of forming the resist film and the step of injecting the impurity each exist at least twice, and the resist film includes the scanning line and the data line. It is formed so as to cover a region where and intersect.
[0023]
According to such a configuration, for example, an LDD structure in which a plurality of semiconductor regions having different impurity concentrations are formed on the same substrate, or a complementary type in which a semiconductor region into which a plurality of different impurities are implanted is formed on the same substrate. In a manufacturing method of manufacturing an electro-optical device through a process of performing ion implantation a plurality of times using a resist film as a mask as in the formation of a transistor structure, the scanning line and the data line are formed in all of the plurality of implantation mask formation processes. Since the resist film is formed so as to cover the intersecting region, the scanning line in the region intersecting with the data line is not etched by the developer used at the time of forming the resist film. As a result, it is possible to prevent the occurrence of cracks in the insulating film interposed between the scanning line and the data line near the area where the scanning line and the data line intersect. A short circuit or disconnection of the data line can be prevented, and an electro-optical device free from display defects can be obtained.
[0024]
According to another aspect of the invention, there is provided a method of manufacturing an electro-optical device, wherein a plurality of scanning lines, a plurality of data lines, a transistor connected to the scanning lines and the data lines, and a region where the scanning lines and the data lines intersect. And a step of forming a first semiconductor layer and a second semiconductor layer on the substrate, and a gate insulating film on the substrate so as to cover the first and second semiconductor layers. A scanning line having a first gate electrode on a gate insulating film at a position corresponding to at least a channel region of the first semiconductor layer, and a gate insulation at a position corresponding to at least the channel region of the second semiconductor layer. Forming a second gate electrode on the film; covering a region where the scanning line and the data line intersect; and forming a first resist film corresponding to the first semiconductor layer; and the first Resist film and Using the second gate electrode as a mask, implanting impurity ions into the second semiconductor layer, covering a region where the scanning line and the data line intersect, and corresponding to the second semiconductor layer, a second resist Forming a film; implanting impurity ions into the first semiconductor layer using the second resist film and the first gate electrode as a mask; and forming an insulating film so as to cover the gate electrode and the scanning line And a step of forming a plurality of data lines on the insulating film so as to intersect the scanning lines.
[0025]
According to such a configuration, when a process of forming a semiconductor layer having different types of impurity ion regions in the same substrate using the resist film as a mask is performed, at the same time as forming the resist film as the mask, Since the resist film is formed so as to cover the scanning line corresponding to the region to be formed, the scanning line is protected from the developing solution, and the scanning line is not etched by the developing solution. As a result, it is possible to prevent the occurrence of cracks in the insulating film that occurs in the vicinity of the area where the scanning line and the data line overlap with each other, prevent a short circuit between the scanning line and the data line or a disconnection of the data line, and display. An electro-optical device free from defects can be obtained.
[0026]
The electro-optical device includes an image display region and a drive circuit region for controlling display in the image display region, and the drive circuit region includes a complementary transistor structure having the first semiconductor layer and the second semiconductor layer. The thin film transistor is disposed, and the first semiconductor layer is disposed in the image display region.
[0027]
According to such a configuration, a thin film transistor for pixel display and a thin film transistor having a complementary transistor structure for a driver circuit can be formed on the same substrate in the same process. For this reason, it is not necessary to manufacture the drive circuit in a separate process and attach it externally, and the manufacturing process of the electro-optical device is greatly reduced.
[0028]
And a step of forming a capacitor line in the same layer as the scan line and substantially parallel to the scan line, and a region where the capacitor line and the data line intersect is covered with the resist film. It is characterized by that. According to such a configuration, similarly to the scanning line, the short circuit between the data line and the capacitive line in the vicinity of the intersection of the data line and the capacitive line is prevented, and an electro-optical device having no display defect is obtained. .
[0029]
Further, at least a part of the scanning line and a layer made of the same layer as the scanning line is covered with the resist film. According to such a configuration, not only the vicinity of the intersection between the data line and the scanning line, or the data line and the capacitive line, but also the scanning line or the capacitive line can be protected from the developing solution. It is possible to prevent the narrowing of the width of the scanning line or the capacitor line caused by the etching. As a result, the line widths of the plurality of scanning lines or capacitance lines in the display surface of the electro-optical device can always be kept constant, so that an electro-optical device having good display characteristics with no display variation in the surface can be obtained.
[0030]
Further, the step of forming the resist film includes a step of applying a resist on the substrate and a step of forming the resist film by exposing and developing the resist. . According to such a configuration, since the resist is applied on the substrate, a resist having a uniform film thickness can be obtained, and as a result, a resist film having a uniform film thickness distribution in the substrate surface can be obtained. it can. Thereby, ion implantation is performed uniformly in the plane, and for example, even when a plurality of thin film transistors having a semiconductor layer is formed on the substrate, there is an effect that variations in characteristics of the thin film transistors do not occur in the plane. Here, as a resist coating method, a spin coat method, a roll coater method, or the like can be used.
[0031]
The scan line and the layer formed of the same layer as the scan line include aluminum. According to such a configuration, since low-resistance aluminum is used, it is possible to obtain a scanning line or a capacitance line with no signal delay on the signal input side and the terminal side, and to obtain an electro-optical device having no display variation. In addition, since low-resistance aluminum is used, the wiring width can be reduced, and the wiring capacity is reduced, so that an electro-optical device with low power consumption can be realized. Furthermore, when a material containing aluminum is used as the electrode material, it is very effective to cover with a resist film because aluminum has a problem of etching with a developer as compared with other metals.
[0032]
The scanning line and the layer made of the same layer as the scanning line have a multilayer structure including a lower layer containing aluminum and an upper layer containing a refractory metal. Furthermore, the upper layer is characterized by comprising a layer containing molybdenum or titanium.
[0033]
According to such a configuration, since a layer containing a refractory metal such as molybdenum or titanium is formed on the layer containing aluminum, an impurity ion activation process performed under a high temperature condition of, for example, 400 ° C. or higher is performed. However, hillocks do not occur, the occurrence of a short circuit between the scanning lines and the data lines due to hillocks can be prevented, and an electro-optical device with good display characteristics can be obtained. Further, when a multilayer structure in which a layer containing a refractory metal is disposed on such a layer containing aluminum is used as the wiring, the scanning line in the region intersecting with the data line is a developing solution during the resist film forming process. As a result, the insulating film covering the scanning line is not cracked, and the scanning line and the data line are short-circuited through the crack. This has the effect of preventing disconnection and obtaining an electro-optical device with good display characteristics.
[0034]
A semiconductor device of the present invention is formed by the above-described manufacturing method. Such a configuration has an effect of obtaining a high-quality electro-optical device.
[0035]
The electro-optical device of the present invention is formed by the above-described manufacturing method. Such a configuration has an effect of obtaining an electro-optical device with good display characteristics.
[0036]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings, taking as an example the case of application to a liquid crystal device as an electro-optical device.
[0037]
The configuration of the liquid crystal device according to the present invention will be described with reference to FIGS. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix that forms an image forming area of a liquid crystal device. FIG. 2 is a plan view of a plurality of pixel groups in an image display area of a TFT array substrate on which data lines, scanning lines, pixel electrodes, and the like are formed. FIG. 3 is a longitudinal sectional view of the image display region and the peripheral drive circuit region of the liquid crystal device, and the longitudinal sectional view of the pixel region is a sectional view taken along line AA ′ of FIG. In each drawing, the scale is different for each layer and each member so that each layer and each member can be recognized on the drawing.
[0038]
In FIG. 1, the liquid crystal device includes an image display area and a peripheral drive circuit area for controlling the image display area.
[0039]
The image display area is formed in a matrix at each of the capacitance lines 3 b and the scanning lines 3 arranged in parallel, the data lines 6 arranged so as to intersect the scanning lines 3, and the intersections between the scanning lines 3 and the data lines 6. And a thin film transistor (hereinafter referred to as TFT) 30 for controlling the pixel electrode 9a. The source of the TFT 30 is electrically connected to the data line 6 to which the image signal is supplied, and the gate of the TFT 30 is electrically connected to the scanning line 3 to which the scanning signal is supplied. The pixel electrode 9a is electrically connected to the drain of the TFT 30, and the image signal S1, S2,..., Sn supplied from the data line 6 is obtained by closing the TFT 30 as a switching element for a certain period. Write at a predetermined timing. Image signals S1, S2,..., Sn written to the liquid crystal via the pixel electrode 9a are held for a certain period with a counter electrode (described later) formed on a counter substrate (described later). .
[0040]
On the other hand, the peripheral drive circuit region is composed of a scanning line drive circuit 104, a data line drive circuit 101, a sampling circuit 301, and a precharge circuit 201. The scanning line driving circuit 104 pulse-sequentially applies the scanning signals G1, G2,..., Gm to the scanning line 3 at a predetermined timing based on the power supplied from the external control circuit, the reference clock CLY, its inverted clock, and the like. Apply with. The data line driving circuit 101 is synchronized with the timing at which the scanning line driving circuit 104 applies the scanning signals G1, G2,..., Gm based on the power supplied from the external control circuit, the reference clock CLX, its inverted clock, and the like. Transfer signals X1, X2,..., Xn from the shift register as sampling circuit drive signals for each data line 6 are supplied to the sampling circuit 301 via the sampling circuit drive signal line 306 at a predetermined timing. The precharge circuit 201 includes, for example, a TFT 202 as a switching element for each data line 6, the precharge signal line 204 is connected to the drain or source electrode of the TFT 202, and the precharge circuit drive signal line 206 is connected to the TFT 202. Connected to the gate electrode. In operation, power of a predetermined voltage necessary for writing the precharge signal NRS from an external power supply is supplied via the precharge signal line 204, and each data line 6 is connected via the precharge circuit drive signal line 206. The precharge circuit drive signal NRG is supplied from the external control circuit so that the precharge signal NRS is written at a timing preceding the supply of the image signals S1, S2,. The precharge circuit 201 preferably supplies a precharge signal NRS (image auxiliary signal) corresponding to the image signals S1, S2,. The sampling circuit 301 includes a TFT 302 for each data line 6, the image signal line 304 is connected to the source electrode of the TFT 302, and the sampling circuit drive signal line 306 is connected to the gate electrode of the TFT 302. When image signals S1, S2,..., Sn are input via the image signal line 304, they are sampled. That is, when transfer signals X1, X2,..., Xn as sampling circuit drive signals are input from the data line drive circuit 101 via the sampling circuit drive signal line 306, the image signals S1, S2 from the image signal lines 304, respectively. ,..., Sn are sequentially applied to the data line 6a.
[0041]
In this embodiment, since polysilicon is used as the semiconductor layer of the TFT 30 in the image display area, the TFT used in the peripheral drive circuit and the TFT 30 in the image display area are formed in the same process on the same substrate. However, it is also possible to form a part of the peripheral drive circuit on a separate substrate and attach it externally.
[0042]
In FIG. 2, a plurality of transparent pixel electrodes 9a are provided in a matrix on the TFT array substrate of the liquid crystal device, and data lines 6 and scanning lines 3 (dotted lines) are respectively provided along vertical and horizontal boundaries of the pixel electrodes 9a. ) And a capacitor line 3b (dotted line). The data line 6 is formed in a shape extending in the vertical direction, and a source electrode 6a, which is a part of the data line 6, is described later in the semiconductor layer 1 (a slanted portion at the lower left) made of a polysilicon film through the contact hole 5a. The data line 6 is formed in the vicinity of the source 6a so as to have a large width. A conductive layer 6b formed in the same layer as the data line 6 is electrically connected to a drain region described later in the semiconductor layer 1 through a contact hole 5b, and further, the conductive layer 6b is connected through a contact hole 8. It is electrically connected to the pixel electrode 9a. Further, the scanning line 3 is disposed so as to face the channel region in the semiconductor layer 1, and the scanning line 3 functions as a gate electrode. In the present embodiment, the number of locations where the semiconductor layer 1 and the scanning line 3 overlap is 2. This is a double gate structure. In the drawing, the portion where the scanning line 3 and the semiconductor layer 1 overlap in a plane, that is, the semiconductor layer at the position corresponding to the gate electrode is hidden by the scanning line and is not shown. The capacitor line 3b extends substantially linearly along the scanning line 3 and has a protruding portion protruding along the data line 6 from a location intersecting with the data line 6, and substantially corresponds to the protruding portion of the semiconductor layer. Some are arranged. That is, the semiconductor layer 1 extends below the data line 6 and the scanning line 3, and the capacitor line 3b also extends along the data line 6 and the scanning line 3. The semiconductor layer 1 and the capacitor line 3b portion are gated. The storage capacitor is formed so as to be opposed to each other through the insulating film 2 which is also an insulating film. The capacitor line 3b overlaps with a part of the pixel electrode 9a in a plane, and forms a storage capacitor also in this region.
[0043]
Next, as shown in the cross-sectional view of FIG. 3, the liquid crystal device 100 includes a liquid crystal layer 50 as an electro-optical material between the TFT array substrate 10 and a counter substrate 80 disposed to face the TFT array substrate 10.
[0044]
In the TFT array substrate 10, the base film 12 made of silicon oxide and the semiconductor layer 1 made of polysilicon are arranged on the glass substrate 60 in the image display region. A gate insulating film 2 is disposed on the semiconductor layer 1. On the gate insulating film 2, there are arranged a scanning line 3 (not shown) having a two-layer structure in which aluminum is a lower layer and titanium is an upper layer, a gate electrode 3a and a capacitance line 3b which are part of the scanning line. . An insulating film 4 is disposed so as to cover the scanning line 3, the gate electrode 3a, and the capacitor line 3b. On the insulating film 4, a data line 6 formed in the same layer and a source that is a part of the data line 6 are disposed. Electrode 6a and conductive layer 6b are arranged. The source electrode 6 a is electrically connected to the source region of the semiconductor layer 1 described later by a contact hole 5 a formed in the gate insulating film 2 and the insulating film 4, and the conductive layer 6 b is formed in the insulating film 4. The contact hole 5b is electrically connected to the drain region of the semiconductor layer 1 described later. Further, an interlayer insulating film 7 is disposed so as to cover the data line 6, the source electrode 6 a, and the conductive layer 6 b, and the conductive layer 6 b is disposed on the interlayer insulating film 7 by a contact hole 8 formed in the interlayer insulating film 7. The pixel electrode 9a made of an ITO (Indium Tin Oxide) film is electrically connected. Finally, an alignment film 16 made of polyimide is disposed so as to cover the pixel electrode 9a. Here, the semiconductor layer 1 of the TFT in the image display region has an LDD (lightly doped drain) structure, and details will be described later.
[0045]
Further, a complementary transistor structure is employed in the peripheral drive circuit region of the TFT array substrate 10. As shown in FIG. 3, the complementary transistor structure includes an N-channel TFT 130 a and a P-channel TFT 130 b, and an N-channel semiconductor layer 1 and a P-channel type are formed on the base layer 12 disposed on the glass substrate 60. The semiconductor layer 1 is disposed, and a gate insulating film 2 is disposed so as to cover them. A gate electrode 103 is arranged on the gate insulating film 2 at a position corresponding to the channel region of the semiconductor layer. Further, the insulating film 4 is disposed so as to cover the gate electrode 103, and the source electrodes 106a and 107a and the drain electrodes 106b and 107b disposed on the insulating film 4 are respectively a source region or a drain region of the corresponding semiconductor layer 1. Is electrically connected. An interlayer insulating film 7 is disposed on these complementary transistor TFTs. Further, the semiconductor layer of the N-channel TFT has an LDD structure.
[0046]
On the other hand, the counter substrate 80 includes a light shielding film 23 formed in a matrix on the glass substrate 20, a counter electrode 21 made of an ITO film sequentially formed so as to cover it, and an alignment film 16 made of polyimide. .
[0047]
Next, a manufacturing method of the TFT array substrate will be described with reference to FIGS. 4 to 12 are cross sections in the image display area and the peripheral circuit area, and the image display area is a cross section taken along line AA ′ in FIG.
[0048]
First, as shown in FIG. 4A, an SiO 2 film is formed on a glass substrate 60 by a PE (plasma enhanced) CVD method or an ECR (electron cyclotron resonance) CVD method. ₂ The film is formed with a thickness of about 200 to 500 nm. This base film has a function of preventing the surface of the glass substrate 60 from being contaminated and impurities contained in the glass substrate from causing deterioration of the characteristics of the TFT 30.
[0049]
Next, as shown in FIG. 4B, an a-Si film 401a is laminated with a thickness of about 30 to 100 nm on the base film by PECVD or LP (low pressure) CVD.
[0050]
Next, as shown in FIG. 4C, excimer laser light such as KrF or XeCl is applied to the a-Si film at 300 to 600 mJ / cm. ² By irradiation, the a-Si film is crystallized to obtain a p-Si film 401b. Excimer laser light irradiation intensity, irradiation time, and the like are appropriately adjusted depending on the film thickness, film quality, and the like of the a-Si film. In this embodiment, since a polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is less expensive than a silicon substrate can be used as the substrate.
[0051]
Next, as shown in FIG. 4D, a resist film 402 is formed in a shape corresponding to the semiconductor layer of each TFT in the image display region and the peripheral driver circuit region.
[0052]
Next, as shown in FIG. 5A, using the resist film 402 as a mask, the p-Si film 401b is etched by RIE (reactive ion etching) using a chlorine-based gas to form the p-Si layer 1. To do. In addition to dry etching such as RIE, wet etching using a chemical solution such as etching using hydrofluoric acid can also be used.
[0053]
Next, as shown in FIG. 5B, after the resist film 402 is peeled off, as shown in FIG. 5C, a mixed gas of TEOS (tetraethyl orthosilicate) and oxygen gas is used as a source gas by PECVD. A gate insulating film 2 having a thickness of 50 to 120 nm is formed. Here, as the source gas, SiH ₄ And oxygen gas may be used.
[0054]
Next, as shown in FIG. 5D, a resist film 403 having a shape in which a portion corresponding to a region functioning as a capacitor in the semiconductor layer 1 in the image display region is removed is formed. Then, using this resist film 403 as a mask, phosphorus ions as impurities are 5 × 10 5 by ion implantation. ¹⁴ -10 ¹⁶ Piece / cm ² The capacitor electrode 1f is formed by injecting the semiconductor layer 1 at a dose of 1 μm. After the implantation, the resist film 403 is peeled off.
[0055]
Next, as shown in FIG. 6A, a 400 nm aluminum film 405a and a 100 nm titanium film 405b are formed on the gate insulating film 2 by PVD (physical vapor deposition).
[0056]
Next, as shown in FIG. 6B, a resist film 404 having a shape corresponding to a scanning line, a gate electrode, and a capacitor line is formed. Using this as a mask, as shown in FIG. 6C, the aluminum film 405a and the titanium film 405b are etched by RIE using a fluorine-based or chlorine-based gas. After etching, the resist film 404 is peeled off, and as shown in FIG. 6 (d), the scanning line 3, the gate electrodes 3a and 103, and the capacitor line having a multilayer film composed of a lower layer made of aluminum and an upper layer made of titanium. 3b is obtained.
[0057]
Next, as shown in FIG. 7A, a resist film 405 is formed which covers the entire image display region and from which the resist is removed only at a position corresponding to the semiconductor layer to be a P-channel TFT in the peripheral circuit region. . This resist film is made of a novolac resin, and is formed by applying a resist on a substrate by spin coating, exposing the resist, and developing a TMAH aqueous solution. Here, since the resist film 405 is formed so as to cover the image display region, the scanning line, the capacitor line, and the gate electrode in the image display region are not etched by the developer. Thereafter, the resist film 405 and the gate electrode 103 corresponding to the P channel type TFT are used as a mask to form 5 × 10 5 on the semiconductor film 1. ¹⁴ -10 ¹⁶ Piece / cm ² Are implanted by ion implantation to obtain the semiconductor layer 1 having the channel region 1a and the source / drain regions 1g and 1h which are self-aligned with the gate electrode 103.
[0058]
Next, as shown in FIG. 7B, the resist film 405 is stripped with a stripping solution.
[0059]
Thereafter, as shown in FIGS. 7C and 13, a resist film 406 is formed. Here, FIG. 13 is a plan view showing a portion where the resist film 406 is formed in the image display region. In the figure, the resist film 406 is indicated by a bold line with a lower right side.
[0060]
As shown in FIG. 7D, the resist film 406 is formed in a shape corresponding to the semiconductor layer to be the P-channel TFT 130a in the peripheral circuit region. On the other hand, as shown in FIG. 13, the resist film 406 in the image display region covers the capacitor line 3b corresponding to the region where the capacitor line 3b and the data line 6 to be formed later overlap, and is formed later on the scanning line 3. It is formed so as to cover the scanning line 3 corresponding to the area where the data line 6 to be overlapped. Here, the resist film 406 is not formed in a region where the semiconductor layer 1 and the scanning line 3 overlap, that is, a region serving as a channel region of the semiconductor layer, but impurity ions are not implanted into this channel region. The resist film 406 may be formed at a position corresponding to the electrode 3a. In the present embodiment, the semiconductor layer as the capacitor electrode corresponding to the region where the data line 6 and the protrusion of the capacitor line 3b overlap is completely covered with the protrusion of the capacitor line 3b in plan view. It has become. For this reason, impurity ions are implanted in the semiconductor layer portion as the capacitor electrode before the capacitor line 3b is formed (FIG. 5D). Therefore, impurity ions are not implanted into the semiconductor layer portion as the capacitor electrode in the process after the capacitor line is formed. Therefore, as shown in FIG. 13, even if the semiconductor layer is arranged, the data line The resist film 406 can be disposed so as to cover the capacitor line in the region where 6 and the capacitor line 3b overlap. The resist film 406 is made of a novolac resin, and is formed by applying a resist on a substrate by spin coating, exposing the resist, and developing with a TMAH aqueous solution. In the present embodiment, since part of the scanning lines 3 and the capacitor lines 3b can be protected from the developer by the resist film 406 during development at the time of forming the resist film, the scanning lines 3 and the capacitor lines 3b It is not etched.
[0061]
Next, using this resist film 406, the gate electrode 3a, the gate electrode 103 corresponding to the N-channel TFT 130a, and the capacitor line 3b as a mask, 1 × 10 ¹³ ~ 2x10 ¹⁴ Piece / cm ² The phosphorus ions are implanted by an ion implantation method. Thus, in the peripheral circuit region, the channel region 1a self-aligned with the gate electrode 103, the high concentration source region 1d to be formed later, the low concentration source region 1b having a lower impurity concentration than the high concentration drain region 1e, the low concentration The semiconductor layer 1 corresponding to the N-channel TFT having the drain region 1c is obtained. Further, in the image display region, two channel regions 1a (only one is shown) are formed so as to sandwich the two channel regions. Impurities are higher than those of the high concentration source region 1d and the high concentration drain region 1e to be formed later. A semiconductor 1 having a low concentration, a low concentration source region 1b and a low concentration drain region 1c is obtained. Next, the resist film 406 is stripped with a stripping solution.
[0062]
Thereafter, as shown in FIGS. 8A and 14, a resist film 407 is formed. FIG. 14 is a plan view showing a portion where the resist film 407 is formed in the image display area. In the figure, the resist film 407 is indicated by a bold line with a lower right side.
[0063]
As shown in FIG. 8A, the resist film 407 covers the peripheral portions of the gate electrode 103 of the N-channel type TFT 130a in the peripheral drive circuit region and the gate electrode 3a in the image display region, and the P-channel type TFT 130b. The semiconductor layer is covered. Further, as shown in FIG. 14, the resist film 407 covers the capacitor line 3b corresponding to the region where the capacitor line 3b and the data line 6 to be formed later overlap, and the scanning line 3 and the data line 6 formed later. Are formed so as to cover the scanning line 3 corresponding to the overlapping region. The resist film 407 is made of a novolak resin, and is formed by applying a resist on a substrate by spin coating, exposing the resist, and developing with a TMAH aqueous solution. In the present embodiment, at the time of this development, a part of the scanning line 3 and the capacitor line 3b can be protected from the developer by the resist film 407, so that the scanning line 3 and the capacitor line 3b are etched. There is no.
[0064]
Next, as shown in FIG. 8A, 5 × 10 5 is applied to the semiconductor layer 1 using the resist film 407 as a mask. ¹⁴ -10 ¹⁶ Piece / cm ² The phosphorus ions are implanted by an ion implantation method. Thereafter, the resist film 407 is stripped with a stripping solution. Thus, as shown in FIG. 8B, the TFT in the image display area and the N-channel TFT in the peripheral drive circuit area have a low concentration source region 1b, a low concentration drain region 1c, and an impurity concentration higher than these. Thus, a semiconductor layer having an LDD structure having the high concentration source region 1d and the high concentration drain region 1e can be obtained.
[0065]
Next, as shown in FIG. 8 (c), SiOOS having a thickness of 500 nm is formed using TEOS and ozone gas as source gases by PECVD so as to cover the gate electrodes 103, 3a and the capacitor line 3b. ₂ An insulating film 4 made of is formed. Thereafter, an activation heat treatment (activation annealing treatment) is performed under a temperature condition of 400 ° C. in order to activate the impurity ions. Here, since the scanning line and the capacitance line at the intersection of the data line, the scanning line, and the capacitance line formed later are not etched by the developer used for forming the resist film in the previous process, The cross section of the capacitor line is not overhanged, and no crack is generated in the insulating film.
[0066]
Next, as shown in FIG. 8D, contact holes for connecting the source / drain regions of each TFT in the peripheral circuit region and the source / drain formed later, and the source region of the TFT in the image display region And a resist film 409 patterned into a shape corresponding to a contact hole for connecting a source hole formed later and a drain hole of a TFT in an image display region and a drain formed later. To do.
[0067]
As shown in FIG. 9A, the insulating film 4 is etched using the resist film 409 as a mask to form contact holes 5, 5a, 5b. Thereafter, the resist film 409 is peeled off to obtain the structure of FIG.
[0068]
Next, as shown in FIG. 9C, an aluminum / titanium multilayer film 410 having a thickness of 300 to 1000 nm is formed on the insulating film 4 by the PVD method. Further, as shown in FIG. 9D, a resist film 411 is formed on the aluminum / titanium multilayer film 410 so that the portions corresponding to the data lines, source, and drain are removed.
[0069]
Next, as shown in FIG. 10A, the resist film 411 is peeled after the aluminum / titanium multilayer film 410 is etched by RIE using chlorine-based gas using the resist film 411 as a mask. As a result, as shown in FIG. 10B, in the peripheral circuit region, the sources electrically connected to the source regions 1d and 1g and the drain regions 1e and 1h of the semiconductor layers of the N-channel TFT and the P-channel TFT, respectively. Electrodes 106a and 107a and drain electrodes 106b and 107b are obtained. In the image display region, the data line 6 and the conductive layer 6b which also serve as the source 6a electrically connected to the source region 1d and the drain region 1e of the semiconductor layer are obtained. Here, since no crack is generated in the insulating film 4, the data line and the scanning line or the capacitor line are not short-circuited through the crack, and there is no disconnection of the data line due to the crack.
[0070]
Next, as shown in FIG. 10C, the insulating film 7 is formed by PECVD using a mixed gas of TEOS and oxygen gas as a source gas so as to cover the source, drain and data lines. Here, as a method for forming the interlayer insulating film 7, an atmospheric pressure CVD method may be used, and as a source gas, a mixed gas of TEOS and ozone gas, or SiH is used. ₄ A mixed gas of oxygen gas and oxygen gas may be used. Further, not only an inorganic film but also an organic film such as an acrylic film can be used. In this case, since a film having a thickness larger than that of the inorganic film can be easily obtained, the film can also be used as a planarizing film.
[0071]
Next, as shown in FIG. 10D, a resist film 413 is formed on the interlayer insulating film 7 from which the resist corresponding to the contact hole connecting the conductive layer 6b and the pixel electrode to be formed later is removed. . Thereafter, as shown in FIG. 11A, the interlayer insulating film 7 is etched by the RIE method or the wet etching method using the resist film 413 as a mask, the resist film 413 is peeled off, and as shown in FIG. Then, an interlayer insulating film 7 having a contact hole 8 is obtained.
[0072]
Next, as shown in FIG. 11C, an ITO film 414 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by sputtering. Thereafter, as shown in FIG. 12A, a resist film 415 corresponding to the pixel electrode shape is formed on the ITO film 414, and the ITO film 414 is wet-etched with aqua regia or HBr using this as a mask, Or CH ₄ Alternatively, by performing dry etching by the RIE method using a gas such as HI, the pixel electrode 9a is obtained as shown in FIG.
[0073]
As described above, in the present embodiment, the resist film is formed so as to cover the scanning line or the capacitive line in the region where the scanning line or the capacitive line and the data line overlap with the formation of the resist film as the mask for ion implantation. By forming the liquid crystal device, it is possible to prevent occurrence of a short circuit between the scan line, the capacitor line, and the data line, and disconnection of the data line, so that a liquid crystal device having no display variation in the plane and having good display characteristics can be obtained. it can.
[0074]
In the present embodiment, the scanning line layer has a multilayer structure in which the lower layer is made of aluminum and the upper layer is made of titanium, so that generation of hillocks can be prevented, and a short circuit between the scanning line layer and the data line layer due to hillocks can be prevented. Further, in the present embodiment, it is possible to prevent the insulating film from cracking due to the overhang shape, which is a problem in the case of such a multilayer structure.
[0075]
In the above embodiment, a multilayer film of aluminum and titanium is used for the scanning line, but instead of aluminum, an aluminum alloy such as an Al—Nd alloy or Al—Si alloy, molybdenum instead of titanium, or these A layer containing a refractory metal that prevents generation of hillocks such as an alloy can also be used. In addition, a multilayer film in which a layer containing aluminum is an upper layer, or a single layer film made of aluminum or an alloy thereof can be used as the scanning line.
[0076]
Further, in the above-described embodiment, the resist films 406 and 407 have shapes covering the scanning lines and the capacitance lines corresponding to the intersections between the data lines and the scanning lines and the intersections between the data lines and the capacitance lines, respectively. However, a resist film may be formed so as to cover the scanning lines and the capacitor lines. As a result, since there is no etching of the scanning lines and the capacitance lines with the developer, the wiring width is not reduced, a uniform wiring width can be obtained within the screen, and there is no display variation and the liquid crystal device has good display characteristics. Can be obtained.
[0077]
However, even in this case, a resist film cannot be formed on the semiconductor layer in the region where ions are implanted.
[0078]
Although the liquid crystal device has been described in the above embodiment, the present invention is not limited to this, and the present invention can also be applied to various electro-optical devices such as a semiconductor device or electroluminescence.
[Brief description of the drawings]
FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of matrix pixels that form an image forming area in a liquid crystal device according to an embodiment.
FIG. 2 is a plan view of a TFT array substrate on which data lines, scanning lines, and pixel electrodes are formed in an image display area of the liquid crystal device according to the embodiment.
3 is a longitudinal sectional view in each of a peripheral circuit region and an image display region of the liquid crystal device of the embodiment, and the longitudinal sectional view in the image display region is a sectional view taken along line AA ′ in FIG. 2; .
FIG. 4 is a process diagram (part 1) illustrating a manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
FIG. 5 is a process diagram (part 2) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
6 is a process diagram (part 3) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order. FIG.
FIG. 7 is a process diagram (part 4) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
FIG. 8 is a process diagram (part 5) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
FIG. 9 is a process diagram (part 6) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
FIG. 10 is a process diagram (part 7) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
FIG. 11 is a process diagram (part 8) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
FIG. 12 is a process diagram (part 9) illustrating the manufacturing process of the TFT array substrate of the liquid crystal device according to the embodiment in order.
13 is a plan view showing the shape of a resist film 406 in the image display region in the step of FIG. 7D.
14 is a plan view showing the shape of a resist film 407 in the image display region in the step of FIG.
FIG. 15 is a partially enlarged view of a thin film transistor for explaining a problem in a conventional method of manufacturing a liquid crystal device.
[Explanation of symbols]
1 ... Semiconductor layer
2 ... Gate insulation film
3 Scanning line
3a ... Gate electrode
4 ... Insulating film
6 ... Data line
6a ... Source electrode
9a: Pixel electrode
60 ... Board
406, 407 ... Resist film

Claims (8)

An electro-optic having a plurality of scanning lines formed of a layer containing aluminum, a plurality of data lines, a transistor connected to the scanning lines and the data lines, and a region where the scanning lines and the data lines intersect A device manufacturing method comprising:
Forming a first semiconductor layer and a second semiconductor layer on a substrate;
Forming a gate insulating film on the substrate so as to cover the first and second semiconductor layers;
A scanning line having a first gate electrode on a gate insulating film at a position corresponding to at least a channel region of the first semiconductor layer, and a second gate on a gate insulating film at a position corresponding to at least the channel region of the second semiconductor layer. Forming an electrode;
Covering a region where the scan line and the data line intersect and forming a first resist film corresponding to the first semiconductor layer;
Implanting first conductivity type impurity ions into the second semiconductor layer using the first resist film and the second gate electrode as a mask;
Covering a region where the scanning line and the data line intersect and forming a second resist film corresponding to the second semiconductor layer;
Implanting impurity ions of a second conductivity type different from the first conductivity type into the first semiconductor layer using the second resist film and the first gate electrode as a mask;
Forming an insulating film so as to cover the gate electrode and the scanning line;
And a step of forming a plurality of data lines on the insulating film so as to intersect with the scanning lines. The electro-optical device includes an image display area and a drive circuit area for controlling display in the image display area,
A thin film transistor having a complementary transistor structure having the first semiconductor layer and the second semiconductor layer is disposed in the driving circuit region,
The method of manufacturing an electro-optical device according to claim 1 , wherein the first semiconductor layer is disposed in the image display region. Forming a capacitance line in the same layer as the scanning line and substantially parallel to the scanning line,
2. The method of manufacturing an electro-optical device according to claim 1 , wherein a region where the capacitor line and the data line intersect is covered with the first resist film and the second resist film . Electrooptical of claim 1 or claim 2, wherein at least a part of the scanning lines and the layer composed of the scanning lines and the same layer is covered with the first resist film and the second resist film Device manufacturing method. The step of forming the first resist film and the second resist film includes:
Applying a resist on the substrate;
4. The method according to claim 1 , further comprising a step of forming the first resist film or the second resist film by exposing and developing the resist . 5. Manufacturing method of the electro-optical device.   6. The method of manufacturing an electro-optical device according to claim 1, wherein the layer made of the same layer as the scanning line includes aluminum.   7. The method of manufacturing an electro-optical device according to claim 6, wherein the scanning line and the layer made of the same layer as the scanning line have a multilayer structure including a lower layer containing aluminum and an upper layer containing a refractory metal.   8. The method of manufacturing an electro-optical device according to claim 7, wherein the upper layer is a layer containing molybdenum or titanium.

Images