JP2001166701A - Manufacturing method for electrooptical device and semiconductor substrate and electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high-quality semiconductor substrate free from an interwiring short circuit, disconnection and the defect of a switching element due to static electricity generated during a manufacturing process and an electrooptical device. SOLUTION: A semiconductor substrate 410 on which many surface segments TFT 200 are provided is constituted so that scanning lines 3 and data lines 6 are arranged by crossing with each other on a substrate 60 and respective end parts of the scanning lines 3 and the data lines 6 are electrically connected to a semiconductor pattern 203 which is arranged at the periphery of a display area through contact holes 204, 205, 206. By making the semiconductor substrate 410 have such a construction, even when static electricity is generated during the manufacturing process of the substrate 410 and during the assembling of an electrooptical device in which TFT array substrates 200 are used, since the static electricity is dispersed to the semiconductor pattern 203 and plural wirings through the pattern and the electricity is never locally charged on the substrate, the interwiring short circuit, the disconnection and the breakage and the characteristic fluctuation of a switching element due the static electricity are prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing an electro-optical device, a semiconductor substrate, and an electro-optical device. In particular, the present invention relates to a manufacturing method and a structure for preventing occurrence of short-circuit failure between wires, disconnection failure, and characteristic fluctuation destruction of switching elements due to static electricity or the like generated during a manufacturing process.

[0002]

2. Description of the Related Art Generally, in the case of an electro-optical device, for example, an active matrix type liquid crystal device having a thin film transistor (hereinafter referred to as a TFT) as a switching element, an electro-optical device such as a liquid crystal layer is provided between a TFT array substrate and a counter substrate. A substance is sandwiched between them.

[0003] Such a TFT array substrate has a plurality of scanning lines and a plurality of data lines arranged crossing each other on the substrate, and a scanning line and a data line arranged at each intersection of the scanning lines and the data lines. And a pixel electrode electrically connected to the thin film transistor.

The TFT array substrate has a data line and a scanning line in order to prevent short-circuiting between wires and disconnection due to static electricity generated during the manufacturing process, and fluctuation and destruction of TFT characteristics due to electrostatic breakdown of an insulating film. A wiring pattern called a rectangular short ring is formed so as to surround and short-circuit the ends of the data line and the scanning line. In the rectangular short ring, the wiring on the side parallel to the scanning line is formed from the same layer as the scanning line, and the wiring on the side parallel to the data line is formed from the same layer as the data line. . The wiring on the side parallel to the scanning lines of the short ring and the wiring on the side parallel to the data lines are short-circuited at the corners of the short ring by contact holes formed in the insulating film interposed between the scanning lines and the data lines. And are electrically connected.

[0005]

However, since the short ring is completed through the process of forming the data line and the scanning line, it is effective against the electrostatic breakdown in the process after the formation of both wires, but the short ring is effective. It was insufficient for electrostatic breakdown in the process before the ring was completed. As a result, static electricity is generated in a process before the short ring is formed, and the substrate is charged, so that the thin film transistor is destroyed, the characteristics change due to the injection of the charge into the insulating film, and the wiring is short-circuited or disconnected. May occur.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and prevents a TFT from being broken or a characteristic from being changed due to static electricity during a TFT array substrate manufacturing process or a panel assembling process, short-circuiting or disconnection of wiring, and a high-quality semiconductor. It is an object to provide a substrate, an electro-optical device, and a method for manufacturing the same.

[0007]

According to another aspect of the present invention, there is provided a method of manufacturing an electro-optical device having a display area on a substrate. Forming a semiconductor pattern adjacent to a region, and forming a plurality of wirings extending from the display region and the display region so as to be electrically connected to the semiconductor pattern. Features.

According to such a configuration of the present invention, since a plurality of wirings are collectively short-circuited by the semiconductor pattern,
Even if static electricity is generated during the manufacturing process, the static electricity is distributed to a plurality of wirings through the semiconductor pattern and the semiconductor pattern.
This has the effect of preventing short-circuiting between wires and disconnection without being locally charged on the substrate.

Further, the end portions of the plurality of wirings are located on the semiconductor pattern. According to such a configuration, since the semiconductor pattern is formed before the wiring is formed, it is possible to prevent a short circuit and a disconnection between the wirings due to static electricity after the wiring is formed, and to obtain a high-quality electro-optical device without a short circuit and a disconnection defect. Can be.

[0010] Further, the plurality of wirings are a first wiring and a second wiring which cross each other, and the semiconductor pattern is formed so as to surround the display area.
As described above, by forming the semiconductor pattern in a ring shape, the first wiring and the second wiring are short-circuited via the semiconductor pattern, and even if static electricity is generated during the manufacturing process, the static electricity is generated by the semiconductor pattern and the second wiring. Since it is dispersed to a plurality of wirings via this, there is an effect that a local short-circuit between the wirings and a disconnection are prevented without being locally charged on the substrate. Further, by forming the semiconductor pattern before forming the first wiring and the second wiring, short-circuiting and disconnection between wirings due to static electricity after the formation of the wiring can be prevented, and a high-quality electro-optical device can be obtained.

The semiconductor device may further include a semiconductor layer electrically connected to a wiring in the display area, wherein the semiconductor layer is formed in the same layer as the semiconductor pattern. According to such a configuration, since the semiconductor pattern and the wiring are short-circuited, even if static electricity is generated, the static electricity is dispersed to the semiconductor pattern and a plurality of wirings via the semiconductor pattern, so that the static electricity is locally formed on the substrate. The switching element having the semiconductor layer is not destroyed by static electricity and the characteristics are not changed. In the case where a switching element in which a gate electrode forming a part of a wiring is provided over a semiconductor layer via an insulating film is provided, an antistatic structure is formed at the same time as the completion of the switching element. This has the effect of preventing electrostatic breakdown and characteristic fluctuations. Further, the semiconductor pattern and the semiconductor layer can be formed at the same time, and the number of manufacturing steps does not increase.

Further, the semiconductor pattern is formed of polysilicon into which impurity ions have been implanted. With such a configuration, there is an effect that a low-resistance semiconductor pattern is obtained.

[0013] The method may further include a step of electrically disconnecting the connection between the wiring and the semiconductor pattern. According to such a configuration, it is possible to obtain an electro-optical device in which a plurality of wirings are insulated from each other and there is no short-circuit or disconnection between the wirings. This cutting is performed after the completion of the semiconductor substrate on which the wiring is arranged on the substrate. For example, when a semiconductor substrate having a semiconductor pattern is used in a liquid crystal device, a TFT array substrate, which is a semiconductor substrate, and a counter substrate are arranged to face each other, and after the liquid crystal panel assembling step of holding liquid crystal between the two substrates, the semiconductor pattern and the semiconductor pattern are immediately formed A cutting step for cutting the connection with the wiring can be provided. Alternatively, after the panel is assembled, a cutting step can be provided immediately before the connecting step of connecting the input terminal portion of the wiring and the external circuit. Further, a cutting step may be provided before the liquid crystal panel assembling step. However, by leaving the semiconductor pattern at the time of assembling the panel, it is possible to prevent a short circuit between wires, disconnection, and destruction of a switching element due to static electricity generated at the time of assembling. As a cutting method, a portion of the substrate where the semiconductor pattern is arranged may be cut by a scribe cutter or the like, or only the connection between the semiconductor pattern and the wiring may be cut by a laser or the like without cutting the substrate. .

Further, a plurality of the display areas are arranged on the substrate. According to such a configuration, a plurality of semiconductor substrates can be obtained from one substrate, and productivity can be improved. In the case of such a multi-panel taking of a plurality of semiconductor substrates from one substrate, the semiconductor pattern may be arranged for each semiconductor substrate,
One semiconductor pattern may be shared by a plurality of semiconductor substrates.

Another method of manufacturing an electro-optical device according to the present invention is as follows.
In a method of manufacturing an electro-optical device having a display region in which a plurality of transistors each having a semiconductor layer are arranged on a substrate, the semiconductor layer is formed on the substrate, and the storage layer is formed of the same layer as the semiconductor layer in the display region. Forming a capacitor electrode and a semiconductor pattern formed of the same layer as the semiconductor layer adjacent to the display region; and extending from the display region and the display region to be electrically connected to the semiconductor pattern. Forming a plurality of wirings, and implanting impurity ions into the storage capacitor electrode and the semiconductor pattern.

According to such a configuration of the present invention, since a plurality of wirings are collectively short-circuited by the semiconductor pattern,
Even if static electricity is generated during the manufacturing process, the static electricity is distributed to a plurality of wirings through the semiconductor pattern and the semiconductor pattern.
This has the effect of preventing short-circuiting between wires and disconnection without being locally charged on the substrate. Further, by implanting the impurity ions into the semiconductor pattern, the resistance of the semiconductor pattern can be reduced. The manufacturing process can be shortened by simultaneously performing the implantation process of (1).

According to another aspect of the present invention, there is provided a method for manufacturing an electro-optical device, comprising the steps of: forming a display region in which a plurality of transistors each having a semiconductor layer are disposed on a substrate; and forming a semiconductor pattern disposed adjacent to the display region. A method for manufacturing an electro-optical device having the display region and a plurality of wirings extending from the display region and formed to be electrically connected to the semiconductor pattern, wherein the semiconductor pattern is formed on the substrate. Forming, forming an insulating film so as to cover the semiconductor pattern, implanting impurity ions into the semiconductor pattern through the insulating film, and forming the insulating film at a predetermined position on the semiconductor pattern. Removing
Forming a conductive film on the insulating film including the predetermined portion. Further, another manufacturing method of the electro-optical device includes a display region on which a plurality of transistors each having a semiconductor layer are disposed on a substrate; a semiconductor pattern disposed adjacent to the display region; In a method of manufacturing an electro-optical device having a plurality of wirings formed to extend from a display region and electrically connect to the semiconductor pattern, a step of forming the semiconductor pattern on the substrate; Implanting impurity ions into the semiconductor pattern, forming an insulating film so as to cover the semiconductor pattern, removing the insulating film at a predetermined location on the semiconductor pattern, and including the predetermined location Forming a conductive film on the insulating film.

According to such a configuration, since a plurality of wirings are collectively short-circuited by the semiconductor pattern, even if static electricity is generated during the manufacturing process, the static electricity is transmitted to the plurality of wirings via the semiconductor pattern and the semiconductor pattern. Therefore, there is an effect that a local short-circuit between wires and disconnection are prevented without being locally charged on the substrate. Furthermore, the resistance of the semiconductor pattern can be reduced by performing ion implantation on the semiconductor pattern. This ion implantation step can be performed directly on the semiconductor pattern or via an insulating film.

The insulating film may be a silicon oxide film.

A semiconductor substrate according to the present invention is a semiconductor substrate having a display region on a substrate, wherein the semiconductor pattern is disposed on the substrate so as to be adjacent to the display region, and the display region and the semiconductor pattern extend from the display region. And a plurality of wirings electrically connected to the semiconductor pattern.

According to such a configuration of the present invention, since a plurality of wirings are collectively short-circuited by the semiconductor pattern,
Even if static electricity is generated during the manufacturing process, the static electricity is dispersed to the semiconductor pattern and a plurality of wirings via the semiconductor pattern.
There is an effect that a short circuit between wires and disconnection are prevented without being locally charged on the substrate. Further, when an electro-optical device is formed using a semiconductor substrate having such a configuration, there is an effect that a short circuit between wires, a disconnection, and the like due to static electricity generated in an assembly process can be prevented.

Further, the end portions of the plurality of wirings are located on the semiconductor pattern. According to such a configuration, since the semiconductor pattern is formed before the wiring is formed, a short circuit between wires due to static electricity after wire formation and disconnection can be prevented, and a high quality semiconductor substrate free from short circuit and disconnection failure can be obtained. it can.

Further, the plurality of wirings include a first wiring and a second wiring which cross each other, and the semiconductor pattern is arranged so as to surround the display area. As described above, by forming the semiconductor pattern in a ring shape, the first wiring and the second wiring are short-circuited via the semiconductor pattern, and even if static electricity is generated during the manufacturing process, the static electricity is generated by the semiconductor pattern and the second wiring. Since it is dispersed to a plurality of wirings via this, there is an effect that a local short-circuit between the wirings and a disconnection are prevented without being locally charged on the substrate. Further, when an electro-optical device is formed using a semiconductor substrate having such a configuration, there is an effect that a short circuit between wires and a disconnection due to static electricity generated in an assembly process are prevented.

Further, a semiconductor layer electrically connected to the wiring in the display area is arranged, and the semiconductor layer is formed of the same layer as the semiconductor pattern. According to such a configuration, since the semiconductor pattern and the wiring are short-circuited, even if static electricity is generated, the static electricity is dispersed to the semiconductor pattern and a plurality of wirings via the semiconductor pattern, so that the static electricity is locally formed on the substrate. And the switching element having the semiconductor layer is not destroyed by static electricity and the characteristics are not changed. Further, when an electro-optical device is formed using a semiconductor substrate having such a configuration, there is an effect that a switching element having a semiconductor layer, which is caused by static electricity generated during an assembling process, is prevented from being destroyed and characteristics from being changed.

Further, the semiconductor pattern is made of polysilicon into which impurity ions have been implanted.
With such a configuration, there is an effect that a low-resistance semiconductor pattern is obtained.

An electro-optical device according to the present invention includes the above-described semiconductor substrate. According to such a configuration, a short circuit between wires due to static electricity, disconnection, destruction of a switching element, characteristic fluctuation, and the like can be prevented even in an assembly process of the electro-optical device, and an effect of obtaining a high-quality electro-optical device can be obtained. Have.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described.
An example in which the invention is applied to a liquid crystal device as an electro-optical device will be described with reference to the drawings. In each of the drawings, the scale of each layer and each member is different in order to make each layer and each member have a size recognizable in the drawings.

The structure of the liquid crystal device according to the present invention will be described with reference to FIG. FIG. 1 is an equivalent circuit of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming a display area of a liquid crystal device.

The liquid crystal device 400 has a liquid crystal panel having a display area in which the scanning lines 3 and the data lines 6 intersecting each other are arranged, and supplies a driving signal to each of the scanning lines 3 and the data lines 6. A driving circuit board on which the scanning line driving circuit 104 and the data line driving circuit 101 are arranged.

The liquid crystal panel has a structure in which a liquid crystal layer is sandwiched between a TFT array substrate and a counter substrate. The opposing substrate includes a light-shielding film formed in a matrix on a glass substrate, an opposing electrode made of an ITO film formed sequentially over the glass substrate, and an alignment film made of polyimide.

In the TFT array substrate 200, the capacitor lines 3b and the scanning lines 3
A data line 6 intersecting the scanning line 3, a pixel electrode 9a arranged in a matrix at each intersection of the scanning line 3 and the data line 6, and a pixel electrode 9a for controlling the pixel electrode 9a. A thin film transistor (hereinafter, referred to as a TFT) 30 is provided. The scanning line driving circuit 104 and the data line driving circuit 101 are connected to terminals of the scanning line 3 and the data line 6, respectively, and supply signals to the respective lines.

In the present embodiment, such a TFT
As shown in FIG. 2, a plurality of TFT substrates obtained by cutting a plurality of semiconductor substrate 410 from a single mother glass 60 as shown in FIG. An array substrate was used.

A multi-faced semiconductor substrate 410 before being separated into individual TFT array substrates 200 will be described below with reference to FIG.
This will be described with reference to FIG. FIG. 2 is a plan view of the multi-faced semiconductor substrate, and FIG. 3 is an enlarged plan view of a region surrounded by a circle A in FIG. FIG. 4 shows the TF when cut along the line BB ′ in FIG.
FIG. 5 is a vertical sectional view of the TFT array substrate when cut along the line CC ′ in FIG. 3.

As shown in FIG. 2, the multi-faced semiconductor substrate 4
Reference numeral 10 denotes a TFT array substrate 200 on the mother glass 60.
Are arranged in four display areas 201 corresponding to. Polysilicon into which P ions have been implanted as a semiconductor pattern 203 (in FIG. 2, diagonally lower right) is disposed between the peripheral portion of the mother glass 60 and the adjacent display region 201. The semiconductor pattern 203 is adjacent to each display area 201 and is arranged in a peripheral portion so as to surround each display area 201. On the mother glass 60,
Each of the display areas 201 and a plurality of linear scanning lines (not shown) extending in the x-axis direction and a plurality of linear data lines (not shown) extending in the y-axis direction. Are arranged so that the input terminal portion of the data line is located at the upper side of each display area 201 and the input terminal portion of the scanning line is located at the left side portion. The ends of the display areas 201 on the input terminal side of the scanning lines and the data lines are located on the semiconductor pattern 203, and the ends of the scanning lines and the data lines are electrically connected to the semiconductor pattern 203. It is in a state where it has been done. The mother glass 60 has a scribe line 411 indicated by a dotted line.
Is cut along a scribe cutter or the like, and separated into individual TFT array substrates 200.

Next, the pixel structure in the display area of the TFT array substrate and the connection structure between the semiconductor pattern and the scanning lines and data lines will be described with reference to FIGS.

As shown in FIG. 3, a plurality of transparent pixel electrodes 9a are arranged in a matrix in the display area of the TFT array substrate.
Are provided, and the data line 6, the scanning line 3 (dotted line) and the capacitor line 3b (dotted line) are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6 is formed in a shape extending in the vertical direction, and the data line 6 is electrically connected to a source region 1d to be described later in the semiconductor layer 1 made of a polysilicon film (a hatched portion falling left) through a contact hole 5a. Connected, and the data line 6 is connected to the source region 1d.
In the vicinity of a, the width is increased. A conductive layer 6b formed in the same layer as the data line 6 is electrically connected to a later-described drain region 1e of the semiconductor layer 1 through a contact hole 5b. Is electrically connected to the pixel electrode 9a. Further, the scanning line 3 is arranged to face the channel region in the semiconductor layer 1, and the scanning line 3 functions as a gate electrode. In the present embodiment, the semiconductor layer 1
And the scanning line 3 overlap at two places,
It has a double gate structure. In the drawing, the scanning line 3
And the semiconductor layer 1 are overlapped in a plane, that is, the semiconductor layer at the position corresponding to the gate electrode is hidden by the scanning line,
Not shown. The capacitance line 3 b extends substantially linearly along the scanning line 3, and has a protruding portion protruding along the data line 6 from a portion intersecting with the data line 6. Some are located. Capacity line 3b
Overlaps a part of the pixel electrode 9a in a plane, forms a capacitance in this region, and further forms a capacitance with the pixel electrode 9a. The semiconductor layer 1 extends below the data line 6 and the scanning line 3, and is disposed opposite to the capacitance line 3 b extending along the data line 6 and the scanning line 3 via the insulating film 2 to reduce the capacitance. Has formed.

The semiconductor pattern 2 is provided around the display area.
03 (in the figure, a hatched portion falling rightward). The end of each scanning line 3 and the end of each data line 6 are located on the semiconductor pattern 203 and are electrically connected to the semiconductor pattern 203. It has been short-circuited. In the wiring portion of the semiconductor pattern 203 arranged in parallel with the scanning line 3, a dummy scanning line 412 arranged in the same layer and in parallel with the scanning line 3 is arranged. Semiconductor pattern 2
03 and the dummy scanning line 412 are in contact holes 205
, And the dummy scanning line 412 and the terminal portion of the data line 6 are electrically connected through the contact hole 206. Further, a wiring portion of the semiconductor pattern 203 arranged in parallel with the data line 6 is electrically connected to an end of the scanning line 3 via a contact hole 204.

The connection structure between the scanning line 3 and the semiconductor pattern 203 and the cross-sectional structure in the display region will be described with reference to FIG. The TFT array substrate 200 is a glass substrate 6
A base film 12 made of silicon oxide, a semiconductor layer 1 made of polysilicon, and a semiconductor pattern 203 are arranged on the substrate 0. On the semiconductor layer 1 and the semiconductor pattern 203, a gate insulating film 2 is arranged. On the gate insulating film 2, a scanning line 3 made of aluminum, a gate electrode 3a which is a part of the scanning line, and a capacitor line 3b are arranged. The end of the scanning line 3 is located on the wiring pattern 203, and the end of the scanning line 3 is electrically connected to the semiconductor pattern 203 by a contact hole 204 formed in the gate insulating film 2. Then, the scanning line 3 and the gate electrode 3a
In addition, an interlayer insulating film 4 is arranged so as to cover the capacitance line 3b. On the interlayer insulating film 4, a data line 6 and a conductive layer 6b formed in the same layer are arranged. The data line 6 is electrically connected to a source region of the semiconductor layer 1 described later by a contact hole 5a formed in the gate insulating film 2 and the interlayer insulating film 4, and a conductive layer 6b is formed in the interlayer insulating film 4. The contact hole 5b is electrically connected to a drain region of the semiconductor layer 1 described later. Further, an interlayer insulating film 7 is arranged to cover the data line 6 and the conductive layer 6b. The conductive layer 6b is formed on the interlayer insulating film 7 by the contact hole 8 formed in the interlayer insulating film 7.
It is electrically connected to the pixel electrode 9a made of an O (Indium Tin Oxide) film. Finally, covering the pixel electrode 9a,
An alignment film 16 made of polyimide is provided. And
If necessary, the substrate is cut along a scribe line 411 indicated by a dotted line to electrically cut the scanning line 3 and the semiconductor pattern 203. Used as an input terminal for supplying a signal from the outside. Here, the TFT in the display area
The semiconductor layer 1 may have an LDD (lightly doped drain) structure.

Next, a connection structure between the data line 6 and the semiconductor pattern 203 will be described with reference to FIG. TFT
In the array substrate 200, a base film 12 made of silicon oxide, a semiconductor layer 1 made of polysilicon, and a semiconductor pattern 203 are arranged on a glass substrate 60. On the semiconductor layer 1 and the semiconductor pattern 203, a gate insulating film 2 is arranged. On the gate insulating film 2, a scanning line (not shown) made of aluminum, a gate electrode (not shown) that is a part of the scanning line, a capacitance line (not shown), and a dummy scanning line 412 are arranged. I have. The dummy scanning line 412 and the semiconductor pattern 203 are electrically connected by a contact hole 205 formed in the gate insulating film 2. Further, scanning lines, gate electrodes, capacitance lines, dummy scanning lines 41
2, an interlayer insulating film 4 is formed. An end of the data line 6 formed on the interlayer insulating film 4 is electrically connected to the dummy scanning line 412 by a contact hole 204 formed in the interlayer insulating film 4. On the data line 6, an interlayer insulating film 7, a pixel electrode (not shown), an alignment film 1
6 are sequentially stacked. It should be noted that the semiconductor pattern 203 may be directly electrically connected via the contact hole 205 or 206.

Next, a method of manufacturing the multi-faced semiconductor substrate 410 shown in FIG. 2, which can take four TFT array substrates, will be described with reference to FIGS. FIG.
11 show sectional views corresponding to FIG. 4 and FIG.

First, as shown in FIG. 6A, a silicon oxide film (SiO 2) is formed as a base film 12 on a glass substrate 60 by a plasma enhanced (PE) CVD method or an ECR (electron cyclotron resonance) CVD method.
₂ ) with a thickness of about 200 to 500 nm. This base film has a function of preventing contamination of the surface of the glass substrate 60, impurities contained in the glass substrate, and the like from deteriorating the characteristics of the TFT 30.

Next, as shown in FIG.
An a-Si film 401a is laminated on the underlying film to a thickness of about 30 to 100 nm by the D method or the LP (low pressure) CVD method.

Next, as shown in FIG.
Excimer laser light such as KrF or XeCl
Irradiation of 100 to 600 mJ / cm ² results in a-S
The i-film is crystallized to obtain a p-Si film 401b. The irradiation intensity, irradiation time, and the like of the excimer laser light are appropriately adjusted depending on the thickness, film quality, and the like of the a-Si film. In the present embodiment, since the polysilicon layer can be obtained at a low temperature by laser annealing, a glass substrate that is less expensive than a silicon substrate can be used as the substrate.

Next, as shown in FIG. 6D, a photoresist film 40 having a shape corresponding to the semiconductor layer of the TFT in the display area and having a shape corresponding to the semiconductor pattern.
Form 2

Next, as shown in FIG. 6E, using the photoresist film 402 as a mask, the p-Si film 401b is etched by RIE (reactive ion etching) using a chlorine-based gas to form a p-Si film 401b in the display region. A semiconductor pattern 203 having a shape surrounding the semiconductor layer 1 and the display region is formed. still,
In addition to dry etching such as RIE, wet etching using a chemical solution such as etching using hydrofluoric nitric acid can also be used.

Next, as shown in FIG. 6F, after the photoresist film 402 is peeled off, as shown in FIG.
Using a mixed gas of TEOS (tetraethylorthosilicate) and oxygen gas as a source gas by a CVD method,
Gate insulating film 2 as a first insulating film having a thickness of 120 nm
To form Here, SiH ₄ and oxygen gas may be used as the source gas.

Next, as shown in FIG. 7A, a photoresist film 403 having a shape in which a region 1f functioning as a capacitor electrode and a region corresponding to the semiconductor pattern 203 in the semiconductor layer 1 in the display region are removed is formed. I do. Then, using this photoresist film 403 as a mask, 5 × 10 ¹⁴ to 10 ¹⁶ phosphorus ions / impurities are used as impurities by ion implantation.
At a dose of ² cm ² , the semiconductor layer 1 and the semiconductor pattern 203 are implanted.
To form After the implantation, the photoresist film 403 is peeled off.

Next, as shown in FIG. 7B, a photoresist film 404 is formed on the gate insulating film 2. Using this as a mask, the gate insulating film 2 is etched to form a contact hole 204 for short-circuiting the semiconductor pattern 203 with an end of a scanning line to be formed later, and the semiconductor pattern 20.
A contact hole 205 for short-circuiting the dummy scan line 3 with a dummy scan line to be formed later is formed. Thereafter, the photoresist film 404 is removed, and as shown in FIG. 7C, contact holes 204 and 205 are formed in the gate insulating film 2 corresponding to the semiconductor pattern 203 by the number of wirings to be formed later. You.

Next, as shown in FIG. 7D, a PVD (physical vapor deposition) is formed on the gate insulating film 2.
Method, a film thickness of 200 to 600 nm, here 400
An aluminum film 405 of nm is formed. Further, a scan line, a gate electrode, a capacitor line,
A photoresist film 406 having a shape corresponding to a dummy scanning line
To form Using this as a mask, the aluminum film 405 is etched by RIE using a fluorine-based or chlorine-based gas as shown in FIG. After the etching, the photoresist film 406 is peeled off, and as shown in FIG.
b, A dummy scanning line 412 is obtained. The end of the scanning line 3 is electrically connected to the semiconductor pattern 203 via the contact hole 204, and the dummy scanning line 412 is electrically connected to the semiconductor pattern 203 via the contact hole 205. Since the plurality of scanning lines 3 are collectively short-circuited to the semiconductor pattern 203 via the contact holes 204,
Even if static electricity occurs during the manufacturing process after the scanning line formation process,
Since the static electricity is dispersed to the plurality of scanning lines 3 via the semiconductor pattern and the semiconductor pattern, the static electricity is not locally charged on the substrate, and the short circuit between wires and the disconnection due to the static electricity can be prevented. In addition, since the switching element having the structure in which the gate electrode is arranged via the gate insulating film is completed at the same time when the above-described antistatic structure is formed by this step, the present step and the subsequent manufacturing steps In this case, switching element destruction and characteristic fluctuation due to static electricity can be prevented.

Next, as shown in FIG. 8A, using the scanning line 3, the gate electrode 3a and the capacitance line 3b as a mask, 5 × 10 ¹⁴ to 10 ¹⁶ phosphorus ions / cm ² are ion-implanted into the semiconductor layer 1. Inject by the injection method. As a result, FIG.
As shown in FIG. 5, a channel region 1a self-aligned with the gate electrode 3a, a low-concentration source region (not shown) arranged so as to sandwich the channel region 1a, a low-concentration drain region 1c, and a low-concentration drain region 1c. High-concentration source region 1d and high-concentration drain region 1e arranged so as to sandwich the region.
The semiconductor layer 1 having the LDD structure corresponding to the N-channel TFT having the following structure is obtained. Here, the high concentration regions 1d and 1e are:
The ion implantation process shown in FIG. 7A and the ion implantation process shown in FIG. 8A are formed by a total of two ion implantation processes, and the low concentration region is formed by the ion implantation process shown in FIG. It is formed by a process.

Next, as shown in FIG.
PEC so as to cover the capacitance line 3b and the dummy scanning line 412.
The interlayer insulating film 4 made of SiO _{2 having} a thickness of 1500 nm is formed by VD using TEOS and ozone gas as source gases. After that, activation heat treatment (activation annealing treatment) is performed at a temperature of 400 ° C. in order to activate the impurity ions.

Next, as shown in FIG. 8D, a high-concentration source region and a high-concentration drain region of the TFT in the display region are formed.
A portion corresponding to a contact hole for connecting a data line 6 to be formed later, a conductive layer 6b, and a contact hole for connecting a dummy scanning line 412 to a data line to be formed later was removed and patterned. A photoresist film 407 is formed.

Next, as shown in FIG. 9A, the interlayer insulating film 4 is etched using the photoresist film 407 as a mask to form contact holes 5a, 5b and 206. Thereafter, the photoresist film 407 is peeled off, and FIG.
(B) structure is obtained.

Next, as shown in FIG. 9C, an aluminum / titanium multilayer film 408 having a thickness of 300 to 1000 nm is formed on the interlayer insulating film 4 by a PVD method.
Further, as shown in FIG. 9D, a photoresist film 40 having a shape in which portions corresponding to data lines, sources, and drains are removed is formed on the aluminum-titanium multilayer film 408.
9 is formed.

Next, as shown in FIG. 10A, using the photoresist film 409 as a mask, the aluminum / titanium film 408 is etched by RIE using a chlorine-based gas, and then the photoresist film 411 is peeled off. As a result, as shown in FIG.
Electrically connected to the high concentration source region 1d of the semiconductor layer of
A conductive layer 6b electrically connected to the data line 6 and the high-concentration drain region 1e is obtained. The end of the data line 6 is electrically connected to the dummy scanning line 412 via the contact hole 206, and the semiconductor pattern 203 and the data line 6 are short-circuited via the dummy scanning line 412. In the present embodiment, the dummy scanning line 412 is formed.
A structure in which the data line and the semiconductor pattern are short-circuited without forming the dummy scanning line 412 may be adopted. By this process,
The scanning lines, data lines, and semiconductor patterns are short-circuited, and short-circuits between wiring due to static electricity generated during a later manufacturing process,
Disconnection, breakage of the TFT, and characteristic fluctuation can be prevented.

Next, as shown in FIG.
Interlayer insulating film 7 covering the lines, conductive layers and data lines with TEOS
PECVD using mixed gas of oxygen and oxygen gas as source gas
Formed by Here, the method for forming the interlayer insulating film 7 is as follows.
In this case, a normal pressure CVD method may be used.
And a mixed gas of TEOS and ozone gas or SiH
_FourA mixed gas of oxygen and oxygen gas may be used. Also, inorganic film
Not only can you use an acrylic or other organic film
In this case, it is easy to obtain a film thicker than the inorganic film.
Therefore, it can be used also as a flattening film.

Next, as shown in FIG. 10D, a photoresist film 414 from which a portion corresponding to a contact hole connecting the conductive layer 6b and a pixel electrode to be formed later is removed is formed on the interlayer insulating film 7. Form. Then, FIG.
As shown in FIG. 11B, the interlayer insulating film 7 is etched by RIE or wet etching using the photoresist film 414 as a mask, the photoresist film 414 is peeled off, and the contact holes 8 are formed as shown in FIG.
Is obtained.

Next, as shown in FIG. 11C, an ITO film 416 having a thickness of about 50 to 200 nm is formed on the interlayer insulating film 7 by a sputtering method. Then, FIG.
As shown in (d), a photoresist film 417 corresponding to the shape of the pixel electrode is formed on the ITO film 416, and the ITO film 416 is wet-etched with aqua regia or HBr using this as a mask, or CH _{4 is used.} Alternatively, by performing dry etching by RIE using a gas such as HI or the like, as shown in FIG.
Get.

Thereafter, a multi-surface semiconductor substrate having a plurality of display regions, which cover the pixel electrodes 9a, is obtained.

In the above manufacturing process, since the semiconductor pattern is formed before the wiring and the switching element are formed, static electricity is generated in the manufacturing process of the TFT array substrate after the formation of the wiring or after the formation of the switching element. However, this static electricity is distributed to the semiconductor patterns and wirings that short-circuit multiple wirings at once, preventing local electrification on the substrate, preventing short-circuiting between wirings, disconnection, destruction of switching elements, and characteristic fluctuation. can do.

Thereafter, the multi-faced semiconductor substrate 410 is cut along the scribe lines 411 as shown in FIG. 2, the semiconductor pattern 203 and the display area 200 are separated, and four TFT array substrates 200 are formed. . Then, the TFT array substrate and the counter substrate are arranged to face each other,
A liquid crystal panel is assembled by sandwiching liquid crystal between both substrates.
Each end of this wiring of the liquid crystal panel becomes an input terminal,
The liquid crystal device is manufactured by being connected to the driving circuit.

In this embodiment, the semiconductor pattern is 1
It is desirable that the resistance be 0 kΩ / sq.

In this embodiment, the TFT array substrate from which the semiconductor pattern has been removed is used at the time of assembling the liquid crystal panel. However, a TFT array substrate from which the semiconductor pattern is left may be used. By leaving the semiconductor pattern at the time of assembling the liquid crystal panel, even if static electricity is generated at the time of assembling, a short circuit between wires, disconnection, destruction of switching elements, and characteristic fluctuation do not occur, and a high quality liquid crystal device can be obtained. In this case, after assembling, the semiconductor pattern on which the wiring is short-circuited and the wiring may be electrically cut by, for example, cutting off the substrate on which the semiconductor pattern is arranged by scribe cutting.

In this embodiment, the wiring of the plurality of TFT array substrates is connected to one common semiconductor pattern in the state of the multi-faced semiconductor substrate. However, a semiconductor pattern is provided for each TFT array substrate. For example, each T
A ring-shaped semiconductor pattern may be formed so as to surround the display area for each FT array substrate.

In this embodiment, a semiconductor substrate in which one glass substrate is multi-faced is described as an example. However, a semiconductor substrate in which only one surface is formed on one glass substrate may be used.

In the present embodiment, the TFT array substrate having the display area and the drive circuit substrate on which the drive circuits are arranged are formed on separate substrates. However, as shown in FIG. The present invention is also applicable to an electro-optical device integrated with a driving circuit in which the driving circuit and the driving circuit are formed on the same substrate.

In this case, as shown in FIG. 12, the TFT array substrate 200 is
Are arranged, a data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the substrate 60, and a scanning line driving circuit 104 is provided along two sides adjacent to this one side. I have. Here, if the delay of the scanning signal supplied to the scanning lines arranged in the display area 201 does not matter, the scanning line driving circuit 104 may be provided on only one side. Further, on the remaining side of the TFT array substrate 200,
A plurality of wirings 105 are provided for connecting the scanning line driving circuits 104 provided on both sides of the display area. The mounting terminal 102 is electrically connected to the data line driving circuit 101 and the scanning line driving circuit 104 by a wiring 103, and functions as an input terminal of an external signal. Further, from the external circuit connection terminal 102, the extension portion 104 extends electrically connected to the mounting terminal 102, and the extension portion 104 is in a state of being short-circuited collectively by the semiconductor pattern 203. . Here, the extending portion 104 corresponds to an end of the wiring 103. Then, if necessary, scribe line 4
The electrical connection between the semiconductor pattern 203 and the wiring 102 is cut, for example, by cutting the substrate 60 along 11. With such a structure, the TFT area is provided in the display area of the TFT array substrate and the area where the driving circuit is arranged.
Needless to say, it is possible to prevent short-circuiting between wires, disconnection, TFT destruction, and characteristic fluctuation due to static electricity generated during an array substrate manufacturing process or a liquid crystal panel assembling process.

Further, in addition to the structure of the present embodiment, a short ring formed in the same layer as the scanning line and the data line may be provided. It can be further prevented. In this case, the short ring surrounds, for example, the display region and is arranged inside the ring-shaped semiconductor pattern. After the TFT array substrate is formed, the short ring is electrically cut by a laser or the like at a portion connecting the wirings to insulate the wirings. When the short ring is cut, the semiconductor pattern and the wiring may be cut electrically together.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming a display area in a liquid crystal device according to an embodiment.

FIG. 2 is a plan view of a semiconductor substrate on which a plurality of TFT array substrates are attached.

FIG. 3 is an enlarged plan view of the TFT array substrate in a region surrounded by a circle A in FIG. 2;

FIG. 4 is a sectional view taken along line BB ′ of FIG. 3;

FIG. 5 is a sectional view taken along line CC ′ of FIG. 3;

FIG. 6 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 7 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 8 is a process view (part 3) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 9 is a process diagram (part 4) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 10 is a process diagram (part 5) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 11 is a process diagram (part 6) for sequentially illustrating the manufacturing process of the TFT array substrate of the liquid crystal device of the embodiment.

FIG. 12 is a plan view when the present invention is applied to a TFT array substrate for a drive circuit integrated type.

DESCRIPTION OF SYMBOLS 1 ... semiconductor layer 3 ... scanning line 6 ... data line 30 ... TFT 60 ... substrate 200 ... TFT array substrate 203 ... semiconductor pattern 204,205,206 ... contact hole 400 ... liquid crystal device 410 ... multi-sided semiconductor substrate 411… Scribe line

Continued on front page F-term (reference) 2H092 GA59 JA25 JA29 JA38 JA42 JA44 JA46 JB13 JB23 JB32 JB33 JB38 JB51 JB57 JB63 JB69 JB79 KA04 KA07 KA12 KA16 KA18 MA05 MA08 MA14 MA15 MA16 MA18 MA19 MA20 MA22 MA27 NA30 PA06 5F110 AA14 AA26 BB01 BB02 CC02 DD02 DD13 EE03 EE41 FF30 GG02 GG13 GG45 GG47 HJ01 HJ04 HJ13 HJ22 HJ23 HM15 NN02 NN04 NN23 NN35 NN72 PP03 QQ04 QQ05 QQ11 5G435 AK17 BB12 CC

Claims (17)

[Claims] 1. A method of manufacturing an electro-optical device having a display area on a substrate, comprising: forming a semiconductor pattern on the substrate adjacent to the display area; and extending the display area and the display area. Forming a plurality of wirings so as to be electrically connected to the semiconductor pattern. 2. The method according to claim 1, wherein ends of the plurality of wirings are located on the semiconductor pattern. 3. The semiconductor device according to claim 1, wherein the plurality of wires are a first wire and a second wire crossing each other, and the semiconductor pattern is formed so as to surround the display region. 3. The method for manufacturing an electro-optical device according to claim 1. 4. The semiconductor device according to claim 1, further comprising a semiconductor layer electrically connected to a wiring in the display area, wherein the semiconductor layer is formed in the same layer as the semiconductor pattern. 9. The method for manufacturing an electro-optical device according to claim 1. 5. The method of manufacturing an electro-optical device according to claim 1, wherein the semiconductor pattern is formed of polysilicon into which impurity ions have been implanted. 6. The method of manufacturing an electro-optical device according to claim 1, further comprising a step of electrically disconnecting the connection between the wiring and the semiconductor pattern. 7. The method of manufacturing an electro-optical device according to claim 1, wherein a plurality of the display areas are arranged and formed on the substrate. 8. A method of manufacturing an electro-optical device having a display region in which a plurality of transistors each having a semiconductor layer are arranged on a substrate, wherein the semiconductor layer is formed on the substrate, and the semiconductor layer is formed on the display region. Forming a storage capacitor electrode formed of the same layer and a semiconductor pattern formed of the same layer as the semiconductor layer adjacent to the display region; and forming the semiconductor pattern extending from the display region and the display region. Forming a plurality of wires so as to be electrically connected to the storage capacitor electrode and implanting impurity ions into the storage capacitor electrode and the semiconductor pattern. 9. A display region in which a plurality of transistors each having a semiconductor layer are disposed on a substrate, a semiconductor pattern disposed adjacent to the display region, and a display region extending from the display region and the display region. In a method of manufacturing an electro-optical device having a plurality of wirings formed so as to be electrically connected to the semiconductor pattern, a step of forming the semiconductor pattern on the substrate, and an insulating step covering the semiconductor pattern Forming a film; implanting impurity ions into the semiconductor pattern via the insulating film; removing the insulating film at a predetermined location on the semiconductor pattern; Forming a conductive film on the insulating film. 10. A display region in which a plurality of transistors each having a semiconductor layer are disposed on a substrate, a semiconductor pattern disposed adjacent to the display region, and a display region extending from the display region and the display region. In a method of manufacturing an electro-optical device having a plurality of wirings formed so as to be electrically connected to the semiconductor pattern, a step of forming the semiconductor pattern on the substrate; and implanting impurity ions into the semiconductor pattern. Forming an insulating film so as to cover the semiconductor pattern; removing the insulating film at a predetermined location on the semiconductor pattern; and conducting a conductive film on the insulating film including the predetermined location Forming an electro-optical device. 11. The method according to claim 9, wherein the insulating film is made of a silicon oxide film. 12. A semiconductor substrate having a display area on a substrate, wherein: a semiconductor pattern disposed on the substrate so as to be adjacent to the display area; and the semiconductor pattern extending from the display area and the display area. And a plurality of wirings electrically connected to each other. 13. The semiconductor substrate according to claim 12, wherein ends of the plurality of wirings are located on the semiconductor pattern. 14. The semiconductor device according to claim 12, wherein the plurality of wirings include a first wiring and a second wiring that cross each other, and the semiconductor pattern is arranged to surround the display area. Item 14. The semiconductor substrate according to item 13. 15. The semiconductor device according to claim 12, wherein a semiconductor layer electrically connected to a wiring in the display area is arranged, and the semiconductor layer is formed of the same layer as the semiconductor pattern. A semiconductor substrate according to claim 1. 16. The semiconductor substrate according to claim 12, wherein said semiconductor pattern is made of polysilicon implanted with impurity ions. 17. An electro-optical device having the semiconductor substrate according to claim 12. Description: