JP5032160B2 - Display device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a display device and a method for manufacturing the same, and more particularly to a technique for improving yield.

  A liquid crystal display device, which is one of thin panels, is widely used in monitors for personal computers and portable information terminal devices, taking advantage of low power consumption, small size, and light weight. In recent years, liquid crystal display devices have also been used as televisions, and televisions based on liquid crystal display devices are about to replace conventional televisions using cathode ray tubes.

  As a liquid crystal display device, an active matrix display device using a thin film transistor (hereinafter referred to as TFT) as a pixel switching element is known. Active matrix display devices have become the mainstream of liquid crystal display devices because they can achieve higher partition quality than passive matrix display devices that do not have elements in the pixels.

  As the TFT, a MOS (Metal Oxide Semiconductor) structure using a semiconductor film is often used. This MOS structure includes a normal stagger type having a top gate and an inverted stagger type having a bottom gate. As the semiconductor film of the TFT, an amorphous silicon thin film, a polycrystalline silicon thin film, or the like can be used, and is appropriately selected depending on the use and performance of the liquid crystal display device. For example, a TFT used for a small panel often uses a polycrystalline silicon thin film. This is because a TFT using a polycrystalline silicon thin film has high mobility and can be miniaturized when used as a pixel switching element, so that high definition of the panel can be achieved. A TFT using a polycrystalline silicon thin film can also be applied to a peripheral circuit that drives pixel switching.

  In a TFT liquid crystal display device (Thin Film Transistor-Liquid Crystal Display, hereinafter referred to as TFT-LCD), a potential is supplied from a data line to a pixel electrode through a TFT as a switching element. The data lines are formed in one wiring layer and extend to the outside of the display area where the pixels are formed. Here, in the manufacturing process, if the data line is disconnected due to a pattern defect or the like when patterning the data line, the signal voltage is not supplied to the pixels connected to the data line after the disconnected position. As a result, there is a problem in that the yield decreases and the manufacturing cost increases.

In Patent Document 1, a redundant wiring of a data line is formed under the data line, and laser irradiation is applied to both sides of the portion where the data line is disconnected to connect the redundant wiring and the remaining data line without disconnecting. Discloses a technique for repairing a broken portion. A technique for repairing the disconnection portion of the data line in this way is also disclosed in Patent Document 2.
JP-A-10-319438 Japanese Patent Laid-Open No. 11-190858

  However, in the display device disclosed in Patent Document 1, the redundant wiring is formed in the wiring layer in which the gate line is formed, the wiring layout of this wiring layer becomes complicated, and the redundant wiring and the gate wiring are mutually connected. The problem is that it is limited by the layout. The present invention has been made in view of such problems, and an object of the present invention is to provide a display device that improves the yield without limiting the wiring layout of each wiring layer.

A display device according to the present invention includes:
An active silicon layer in which element regions of a plurality of switching elements connected to the pixel electrode and arranged in a matrix are formed;
A base silicon layer comprising the same layer as the active silicon layer;
A data line for supplying a signal voltage to the switching element;
A gate line for supplying a gate voltage to the switching element;
The data line and is formed in a wiring layer different from the gate line, have a redundant wiring and to be substituted for the data lines in the defective portion of the data line,
The redundant wiring is characterized in that it is formed on the base silicon layer .

  According to the display device of the present invention, the yield can be improved without restricting the wiring layout of each wiring layer.

Embodiments according to the present invention will be described below with reference to the accompanying drawings.
[First Embodiment]
A liquid crystal display device will be described as an example of a display device to which the present invention is applied. FIG. 1 is a cross-sectional view showing a liquid crystal display device 10 according to a first embodiment to which the present invention is applied. The liquid crystal display device 10 includes a display panel 11 and a backlight 12. The liquid crystal display panel 11 is configured to display an image based on an input display signal. The backlight 12 is disposed on the non-viewing side of the liquid crystal display panel 11 and is configured to irradiate light to the viewing side via the liquid crystal display panel 11.

  The liquid crystal display panel 11 includes a thin film transistor array substrate (hereinafter referred to as a TFT array substrate) 13, a counter substrate 14, a sealing agent 15, a liquid crystal 16, a spacer 17, an alignment film 18, and a polarizing plate 19. The TFT array substrate 13 and the counter substrate 14 are disposed to face each other. The sealing agent 15 is formed in a frame shape, and bonds the edges of the TFT array substrate 13 and the counter substrate 14 together. The liquid crystal 16 is sealed in a space surrounded by both substrates and a frame-shaped sealing agent 15.

  The spacer 17 is interposed between the TFT array substrate 13 and the counter substrate 14, and is configured to keep the distance between the TFT array substrate 13 and the counter substrate 14 constant. The alignment film 18 is disposed between the liquid crystal 16 and the TFT substrate 13 and between the liquid crystal 16 and the counter substrate 14 and is configured to align the liquid crystal. The polarizing plate 19 is provided on the viewing side of the TFT array substrate 13 and the non-viewing side of the counter substrate 14, and is configured to transmit or absorb a specific polarization component.

  FIG. 2 is a plan view showing the configuration of the TFT array substrate 13. The TFT array substrate 13 has a display area 21 and a peripheral area 22. The display area 21 is formed in a rectangular shape, and the peripheral area 22 is formed in a frame shape so as to surround the display area 21. In the peripheral region 22, the TFT array substrate 13 and the counter substrate 14 are bonded together by the frame-shaped sealing agent 15.

  In the display region 21, gate lines GL, data lines DL, and pixels 23 are formed. A plurality of gate lines GL extend in parallel and are connected to a gate line driving circuit 24 disposed in the peripheral region 22. A plurality of data lines DL are formed so as to intersect with the gate lines DL, and are connected to a data line driving circuit 25 disposed in the peripheral region 22. The pixels 23 are regions surrounded by adjacent gate lines GL and adjacent data lines DL, and are arranged in a matrix.

  The pixel 23 includes a thin film transistor (hereinafter referred to as a TFT element) 26, a pixel electrode 27, and a capacitor 28. The TFT element 26 has a gate connected to the gate line GL, a source connected to the data line DL, and a drain connected to the pixel electrode 27. The pixel electrode 27 is disposed to face a counter electrode (not shown) formed on the counter substrate 14. A common potential is supplied to the counter electrode. Thereby, the electric field applied to the liquid crystal 16 between the pixel electrode 27 and the counter electrode is controlled by the signal voltage supplied to the TFT element 26. The capacitor 28 is connected between the drain of the TFT element 26 and the pixel electrode 27, and is configured to store the charge of the signal input to the pixel electrode 27.

  In FIG. 2, the gate drive line circuit 24 and the data line drive circuit 25 are directly mounted in the peripheral region 22, but the gate line drive circuit 24 and the data line drive circuit 25 are mounted outside the TFT array substrate 13. You may comprise.

  Next, the operation of the liquid crystal display device 10 configured as described above will be described. A gate signal is supplied from the gate line driving circuit 24 to each gate line GL. When a drive voltage is supplied to a certain gate line GL by this gate signal, all the TFT elements 26 connected to the gate line GL are turned on. On the other hand, a signal voltage is supplied from the data line driving circuit 25 to each data line DL. As a result, charges corresponding to the signal voltage are accumulated in the pixel electrode 27. As a result, the arrangement of the liquid crystal 16 between the pixel electrode 27 and the counter electrode changes according to the potential difference between the pixel electrode 27 and the counter electrode (not shown), and the amount of light transmitted through the liquid crystal display panel 11 changes. Thus, when the signal voltage is changed for each pixel 23, a desired image can be displayed.

  Next, a detailed configuration of the TFT array substrate 13 will be described with reference to FIGS. FIG. 3 is a partial plan view showing a detailed configuration of the TFT array substrate 13, and FIG. 4 is a cross-sectional view taken along the line AA ′ of FIG. The TFT array substrate 13 includes an insulating substrate 31, a polysilicon layer Po, a first metal layer M1, a second metal layer M2, a third metal layer M3, a gate insulating film 32, a first interlayer insulating film 33, and a second interlayer insulating. A film 34 and a transparent electrode film 35 are provided.

  As shown in FIG. 4, the TFT array substrate 13 has an insulating substrate 31. The insulating substrate 31 can be constituted by a transparent glass substrate or quartz substrate. A polysilicon layer Po partially doped with impurities is formed on the insulating substrate 31. A region doped with impurities is indicated by a vertical line portion. The polysilicon layer Po has an active polysilicon layer 36 and a base polysilicon layer 37. The active polysilicon layer 36 and the base polysilicon layer 37 are each formed in an island shape. In the active polysilicon layer 36, impurity diffusion regions doped with impurities constitute a source region S and a drain region D of the TFT element 26. Further, a channel region of the TFT element 26 is formed between the source region S and the drain region D. The TFT element 26 may have an LDD (Lightly Doped Drain) structure. The base polysilicon layer 37 is formed in parallel with the data line DL (FIG. 3).

  On the source region S and drain region D of the active polysilicon layer 36, a source side contact metal 39 and a drain side contact metal 40 are formed, respectively. The drain side contact metal 40 and the active polysilicon layer 36 are configured to function as a lower electrode of the capacitor 28. Redundant wiring 41 is formed on the base polysilicon layer 37. As shown in FIG. 3, the redundant wiring 41 is formed below the data line DL in parallel. The source side contact metal 39, the drain side contact metal 40, and the redundant wiring 41 are formed on the same wiring layer. This wiring layer is referred to as a first metal layer M1.

  A gate insulating film 32 is formed on the first metal layer M1 so as to cover the first metal layer M1. A gate electrode layer 42 is formed on the gate insulating film 32 at a position corresponding to the channel region of the active polysilicon layer 36. An upper capacitor electrode layer 43 is formed on the gate insulating film 32 at a position corresponding to the drain side contact metal 40. The upper capacitor electrode layer 43 is configured to function as an upper electrode of the capacitor 28. The gate electrode layer 42 and the upper capacitor electrode layer 43 are formed on the same wiring layer, and this wiring layer is referred to as a second metal layer M2.

  A first interlayer insulating film 33 is formed on the second metal layer M2 so as to cover the second metal layer M2. A source electrode layer 44 is formed on the first interlayer insulating film 33 at a position corresponding to the redundant wiring 41. The source electrode layer 44 extends in the left-right direction in FIG. 3 and constitutes the data line DL. Here, the wiring layer on which the source electrode layer 44 is formed is referred to as a third metal layer M3. A second interlayer insulating film 34 is formed on the third metal layer M3 so as to cover the third metal layer M3.

  On the second interlayer insulating film 34, a source wiring 45 connected to the source electrode layer 44 and the source side metal contact 39 is formed. The source wiring 45 is connected to the source electrode layer 44 through the first source side contact hole 46 and is connected to the source side contact metal 39 through the second source side contact hole 47. A pixel electrode 27 connected to the drain side contact metal 40 is formed on the second interlayer insulating film 34. The pixel electrode 27 is connected to the drain side contact metal 40 through the drain side contact hole 48. The source wiring 45 and the pixel electrode 27 are constituted by the transparent conductive film 35 of the same layer.

  Next, a manufacturing method of the TFT array substrate 13 configured as described above will be described. First, an amorphous silicon film is formed on the insulating substrate 31 to a thickness of 50 nm to 70 nm by plasma CVD (Chemical Vapor Deposition). Note that a silicon nitride film, a silicon oxide film, or a stacked film of a silicon nitride film and a silicon oxide film may be formed as a base film before the amorphous silicon film is formed. Thereafter, excimer laser annealing, YAG laser annealing, or the like is used to melt the amorphous silicon film, and then cooled and solidified to obtain the polysilicon layer Po. Thereafter, the polysilicon layer Po is processed into an island by dry etching to form an active polysilicon layer 36 and a base polysilicon layer 37. The base polysilicon layer 37 is formed so as to exist at a position corresponding to the entire lower surface of the source electrode layer 44 formed in a later step.

  Next, a first metal layer M1 made of Mo, Cr, W, Ti, or the like is formed on the entire surface of the polysilicon layer Po. Thereafter, patterning is performed to form the source side contact metal 39, the drain side contact metal 40, and the redundant wiring 41. In the above description, the photoengraving process is performed using a mask pattern in which the polysilicon layer Po and the first metal layer M1 are different from each other, but the polysilicon layer Po and the first metal are used by using a halftone or gray tone technique. It is also possible to pattern the layer M1 with one mask pattern.

  Next, the gate insulating film 32 is formed on the first metal layer M1 using a plasma CVD method. Thereafter, a second metal layer M2 is formed on the gate insulating film 32 by a sputtering method. As the sputtering method, a sputtering method using a DC (Direct Current) magnetron can be used. Thereafter, the gate electrode layer 42 and the upper capacitor electrode layer 43 are formed by patterning the second metal layer M2. The second metal layer M2 can be composed of Mo, Cr, W, Al, Ta, or a metal film containing these as main components.

  Next, using the gate electrode layer 42 as a mask, an impurity is introduced into the lower active polysilicon layer 36 by ion implantation or ion doping. Here, if phosphorus is used as the impurity to be introduced, the TFT element 26 becomes an n-type transistor, and if boron is used, it becomes a p-type transistor. Further, an n-type channel region and a p-type channel region are formed on the same substrate by masking the other channel region with a resist or the like while introducing one impurity, and the n-type and p-type TFT elements 26 are formed. It is also possible to form. In this case, the gate electrode layer for the n-type transistor gate and the gate electrode layer for the p-type transistor may be separately formed twice at positions corresponding to the n-type channel region and the p-type channel region.

  Next, a first interlayer insulating film 33 is formed on the second metal layer M2 by depositing a silicon oxide film or a silicon nitride film using a plasma CVD method. Thereafter, by performing a heat treatment at 400 ° C. or higher, the impurities introduced into the polysilicon layer Po are thermally diffused. As a result, the source region S and the drain region D are formed in the active polysilicon layer 36.

  Next, a third metal layer M3 is formed on the first interlayer insulating film 33 by a sputtering method. As this sputtering method, a sputtering method using a DC magnetron can be used. The third metal layer M3 can be composed of Al or an alloy film containing Al as a main component. Moreover, it can also be comprised by Mo, Cr, W, Ta, and the alloy film which has these as a main component. Moreover, you may comprise so that these alloy films may be laminated | stacked. Next, the third metal layer M3 is patterned by etching to form the source electrode layer 44. Etching of the third metal layer M3 may be either wet etching or dry etching.

  Next, a silicon nitride film is formed so as to cover the third metal layer M3, and a second interlayer insulating film 34 is formed. Next, the first source-side contact hole 46 is formed by dry etching from the surface of the second interlayer insulating film 34 until it reaches the third metal layer M3. Further, the second source side contact hole 47 and the drain side contact hole 48 are formed from the surface of the second interlayer insulating film 34 to the first metal layer M1.

  Next, a transparent conductive film 35 is formed on the second interlayer insulating film 34. As the transparent conductive film 35, ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) containing indium oxide as a main component can be used. The transparent electrode film 35 is formed so as to cover the contact holes 46 to 48. Thereafter, by patterning the transparent electrode film 35, the source wiring 45 and the pixel electrode 27 are formed. Thereby, the TFT array substrate 13 shown in FIGS. 3 and 4 is obtained.

  In the TFT array substrate 13 manufactured as described above, the source electrode layer 44 formed on the third metal layer M3, that is, the data line DL may be disconnected in the manufacturing process. The disconnection portion of the data line DL is detected by a pattern defect inspection in the manufacturing process, a pattern defect inspection after the TFT array substrate 13 is completed, an electrical inspection, and the like. When the disconnection of the data line DL is detected, a laser is irradiated to the data line DL of the undisconnected part located on both sides of the disconnection part of the data line DL, and the data line DL (source of the undisconnected part) The electrode layer 44) and the redundant wiring 41 are connected. As a result, the data line DL that is not disconnected—the redundant wiring 41 positioned below the disconnected part of the data line DL—the data line DL that is not disconnected is connected, and conduction is ensured to avoid the disconnected part. That is, the data line DL is replaced at the position where the redundant wiring 41 is disconnected.

  Thus, by forming the redundant wiring 41 below the data line DL and replacing the redundant line 41 at the defective portion of the data line DL, it is possible to ensure conduction at the disconnected portion of the data line DL. As a result, the yield of the entire TFT array substrate 13 can be improved and the productivity can be improved. Further, since the redundant wiring 41 is formed in a wiring layer (M1) different from the wiring layer (M2, M3) in which the data line DL and the gate line GL are formed, the wiring layout of each wiring layer by other wirings. Is not constrained.

  Further, since the redundant wiring 41 is also formed at a position that intersects with the gate line GL, even if the data line DL is disconnected near the intersection of the redundant wiring 41 and the gate GL, the redundant wiring 41 and the redundant wiring 41 are redundant. The data line can be repaired by replacing the wiring 41.

  Further, since the first metal layer M1 is formed on the polysilicon layer Po, it is possible to prevent the polysilicon layer Po from penetrating when a contact hole is formed. Further, by disposing the first metal layer M1 on the polysilicon layer Po, the first metal layer M1 functions as a lower electrode of the capacitor 28, so that the voltage dependency of the capacitor 28 can be reduced.

[Second Embodiment]
FIG. 5 is a cross-sectional view showing the configuration of the TFT array substrate 13A according to the second embodiment. Note that the overall configuration of the liquid crystal display device is substantially the same as that of the first embodiment, and thus the description thereof is omitted. As shown in FIG. 3, the base polysilicon 37 is not formed on the TFT array substrate 13 </ b> A according to the second embodiment. Thus, even if the base polysilicon 37 is omitted, the effect of the present invention can be obtained. Since the other configurations are substantially the same as those in the first embodiment, the description thereof is omitted by giving the same reference numerals.
Thus, by removing the base polysilicon layer 37, the position where the redundant wiring 41 is formed is lowered. Thereby, the coverage of the step portion of the gate insulating film 32 formed on the redundant wiring 41 is improved, and the breakdown voltage of the gate insulating film 32 can be improved. Thereby, the reliability of the TFT array substrate 13A can be improved.

[Third embodiment]
FIG. 6 is a plan view showing a configuration of a TFT array substrate 13B according to the third embodiment. Note that the overall configuration of the liquid crystal display device is substantially the same as that of the first embodiment, and thus the description thereof is omitted. In the third embodiment, the base polysilicon layer 37 and the redundant wiring 41 are removed at the intersection of the gate electrode layer 42 extending in the vertical direction of the paper, the base polysilicon layer 37 and the redundant wiring 41 extending in the horizontal direction of the paper. .

  At the position where the gate electrode layer 42 and the redundant wiring 41 intersect, the gate electrode layer 42 and the redundant wiring 41 are opposed to each other with the gate insulating film 32 interposed therebetween, so that the breakdown voltage of the gate insulating film 32 may be lowered. In contrast, in the third embodiment, the base polysilicon layer 37 and the redundant wiring 41 that intersect with the gate electrode layer 42 are removed, so that the gate insulating film at the intersection between the gate electrode layer 42 and the redundant wiring 41 is removed. A withstand voltage of 32 is secured. Thereby, the productivity and reliability of the TFT array substrate 13 can be improved.

  As in the second embodiment, the base polysilicon layer 37 need not be formed not only at the intersection with the gate electrode layer 42 but also over the entire surface.

[Fourth Embodiment]
FIG. 7 is a cross-sectional view showing a configuration of a TFT array substrate 13C according to the fourth embodiment of the present invention. Note that the overall configuration of the liquid crystal display device is substantially the same as that of the first embodiment, and thus the description thereof is omitted. In the fourth embodiment, a spare redundant wiring 50 serving as a spare redundant wiring is also formed below the data line DL in the second metal layer M2. That is, it has a two-layer structure in which redundant wiring is also formed on the first metal layer M1 and the second metal layer M2. Note that the spare redundant wiring 50 formed in the second metal layer M2 is removed at the intersection with the gate electrode layer 42 and the upper capacitor electrode layer 43 formed in the second metal layer M2, and the gate electrode layer 42 and the upper capacitor are removed. It is formed so as not to be short-circuited with the electrode layer 43. As in the second embodiment, the base polysilicon layer 37 can be omitted in the fourth embodiment.
In the TFT array substrate 13C configured as described above, the spare redundant wiring 50 formed in the second metal layer M2 is used as a redundant wiring in a normal state. The redundant wiring 41 formed in (1) is used as a redundant wiring.

Here, when a thin refractory metal film is used for the first metal layer M1, impurities due to ion doping are introduced through the first metal layer M1, and the first metal layer M1 and the polysilicon layer are also introduced. By forming silicide between Po, the contact resistance between the first metal layer M1 which is a refractory metal film and the polysilicon layer Po is further reduced. Further, since the first metal layer M1 is thin and does not generate hillocks, the first metal layer M1 has an advantage that the gate insulating film can be satisfactorily covered.
On the other hand, the first metal layer M1 formed of a thin refractory metal film is not necessarily optimized as a wiring material. When the first metal layer M1 is used as a redundant wiring, the first metal layer M1 is not necessarily optimized. There is a case in which the wiring resistance increases at the repaired portion of the metal layer M1.

  However, even if the above-described advantages and disadvantages are present, in the fourth embodiment, the second metal layer M2 having a wiring resistance smaller than that of the first metal layer M1 is usually used as the redundant wiring. The first metal layer M1 is used as a redundant wiring at a place where it is difficult to repair the second metal layer M2, thereby suppressing the increase in resistance of the redundant wiring to the minimum and arranging the first metal layer M1. The above-mentioned merit obtained by this can also be obtained. Of course, the configuration in which the spare redundant wiring 50 is provided in the second metal layer M2 as in the fourth embodiment can also be applied to the first to third embodiments.

  In the first to fourth embodiments, the present invention is applied to the liquid crystal display device. However, the present invention is not limited to this and can be applied to other various display devices. . In the first to fifth embodiments, a positive stagger type TFT having a top gate structure is taken as an example, but the present invention is not limited to this. In a display device having other various TFTs, a redundant wiring can be formed in a wiring layer different from the gate electrode layer, and the data line DL and the redundant wiring can be connected at the disconnection portion of the data line DL. As a result, even in a TFT having another configuration, the effect of the present invention of improving the yield can be obtained.

1 is a cross-sectional view showing a liquid crystal display device 10 according to a first embodiment of the present invention. 3 is a plan view showing a configuration of a TFT array substrate 13. FIG. 4 is a partial plan view showing a detailed configuration of a TFT array substrate 13. FIG. It is AA 'sectional drawing of FIG. It is sectional drawing which shows the detailed structure of TFT array substrate 13B which concerns on 2nd Embodiment. It is a top view which shows the detailed structure of TFT array substrate 13C which concerns on 3rd Embodiment. It is sectional drawing which shows the detailed structure of TFT array substrate 13D which concerns on 4th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Liquid crystal display device 11 ... Liquid crystal display panel 12 ... Backlight 13 ... TFT array substrate 14 ... Opposite substrate 15 ... Sealing material 16 ... Liquid crystal 17 ... Spacer 18 ... Alignment film 19 ... Polarizing plate 21 ... Display area 22 ... Peripheral area 23 ... Pixel 24 ... Gate line drive circuit 25 ... Data line drive circuit 26 ... TFT element 27 ... Pixel electrode 28 ... Capacitor 31 ... Insulating substrate 32 ... Gate insulating film 33 ... First interlayer insulating film 34 ... Second interlayer insulating film 35 ... Transparent conductive film 36 ... Active polysilicon layer 37 ... Base polysilicon layer 39 ... Source side contact metal 40 ... Drain side contact metal 41 ... Redundant wiring 42 ... Gate electrode layer 43 ... Upper part Capacitor electrode layer 44 ... Source electrode layer 45 ... Source wiring 50 ... Preliminary redundant wiring

Claims (7)

An active silicon layer in which element regions of a plurality of switching elements connected to the pixel electrode and arranged in a matrix are formed;
A base silicon layer comprising the same layer as the active silicon layer;
A data line for supplying a signal voltage to the switching element;
A gate line for supplying a gate voltage to the switching element;
The data line and is formed in a wiring layer different from the gate line, have a redundant wiring and to be substituted for the data lines in the defective portion of the data line,
The display device , wherein the redundant wiring is formed on the base silicon layer . A conductive film connected to the redundant wiring via a first contact hole and connected to the data line via a second contact hole;
The display device according to claim 1 , wherein the redundant wiring is formed to be positioned below the data line. The display device according to claim 1 , wherein the redundant wiring is removed at a portion intersecting with the gate line. The further pre-redundant wiring in the wiring layer of the gate line and the same layer is formed, the preliminary redundant wiring any one of claims 1 to 3, characterized in that it is removed in the portion crossing the gate line 1 The display device according to item. An insulating substrate;
An active silicon layer formed on the insulating substrate and having an element region of a switching element formed thereon;
A base silicon layer comprising the same layer as the active silicon layer;
A redundant wiring formed on the insulating substrate and replaced with the data line at a defective portion of the data line;
A gate insulating film formed to cover the redundant wiring;
A gate line formed on the gate insulating film;
A first interlayer insulating film formed to cover the gate line;
The data line formed on the first interlayer insulating film and positioned on the redundant wiring;
A second interlayer insulating film formed to cover the data line;
The second is formed on the interlayer insulating film, which is connected to the redundant wiring through the first contact hole, have a connection to a conductive layer on the data line through the second contact hole,
The display device , wherein the redundant wiring is formed on the base silicon layer . An active silicon layer and a base silicon layer in which an active region of a switching element is formed on an insulating substrate are formed in the same layer ,
Forming a redundant wiring to be replaced with the data line at a defective portion of the data line on the base silicon layer ;
Forming a gate insulating film on the redundant wiring;
Forming a gate electrode layer on the first interlayer insulating film;
Forming a first interlayer insulating film on the gate electrode layer;
Forming the data line on the first interlayer insulating film;
Forming a second interlayer insulating layer on the data line;
Forming a first contact hole reaching the redundant wiring from the surface of the second interlayer insulating film and a second contact hole reaching the data line from the surface of the second interlayer insulating film;
A method for manufacturing a display device, comprising: forming a conductive film so as to cover the first contact hole and the second contact hole. The method for manufacturing a display device according to claim 6, wherein the redundant wiring and the data line are connected so as to sandwich a defective portion of the data line.

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