JP2008305860A - Thin-film transistor, display unit, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor whose peripheral circuits can be integrated by reducing the layout area of contact holes, a display unit on which this thin-film transistor is mounted, and to provide a manufacturing method therefor. <P>SOLUTION: This thin-film transistor comprises a gate electrode 7, a semiconductor layer, having a source region 4a and a drain region 4c which sandwich a channel region 4b, electrically conductive thin films 5, formed in contact with the source region and the drain region in the channel width direction, respectively, and electrodes on the electrically conductive thin films, connected to the source and drain regions via contact holes opposed to the gate electrode in the channel length direction, respectively. The dimension of the electrically conductive thin film in the channel length direction, in at least a part thereof in the non-neighborhood of the contact hole formation region is made smaller than that in the neighborhood of the contact hole formation region. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a thin film transistor, a display device, and a manufacturing method thereof.

  A plurality of signal lines and a plurality of scanning lines are arranged in a lattice pattern, and a thin film transistor (TFT) (for example, Patent Document 1) is formed as a switching element in a pixel region surrounded by the signal lines and the scanning lines. An active matrix display device has been developed. This active matrix display device has better image quality than a passive matrix display device, and occupies the mainstream of organic EL display devices and liquid crystal display devices. LTPS-TFT using low temperature poly silicon (LTPS) as a channel active layer of TFT has high electron mobility. By utilizing this LTPS-TFT, the performance of active matrix display devices has been greatly improved.

  For example, LTPS-TFT is applied to a peripheral circuit section for driving a switching element. By using the LTPS-TFT for forming a circuit around the display device, the use of an IC and an IC mounting substrate can be reduced. Thereby, the structure of a display apparatus can be simplified and the highly reliable display apparatus with a narrow frame is implement | achieved.

  In the liquid crystal display device, when an LTPS-TFT is used as a switching element for each pixel, not only can the capacitance be reduced, but also the area of the storage capacitor connected to the drain side can be reduced. Therefore, a liquid crystal display device (LCD) having a high resolution and a high aperture ratio can be realized. Accordingly, the LTPS-TFT is a leading panel for realizing a high-resolution liquid crystal display device of QVGA (pixel number: 240 × 320) or VGA (pixel number: 480 × 640) with a small panel for cellular phones. Playing a role.

  A configuration of an LTPS-TFT according to a conventional example will be described with reference to FIGS. FIG. 14 is a partial top view showing the structure of an LTPS-TFT according to a conventional example. 15 is a cross-sectional view taken along the line XVI-XVI ′ in FIG. 14, showing a cross-sectional structure cut along the channel length direction (X direction in FIG. 14) in which the source region and the drain region are formed. . In FIG. 14, for convenience of explanation, the positions of the source electrode 90 and the drain electrode 91 are illustrated in order to clarify the position where the contact hole is formed.

  As shown in FIGS. 14 and 15, the TFT 80 according to the conventional example has a base film 82 formed on a substrate 81 made of a transparent insulating substrate such as glass. A polycrystalline semiconductor layer (hereinafter also referred to as “semiconductor layer”) 84 made of polysilicon is formed in an island shape on the base film 82. The semiconductor layer 84 includes a source region 84a and a drain region 84c, and a channel region 84b disposed between these regions. A gate insulating film 86 is formed so as to cover the semiconductor layer 84, and a gate electrode 87 is formed on the opposite side of the channel region 84b with the gate insulating film 86 interposed therebetween.

  An interlayer insulating film 88 is formed on the gate electrode 87 so as to cover the gate electrode 87 and the gate insulating film 86. A contact hole 89 that penetrates the interlayer insulating film 88 and the gate insulating film 86 is provided on the source region 84 a and the drain region 84 c of the semiconductor layer 84. The source electrode 90 and the drain electrode 91 are electrically connected to the source region 84 a and the drain region 84 c of the semiconductor layer 84 through these contact holes 89. In FIG. 15, four contact holes are formed in each of the source region 84a and the drain region 84c.

When a voltage is applied to the gate electrode 87 of the TFT 80 according to the conventional example, a charge layer (inversion layer) is formed near the boundary with the gate insulating film 86 in the channel region 84 b of the semiconductor layer 84. At this time, when a potential difference is applied between the source region 84a and the drain region 84c of the semiconductor layer 84, a current flows between the source region 84a and the drain region 84c through the inversion layer. In the case of an n-type TFT, the current actually flows as electrons formed in the inversion layer move in the direction opposite to the current flow.
Patent Document 2 will be described later.
JP-A-7-147411 JP, 2002-50767, A FIG. 2, FIG.

  In such a display device, a narrower frame by integrating peripheral circuits, a higher aperture ratio of a display area, and higher resolution have been increasingly required in recent years. For this reason, it is desired to reduce the layout area of the thin film transistor. Under such circumstances, the area occupied by the contact hole in the layout area of the thin film transistor cannot be ignored. In particular, in the type having a wide channel width, it is necessary to provide a large number of contact holes, which is a more serious problem.

  The present invention has been made in view of the above circumstances, and provides a thin film transistor capable of integrating peripheral circuits by reducing a contact hole layout area, a display device including the thin film transistor, and a method for manufacturing the same. The purpose is to do.

  The thin film transistor according to the present invention includes a gate electrode, a channel region formed under the gate electrode, a semiconductor layer having a source region and a drain region sandwiching the channel region, and a channel width with respect to the source region and the drain region. A conductive thin film formed so as to be in contact with each other in a direction, and a source connected to the source region via a contact hole formed on the conductive thin film so as to face the gate electrode in a channel length direction. An electrode, and a drain electrode connected to the drain region, wherein the dimension of the conductive thin film in the channel length direction is smaller than at least a portion near the contact hole formation region with respect to the vicinity of the contact hole formation region Is.

  The thin film transistor according to the present invention has an excellent effect that the layout area of the contact hole can be reduced and the peripheral circuit can be integrated.

  Hereinafter, an example of an embodiment to which the present invention is applied will be described. It goes without saying that other embodiments may also belong to the category of the present invention as long as they match the gist of the present invention.

[Embodiment 1]
The display device according to the first embodiment is an active matrix display device having a thin film transistor as a switching element. Here, a transmissive active matrix liquid crystal display device will be described as an example of the display device. FIG. 1 is a cross-sectional view illustrating the configuration of the liquid crystal display device 100 according to the first embodiment, and FIG. 2 is a plan view illustrating the configuration of the liquid crystal display device 100. For convenience of explanation, the counter substrate and the like are not shown in FIG.

  As shown in FIG. 1, the liquid crystal display device 100 includes a liquid crystal display panel 101 and a backlight 102. The liquid crystal display panel 101 is configured to display an image based on an input display signal. The backlight 102 is disposed on the non-viewing side of the liquid crystal display panel 101 and is configured to irradiate light to the viewing side via the liquid crystal display panel 101.

  1 and 2, the liquid crystal display panel 101 includes a thin film transistor array substrate (hereinafter referred to as “TFT array substrate”) 103, a counter substrate 104, a sealing material 105, a liquid crystal 106, a spacer 107, gate lines (scanning lines). ) 108, a source line (signal line) 109, an alignment film 110, a counter electrode 111, a polarizing plate 112, a gate driver IC 113, a source driver IC 114, and the like.

  As shown in FIG. 2, the TFT array substrate 103 has a display area 115 and a peripheral area 116. The display area 115 is formed in a rectangular shape, and the peripheral area 116 is formed in a frame shape so as to surround the display area 115. In this peripheral region 116, the TFT array substrate 103 and the counter substrate are bonded together by a frame-shaped sealing material 105.

  A plurality of gate lines 108 and a plurality of source lines 109 are formed in the display region 115. The plurality of gate lines 108 are provided in parallel to each other. A plurality of source lines 109 are provided in parallel to each other in the direction perpendicular to the gate lines 108. The gate line 108 and the source line 109 are formed so as to cross each other.

  A thin film transistor (TFT) 118 is provided near the intersection of the gate line 108 and the source line 109. A pixel electrode (not shown) is formed in a region surrounded by the adjacent gate line 108 and source line 109. Accordingly, a region surrounded by the adjacent gate line 108 and source line 109 is a pixel 117. Accordingly, the pixels 117 are arranged in a matrix on the TFT array substrate 103.

  The gate of the TFT 118 is connected to the gate line 108, the source is connected to the source line 109, and the drain is connected to the pixel electrode. The pixel electrode is formed of a transparent conductive thin film such as ITO (Indium Tin Oxide). A region where the plurality of pixels 117 are formed is a display region 115.

  In the liquid crystal display panel 101, as shown in FIG. 1, a liquid crystal 106 is sealed in a space between a TFT array substrate 103 and a counter substrate 104 that are arranged to face each other and a sealing material 105 that bonds the two substrates. . A distance between the two substrates is maintained by a spacer 107 so as to have a predetermined interval. As the TFT array substrate 103 and the counter substrate 104, for example, an insulating substrate such as light transmissive glass, polycarbonate, or acrylic resin is used.

  In the TFT array substrate 103, an alignment film 110 is formed on each of the electrodes and wirings described above. On the other hand, a color filter (not shown), a BM (Black Matrix) (not shown), a counter electrode 111, an alignment film 110, and the like are formed on the surface of the counter substrate 104 facing the TFT array substrate 103. The counter electrode 111 may be disposed on the TFT array substrate 103 side. Further, polarizing plates 112 are attached to the outer surfaces of the TFT array substrate 103 and the counter substrate 104, respectively.

  As shown in FIG. 2, a gate driver IC 113 and a source driver IC 114 are provided in the peripheral region 116 of the TFT array substrate 103. The gate line 108 extends from the display area 115 to the peripheral area 116. The gate line 108 is connected to the gate driver IC 113 at the end of the TFT array substrate 103. Similarly, the source line 109 extends from the display area 115 to the peripheral area 116. The source line 109 is connected to the source driver IC 114 at the end of the TFT array substrate 103. A first external wiring 119 is connected in the vicinity of the gate driver IC 113. A second external wiring 120 is connected in the vicinity of the source driver IC 114. The first external wiring 119 and the second external wiring 120 are wiring boards such as an FPC (Flexible Printed Circuit), for example.

  Various signals from the outside are supplied to the gate driver IC 113 via the first external wiring 119 and to the source driver IC 114 via the second external wiring 120. The gate driver IC 113 supplies a gate signal (scanning signal) to the gate line 108 based on a control signal from the outside. By this gate signal, the gate lines 108 are sequentially selected. The source driver IC 114 supplies a display signal to the source line 109 based on an external control signal and display data. Thereby, the display voltage according to display data can be supplied to each pixel electrode.

  Here, the gate driver IC 113 and the source driver IC 114 are directly mounted on the TFT array substrate 103 by using a COG (Chip On Glass) technique, but the configuration is not limited to this. For example, the driver IC may be connected to the TFT array substrate 103 by TCP (Tape Carrier Package).

  As shown in FIG. 1, a backlight 102 is provided on the back of the liquid crystal display panel 101. The backlight 102 irradiates the liquid crystal display panel 101 with light from the non-viewing side of the liquid crystal display panel 101. As the backlight 102, for example, a backlight having a general configuration including a light source, a light guide plate, a reflection sheet, a diffusion sheet, a prism sheet, a reflection polarizing sheet, and the like can be used.

  Next, a driving method of the liquid crystal display device 100 configured as described above will be described. As described above, a scanning signal is supplied to each gate line 108 from the gate driver IC 113. Each scanning signal turns on all TFTs 118 connected to one gate line 108 simultaneously. Then, a display signal is supplied from the source driver IC 114 to each source line 109, and charges corresponding to the display signal are accumulated in the pixel electrodes. The arrangement of liquid crystals between the pixel electrode and the counter electrode 111 changes in accordance with the potential difference between the pixel electrode to which the display signal is written and the counter electrode 111. As a result, the amount of light transmitted through the liquid crystal display panel 101 changes. Thus, a desired image can be displayed by changing the display voltage for each pixel 117.

  Next, the detailed configuration of the TFT array substrate 103 will be described in detail. FIG. 3 is a top view showing a configuration in the vicinity of the TFT 118 formed on the TFT array substrate 103. 4 is a cross-sectional view taken along the line IV-IV ′ of FIG. 3, and shows a cross-sectional structure cut along the channel length direction (X direction in FIG. 3) in which the source region and the drain region are formed. ing. As the channel active layer of the TFT 118, low temperature poly silicon (LTPS) which is crystalline silicon is used.

As shown in FIGS. 3 and 4, the TFT array substrate 103 includes an insulating substrate 1, a base film 2, a polycrystalline semiconductor layer 4, a conductive thin film 5, a gate insulating film 6, a gate electrode 7, and a first interlayer insulating layer 8. Contact hole 9, source electrode 10, drain electrode 11 and the like.
For convenience of explanation, in FIG. 3, the gate insulating film 6, the first interlayer insulating layer 8, the source electrode 10, and the drain electrode 11 are illustrated so that the shape of the polycrystalline semiconductor layer 4 can be easily observed. Omitted and only the formation position of the contact hole 9 is shown. Also, the taper portion of the polycrystalline semiconductor layer 4 is not shown. The arrows in the polycrystalline semiconductor layer 4 in FIG. 3 indicate the direction of current. In the display device according to the first embodiment, the TFT 118 is disposed in the pixel 117 in the display region 115.

The insulating substrate 1 can be composed of a transmissive substrate such as a glass substrate or a quartz substrate. A base film 2 is formed on the insulating substrate 1. As the base film 2, for example, a SiN film or a SiO ₂ film which is a transmissive insulating film can be used. On the base film 2, an island-shaped polycrystalline semiconductor layer 4 is formed.

  As shown in FIG. 4, the polycrystalline semiconductor layer 4 includes a source region 4a, a drain region 4c, and a channel region 4b sandwiched therebetween. The source region 4a and the drain region 4c are conductive regions containing impurities. The polycrystalline semiconductor layer 4 has a tapered end. Therefore, the gate insulating film 6 formed on the polycrystalline semiconductor layer 4 is satisfactorily covered. Therefore, defects such as dielectric breakdown can be sufficiently suppressed, which contributes to improvement of the reliability of the TFT 118.

  Conductive thin films 5 are stacked in the channel width direction (Y direction in FIG. 3) on the source region 4a and drain region 4c, respectively. For example, the conductive thin film 5 is made of Mo and can have a thickness of 20 nm, a width of 2 μm, and the like. The conductive thin film 5 has only to be stacked over the channel width direction (Y direction in FIG. 3) of the source region 4a and drain region 4c, and the stacked region in the channel length direction (X direction in FIG. 3) is arbitrary. . Like this Embodiment 1, you may arrange | position only to the edge part side of the polycrystalline semiconductor layer 4, and may arrange | position to the whole area | region. However, it is preferable to keep the facing distance to the channel layer constant from the viewpoint of applying a uniform voltage.

  As shown in FIG. 3, the conductive thin film 5 has a dimension D2 in the channel length direction of the first contact hole 9 formation region non-near vicinity A2 from a dimension D1 in the channel length direction of the first contact hole 9 formation region vicinity A1. Is also configured to be smaller.

  A gate insulating film 6 which is an insulating layer is formed on the polycrystalline semiconductor layer 4 and the conductive thin film 5 so as to be in contact with and cover them. A gate electrode 7 is formed on the gate insulating film 6 at a position facing the channel region 4b. A first interlayer insulating film 8 is formed so as to cover the gate insulating film 6 and the gate electrode 7. In the first interlayer insulating film 8 and the gate insulating film 6, a first contact hole 9 penetrating from the surface of the first interlayer insulating film 8 to the conductive thin film 5 is disposed at a position facing the gate electrode 7. A first electrode is disposed in the first contact hole 9. Of the first electrodes, those that are electrically connected to the source region 4 a via the conductive thin film 5 function as the source electrode 10, and those that are electrically connected to the drain region 4 c function as the drain electrode 11. In the first embodiment, one contact hole is formed on each of the source region 4a side and the drain region 4c side.

  In the TFT according to the conventional example, as shown in FIG. 15, the conductive thin film was not formed on the source region 84a and the drain 84c region. That is, the source region and the drain region are formed only of the conductive region containing impurities in the polycrystalline semiconductor layer. Therefore, the sheet resistance becomes as high as several kΩ, so that it is difficult to apply a uniform voltage, and a voltage drop tends to occur in the channel width direction. That is, in order to flow current substantially uniformly in the channel width direction, it is necessary to uniformly arrange contact holes in the source / drain regions as shown in FIG. For this reason, a large number of contact holes have to be formed for those having a wide channel width.

  In the TFT array substrate 103 according to the first embodiment, the conductive thin film 5 having a low resistance is stacked over the channel width direction of the source region 4a and the drain region 4c. Since the conductive thin film is made of a low-resistance material of about 5 to 50Ω / □, the voltage supplied to the source region 4a and the drain region 4c through the first contact hole 9 is almost equal to the channel width direction. It becomes possible to make it uniform. Therefore, even in a TFT having a wide channel width, it is possible to reduce the number of first contact holes 9 while maintaining the performance of the TFT without uniformly arranging the first contact holes 9 in the channel width direction.

  For this reason, the area occupied by the layout region of the first contact hole can be reduced. Specifically, as shown in FIG. 3, in the source region 4a, the dimension D4 in the channel length direction of the first contact hole 9 formation region non-near vicinity A2 is defined as the channel length of the first contact hole 9 formation region vicinity A1. It can be made smaller than the dimension D3 in the direction. The same applies to the drain region 4c. In the case of the conductive thin film 5, the dimension D2 in the channel length direction of the vicinity A2 of the first contact hole 9 is smaller than the dimension D1 of the vicinity of the formation area A1 of the first contact hole 9 in the channel length direction. can do. As a result, integration of peripheral circuits can be achieved, which can contribute to narrowing the frame, increasing the aperture ratio of the display area, and increasing the resolution.

  In Patent Document 2, in the MOSFET semiconductor device, an arrangement area is set so that the contact hole is formed away from the gate electrode, specifically, the gate electrode and the contact hole are not opposed in the channel length direction. A defining example is disclosed. An example in which a silicide layer is formed in the source region and the drain region is disclosed. However, since the arrangement area of the contact hole is defined, it cannot be said that the degree of freedom in design is high. Further, it cannot be said that the position of forming the silicide layer is limited to the upper layer of the semiconductor layer, and the degree of design freedom is high.

Next, a manufacturing method of the TFT 118 configured as described above will be described. 5 and 6 are manufacturing process diagrams for explaining a manufacturing method of the TFT 118. First, as shown in FIG. 5A, a base film 2 is formed on an insulating substrate 1. In the first embodiment, the SiN film 2a is formed on the insulating substrate 1 by the CVD (CVD: Chemical Vapor Deposition) method, and the SiO ₂ film 2b is formed thereon. The film thickness of the SiN film 2a can be, for example, 40 to 60 nm, and the film thickness of the SiO ₂ film 2b can be, for example, 180 to 220 nm. The underlying film 2 is provided mainly for the purpose of preventing mobile ions such as Na from the glass substrate from diffusing into the semiconductor layer, and is not limited to the above-described film configuration and film thickness. .

  Next, an amorphous semiconductor film 3 is formed on the base film 2 by a CVD method. In the first embodiment, a silicon (Si) film is used as the amorphous semiconductor film 3. The silicon film is preferably formed to a thickness of 30 to 100 nm, more preferably 60 to 80 nm (see FIG. 5a). The base film 2 and the amorphous semiconductor film 3 are preferably formed continuously in the same apparatus or the same chamber. Thereby, it is possible to prevent contaminants such as boron (B) existing in the air atmosphere from being taken into the interface of each film.

  Note that it is preferable to perform annealing at a high temperature after the amorphous semiconductor film 3 is formed. This is to reduce hydrogen contained in a large amount in the amorphous semiconductor film 3 formed by the CVD method. In Embodiment 1, the inside of the chamber held in a low vacuum state in a nitrogen atmosphere was heated to about 480 ° C., and the substrate on which the amorphous semiconductor film 3 was formed was held for 45 minutes. By such treatment, when the amorphous semiconductor film 3 is crystallized, hydrogen is not rapidly desorbed even if the temperature rises. Then, it becomes possible to suppress the roughness of the surface of the amorphous semiconductor film 3. By the above process, the configuration shown in FIG.

  Subsequently, the natural oxide film formed on the surface of the amorphous semiconductor film 3 is removed by etching with hydrofluoric acid or the like. Thereafter, a laser beam 12 is irradiated from above the amorphous semiconductor film 3 while blowing a gas such as nitrogen to the amorphous semiconductor film 3 as shown in FIG. The laser beam 12 is irradiated to the amorphous semiconductor film 3 after being converted into a linear beam shape through a predetermined optical system. In the first embodiment, the second harmonic (oscillation wavelength: 532 nm) of a YAG laser is used as the laser beam 12. An excimer laser can be used instead of the second harmonic of the YAG laser. The laser light irradiation is performed while blowing nitrogen to the amorphous semiconductor film 3. Thereby, the protruding height generated at the crystal grain boundary portion can be suppressed. In the first embodiment, the average roughness Ra of the crystal surface is reduced to 3 nm or less. The polycrystalline semiconductor layer 4 is formed by irradiating the amorphous semiconductor film 3 with laser light.

A resist that is a photosensitive resin is applied onto the polycrystalline semiconductor layer 4 by spin coating. The applied resist is subjected to a known photolithography method such as exposure and development. Thereby, the photoresist is patterned into a desired shape. Thereafter, the polycrystalline semiconductor layer 4 is etched to remove the photoresist pattern. Thereby, the polycrystalline semiconductor layer 4 is patterned into a desired shape. In the first embodiment, the polycrystalline semiconductor layer 4 is formed in an island shape by a dry etching method using a gas in which CF ₄ and O ₂ are mixed. Since O ₂ is mixed in the gas used for the etching, the resist formed by the photoengraving method can be etched while being retracted. Therefore, the polycrystalline semiconductor layer 4 can have a structure having a tapered shape at the end. By the above process, the configuration shown in FIG.

Next, a conductive thin film is formed. As the conductive thin film, Cr, Mo, W, Ti, Ta, or an alloy film containing these as main components can be used. In the first embodiment, the Mo film has a thickness of about 20 nm and is formed by a sputtering method using a DC magnetron. Here, although the film thickness of the conductive thin film is 20 nm, it may be 25 nm or less. When the film thickness of the conductive thin film exceeds 25 nm, it functions as a mask in impurity ion doping performed in the subsequent process. That is, the impurity ions cannot sufficiently reach the polycrystalline semiconductor layer 4 positioned below the conductive thin film, and ohmic contact between the conductive thin film 5 and the polycrystalline semiconductor layer 4 cannot be obtained. On the other hand, the lower limit of the thickness of the conductive thin film is not particularly limited. The sheet resistance of the conductive thin film is about two orders of magnitude lower than the sheet resistance (several kΩ / □) of the polycrystalline semiconductor film. Therefore, if a thin conductive film is formed, a desired voltage is applied to the source region and the drain region. It can be applied reliably. However, when Mo, W, Ti, or the like is used as the conductive thin film, the conductive thin film is not a little due to dry etching gas (for example, CF ₄ / O ₂ or CHF ₃ / O ₂ / Ar gas) used when forming the contact hole. It will be etched. If the conductive thin film at the bottom of the contact hole is removed, a desired voltage cannot be reliably applied to the source region and the drain region. For this reason, the film thickness of the conductive thin film needs to be a film thickness that allows for the amount of shaving due to the over-etching. From this viewpoint, it is preferable that the thickness of the conductive thin film 5 be 10 nm or more in consideration of etching selectivity.

  Subsequently, a resist, which is a photosensitive resin, is applied onto the conductive thin film 5 by spin coating or the like, and the applied resist is patterned into a desired shape by a series of photolithography methods such as exposure and development. Subsequently, the conductive thin film 5 is etched to remove the photoresist pattern. Through a series of steps, the conductive thin film 5 is patterned into a desired shape. In the first embodiment, the conductive thin film 5 is processed to have the configuration shown in FIG. 3 by wet etching using a chemical solution in which phosphoric acid and nitric acid are mixed.

  The polycrystalline semiconductor layer 4 and the conductive thin film 5 can also be formed by a single photolithography process using a known halftone mask. That is, the photoresist in the desired polycrystalline semiconductor layer shape portion is half-exposed to form a thin film thickness, and the desired conductive thin film shape portion in the photoresist film thickness is formed thick. Using such a resist pattern, first, the conductive thin film 5 and the polycrystalline semiconductor layer 4 are patterned. Then, by ashing, the portion of the resist where the thickness of the photoresist film is previously thinned is removed, leaving only the photoresist pattern of the desired conductive thin film shape portion. The conductive thin film 5 may be patterned again using the remaining photoresist pattern.

Next, a gate insulating film 6 is formed so as to cover the entire substrate surface on the polycrystalline semiconductor layer 4 and the conductive thin film 5. As the gate insulating film 6, a SiN film, a SiO ₂ film or the like is used. In the first embodiment, a SiO ₂ film is used as the gate insulating film 6 and is formed to a thickness of 50 to 100 nm by a CVD method. Moreover, the surface average roughness of the polycrystalline semiconductor layer 4 was set to Ra <= 3nm, and the edge part of the polycrystalline semiconductor layer 4 pattern was made into the taper shape. Therefore, the coverage of the gate insulating film 6 is high, and initial failures can be greatly reduced. With the above process, the configuration shown in FIG.

Next, a layer for forming the gate electrode 7 and the wiring is formed. This layer can be composed of Mo, Cr, W, Ta or an alloy film containing these as main components. In this embodiment, Mo was formed to a thickness of 200 to 400 nm by a sputtering method using a DC magnetron. Then, using a known photoengraving method, patterning is performed into a desired shape to form the gate electrode 7 and wiring (not shown). In the first embodiment, the gate electrode 7 is etched by a wet etching method using a chemical solution in which phosphoric acid and nitric acid are mixed. Instead of this, it is also possible to carry out by a dry etching method using a gas in which SF ₆ and O ₂ are mixed.

  Next, an impurity element is introduced into the source / drain regions of the polycrystalline semiconductor layer 4 using the formed gate electrode 7 as a mask. P or B can be used as the impurity element introduced here. If P is introduced, an n-type TFT 118 can be formed, and if B is introduced, a p-type TFT 118 can be formed. Further, if the processing of the gate electrode 7 is performed twice for the n-type TFT gate electrode and the p-type TFT gate electrode, the n-type and p-type TFT 118 can be separately formed on the same substrate. The introduction of impurity elements such as P and B was performed using an ion doping method. Through the above steps, the gate electrode 7, the source region 4a, and the drain region 4c are formed, and the structure shown in FIG. 6C is obtained.

Next, a first interlayer insulating film 8 is formed so as to cover the entire substrate surface above the gate electrode 7. In the first embodiment, the first interlayer insulating film 8 is formed by the CVD method with the SiO ₂ film having a thickness of 500 to 1000 nm. And it hold | maintained for about 1 hour in the annealing furnace heated at 450 degreeC in nitrogen atmosphere. Thereby, the impurity element introduced into the source / drain regions of the polycrystalline semiconductor layer 4 is further activated. By the above process, the configuration shown in FIG.

Next, the formed gate insulating film 6 and first interlayer insulating film 8 are patterned into a desired shape using a known photolithography method. Here, contact holes 9 reaching the conductive thin film 5 formed above the source region 4a and the drain region 4c of the polycrystalline semiconductor layer 4 are formed. That is, in the contact hole 9, the gate insulating film 6 and the first interlayer insulating film 8 are removed, and the conductive thin film 5 is exposed. In the first embodiment, the contact hole 9 is etched by a dry etching method using a mixed gas of CHF ₃ , O ₂ and Ar. By the above process, the configuration shown in FIG.

  Next, a first electrode layer for forming the source electrode 10, the drain electrode 11, and the wiring (not shown) is formed. The first electrode layer may be Mo, Cr, W, Al, Ta, or an alloy film containing these as a main component. Moreover, it is good also as a multilayer structure which laminated | stacked these. In this embodiment, a Mo / Al / Mo laminated structure is used, and the film thickness is 200 to 400 nm for the Al film, and 50 to 150 nm for the Al lower layer and the upper Mo film. These were formed by a sputtering method using a DC magnetron.

Next, the formed first electrode layer is patterned into a desired shape using a known photoengraving method to form a source electrode 10, a drain electrode 11, and a wiring (not shown). In the first embodiment, as a means for forming these, a dry etching method using a mixed gas of SF ₆ and O _{2 and} a mixed gas of Cl ₂ and Ar is used. Through the above steps, the source electrode 10 connected to the conductive thin film 5 is formed on the source region 4a, and the drain electrode 11 connected to the conductive thin film 5 is formed on the drain region 4c. As a result, the configuration shown in FIG.

Through these series of steps, the TFT 118 can be manufactured. Subsequently, a second interlayer insulating film 15 is formed so as to cover the source electrode and the drain electrode, and after performing patterning by a series of photolithography processes, an etching process is performed (see FIG. 7). In the first embodiment, the SiN film is formed by the CVD method so that the film thickness becomes 200 to 300 nm. A second contact hole 16 reaching the drain electrode 11 is formed from the surface of the second interlayer insulating film 15. That is, in the second contact hole 16, the second interlayer insulating film 15 is removed and the drain electrode 11 is exposed. The second contact hole 15 was etched by a dry etching method using a mixed gas of CF ₄ and O ₂ .

Next, a second electrode layer for forming a pixel electrode or the like is formed. As the second electrode layer 17, a conductive thin film having transparency such as ITO or IZO is used. In the first embodiment, ITO was formed by a sputtering method using a DC magnetron so as to have a film thickness of 80 to 120 nm. For sputtering, a mixture of Ar gas, O ₂ gas, and H ₂ O gas was used. Thereby, an amorphous transparent conductive thin film that is easy to process is obtained.

  Thereafter, the formed second electrode layer was patterned into a desired shape using a known photoengraving method to form a pixel electrode 17. The etching process was performed by a wet etching method using a chemical solution mainly composed of oxalic acid. Then, annealing for crystallizing the amorphous transparent conductive thin film is performed.

  When the TFT array substrate manufactured here is used for a liquid crystal display device, ITO is generally used for the transparent conductive thin film on the second interlayer insulating film 15 for each pixel. The pixel electrode 17 is connected to the drain electrode 11 through a contact hole. The TFT array substrate is formed by the above process.

According to the first embodiment, the conductive thin film 5 is formed on the polycrystalline semiconductor layer 4 that forms the source region and the drain region of the TFT. By stacking the low-resistance conductive thin film 5 on the polycrystalline semiconductor layer 4 to be the source region 4a and the drain region 4c in this way, it is possible to reliably apply a desired voltage to the source region and the drain region. . There is no need to arrange the contact holes evenly in the channel width direction, and the number of contact holes can be reduced. Therefore, the area for arranging the contact holes can be reduced.
Furthermore, since the end portion of the polycrystalline semiconductor layer is tapered, the gate insulating film formed on the polycrystalline semiconductor layer is satisfactorily covered, and defects such as dielectric breakdown can be sufficiently suppressed. In addition, the polycrystalline semiconductor layer 4 according to the first embodiment has a very thin film thickness of 30 to 100 nm and a small gate insulating film / polycrystalline semiconductor layer selection ratio. Therefore, when the gate insulating film is removed, It was difficult to leave the crystalline semiconductor layer stably. According to this embodiment, since the conductive thin film 5 is laminated, this problem can be improved.

[Embodiment 2]
Next, an example of a TFT different from the above embodiment will be described. In the following description, the same elements as those in the above embodiment are denoted by the same reference numerals, and the description thereof is omitted as appropriate.

  FIG. 8 is a top view showing a configuration in the vicinity of the TFT 218 formed on the TFT array substrate according to the second embodiment. 9A is a cross-sectional view taken along the line IXa-IXa ′ of FIG. 8, and FIG. 9B is a cross-sectional view taken along the line IXb-IXb ′ of FIG. 9 shows a cross-sectional structure cut along the formed channel length direction (X direction in FIG. 8).

  The TFT 218 according to the second embodiment has the same configuration as the TFT according to the first embodiment except for the following points. That is, in the first embodiment, in the source region and the drain region, the dimension in the channel length direction of the contact hole formation region non-near vicinity A2 is made smaller than the dimension in the channel length direction in the vicinity of the contact hole formation region A1. However, in the second embodiment, the dimensions of the source region 24a and the drain region 24c in the channel length direction are constant over the entire channel width direction. Specifically, in each of the source region 24a and the drain region 24c, both the dimension in the channel length direction in the vicinity of the contact hole 9 formation region A1 and the dimension in the channel length direction in the vicinity of the contact hole 9 formation region A2 have a width of D6. It was configured to be the same.

  In the first embodiment, the conductive thin film 5 is formed on the polycrystalline semiconductor layer 4, whereas in the second embodiment, as shown in FIG. 9A, the polycrystalline semiconductor layer is formed. 4 in that it is formed not only on the upper layer of 4 but also on the side wall portion thereof and on the insulating substrate 1 in a region extending in the vicinity of the polycrystalline semiconductor layer 4. More specifically, the conductive thin film 5 is formed only in the upper layer of the polycrystalline semiconductor layer 4 in the contact hole 9 formation region non-near vicinity A2. On the other hand, in the vicinity A1 of the contact hole 9 formation region, the conductive thin film 5 is formed over the side wall portion of the semiconductor layer and the vicinity of the semiconductor layer as described above (region indicated by D5 in FIG. 8).

  Further, the second embodiment is different in that the contact hole 9 is formed in the non-stacked region D5 where the polycrystalline semiconductor layer 4 and the conductive thin film 5 are not stacked. Another difference is that the end of the polycrystalline semiconductor layer 4 is not tapered.

  According to the second embodiment, the conductive thin film 25 is formed from the upper layer to the vicinity of the periphery of the polycrystalline semiconductor layer forming the source region and the drain region of the TFT. By bringing the low-resistance conductive thin film 25 into contact with the polycrystalline semiconductor layer 24 serving as the source region 24a and the drain region 24c, a desired voltage can be reliably applied to the source region and the drain region. It is not necessary to arrange the contact holes uniformly in the channel width direction, and the number of contact holes can be reduced, so that the area for arranging the contact holes can be reduced. Further, by forming the contact hole 9 in the non-stacked region of the polycrystalline semiconductor layer 24, the degree of design freedom can be increased. Also in the second embodiment, the end portion of the polycrystalline semiconductor layer 24 can be tapered. By adopting the tapered shape, the coverage of the conductive thin film can be kept good, and problems such as disconnection can be sufficiently suppressed. In addition, the coverage of the gate insulating film stacked thereon is also improved, and defects such as dielectric breakdown can be sufficiently suppressed.

[Embodiment 3]
FIG. 10 is a top view showing a configuration in the vicinity of the TFT 318 formed on the TFT array substrate according to the third embodiment. 11A is a cross-sectional view taken along the line XIa-XIa ′ of FIG. 10, and FIG. 11B is a cross-sectional view taken along the line XIb-XIb ′ of FIG. 10, where the source region and the drain region are formed. A cross-sectional structure cut along the channel length direction (X direction) is shown.

  The TFT 318 according to the third embodiment has the same configuration as the TFT according to the second embodiment except for the following points. That is, in the second embodiment, as shown in FIG. 9A, the conductive thin film 25 is formed not only on the upper layer of the polycrystalline semiconductor layer 24 but also on the side wall portion and the insulating substrate 1 and on the polycrystalline semiconductor layer 24. The present embodiment is different in that the conductive thin film 35 is formed in the upper layer of the base film 2 and in the lower layer of the polycrystalline semiconductor layer 24 in the third embodiment. More specifically, the conductive thin film 35 and the polycrystalline semiconductor layer 24 have a laminated structure in the region A2 near the contact hole 9 formation region, and the conductive thin film 35 is formed below the polycrystalline semiconductor layer 24. Yes. On the other hand, in the vicinity A 1 of the contact hole 9 formation region, there are a laminated region and a non-laminated region of the conductive thin film 35 and the polycrystalline semiconductor layer 24. That is, there is a region where the polycrystalline semiconductor layer 24 is not formed on the conductive thin film 35.

  According to the third embodiment, the conductive thin film 35 is formed over the channel width direction of the lower layer of the polycrystalline semiconductor layer that forms the source region and the drain region of the TFT. By bringing the low-resistance conductive thin film 35 into contact with the polycrystalline semiconductor layer serving as the source region and the drain region, it is possible to reliably apply a desired voltage to the source region and the drain region. Thereby, it is not necessary to arrange the contact holes evenly in the channel width direction, and the number of contact holes can be reduced. As a result, the area for arranging the contact holes can be reduced. Further, by forming the contact hole 9 in the conductive thin film 35 on the non-stacked region with the semiconductor layer, the degree of freedom in design can be increased.

[Embodiment 4]
FIG. 12 is a top view showing a configuration in the vicinity of the TFT 418 formed on the TFT array substrate according to the fourth embodiment. 13 is a cross-sectional view taken along the line XIII-XIII ′ of FIG. 12, showing a cross-sectional structure cut along the channel length direction (X direction in FIG. 12) in which the source region and the drain region are formed. ing.

The TFT 418 according to Embodiment 4 has the same configuration as the TFT of Embodiment 1 except for the following points. That is, as shown in FIG. 7 in the first embodiment, the conductive thin film 5 on the source region 4a and the source electrode 10 are connected from the surface of the first interlayer insulating film 8 through the first contact hole 9, and the drain. The conductive thin film 5 and the drain electrode 11 on the region 4c are connected. In addition, the drain electrode 11 is connected to the pixel electrode 17 through the second contact hole 16 formed on the surface of the second interlayer insulating film 15. On the other hand, in the fourth embodiment, as shown in FIG. 13, the conductive thin film connecting contact hole 42 penetrating from the surface of the second interlayer insulating film 15 to the conductive thin film 5 above the source region 4a, and the first interlayer insulating A first electrode connection contact hole 43 connected to the first electrode layer 41 formed on the film 8 is provided.

  Conventionally, since the pixel electrode is a transparent conductive oxide film, it has been difficult to obtain a good contact resistance by directly contacting the source region 4a, the drain region 4c, and the pixel electrode. This is because the polycrystalline semiconductor layer is oxidized at the interface between the pixel electrode and the polycrystalline semiconductor layer, and an insulating oxide is formed at the interface.

  According to the fourth embodiment, since the conductive thin film is formed on the polycrystalline semiconductor layer 4, even when the pixel electrode and the conductive thin film are directly connected through the contact hole, good contact resistance is obtained. be able to.

  In the above conventional example, the pixel electrode is contacted via the source / drain electrodes which are metallic conductive films. For this reason, it manufactured by the following processes. That is, first, after forming the first interlayer insulating film, contact holes are formed to form a source electrode and a drain electrode. Next, a second interlayer insulating film is formed on the source electrode and the drain electrode, and a contact hole for connecting the pixel electrode and the drain electrode is connected.

  According to the fourth embodiment, after forming the first interlayer insulating film and the second interlayer insulating film, it is possible to pattern the contact holes at the same time and connect the wirings with the transparent conductive film used for the pixel electrodes. Become. As a result, the number of photoengraving steps can be reduced, and productivity can be improved.

  In addition to the above configuration, the contact form of the conductive thin film with respect to the polycrystalline semiconductor layer can be configured, for example, as in Embodiments 2 and 3 above. The formation position of the conductive thin film connection contact hole 42 can also be provided on a non-laminated region with the polycrystalline semiconductor layer as in the second and third embodiments.

  It is also possible to mount the TFT according to the present invention on an organic EL display device or the like. In the case of an organic EL display device, a planarizing film having a contact hole is provided on the drain electrode 11 of the TFT 118. An anode electrode is formed on the planarizing film and connected to the drain electrode through the contact hole.

FIG. 3 is a cross-sectional view illustrating a configuration of the liquid crystal display device according to the first embodiment. FIG. 2 is a plan view showing the configuration of the liquid crystal display device according to the first embodiment. FIG. 3 is a top view showing a configuration in the vicinity of the TFT according to the first embodiment. FIG. 4 is a cross-sectional view taken along the line IV-IV ′ of FIG. 3. FIG. 6 is a manufacturing process diagram of the TFT according to the first embodiment. FIG. 6 is a manufacturing process diagram of the TFT according to the first embodiment. FIG. 3 is a cross-sectional view illustrating a configuration of a TFT array substrate according to the first embodiment. FIG. 6 is a top view showing a configuration in the vicinity of a TFT according to a second embodiment. (A) is IXa-IXa 'cutting part sectional drawing of FIG. 8, (b) is IXb-IXb' cutting part sectional drawing of FIG. FIG. 6 is a top view showing a configuration in the vicinity of a TFT according to a third embodiment. (A) is XIa-XIa 'cutting part sectional drawing of FIG. 10, (b) is XIa-XIa' cutting part sectional drawing of FIG. FIG. 6 is a top view showing a configuration in the vicinity of a TFT according to a fourth embodiment. FIG. 13 is a cross-sectional view taken along the line XIII-XIII ′ of FIG. 12. The partial top view which shows the structure of the LTPS-TFT concerning a prior art example. FIG. 15 is a cross-sectional view taken along the line XVI-XVI ′ of FIG. 14.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Base film 3 Amorphous semiconductor films 4 and 24, Polycrystalline semiconductor layers 4a and 24a Source regions 4b and 24b Channel regions 4c and 24c Drain regions 5, 25 and 35 Conductive thin film 6 Gate insulating film 7 Gate electrode 8 Interlayer insulating layer 9 Contact hole 10 Source electrode 11 Drain electrode 12 Laser beam 42 Contact hole for connecting conductive thin film 43 Contact hole for connecting electrode 100 Liquid crystal display device 101 Liquid crystal display panel 102 Backlight 103 Array substrate 104 Counter substrate 105 Sealing material 106 Liquid crystal 107 Spacer 108 Gate line 109 Source line 110 Alignment film 111 Counter electrode 112 Polarizing plate 115 Display area 116 Peripheral area 117 Pixel 119 First external wiring 120 Second external wiring

Claims (11)

A gate electrode;
A semiconductor layer having a channel region formed under the gate electrode, a source region and a drain region sandwiching the channel region;
A conductive thin film formed so as to be in contact with the source region and the drain region over the channel width direction;
A source electrode connected to the source region and a drain electrode connected to the drain region through a contact hole formed on the conductive thin film so as to face the gate electrode in the channel length direction. ,
A thin film transistor in which the dimension of the conductive thin film in the channel length direction is smaller than at least a portion near the contact hole formation region with respect to the vicinity of the contact hole formation region.   The thin film transistor according to claim 1, wherein the contact hole is formed in a non-stacked region with the semiconductor layer on the conductive thin film.   2. The thin film transistor according to claim 1, wherein dimensions of the source region and the drain region in a channel length direction are smaller than at least a portion near the contact hole forming region with respect to the vicinity of the contact hole forming region. . A gate electrode;
A semiconductor layer having a channel region formed under the gate electrode, a source region and a drain region sandwiching the channel region;
A conductive thin film formed so as to be in contact with the source region and the drain region over the channel width direction;
Via a contact hole formed on the conductive thin film, a source electrode connected to the source region, and a drain electrode connected to the drain region,
The contact hole is formed in a non-stacked region with the semiconductor layer on the conductive thin film,
A thin film transistor in which the dimension of the conductive thin film in the channel length direction is smaller than at least a portion near the contact hole formation region with respect to the vicinity of the contact hole formation region.   5. The thin film transistor according to claim 1, wherein the conductive thin film has a stacked region that is stacked immediately above the semiconductor layer.   5. The thin film transistor according to claim 1, wherein the conductive thin film has a stacked region stacked immediately below the semiconductor layer.   The thin film transistor according to claim 1, wherein the conductive thin film is formed over an upper layer and a side wall of the semiconductor layer and the substrate in the vicinity of the semiconductor layer.   The thin film transistor according to claim 1, wherein the conductive thin film is made of Mo, Cr, W, Ti, Ta, or an alloy containing these as a main component.   A display device formed using the thin film transistor according to claim 1. A semiconductor layer formed on a substrate and having a source / drain region and a channel region disposed between the source / drain regions;
A conductive thin film formed so as to be in contact with each of the source region and the drain region over the channel width direction;
A gate insulating film formed on the semiconductor layer;
A gate electrode disposed on the opposite side of the channel region via the gate insulating film;
A first interlayer insulating film covering the gate electrode and the gate insulating film;
A first electrode layer formed on the first interlayer insulating film;
A second interlayer insulating film formed on the first electrode layer;
Formed on the second interlayer insulating film, connected to the conductive thin film via a conductive thin film connecting contact hole, and connected to the first electrode layer via a first electrode layer connecting contact hole; Two electrode layers,
A display device in which the dimension of the conductive thin film in the channel length direction is smaller than at least a portion of the conductive thin film connecting contact hole forming region in the vicinity of the conductive thin film connecting contact hole forming region. Forming a semiconductor layer having a source / drain region and a channel region disposed between the source / drain regions on a substrate;
Forming a conductive thin film on the substrate;
Forming a gate insulating film on the semiconductor layer;
Forming a gate electrode layer on the gate insulating film;
Forming a first interlayer insulating film on the gate electrode layer;
Forming a first electrode layer on the first interlayer insulating film;
Forming a second interlayer insulating film on the first electrode layer;
Forming a conductive thin film connecting contact hole reaching the conductive thin film from the surface of the second interlayer insulating film and a first electrode layer connecting contact hole reaching the first electrode layer from the surface of the second interlayer insulating film; When,
Forming a second electrode layer so as to cover the conductive thin film connecting contact hole and the first electrode layer connecting contact hole,
In a display device, the dimension of the conductive thin film in the channel length direction is formed so that at least a part of the conductive thin film connecting contact hole forming region is not near the conductive thin film connecting contact hole forming region. Production method.

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