JPH06160904A - Liquid crystal display device and its production - Google Patents

Liquid crystal display device and its production

Info

Publication number
JPH06160904A
JPH06160904A JP31682592A JP31682592A JPH06160904A JP H06160904 A JPH06160904 A JP H06160904A JP 31682592 A JP31682592 A JP 31682592A JP 31682592 A JP31682592 A JP 31682592A JP H06160904 A JPH06160904 A JP H06160904A
Authority
JP
Japan
Prior art keywords
wiring
wirings
scanning
liquid crystal
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31682592A
Other languages
Japanese (ja)
Inventor
Hiroshi Miyama
博 深山
Takuya Kumagai
卓也 熊谷
Yasuto Sekado
康人 瀬角
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP31682592A priority Critical patent/JPH06160904A/en
Publication of JPH06160904A publication Critical patent/JPH06160904A/en
Pending legal-status Critical Current

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  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)

Abstract

PURPOSE:To provide the liquid crystal display device which decreases the man- hours for production, lowers the disconnection defects generation rate of respective wirings and to lower the resistance of respective wirings relating to the structure of the active matrix type liquid crystal display device constituted by using thin-film transistors (TFTs) switching elements and the process for production of such structure. CONSTITUTION:Scanning lines for driving TFTs and signal wirings are constituted by simultaneously forming the first signal wirings 17 (b) which are a part of the signal wirings at the time of forming the first scanning wirings 17 (a), further, forming the second scanning wirings 16 (b) which are a part of the scanning wirings at the time of forming the second signal wirings 16 (a) and bringing the respective wirings into electrical contact partially with each other via aperture contact parts 18, 19. As a result, the number of patterning times is decreased and since the respective wirings can be made into redundancy constitution, there are the effect of decreasing man-hours for production, drastically lessening the disconnection defect generation rate of the respective wirings and preventing the delaying of the signals by the lowered resistance of the respective wirings.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は液晶表示装置、とりわけ
薄膜トランジスタをスイッチング素子として用いたアク
ティブマトリクス型液晶表示装置とその製造方法に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to an active matrix liquid crystal display device using a thin film transistor as a switching element and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、微細加工技術と液晶材料の進歩に
より、液晶パネルを用いたテレビ画像表示装置が商用ベ
ースで提供されている。また、その方式としては画素毎
にスイッチング素子を内蔵させた、いわゆるアクティブ
マトリクス方式が高コントラスト,高解像度等の利点か
ら主流になりつつある。
2. Description of the Related Art In recent years, due to advances in fine processing technology and liquid crystal materials, television image display devices using liquid crystal panels have been provided on a commercial basis. Further, as the method, a so-called active matrix method in which a switching element is built in each pixel is becoming mainstream because of advantages such as high contrast and high resolution.

【0003】図4はアクティブマトリクス型の液晶パネ
ルの等価回路で、走査線群1と信号線群2との交差点毎
に、例えば電界効果型の薄膜トランジスタ(以下電界効
果型トランジスタと呼ぶ)のスイッチング素子3と、液
晶セル4が配置される。5は全ての液晶セル4に共通し
た透明導電層よりなる対向電極である。
FIG. 4 is an equivalent circuit of an active matrix type liquid crystal panel. For each intersection of the scanning line group 1 and the signal line group 2, for example, a switching element of a field effect type thin film transistor (hereinafter referred to as a field effect type transistor). 3 and the liquid crystal cell 4 are arranged. Reference numeral 5 is a counter electrode made of a transparent conductive layer common to all liquid crystal cells 4.

【0004】図5は一般的なアクティブマトリクス方式
の単位画素の平面配置図であり同図A−A′線上の断面
図を図6に示す。以下図を参照しながら従来の液晶パネ
ルについて説明する。
FIG. 5 is a plan view of a unit pixel of a general active matrix system, and FIG. 6 is a sectional view taken along the line AA 'in FIG. A conventional liquid crystal panel will be described below with reference to the drawings.

【0005】透明の絶縁性基板14、例えばガラス基板
の一主面上に画素電極6を透明導電層例えばITOを用
い選択的に形成する。そして、走査線(走査電極)と電
界効果型トランジスタのゲートを兼ねる導電層7を第1
の導電層7(a)、例えばCr薄膜と、第2の導電層7
(b)、例えばMoSi2薄膜との連続的な積層によっ
て選択的に被着形成する。つぎに例えばSi34よりな
る第1の絶縁層15、不純物をほとんど含まない第1の
非晶質シリコン層11、そして第2の絶縁層13を例え
ばSi34により好ましくは連続的に被着する。その
後、第2の絶縁層13をソース・ドレイン配線形成時の
エッチングストッパとして電界効果型トランジスタのチ
ャネル部に島状にパタニングする。次に第1の非晶質シ
リコン層11とソース・ドレイン配線8,9との間のオ
ーミック性を改善する目的で例えば燐を含んだ第2の非
晶質シリコン層12を被着後、第1の非晶質シリコン層
11と同時に電界効果型トランジスタのチャネル部に島
状にパタニングする。最後に信号線(信号電極)8及び
ドレイン配線9を例えば
Pixel electrodes 6 are selectively formed on one main surface of a transparent insulating substrate 14, for example, a glass substrate, by using a transparent conductive layer such as ITO. Then, the conductive layer 7 that also serves as the scanning line (scanning electrode) and the gate of the field effect transistor is formed as the first layer.
Conductive layer 7 (a) of, for example, a Cr thin film, and the second conductive layer 7
(B) Selectively deposit by, for example, continuous lamination with a MoSi 2 thin film. Next, the first insulating layer 15 made of, for example, Si 3 N 4 , the first amorphous silicon layer 11 containing almost no impurities, and the second insulating layer 13 are made of, for example, Si 3 N 4 , preferably continuously. Put on. Then, the second insulating layer 13 is patterned in an island shape on the channel portion of the field effect transistor as an etching stopper at the time of forming the source / drain wiring. Next, for the purpose of improving the ohmic property between the first amorphous silicon layer 11 and the source / drain wirings 8 and 9, a second amorphous silicon layer 12 containing, for example, phosphorus is deposited, and then a second amorphous silicon layer 12 is deposited. Simultaneously with the first amorphous silicon layer 11, the island-shaped patterning is performed on the channel portion of the field effect transistor. Finally, the signal line (signal electrode) 8 and the drain wiring 9 are, for example,

【0006】[0006]

【外1】 [Outer 1]

【0007】で選択的に被着形成することにより、液晶
表示装置が完成する。
The liquid crystal display device is completed by selectively forming and depositing with.

【0008】[0008]

【発明が解決しようとする課題】液晶パネルのさらなる
高密度化及び大画面化を達成するためにも画像表示上の
無欠陥化が切望されている。しかしながら上記の様な構
成では、構造及び製造プロセスが複雑であるため、この
無欠陥化の実現は非常に困難であるという問題を有して
いる。この無欠陥化を困難にしている原因の一つに、信
号配線、並びに走査配線の欠陥(断線)がある。実際に
断線を防ぐ方法として、各配線を2層構造として各層で
発生する断線欠陥をそれぞれの層が補う構造がとられて
いる。しかしこの構造では、各配線が2層構造となるた
め配線を形成する際、各配線用のパターンを2回形成す
ることが必要であり、そのため配線用導電層の形成から
フォトエッチング工程が本来必要な数の2倍に工数が増
加し、低コスト化に大きな課題を有している。また、画
面サイズの大型化に伴い信号配線、並びに走査配線の抵
抗値増大の課題もある。特に走査配線の抵抗増大は信号
の遅延となり、画像上信号配線方向の輝度傾斜等の原因
となり大きな課題である。
In order to achieve higher density and larger screen of the liquid crystal panel, it is desired to make the image display defect-free. However, the above-mentioned configuration has a problem that it is very difficult to realize defect-free because the structure and manufacturing process are complicated. One of the reasons that makes it difficult to eliminate defects is a defect (disconnection) in the signal wiring and the scanning wiring. As a method of actually preventing disconnection, a structure is adopted in which each wiring has a two-layer structure and each layer compensates for a disconnection defect generated in each layer. However, in this structure, since each wiring has a two-layer structure, it is necessary to form the pattern for each wiring twice when forming the wiring, and therefore the photoetching process is originally required from the formation of the conductive layer for wiring. The number of man-hours is doubled, and there is a big problem in cost reduction. Further, there is a problem that the resistance value of the signal wiring and the scanning wiring increases as the screen size increases. In particular, an increase in the resistance of the scanning wiring causes a signal delay, which causes a luminance gradient in the image signal wiring direction, which is a serious problem.

【0009】本発明は上記課題に鑑み、信号配線、並び
に走査配線の断線欠陥発生を工数を増加させることなく
防止し、更に前記両配線の低抵抗化を図る構造を有する
液晶表示装置を提供するものである。
In view of the above problems, the present invention provides a liquid crystal display device having a structure for preventing the occurrence of disconnection defects in signal wirings and scanning wirings without increasing the number of steps and further reducing the resistance of both wirings. It is a thing.

【0010】[0010]

【課題を解決するための手段】本発明はかかる点に鑑
み、走査配線を形成する際、第1の走査配線と同時に第
1の信号配線の一部を同時に形成し、絶縁層を介して信
号配線を形成する際、第2の信号配線と第2の走査配線
を同時に形成する。この時絶縁層の一部に予め形成して
いおいた開口部を通じて第1の走査配線と第2の走査配
線を、更に第1の信号配線と第2の信号配線をそれぞれ
電気的に接続することにより走査配線、信号配線を形成
する。
SUMMARY OF THE INVENTION In view of the above, the present invention is directed to forming a scanning wiring, forming a part of the first signal wiring at the same time as the first scanning wiring, and transmitting a signal through an insulating layer. When forming the wiring, the second signal wiring and the second scanning wiring are simultaneously formed. At this time, the first scan wiring and the second scan wiring, and the first signal wiring and the second signal wiring are electrically connected to each other through an opening previously formed in a part of the insulating layer. Thus, scanning wiring and signal wiring are formed.

【0011】[0011]

【作用】本発明は上記した構成により、走査配線,信号
配線と同一層の導電層を用いて、それぞれを複数層に構
成することが可能となるため、例え一方の導電層に断線
が発生しても他の導電層によってその欠陥を補うことが
可能となる。特に走査配線、信号配線のそれぞれの層を
形成するだけで、各配線は一部を除いて2層構成とな
り、高品質を維持しつつ製作工数の削減が可能となる。
また、走査配線、並びに信号配線を複数層の導電層によ
って構成することから、それぞれの配線を低抵抗化する
ことができ、例えば走査配線においては印加された走査
信号の遅延による走査配線方向の輝度傾斜といった画像
不良を対策し、正常な画像を提供するに充分なゲート配
線の低抵抗化も達成できるものである。
According to the present invention, since the scanning wiring and the signal wiring can be formed in a plurality of layers by using the same conductive layer as the above structure, a disconnection occurs in one conductive layer. However, the defect can be compensated by another conductive layer. Particularly, only by forming the respective layers of the scanning wiring and the signal wiring, each wiring has a two-layer structure except a part, and it is possible to reduce the number of manufacturing steps while maintaining high quality.
Further, since the scanning wiring and the signal wiring are composed of a plurality of conductive layers, it is possible to reduce the resistance of each wiring. For example, in the scanning wiring, the luminance in the scanning wiring direction due to the delay of the applied scanning signal. It is also possible to take measures against image defects such as tilting and achieve a low resistance of the gate wiring sufficient to provide a normal image.

【0012】[0012]

【実施例】図1は、本発明の一実施例によるアクティブ
マトリクス型の液晶表示装置の単位画素の平面配置図で
あり、同図のA−A′線上の断面図を図2に、B−B′
線上の断面図を図3にそれぞれ示す。
1 is a plan view of a unit pixel of an active matrix type liquid crystal display device according to an embodiment of the present invention. FIG. 2 is a sectional view taken along line AA 'in FIG. B '
A cross-sectional view on the line is shown in FIG. 3, respectively.

【0013】まず、図1に示すように、ガラス基板上に
透明電極からなる画素電極20をパターン形成し、この
画素電極20とは電気的に分離して、第1の走査配線1
7(a)と信号配線の一部となる第1の信号配線17
(b)を、さらに第1の走査配線17(a)と電気的に
分離して、同一層からなる導電層(例えばCr,(外
1)等)を用いてフォトエッチング法によりパタニング
する。次に第1の走査配線17(a)と第1の信号配線
17(b)上には、図2および図3に示すように、この
後形成する第2の信号配線16(a)、第2の走査配線
16(b)との絶縁を保つための第1の絶縁層26(例
えばSi34)が少なくとも第1の走査配線17
(a)、並びに第1の信号配線17(b)上に形成され
る。また、電界効果型トランジスタ部には、第1の絶縁
層26上に不純物をほとんど含まない第1の非晶質シリ
コン層21、第2の絶縁層22を連続的に被着し、その
後、第2の絶縁層22を、この後形成する第2の信号配
線16(a)、第2の走査配線16(b)、並びにドレ
イン配線23の形成時のエッチングストッパとして電界
トランジスタのチャネル部に島状にパタニングする。次
に第1の非晶質シリコン層21と第2の信号配線16
(a)、並びにドレイン配線23との間のオーミック性
を改善する目的で、例えば燐を含んだ第2の非晶質シリ
コン層25を被着後、第1の非晶質シリコン層21と同
様に電界効果型トランジスタのチャネル部に島状にパタ
ニングする。次に、この後形成する第2の信号配線16
(a)、第2の走査配線16(b)、並びにドレン配線
23とそれぞれの配線、並びに電極と電気的に導通をと
るための開口コンタクト部18,19,24がそれぞれ
設けられる。次に各開口コンタクト部が設けられた基板
上に導電層を形成し、この導電層をパタニングすること
により、第2の信号配線16(a)、前記第2の信号配
線とは電気的に分離した第2の走査配線16(b)、並
びにドレイン配線23を形成する。
First, as shown in FIG. 1, a pixel electrode 20 made of a transparent electrode is pattern-formed on a glass substrate, and the pixel electrode 20 is electrically separated from the pixel electrode 20.
7 (a) and the first signal wiring 17 which becomes a part of the signal wiring
Further, (b) is electrically separated from the first scanning wiring 17 (a), and is patterned by a photoetching method using a conductive layer made of the same layer (for example, Cr, (outer 1), etc.). Next, on the first scanning wiring 17 (a) and the first signal wiring 17 (b), as shown in FIGS. 2 and 3, the second signal wiring 16 (a) and the second signal wiring 16 (a) formed later are formed. The first insulating layer 26 (for example, Si 3 N 4 ) for maintaining insulation with the second scanning wiring 16 (b) is at least the first scanning wiring 17
(A) and the first signal wiring 17 (b). Further, in the field effect transistor portion, the first amorphous silicon layer 21 containing almost no impurities and the second insulating layer 22 are continuously deposited on the first insulating layer 26, and then the first insulating layer 26 is formed. The second insulating layer 22 is used as an etching stopper at the time of forming the second signal wiring 16 (a), the second scanning wiring 16 (b), and the drain wiring 23, which will be formed later, in the channel portion of the electric field transistor. Pattern. Next, the first amorphous silicon layer 21 and the second signal wiring 16
In order to improve ohmic contact between (a) and the drain wiring 23, the second amorphous silicon layer 25 containing, for example, phosphorus is deposited, and then the same as the first amorphous silicon layer 21. Then, an island pattern is formed on the channel portion of the field effect transistor. Next, the second signal wiring 16 to be formed later is formed.
(A), the second scanning wiring 16 (b), the drain wiring 23, and the respective wirings, and the opening contact portions 18, 19, 24 for electrically connecting with the electrodes are provided. Next, a conductive layer is formed on the substrate provided with the opening contact portions, and the conductive layer is patterned to electrically separate the second signal wiring 16 (a) from the second signal wiring. The second scanning wiring 16 (b) and the drain wiring 23 are formed.

【0014】この状態において、第1の走査配線17
(a)と第2の走査配線16(b)が第2の走査配線1
6(b)の両端部に設けられた開口コンタクト部19に
よって電気的に導通が得られ(図2参照)、また、同様
に第1の信号配線17(b)と第2の信号配線16
(a)が開口コンタクト部18によって電気的な導通が
得られる(図3参照)。また、ドレイン配線23は画素
電極20と開口コンタクト部24によって電気的な導通
が得られる。ここで、第1の走査配線17(a)と第2
の信号配線16(a)を各画素ごとに1本の連続した配
線として形成することにより各画素に信号を供給するこ
とができる。
In this state, the first scanning wiring 17
(A) and the second scanning wiring 16 (b) are the second scanning wiring 1
Electrical continuity is obtained by the opening contact portions 19 provided at both ends of 6 (b) (see FIG. 2), and similarly, the first signal wiring 17 (b) and the second signal wiring 16 are also provided.
In (a), electrical continuity is obtained by the opening contact portion 18 (see FIG. 3). Further, the drain wiring 23 can be electrically connected by the pixel electrode 20 and the opening contact portion 24. Here, the first scan line 17 (a) and the second scan line 17 (a)
It is possible to supply a signal to each pixel by forming the signal wiring 16 (a) as a continuous wiring for each pixel.

【0015】以上の様に、本実施例はアクティブマトリ
クス型の液晶表示装置において、第1の走査配線を形成
する際に信号配線の一部となる第1の信号配線を、ま
た、第2の信号配線を形成する際に第2の走査配線の一
部を形成し、それぞれ第1の配線と第2の配線は両者の
間に設けらえた層の一部に開口部を設け、電気的に接触
を図るようにしたものである。この構造により走査配線
と信号配線の2層で両者を冗長構成にすることが可能と
なり、各配線の断線欠陥の大幅な減少が可能である。ま
た、それぞれの配線が2層構造となることから各配線の
低抵抗化も可能となる。
As described above, in this embodiment, in the active matrix type liquid crystal display device, the first signal wiring which becomes a part of the signal wiring when forming the first scanning wiring, and the second signal wiring are formed. When forming the signal wiring, a part of the second scanning wiring is formed, and each of the first wiring and the second wiring is provided with an opening portion in a part of a layer provided therebetween, and electrically. It is designed to make contact. With this structure, the two layers of the scanning wiring and the signal wiring can be made redundant, and the disconnection defect of each wiring can be greatly reduced. Further, since each wiring has a two-layer structure, it is possible to reduce the resistance of each wiring.

【0016】[0016]

【発明の効果】以上説明したように本発明によれば、走
査配線と信号配線は、それぞれ1回のパタニングによっ
て両配線を冗長構成とすることが可能となり、パタニン
グ回数の削減を図って、しかも冗長構成となることか
ら、例え一方の配線に断線が発生しても他の一方の配線
がこれをカバーすることが可能となり、工数削減と同時
に製造歩留まりを飛躍的に改善できる。また、各配線は
2層構造となることから各配線抵抗を低くすることが可
能となり、低抵抗化によって各信号の遅延課題に対して
も効果がある。
As described above, according to the present invention, both the scanning wiring and the signal wiring can be redundantly configured by performing the patterning once, thereby reducing the number of times of patterning and Due to the redundant configuration, even if a wire breakage occurs in one wire, the other wire can cover the wire breakage, and the manufacturing yield can be dramatically improved while reducing the man-hours. Further, since each wiring has a two-layer structure, each wiring resistance can be reduced, and the reduction in resistance is effective for the delay problem of each signal.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例にかかる液晶表示装置の要部
平面図
FIG. 1 is a plan view of a main part of a liquid crystal display device according to an embodiment of the present invention.

【図2】同装置の要部断面図FIG. 2 is a sectional view of the main part of the same device.

【図3】同装置の要部断面図FIG. 3 is a sectional view of the main part of the device.

【図4】一般的アクティブマトリクス型液晶パネルの等
価回路図
FIG. 4 is an equivalent circuit diagram of a general active matrix type liquid crystal panel.

【図5】従来例の液晶表示装置の要部拡大図FIG. 5 is an enlarged view of a main part of a conventional liquid crystal display device.

【図6】同装置の要部断面図FIG. 6 is a sectional view of the main part of the device.

【符号の説明】[Explanation of symbols]

16(a) 第2の信号配線 16(b) 第2の走査配線 17(a) 第1の走査配線 17(b) 第1の信号配線 18,19,24 開口コンタクト部 16 (a) Second signal wiring 16 (b) Second scanning wiring 17 (a) First scanning wiring 17 (b) First signal wiring 18, 19, 24 Opening contact portion

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 一対の基板上に液晶が封入され、前記基
板の一方の基板上にマトリクス状に配列された画素電極
と、前記画素電極に近接して接続されてなる薄膜トラン
ジスタと、前記薄膜トランジスタのソース電極に接続さ
れてなる信号配線と、前記薄膜トランジスタのゲート電
極に接続されてなる走査配線を有し、前記信号配線、あ
るいは前記走査配線の少なくとも一方が、第1,第2の
2層の配線から構成され、この第1,第2の配線の間に
開口部を有する絶縁層が設けられ、この開口部を介して
前記第1,第2の2層の配線が電気的に接触を保って配
置されている液晶表示装置。
1. A liquid crystal is sealed on a pair of substrates, pixel electrodes arranged in a matrix on one substrate of the substrates, a thin film transistor formed adjacent to the pixel electrodes, and a thin film transistor of the thin film transistor. A signal wiring connected to a source electrode and a scanning wiring connected to a gate electrode of the thin film transistor are provided, and at least one of the signal wiring and the scanning wiring is a wiring of first and second layers. An insulating layer having an opening is provided between the first and second wirings, and the wirings of the first and second two layers maintain electrical contact through the opening. Liquid crystal display device that is arranged.
【請求項2】 走査配線あるいは信号配線を構成する第
1,第2の配線は、そのいずれか一方が前記走査配線と
前記信号配線の交差部を除いて設けられている請求項1
記載の液晶表示装置。
2. The scanning wiring or the signal wiring, the first wiring, the second wiring, either one is provided except for the intersection of the scanning wiring and the signal wiring.
The described liquid crystal display device.
【請求項3】 第1の走査配線を形成する際に第1の信
号配線を同時に形成し、第2の信号配線を形成する際に
第2の走査配線を同時に形成することを特徴とする請求
項1あるいは2いずれか記載の液晶表示装置の製造方
法。
3. The first signal wiring is simultaneously formed when forming the first scanning wiring, and the second scanning wiring is simultaneously formed when forming the second signal wiring. Item 3. A method for manufacturing a liquid crystal display device according to item 1 or 2.
JP31682592A 1992-11-26 1992-11-26 Liquid crystal display device and its production Pending JPH06160904A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31682592A JPH06160904A (en) 1992-11-26 1992-11-26 Liquid crystal display device and its production

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31682592A JPH06160904A (en) 1992-11-26 1992-11-26 Liquid crystal display device and its production

Publications (1)

Publication Number Publication Date
JPH06160904A true JPH06160904A (en) 1994-06-07

Family

ID=18081343

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31682592A Pending JPH06160904A (en) 1992-11-26 1992-11-26 Liquid crystal display device and its production

Country Status (1)

Country Link
JP (1) JPH06160904A (en)

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