JPH02157827A - Thin film transistor array device - Google Patents
Thin film transistor array deviceInfo
- Publication number
- JPH02157827A JPH02157827A JP63313341A JP31334188A JPH02157827A JP H02157827 A JPH02157827 A JP H02157827A JP 63313341 A JP63313341 A JP 63313341A JP 31334188 A JP31334188 A JP 31334188A JP H02157827 A JPH02157827 A JP H02157827A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- thin film
- drain electrode
- film transistor
- picture element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 30
- 239000010408 film Substances 0.000 claims abstract description 33
- 239000011229 interlayer Substances 0.000 claims abstract description 13
- 230000007547 defect Effects 0.000 abstract description 8
- 238000004519 manufacturing process Methods 0.000 abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 238000005121 nitriding Methods 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 12
- 229910052581 Si3N4 Inorganic materials 0.000 description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 10
- 239000011521 glass Substances 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は液晶デイスプレィ用の薄膜トランジスタアレイ
装置の製造に利用される。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is utilized in the manufacture of thin film transistor array devices for liquid crystal displays.
本発明は画素電極（ピクセル電極）を有する薄膜トラン
ジスタアレイ装置に関し、特に、そのドレイン・ソース
電極と画素電極の構成に関する。The present invention relates to a thin film transistor array device having a pixel electrode, and particularly to the structure of the drain/source electrode and the pixel electrode.
本発明は、アレイ状に配列された複数の薄膜トランジス
タと、各薄膜トランジスタのソース電極またはドレイン
電極にそれぞれ接続された画素電極とを備えた薄膜トラ
ンジスタアレイ装置において、
前記ソース電極またはドレイン電極と前記画素電極との
接゛続を、前記ソース電極および前記ドレイン電極上に
設けられた絶縁膜中の開口部を介して行うようにするこ
とにより、
前記画素電極と前記ソース電極または前記ドレイン電極
との短絡を防止し、製品の製造歩留りの向上を図ったも
のである。The present invention provides a thin film transistor array device including a plurality of thin film transistors arranged in an array, and pixel electrodes connected to the source electrode or drain electrode of each thin film transistor, in which the source electrode or drain electrode and the pixel electrode are connected to each other. By making the connection through an opening in an insulating film provided on the source electrode and the drain electrode, a short circuit between the pixel electrode and the source electrode or the drain electrode is prevented. The aim is to improve the manufacturing yield of the product.
従来、液晶デイスプレィ用の薄膜トランジスタアレイ装
置においては、トランジスタ部アイランドを形成した後
、金属によりドレイン電極およびソース電極を形成し、
次に、透明導電膜を成膜し、パターン形成グすることに
よりソース画素電極を形成していた。Conventionally, in a thin film transistor array device for a liquid crystal display, after forming a transistor island, a drain electrode and a source electrode are formed using metal.
Next, a transparent conductive film is formed and patterned to form a source pixel electrode.
第３図はかかる従来の薄膜トランジスタアレイ装置の要
部を示す模式的縦断面図である。ドレイン電極６および
ソース電極７は、Ｃｒ （クロム）を３０００人スパッ
タにより成膜しパターン化して形成され、しかる後、Ｉ
Ｔ Ｏ（Ｉｎ２ＬとＳｎＯ□との混合物、Ｉｎｄｉｕ
ｍ Ｔｉｎ ０ｘｉｄｅ）をスパッタにより８００人成
膜し、パターン化することにより画素電極１０が形成さ
れる。FIG. 3 is a schematic vertical sectional view showing the main parts of such a conventional thin film transistor array device. The drain electrode 6 and the source electrode 7 are formed by forming a film of Cr (chromium) by 3000 sputtering and patterning it.
T O (mixture of In2L and SnO□, Indiu
The pixel electrode 10 is formed by forming a film of 800 mTin oxide) by sputtering and patterning it.
なお、第３図において、１はガラス基板、２はゲート電
極、３はゲート絶縁膜としてのシリコン窒化膜、４は真
性アモルファスシリコン層（以下、ｉ −ａ−５ｉとい
う。）、および５はｎ＋型アモルファスシリコン層（以
下、ｎ” −ａ−３ｉトいう。）である。In FIG. 3, 1 is a glass substrate, 2 is a gate electrode, 3 is a silicon nitride film as a gate insulating film, 4 is an intrinsic amorphous silicon layer (hereinafter referred to as i-a-5i), and 5 is n+ This is an amorphous silicon layer (hereinafter referred to as n''-a-3i).
前述した従来の薄膜トランジスタアレイ装置においては
、ドレイン電極６と画素電極１０が接続されたソース電
極７が同一面内に形成されるため、ＰＲ（ホトレジスト
）欠陥により、ドレイン電極一画素電極間の短絡欠陥が
発生する欠点がある。In the conventional thin film transistor array device described above, since the source electrode 7 to which the drain electrode 6 and the pixel electrode 10 are connected is formed in the same plane, short-circuit defects between the drain electrode and the pixel electrode may occur due to PR (photoresist) defects. There is a drawback that this occurs.
特に、デイスプレィ用薄膜トランジスタアレイ装置の場
合、画素開口率を大きくするため、ドレインラインと画
素電極間の間隔はできる限り狭くすることが望ましいた
め、この短絡欠陥の発生頻度は、他のパターン形成と比
べ格段に高いものとなり、薄膜トランジスタアレイ装置
の歩留りを低下させる大きな要因となっている。In particular, in the case of thin film transistor array devices for displays, it is desirable to make the interval between the drain line and pixel electrode as narrow as possible in order to increase the pixel aperture ratio, so the frequency of occurrence of this short circuit defect is lower than that of other pattern formations. This has become a significant factor in reducing the yield of thin film transistor array devices.
本発明の′目的は、前記の欠点を除去することにより、
画素電極とソース電極またはドレイン電極との短絡欠陥
の発生を防止し、製品の歩留りを向上できる薄膜トラン
ジスタアレイ装置を提供することにある。The object of the invention is to eliminate the above-mentioned drawbacks,
It is an object of the present invention to provide a thin film transistor array device that can prevent short-circuit defects between a pixel electrode and a source or drain electrode, and can improve product yield.
本発明は、アレイ状に配列された複数の薄膜トランジス
タと、この薄膜トランジスタにそれぞれ接続された複数
の画素電極とを備えた薄膜トランジスタアレイ装置にお
いて、前記薄膜トランジスタのソース電極およびドレイ
ン電極上に層間絶縁膜を設け、この層間絶縁膜中に設け
られた開口部を介して前記ソース電極またはドレイン電
極と前記画素電極とを接続したことを特徴とする。The present invention provides a thin film transistor array device including a plurality of thin film transistors arranged in an array and a plurality of pixel electrodes respectively connected to the thin film transistors, in which an interlayer insulating film is provided on the source electrode and drain electrode of the thin film transistor. , the source electrode or the drain electrode and the pixel electrode are connected through an opening provided in the interlayer insulating film.
画素電極とソース電極またはドレイン電極との接続は、
層間絶縁膜中の開口部を介して行われる。The connection between the pixel electrode and the source or drain electrode is
This is done through an opening in an interlayer insulating film.
従って、画素電極とソース電極またはドレイン電極間に
は層間絶縁膜（例えば窒化シリコン膜）が介在し、たと
え、ＰＲ欠陥が存在しても両電極間が電気的に短絡する
ことはなくなり、製品の製造歩留りを向上させることが
可能となる。Therefore, an interlayer insulating film (for example, a silicon nitride film) is interposed between the pixel electrode and the source or drain electrode, and even if a PR defect exists, there will be no electrical short circuit between the two electrodes, and the product It becomes possible to improve manufacturing yield.
以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.
第１図は本発明の第一実施例の要部を示す模式的縦断面
図で、一つの薄膜トランジスタを取り出して示したもの
である。FIG. 1 is a schematic vertical cross-sectional view showing the main parts of a first embodiment of the present invention, and shows one thin film transistor taken out.
本第−実施例は、アレイ状に配列された複数の薄膜トラ
ンジスタと、この薄膜トランジスタにそれぞれ接続され
た複数の画素電極１０とを備えた薄膜トランジスタアレ
イ装置において、
前記薄膜トランジスタのソース電極７およびドレイン電
極６上に層間絶縁膜としてのシリコン窒化（ＳｉＮｘ）
膜８を設け、このシリコン窒化膜８に設けられた開口部
９を介してソース電極７と画素電極１０とを接続したも
のである。The present embodiment is a thin film transistor array device including a plurality of thin film transistors arranged in an array and a plurality of pixel electrodes 10 respectively connected to the thin film transistors. Silicon nitride (SiNx) as an interlayer insulating film
A film 8 is provided, and the source electrode 7 and the pixel electrode 10 are connected through an opening 9 provided in the silicon nitride film 8.
なお、第１図において、１はガラス基板、２はゲート電
極、３はゲート絶縁膜、４はｉ −ａ −３ｉ層、およ
び５はｎ”−ａ−３ｉ層である。In FIG. 1, 1 is a glass substrate, 2 is a gate electrode, 3 is a gate insulating film, 4 is an i-a-3i layer, and 5 is an n''-a-3i layer.
本発明の特徴は、第１図において、開口部９を有するシ
リコン窒化膜８を設けたことにある。A feature of the present invention is that, as shown in FIG. 1, a silicon nitride film 8 having an opening 9 is provided.
次に、本第−実施例の製造方法について説明する。Next, the manufacturing method of this embodiment will be explained.
ガラス基板１上にゲート電極２が形成され、ゲート絶縁
膜として窒化シリコン膜３が３００ＯＡ、 ）ランジス
タ層としてｉ −ａ−３ｉ層４が３０００人、オーミッ
クコンタクト層としてｎ”−ａ−３ｉ層５が５０ＯＡ、
それぞれ形成される。次に、トランジス夕部以外のｉ
−ａ−３ｉ層４およびｎ“−ａ −３ｉ層５が除去され
、ドレイン電極６およびソース電極７となるＣｒが３０
００ Ａスパッタにより形成されパターン化される。そ
の後、層間絶縁膜として窒化シリコン膜８を１０００人
形成し、開口部９をエツチングにより形成し、ＩＴＯ８
００人をスパッタにより形成して、パターンニングし画
素電極１０を形成する。A gate electrode 2 is formed on a glass substrate 1, a silicon nitride film 3 of 300 OA as a gate insulating film, an i-a-3i layer 4 of 3000 OA as a transistor layer, and an n''-a-3i layer 5 as an ohmic contact layer. is 50OA,
Each is formed. Next, i other than the transistor Yube
-a-3i layer 4 and n"-a -3i layer 5 are removed, and Cr, which will become the drain electrode 6 and source electrode 7, is
It is formed and patterned by 00A sputtering. Thereafter, a silicon nitride film 8 was formed as an interlayer insulating film, and an opening 9 was formed by etching.
The pixel electrode 10 is formed by sputtering and patterning.
本第二実施例によれば、ドレイン電極６と画素電極１０
の間には窒化シリコン膜８が存在し、たとえＰＲ欠陥が
存在しても、画素電極１０とドレイン電極６が電気的に
短絡することはない。According to the second embodiment, the drain electrode 6 and the pixel electrode 10
A silicon nitride film 8 exists between them, and even if a PR defect exists, the pixel electrode 10 and the drain electrode 6 will not be electrically short-circuited.
第２図は本発明の第二実施例の要部を示す模式的縦断面
図である。FIG. 2 is a schematic vertical sectional view showing the main parts of a second embodiment of the present invention.
本第二実施例は、層間絶縁膜をポリイミド膜１１によっ
て形成し、その開口部９によって、ソース電極７と画素
電極１０とを接続したものである。In the second embodiment, the interlayer insulating film is formed of a polyimide film 11, and the source electrode 7 and the pixel electrode 10 are connected through the opening 9 thereof.
本発明の特徴は、第２図に右いて開口部９を有するポリ
イミド膜１１を設けたことにある。The feature of the present invention is that a polyimide film 11 having an opening 9 on the right side in FIG. 2 is provided.
本発明の第二実施例は、窒化シリコン膜８の代わりにポ
リイミド膜１１を形成することで、前述の第一実施例と
同様にして製造される。A second embodiment of the present invention is manufactured in the same manner as the first embodiment described above, except that a polyimide film 11 is formed in place of the silicon nitride film 8.
本第二実施例では、薄膜トランジスタアレイ装置の表面
が平坦な形状となり、液晶パネル形成におけるギャップ
制御、および配向制御が行いやすい利点がある。The second embodiment has the advantage that the surface of the thin film transistor array device has a flat shape, making it easy to perform gap control and alignment control in forming a liquid crystal panel.
なお、前述の説明は、画素電極とソース電極とが接続さ
れる場合について行ったけれども、ソース電極の代わり
に画素電極とドレイン電極とが接続される場合も同様で
ある。Note that although the above description was made for the case where the pixel electrode and the source electrode are connected, the same applies to the case where the pixel electrode and the drain electrode are connected instead of the source electrode.
以上説明したように、本発明は、薄膜トランジスタのド
レイン・ソース電極と画素電極の間に眉間絶縁膜を設け
、この層間絶縁膜中の開口部を介して両者を接続するこ
とにより、両者の短絡欠陥を大幅に低減でき、製品の歩
留りを向上できる効果がある。As explained above, the present invention provides a glabellar insulating film between the drain/source electrode of a thin film transistor and a pixel electrode, and connects the two through an opening in the interlayer insulating film, thereby preventing short-circuit defects between the two. This has the effect of significantly reducing product yield and improving product yield.
第１図は本発明の第一実施例の要部を示す模式％式％
第２図は本発明の第二実施例の要部を示す模式的縦断面
図。
第３図は従来例の要部を示す模式的縦断面図。
１・・・ガラス基板、２・・・ゲート電極、３．８・・
・シリコン窒化膜、４・・・ｉ −ａ−３ｉ層、５・・
・ｎ” −ａ−３ｉ層、６・・・ドレイン電極、７・・
・ソース電極、９・・・開口部、１０・・・画素電極、
１１・・・ポリイミド膜。FIG. 1 is a schematic diagram showing the main parts of a first embodiment of the present invention. FIG. 2 is a schematic vertical sectional view showing the main parts of a second embodiment of the invention. FIG. 3 is a schematic vertical sectional view showing the main parts of a conventional example. 1...Glass substrate, 2...Gate electrode, 3.8...
・Silicon nitride film, 4...i-a-3i layer, 5...
・n"-a-3i layer, 6... drain electrode, 7...
- Source electrode, 9... opening, 10... pixel electrode,
11... Polyimide film.
Claims (1)
この薄膜トランジスタにそれぞれ接続された複数の画素
電極とを備えた薄膜トランジスタアレイ装置において、 前記薄膜トランジスタのソース電極およびドレイン電極
上に層間絶縁膜を設け、 この層間絶縁膜中に設けられた開口部を介して前記ソー
ス電極またはドレイン電極と前記画素電極とを接続した ことを特徴とする薄膜トランジスタアレイ装置。[Claims] 1. A plurality of thin film transistors arranged in an array;
In a thin film transistor array device including a plurality of pixel electrodes each connected to the thin film transistor, an interlayer insulating film is provided on the source electrode and drain electrode of the thin film transistor, and an interlayer insulating film is provided through an opening provided in the interlayer insulating film. A thin film transistor array device characterized in that the source electrode or the drain electrode and the pixel electrode are connected.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63313341A JPH02157827A (en) | 1988-12-12 | 1988-12-12 | Thin film transistor array device |
| DE68921567T DE68921567T2 (en) | 1988-11-30 | 1989-11-29 | Liquid crystal display panel with reduced pixel defects. |
| EP89312448A EP0372821B1 (en) | 1988-11-30 | 1989-11-29 | Liquid crystal display panel with reduced pixel defects |
| US07/695,260 US5166816A (en) | 1988-11-30 | 1991-05-31 | Liquid crystal display panel with reduced pixel defects |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63313341A JPH02157827A (en) | 1988-12-12 | 1988-12-12 | Thin film transistor array device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02157827A true JPH02157827A (en) | 1990-06-18 |
Family
ID=18040080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63313341A Pending JPH02157827A (en) | 1988-11-30 | 1988-12-12 | Thin film transistor array device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02157827A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06118432A (en) * | 1992-10-09 | 1994-04-28 | Seiko Epson Corp | Liquid crystal display device |
| JPH06138489A (en) * | 1992-10-29 | 1994-05-20 | Seiko Epson Corp | Liquid crystal display device |
| US7169657B2 (en) | 1992-03-26 | 2007-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| JP2011097103A (en) * | 2008-09-19 | 2011-05-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62257130A (en) * | 1986-04-30 | 1987-11-09 | Sharp Corp | Liquid crystal display device |
-
1988
- 1988-12-12 JP JP63313341A patent/JPH02157827A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62257130A (en) * | 1986-04-30 | 1987-11-09 | Sharp Corp | Liquid crystal display device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7169657B2 (en) | 1992-03-26 | 2007-01-30 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| US7781271B2 (en) | 1992-03-26 | 2010-08-24 | Semiconductor Energy Laboratory Co., Ltd. | Process for laser processing and apparatus for use in the same |
| JPH06118432A (en) * | 1992-10-09 | 1994-04-28 | Seiko Epson Corp | Liquid crystal display device |
| JPH06138489A (en) * | 1992-10-29 | 1994-05-20 | Seiko Epson Corp | Liquid crystal display device |
| JP2011097103A (en) * | 2008-09-19 | 2011-05-12 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
| US9343517B2 (en) | 2008-09-19 | 2016-05-17 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US10032796B2 (en) | 2008-09-19 | 2018-07-24 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US10559599B2 (en) | 2008-09-19 | 2020-02-11 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
| US11610918B2 (en) | 2008-09-19 | 2023-03-21 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
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