JPH0340511B2 - - Google Patents
Info
- Publication number
- JPH0340511B2 JPH0340511B2 JP60214570A JP21457085A JPH0340511B2 JP H0340511 B2 JPH0340511 B2 JP H0340511B2 JP 60214570 A JP60214570 A JP 60214570A JP 21457085 A JP21457085 A JP 21457085A JP H0340511 B2 JPH0340511 B2 JP H0340511B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- address
- address line
- lines
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010408 film Substances 0.000 claims description 56
- 239000010409 thin film Substances 0.000 claims description 27
- 239000002184 metal Substances 0.000 claims description 11
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 239000010407 anodic oxide Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 7
- 239000011229 interlayer Substances 0.000 claims description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 230000007547 defect Effects 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000010410 layer Substances 0.000 description 4
- 239000011159 matrix material Substances 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 238000002048 anodisation reaction Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、薄膜トランジスタアレイにより駆動
される液晶等の表示装置の駆動回路基板に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a driving circuit board for a display device such as a liquid crystal device driven by a thin film transistor array.
近年、アモルフアスのSiや多結晶のCdS、
CdSeなどの半導体薄膜を用いた薄膜トランジス
タをスイツチング素子としたアクテイブ・マトリ
クス型の表示装置が注目されている。薄膜トラン
ジスタアレイは、ガラス基板等を用いて低温プロ
セスで形成することができるため、安価に大面積
の表示装置を実現できるという利点を有する。
In recent years, amorphous Si, polycrystalline CdS,
Active matrix display devices that use thin film transistors made of semiconductor thin films such as CdSe as switching elements are attracting attention. Thin film transistor arrays can be formed using a glass substrate or the like in a low-temperature process, and therefore have the advantage that a large-area display device can be realized at low cost.
第５図はこの様なアクテイブ・マトリクス型の
表示装置の等価回路を示す。図において、
Ａ（A11，A12，…）はアドレス線、Ｄ（D11，
D12，…）は画像信号が供給されるデータ線であ
り、これらアドレス線Ａとデータ線Ｄの各交差位
置に画素に対応して薄膜トランジスタＴ（T11，
T12，…）が形成される。薄膜トランジスタＴの
ゲート電極はアドレス線Ａに、ソース電極はデー
タ線Ｄに、ドレイン電極は表示素子Ｓ（S11，S12，
…）の画素電極にそれぞれ接続されている。表示
素子Ｓとしては、液晶素子、エレクトロルミネセ
ンス（EL）素子、エレクトロクロミツク素子等
が用いられる。表示素子Ｓとして液晶素子を用い
る場合通常、図示のように駆動電圧を保持するた
めのキヤパシタＣ（C11，C12，…）が設けられる。
アドレス線Ａ、データ線Ｄ、薄膜トランジスタ
Ｔ、キヤパシタＣおよび表示素子Ｓの画素電極は
絶縁性基板上に集積形成されて駆動回路基板構成
する。そしてこの駆動回路基板と対向電極が形成
された透明基板の間に液晶層を挟持することによ
り、アクテイブ・マトリツクス型液晶表示装置が
得られる。なお、薄膜トランジスタＴのオフ抵抗
および表示素子の抵抗が充分に高い場合には、キ
ヤパシタＣを必要としない。 FIG. 5 shows an equivalent circuit of such an active matrix type display device. In the figure, A (A 11 , A 12 ,...) is an address line, and D (D 11 , ...) is an address line.
D 12 ,...) are data lines to which image signals are supplied, and thin film transistors T (T 11 ,...) are placed at each intersection of the address line A and data line D corresponding to the pixel.
T 12 ,…) are formed. The gate electrode of the thin film transistor T is connected to the address line A, the source electrode is connected to the data line D, and the drain electrode is connected to the display element S (S 11 , S 12 ,
...) are respectively connected to the pixel electrodes. As the display element S, a liquid crystal element, an electroluminescent (EL) element, an electrochromic element, etc. are used. When a liquid crystal element is used as the display element S, capacitors C (C 11 , C 12 , . . . ) for holding a driving voltage are usually provided as shown in the figure.
Address lines A, data lines D, thin film transistors T, capacitors C, and pixel electrodes of display elements S are integrally formed on an insulating substrate to constitute a driving circuit board. By sandwiching a liquid crystal layer between this drive circuit board and a transparent substrate on which a counter electrode is formed, an active matrix type liquid crystal display device can be obtained. Note that if the off-resistance of the thin film transistor T and the resistance of the display element are sufficiently high, the capacitor C is not required.
この種の表示装置を高精細あるいは大面積に実
現する場合には、用いる薄膜トランジスタの数が
非常に多くなる。例えば、アドレス400×データ
400の場合、素子数は160000となる。この様な多
数の薄膜トランジスタアレイを完全に製作するこ
とは困難であり、種々の欠陥が発生する。その原
因としては、(1)多層配線間あるいはキヤパシタの
電気的短絡、(2)配線の解放、(3)薄膜トランジスタ
の欠陥、等がある。表示装置として点欠陥を許容
した場合、配線の解放は容易に救済することがで
きる。例えばアドレス線が途中の一点で断線した
場合には、アドレス線の両方から信号を供給する
ようにすることにより、救済できる。またキヤパ
シタは、薄膜トランジスタのオフ抵抗を充分に大
きくし液晶の抵抗率を上げれば設ける必要がない
ため、この部分で致命的な欠陥とならない。しか
し、配線の短絡事故は致命的な大きい欠陥とな
る。たとえばアドレス線とデータ線が短絡する
と、これらの配線に沿つて線欠陥となる。しかも
この短絡は簡単には補修により救済することがで
きない。 When realizing this type of display device with high definition or a large area, the number of thin film transistors used becomes extremely large. For example, address 400 x data
In the case of 400, the number of elements is 160000. It is difficult to completely manufacture such a large number of thin film transistor arrays, and various defects occur. The causes include (1) electrical short circuits between multilayer interconnects or capacitors, (2) open interconnects, and (3) defects in thin film transistors. If a point defect is tolerated in the display device, it can be easily repaired by opening the wiring. For example, if an address line is broken at one point on the way, it can be repaired by supplying signals from both address lines. Further, since it is not necessary to provide a capacitor if the off-resistance of the thin film transistor is sufficiently increased and the resistivity of the liquid crystal is increased, this portion does not become a fatal defect. However, a short-circuit accident in the wiring can be a major, fatal defect. For example, if an address line and a data line are shorted, line defects will occur along these lines. Moreover, this short circuit cannot be easily relieved by repair.
この様な多層配線間の短絡を防止する方法とし
て、アドレス線兼ゲート電極を例えばTa膜によ
り形成してその表面に陽極酸化膜を形成し、更に
その上にSiO2膜またはSi3N4膜を堆積するとい
う、ゲート絶縁膜を２層構造とすることが提案さ
れている（特公昭60−54478号公報）。しかしこの
方法では、Ta膜の陽極酸化によりアドレス線の
抵抗が大きくなつてしまう。例えば、220×240画
素で44mm×60mmの画面をつくる薄膜トランジスタ
アレイを考える。1500ÅのTa膜で配線抵抗約
60KΩのアドレス線を表面から約700Å酸化する
と、配線抵抗は約110KΩになる。このように配
線抵抗が大きくなると、アドレスパルスの遅延に
よる波形歪みが大きくなる。この結果アドレス線
の信号入力端部と終端部での画素への書込みに差
が生じ画質の均一性が大きく損われることにな
る。Ta膜の膜厚を大きくすれば配線抵抗を小さ
くすることができるが、余り厚くすると膜の剥が
れやデータ線の断線の原因となる。 As a method to prevent such short circuits between multilayer wiring, the address line/gate electrode is formed of, for example, a Ta film, an anodic oxide film is formed on the surface thereof, and then an SiO 2 film or a Si 3 N 4 film is formed on the surface of the address line/gate electrode. It has been proposed to form a gate insulating film with a two-layer structure by depositing (Japanese Patent Publication No. 60-54478). However, with this method, the resistance of the address line increases due to anodic oxidation of the Ta film. For example, consider a thin film transistor array that creates a 44 mm x 60 mm screen with 220 x 240 pixels. Wiring resistance is approx. with 1500Å Ta film
If a 60KΩ address line is oxidized by approximately 700Å from the surface, the wiring resistance will be approximately 110KΩ. When the wiring resistance increases in this way, waveform distortion due to address pulse delay increases. As a result, there is a difference in writing to pixels at the signal input end and the terminal end of the address line, resulting in a significant loss of uniformity in image quality. Wiring resistance can be reduced by increasing the thickness of the Ta film, but if it is too thick, it may cause peeling of the film or disconnection of the data line.
また、Ta膜によるアドレス線およびゲート電
極を形成し、その上にSiO2膜を堆積した後、
SiO2膜のピンホール部のみをピンホールを介し
て陽極酸化する方法も考えられている（特公昭60
−54478号公報）。しかしこの方法は、その後に
SiO2膜に孔が開いた場合に多層配線間の短絡を
生じるため、短絡防止策として不充分である。 In addition, after forming address lines and gate electrodes using a Ta film and depositing a SiO 2 film on them,
A method of anodic oxidation of only the pinhole portion of the SiO 2 film through the pinhole has also been considered (Special Publication Act of 1983).
-54478). But this method then
If a hole opens in the SiO 2 film, it will cause a short circuit between multilayer wiring, so it is insufficient as a measure to prevent short circuits.
本発明は上記した点に鑑みなされたもので、配
線抵抗を大きくすることなく多層配線間の短絡を
確実に防止し、もつて優れた画像表示を可能とす
る表示装置用駆動回路基板を提供することを目的
とする。
The present invention has been made in view of the above-mentioned points, and provides a drive circuit board for a display device that reliably prevents short circuits between multilayer wiring without increasing wiring resistance, thereby enabling excellent image display. The purpose is to
本発明は、絶縁性基板上に所定の金属膜により
アドレス線およびゲート電極を形成し、この上に
絶縁膜を介してアドレス線と交差するデータ線を
形成し、アドレス線とデータ線の各交差位置には
薄膜トランジスタを配置する表示装置用駆動回路
基板において、前記アドレス線のデータ線と交差
する位置およびゲート電極表面にのみ選択的に陽
極酸化膜を形成し、これらの部分のみを２層の絶
縁膜構造とする。
The present invention forms address lines and gate electrodes using a predetermined metal film on an insulating substrate, forms data lines that intersect with the address lines through an insulating film, and forms each intersection of the address line and the data line. In a display drive circuit board in which thin film transistors are arranged, an anodic oxide film is selectively formed only at the positions where the address line intersects with the data line and on the gate electrode surface, and only these parts are covered with two layers of insulation. It has a membrane structure.
本発明によれば、層間絶縁膜を陽極酸化膜を含
む２層絶縁膜構造とすることにより、多層配線間
の短絡を確実に防止することができる。しかも陽
極酸化膜を設けるのはアドレス線の一部およびゲ
ート電極部分のみであるため、アドレス線の高抵
抗化を招くことはない。従つて本発明によれば、
信頼性が高く、かつ優れた表示画像が得られる表
示装置用駆動回路基板が実現する。
According to the present invention, by forming the interlayer insulating film into a two-layer insulating film structure including an anodic oxide film, short circuits between multilayer interconnections can be reliably prevented. Moreover, since the anodic oxide film is provided only on a portion of the address line and the gate electrode portion, the resistance of the address line does not increase. According to the invention, therefore:
A drive circuit board for a display device that is highly reliable and provides an excellent display image is realized.
以下本発明の実施例を説明する。 Examples of the present invention will be described below.
第１図ａ〜ｃは一実施例の駆動回路基板であ
り、ａは平面図、ｂおよびｃはそれぞれａのＡ−
A′およびＢ−B′断面図である。具体的には44mm
×60mmの画面の液晶表示装置用として構成された
ものである。これを製造工程に従つて説明する
と、絶縁性基板として例えばコーニング7059など
のガラス基板１を用い、先ずこの上にTa膜を
1500Åスパツタし、これをパターン形成したアド
レス線２およびこれから突設した形のゲート電極
３を形成する。次にフオトレジストパターンを形
成し、100Vの電圧で露出しているTa膜表面を陽
極酸化して、ゲート電極３上およびアドレス線２
のうち後にデータ線が交差する部分（第１図ａに
斜線を施して示した領域）上に選択的に陽極酸化
膜４（４1，４2）を形成する。この後全面にプラ
ズマCVDにより2500ÅのSiO2膜５を堆積し、続
いて半導体薄膜としてアンドープのアモルフアス
Si（ａ−Si）膜６とn+型ａ−Si膜７を堆積し、第
１図ａに破線で囲んだ領域にこれらの半導体薄膜
を島状に残すようにパターン形成する。次にITO
膜を1500Åスパツタし、これをパターン形成して
画素電極８を形成する。そしてAl膜を1μｍ蒸着
し、パターニングしてデータ線９、これから突設
した形のソース電極１０および画素電極８に接続
されるドレイン電極１１を形成する。最後に薄膜
トランジスタのチヤンネル領域部のn+型ａ−Si膜
７をCDE法により除去する。 Figures 1a to 1c show the drive circuit board of one embodiment, where a is a plan view, b and c are A-A of a, respectively.
They are A' and BB' sectional views. Specifically 44mm
It is designed for use in liquid crystal display devices with a 60 mm screen. To explain this according to the manufacturing process, a glass substrate 1 such as Corning 7059 is used as an insulating substrate, and a Ta film is first deposited on it.
Sputtering is performed to a thickness of 1500 Å to form an address line 2 and a gate electrode 3 projecting therefrom. Next, a photoresist pattern is formed, and the exposed Ta film surface is anodized with a voltage of 100V, and the surface of the gate electrode 3 and the address line 2 are
An anodic oxide film 4 (4 1 , 4 2 ) is selectively formed on the portion where the data lines intersect later (the area indicated by diagonal lines in FIG. 1a). After that, a 2500 Å SiO 2 film 5 is deposited on the entire surface by plasma CVD, and then an undoped amorphous amorphous film is deposited as a semiconductor thin film.
A Si (a-Si) film 6 and an n + type a-Si film 7 are deposited and patterned so that these semiconductor thin films are left in the form of islands in the region surrounded by broken lines in FIG. 1a. Then ITO
A film of 1500 Å is sputtered and patterned to form the pixel electrode 8. Then, an Al film is deposited to a thickness of 1 μm and patterned to form a data line 9, a source electrode 10 projecting from the data line 9, and a drain electrode 11 connected to the pixel electrode 8. Finally, the n + type a-Si film 7 in the channel region of the thin film transistor is removed by the CDE method.
本実施例では、アドレス線の抵抗は陽極酸化前
の値60KΩに対して66KΩであり、その増加は殆
ど問題にならない。またアドレスパルスの遅延は
全面陽極酸化した場合の約1/2に止まり、従つて
表示のばらつきが少なくなる。 In this embodiment, the resistance of the address line is 66KΩ compared to the value of 60KΩ before anodization, and the increase causes almost no problem. In addition, the delay of the address pulse is only about half that of the case where the entire surface is anodized, and therefore the display variation is reduced.
第２図は別の実施例の要部構成を第１図ａに対
応させて示す。先の実施例と対応する部分には同
一符号を付して詳細な説明は省略する。先の実施
例では、アドレス線から突設する形でゲート電極
を形成したのに対して、この実施例ではアドレス
線上に薄膜トランジスタを構成している。このよ
うな構成の場合にも、アドレス線２上およびゲー
ト電極３上に斜線を施して示したように選択的に
陽極酸化膜４（４1，４2）を形成することによ
り、先の実施例と同様の効果が得られる。 FIG. 2 shows the main structure of another embodiment in correspondence with FIG. 1a. Portions corresponding to those in the previous embodiment are designated by the same reference numerals and detailed explanations will be omitted. In the previous embodiment, the gate electrode was formed to protrude from the address line, whereas in this embodiment, the thin film transistor is formed on the address line. Even in the case of such a structure, by selectively forming the anodic oxide film 4 (4 1 , 4 2 ) on the address line 2 and the gate electrode 3 as shown by hatching, the previous implementation can be performed. The same effect as in the example can be obtained.
第３図ａ，ｂは更に他の実施例の要部構成を示
す平面図とそのＣ−C′断面図である。ここでも先
の実施例と対応する部分には同一符号を付してあ
り、詳細な説明は省略する。この実施例が第１図
の実施例と異なる点は、アドレス線２のうち陽極
酸化されていない部分で酸化膜５にできるだけ大
きい開口を開けて、アドレス線２にコンタクトす
る金属配線１２を積層していることである。これ
により、アドレス線のより一層の低抵抗化が図ら
れる。具体的に金属配線１２として1μｍのAl配
線を用いて、アドレス線の抵抗を約20KΩにまで
低下させることができた。 FIGS. 3a and 3b are a plan view and a sectional view taken along the line C-C' of another embodiment. Here too, parts corresponding to those in the previous embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. The difference between this embodiment and the embodiment shown in FIG. 1 is that an opening as large as possible is made in the oxide film 5 in the part of the address line 2 that is not anodized, and a metal wiring 12 in contact with the address line 2 is laminated. This is what is happening. This makes it possible to further reduce the resistance of the address line. Specifically, by using a 1 μm Al wire as the metal wire 12, the resistance of the address line could be reduced to about 20 KΩ.
第４図ａ，ｂは、第３図の実施例を変形した実
施例の平面図とそのＤ−D′断面図である。この
実施例では、アドレス線２にコンタクトさせて重
ねる金属配線１３を、アドレス線２に沿つて連続
的に配設している。従つてこの金属配線１３とデ
ータ線９の絶縁のためにデータ線９上に約1μｍ
のポリイミド膜１４を設けている。この実施例の
場合更にアドレス線の低抵抗化が可能であり、金
属配線１３として1μｍのAl膜を用いて約1KΩの
アドレス線抵抗が実現できた。 FIGS. 4a and 4b are a plan view and a sectional view taken along line D-D' of an embodiment modified from the embodiment shown in FIG. In this embodiment, the metal wiring 13 is continuously arranged along the address line 2 so as to be in contact with and overlap the address line 2 . Therefore, in order to insulate the metal wiring 13 and the data line 9, there is a gap of about 1 μm on the data line 9.
A polyimide film 14 is provided. In this embodiment, it is possible to further reduce the resistance of the address line, and by using a 1 μm Al film as the metal wiring 13, an address line resistance of approximately 1 KΩ was achieved.
第３図および第４図の実施例のようにアドレス
線に更に金属配線を積み重ねる場合、本発明の構
造では陽極酸化膜が部分的に形成されていて、コ
ンタクト孔形成のためのエツチングはSiO2膜に
対してのみ行なえばよく、エツチングの困難な
TaOに対しては必要でないので、工程が容易で
ある。 When metal wiring is further stacked on the address line as in the embodiments shown in FIGS. 3 and 4, in the structure of the present invention, the anodic oxide film is partially formed, and the etching for forming the contact hole is performed using SiO 2 . It only needs to be etched on the film, which is difficult to etch.
Since it is not necessary for TaO, the process is easy.
本発明は上記した実施例に限られるものではな
い。例えばアドレス線を構成する金属膜はTaに
限らず、Ti、Alなど陽極酸化できるものであれ
ばよい。薄膜トランジスタを構成する半導体薄膜
もａ−Siに限らず、多結晶SiやCdSe、CdSなど
を用いることができる。層間絶縁膜としても、
SiO2膜の他、Si3N4膜やAl2O3膜等を用いること
ができる。 The present invention is not limited to the embodiments described above. For example, the metal film constituting the address line is not limited to Ta, but may be any other material that can be anodized, such as Ti or Al. The semiconductor thin film constituting the thin film transistor is not limited to a-Si, and polycrystalline Si, CdSe, CdS, etc. can be used. Also as an interlayer insulation film,
In addition to the SiO 2 film, a Si 3 N 4 film, an Al 2 O 3 film, etc. can be used.
その他本発明はその趣旨を逸脱しない範囲で
種々変形して実施することができる。 In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.
第１図ａ〜ｃは本発明の一実施例の駆動回路基
板を示す図、第２図は他の実施例の駆動回路基板
の要部構成を示す図、第３図ａ，ｂおよび第４図
ａ，ｂは更に他の実施例の駆動回路基板の要部構
成を示す図、第５図はアクテイブ・マトリクス型
液晶表示装置の等価回路を示す図である。
１……ガラス基板、２……アドレス線（Ta
膜）、３……ゲート電極（Ta膜）、４（４1，４2）
……陽極酸化膜、５……CVDSiO2膜、６……ａ
−Si膜、７……n+型ａ−Si膜、８……画素電極、
９……データ線（Al膜）、１０……ソース電極
（Al膜）、１１……ドレイン電極（Al膜）、１２，
１３……金属配線、１４……ポリイミド膜。
1A to 1C are diagrams showing a drive circuit board according to one embodiment of the present invention, FIG. 2 is a diagram showing the main part configuration of a drive circuit board according to another embodiment, and FIGS. Figures a and b are diagrams showing the main part configuration of a drive circuit board of still another embodiment, and Figure 5 is a diagram showing an equivalent circuit of an active matrix type liquid crystal display device. 1...Glass substrate, 2...Address line (Ta
film), 3...gate electrode (Ta film), 4 (4 1 , 4 2 )
...Anodized film, 5...CVDSiO 2 film, 6...a
-Si film, 7...n + type a-Si film, 8... pixel electrode,
9... Data line (Al film), 10... Source electrode (Al film), 11... Drain electrode (Al film), 12,
13...Metal wiring, 14...Polyimide film.
Claims (1)
本のアドレス線と、このアドレス線が形成された
基板上に層間絶縁膜を介して形成されてアドレス
線と交差する方向に走る複数本のデータ線と、こ
れらアドレス線とデータ線の各交差位置に形成さ
れた複数の薄膜トランジスタと、これら薄膜トラ
ンジスタを介して選択的に前記データ線に接続さ
れて表示素子に駆動電圧を印加する複数の画素電
極とを有し、前記薄膜トランジスタが、前記アド
レス線と一体形成されたゲート電極と、このゲー
ト電極上にゲート絶縁膜を介して形成された半導
体薄膜と、この半導体薄膜上に形成された前記デ
ータ線と連続するソース電極および前記画素電極
に接続されるドレイン電極とから構成された表示
装置用駆動回路基板において、前記アドレス線の
うち前記データ線と交差する部分および前記ゲー
ト電極の表面に選択的に前記アドレス線およびゲ
ート電極を構成する金属の陽極酸化膜が形成さ
れ、この陽極酸化膜上に層間絶縁膜が積層されて
いることを特徴とする表示装置用駆動回路基板。 ２ 前記半導体薄膜はアモルフアスSi膜である特
許請求の範囲第１項記載の表示装置用駆動回路基
板。 ３ 前記アドレス線の陽極酸化膜が形成されてい
ない部分にコンタクトしてアドレス線の抵抗を低
減するための金属配線が形成されている特許請求
の範囲第１項記載の表示装置用駆動回路基板。[Claims] 1. An insulating substrate, a plurality of address lines formed on this substrate, and a plurality of address lines formed on the substrate on which the address lines are formed via an interlayer insulating film to intersect with the address lines. A plurality of data lines running in the direction, a plurality of thin film transistors formed at each intersection of these address lines and data lines, and a drive voltage that is selectively connected to the data lines through these thin film transistors to apply a driving voltage to the display element. The thin film transistor includes a gate electrode formed integrally with the address line, a semiconductor thin film formed on the gate electrode via a gate insulating film, and a semiconductor thin film formed on the semiconductor thin film. In a display device drive circuit board comprising a source electrode continuous with the formed data line and a drain electrode connected to the pixel electrode, a portion of the address line intersecting with the data line and the gate electrode A drive circuit board for a display device, characterized in that a metal anodic oxide film constituting the address lines and gate electrodes is selectively formed on the surface of the substrate, and an interlayer insulating film is laminated on the anodic oxide film. 2. The drive circuit board for a display device according to claim 1, wherein the semiconductor thin film is an amorphous Si film. 3. The drive circuit board for a display device according to claim 1, wherein a metal wiring is formed in contact with a portion of the address line where the anodic oxide film is not formed to reduce the resistance of the address line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214570A JPS6276545A (en) | 1985-09-30 | 1985-09-30 | Drive circuit substrate for display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60214570A JPS6276545A (en) | 1985-09-30 | 1985-09-30 | Drive circuit substrate for display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6276545A JPS6276545A (en) | 1987-04-08 |
| JPH0340511B2 true JPH0340511B2 (en) | 1991-06-19 |
Family
ID=16657900
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60214570A Granted JPS6276545A (en) | 1985-09-30 | 1985-09-30 | Drive circuit substrate for display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6276545A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2620240B2 (en) | 1987-06-10 | 1997-06-11 | 株式会社日立製作所 | Liquid crystal display |
| JP2786628B2 (en) * | 1987-10-15 | 1998-08-13 | シャープ株式会社 | Liquid crystal panel electrode structure |
| JPH0816758B2 (en) * | 1989-02-17 | 1996-02-21 | 松下電器産業株式会社 | Liquid crystal image display device and method of manufacturing the same |
| US5485019A (en) * | 1992-02-05 | 1996-01-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for forming the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
-
1985
- 1985-09-30 JP JP60214570A patent/JPS6276545A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54154289A (en) * | 1978-05-26 | 1979-12-05 | Matsushita Electric Ind Co Ltd | Manufacture of thin-film transistor array |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6276545A (en) | 1987-04-08 |
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|---|---|---|---|
| EXPY | Cancellation because of completion of term |