JPH01134342A - Active matrix substrate - Google Patents

Abstract

PURPOSE:To prevent a source bus line from being broken by branching a source line into plural lines at the intersection part of gate and source lines of a thin film transistor(TR) array formed in a matrix on an insulating substrate, interposing an insulator or laminate of an insulator and a semiconductor and forming respective layers separately in an island shape. CONSTITUTION:A by-pass line 2 is formed in parallel to the gate bus line 1 and connected through a through hole 3 of an inter-layer insulating film to form two-layered structure. No by-pass line is provided at a part 4 of intersection with the source bus line. A by-pass line 6 is formed at the intersection part 4 separately from the source bus line 5 to form the laminate structure of a conductor thin film through the inter-layer insulating film and through hole 9. At the intersection part, an a-Si(n<+>)/a-Si(i) layer 7 and an etching stopper SiNx layer 8 are separated in an island shape to reduce the possibility of the breaking of the source bus line due to the separation of the layers 7 and 8. This constitution improves the picture quality of the active matrix display device.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to an active matrix substrate including a thin film transistor array, which constitutes an active matrix display device in combination with a liquid crystal or the like. [Prior art and its problems 1 In an active matrix display device, the occurrence of pixel defects or linear defects is a serious quality defect. In order to prevent these defects, it is necessary to eliminate disconnections of gate bus lines and source bus lines, leakage between lines, and malfunctions of thin film transistors (hereinafter referred to as TPT) in the active matrix substrate. The causes of these defects include dust, foreign matter, or film peeling during the photolithography process or thin film forming process. A TPT active matrix substrate with a conventional structure will be explained below. FIG. 24 shows a TPT active matrix substrate in which picture elements (A□,) each containing TPT are arranged in a matrix. The TPT, pass line, and picture element electrode of the conventional structure are shown in FIGS. 22 and 23. FIG. 23 is a diagram showing a BB' cross section in FIG. 22. The gate bus lines a and b are formed on the glass substrate S using tantalum (Ta).
), and the gate oxide film is made of tantalum oxide (Taxes
) layer c1 has a double structure of silicon nitride (SiNx) layer d, semiconductor layers e and f are intrinsic amorphous silicon (a-3i(i)), and source bus line g. h is titanium (Ti), drain electrodes i and j are titanium, picture element electrodes, l is ITO film (indium oxide transparent conductive film)
, between the semiconductor layer and the source/drain electrodes are silicon nitride Ilr+m and n" type amorphous silicon (a-5i (n) layers p,
q is formed. In addition, at the intersection of source bus line g and gate bus line a, a
-3i(i)/a-3i (n layers In this case, linear defects occur in active matrix substrates with a conventional structure.Furthermore, if the TPT is damaged for some reason, pixel defects occur in active matrix substrates with a conventional structure.Therefore, conventional methods have been used to prevent these defects. Therefore, countermeasures have been taken in the process, but it has been difficult to completely prevent them.In view of the above-mentioned drawbacks, the present invention aims to prevent linear defects due to disconnection of source bus lines in active matrix substrates. It is an object of the present invention to provide a structure of an active matrix substrate for improving the image quality of an active matrix display device. A thin film transistor array is formed in a matrix on a substrate, and at a cross section between a gate bus line and a source bus line of the transistor array, the source bus line branches into two or more lines. , between the source bus line and the gate bus line, there is a layer of an insulator or a layer of one or more superimposed layers of an insulator and a semiconductor, and each core layer is
It is characterized by being formed in isolated islands. [Operation] The probability of occurrence of disconnection of the source bus line and leakage between the source bus line and the gate bus line in the active matrix substrate is reduced. [Example 1] Figure 1 shows an amorphous silicon (a-Si) semi-quadruple TFT with various redundancies, which is an example of the present invention.
An active matrix substrate is shown. Reference numbers 1.5 are a gate bus line and a source bus line, respectively. T
FTII is an electrode 13 drawn out from the gate bus line.
and an electrode 15 drawn out from the source bus line. Further, reference number 14 is a drain electrode,
It is connected to 170g12 which is a transparent conductive film. The above basic configuration is the same as the conventional example. The various redundant parts of the present invention are described below: ■Gate bus line,
■Explain the source bus line and ■picture elements. ■Gate bus line A bypass line 2 is provided in parallel with the normal gate bus line 1. By providing a bypass in this manner, the line width of the pass line is effectively increased. Furthermore, even if the pass line material peels off, the probability that both pass lines 1.2 will peel off at the same time is lower than the probability of peeling off when there is only one pass line. Even if peeling occurs in the TPT, by providing the above redundancy, the TPT as a whole will be defect-free and have good operability. Furthermore, as shown in FIG. 21, the gate bus line is made of two layers of conductive thin film, titanium and tantalum, and an insulating thin film is provided between each layer of the conductive thin film. A through hole 3 is provided for electrically connecting each layer of the conductor thin film. By connecting each conductive film through the through hole 3,
It is also effective in reducing the resistance of gate bus lines. Further, the cross section 4 with the source bus line is not provided with a bypass section in order to reduce the number of crosses. This is because if the number of cross portions is increased, vertical leakage between the source and gate becomes more likely to occur, and stray capacitance also increases. (2) Source Bus Line In addition to the normal source bus line 5, a bypass line 6 is provided at the intersection with the gate bus line. Providing the bypass line 6 effectively increases the source line width. Further, as in the case of the gate bus line, the probability of occurrence of peeling of the entire source bus line can be reduced. Further, as detailed cross sections are shown in FIGS. 16 to 20, the source bus line is also formed from two or more layers of conductive thin films, and an insulating thin film is provided between each layer of the conductive thin films. Therefore, through holes 9 are provided for electrically connecting each layer of the conductor thin film. Through hole 9
By connecting the conductor thin films through the conductor thin film, it is effective to prevent disconnection of the source bus line and at the same time reduce the resistance of the source bus line. Reference numbers 7 and 8 are semiconductor films for preventing leakage between the source bus line and the gate bus line, respectively 6a-3i(n'')/a
-S1(i) layer, etching stopper -5iNX layer. 7 and 8 are formed separately into islands at each cross portion. This is a-5i(n”)/a-3
The probability of disconnection of the source bus line at the cross section due to peeling of the i(i) layer 7 and the etching stopper SiNx layer 8 is reduced by the redundancy of separating into island shapes. (2) Picture element Two TFTs for driving each picture element are provided for each picture element, such as TFT II and 11. Here, two TPTs are connected to a picture element in parallel via a TPT connection read gate line 13 extending from the gate bus line in parallel to the source bus line. That is, TFTI l', 11 is connected to the same gate bus line and the same source bus line. In order to reduce the probability of simultaneous source or gate disconnection in two TPTs, the interval is made as large as possible. Furthermore, as will be described later, the drain electrode 14 has a two-layer structure using titanium and ITO, which is a pixel electrode material (see FIG. 19,
(See Figure 20). Reference numbers 1, 5, 13, etc. above are used to represent the source bus line, gate bus line, lead-out line from the gate bus line, etc., but below they will also represent the thin film layers that constitute them. .

[Manufacturing process description]

Next, the manufacturing process of the TPT active matrix substrate shown in FIG. 1 will be explained with reference to FIGS. 2 to 8. Note that the hatched portions shown in the following figures indicate the portions that are formed or processed in the process at that time. (Process 1) As shown in FIG. 2, tantalum is deposited to a thickness of 500 to 5,000 on a transparent insulating glass substrate 50, and patterned as shown in the shaded area by a photolithography process. In FIG. 2, a gate bypass line 2 is provided in parallel with a normal gate bus line 1. Furthermore, no bypass line is formed at the cross section 4 with the source bus line. This is because, as described above, if the number of cross sections between the source and gate is increased, vertical leakage between the source and gate becomes more likely to occur, and the stray capacitance also increases. (Process 2) Next, as shown in the shaded area in FIG. 3, except for the source bus line 5 in FIG.
Form Ta205 of ~5000 people. (Process 3) Then, by PCVD method, a gate insulating film SiNx layer,
a-3i (i) Semiconductor layer, etching stopper SiN
After forming the x layer to have a film thickness of 500A to 6000A, 50 to 4000A, and 300A to 5000A, respectively, the etching stopper layer is patterned using a photolithography process to form only the etching stopper layer as shown in the shaded area 8 in FIG. (See Figure 13). (Process 4) Then, after forming a-3i (n layers) with a film thickness of 200A to 2000 by the PCVD method, the shaded area 7°7 in Fig.
As shown in FIG. As shown in , a through hole 9 is made in the SiNx layer which is the gate insulating film on the source bus line.
A through hole 3 is also opened in the x/T ax Os layer. Two through holes can be drilled in each. This is to provide redundancy and reduce defects in the through holes in case one of the through holes is blocked due to a defect in the photolithography process (first
(See Figures 6 and 21). (Process 6) Next, titanium is sputter-deposited to a film thickness of 500 to 5000 Å, and titanium a-5i (n) is etched as shown in the hatched pattern in FIG. The titanium vapor-deposited in this process is electrically connected to the tank pattern formed in (process 1) through the through-hole 9.3 by entering the titanium itself into the through-hole. Both the line and source bus line have a top and bottom double structure of titanium and tantalum (Figures 17 and 18).
(see figure). (Process 7) Next, ITO, which is the picture element electrode material, is coated with a film thickness of 300 to 3
After sputter deposition, the ITO film is patterned as shown in the shaded area in FIG. 8 using a photolithography process. Note that ITO is patterned not only on the picture element electrode and the drain electrode 14 of the TFT but also on the source bus line and a part of the gate bus line (process 6).
It is possible to suppress the occurrence of disconnection of titanium due to

[Explanation of the manufacturing process using cross-sectional diagrams]

Next, the manufacturing process of the active matrix substrate according to the present invention will be explained with reference to the AA' cross section in FIG. FIG. 9 shows a film with a thickness of 500A to 500A on a glass substrate 50.
This shows the state where tantalum was deposited by 0 persons. Next, the tantalum shown in FIG. 9 is patterned to have a cross section as shown in FIG. 1O using the pattern shown in FIG. Then, as shown in the shaded area in FIG. 3, only the gate bus line is oxidized to form an oxide film as shown in FIG. 11. Then, the gate oxide film SiNx and the semiconductor layer a are formed using the PCvD method.
-S 1(i), film thickness of etching stopper layer: 500 to 6000, 50 to 4000, 30
0A to 5,000 people (Figure 12). Then, by a photolithography process, the etching stopper layer shown in FIG. 12 is formed into the island-shaped etching stopper layer 8 shown in FIG. 4 (FIG. 13). Film thickness: 200A ~ 20mm by PCVD method
00 A semiconductor layer a-5i (n layers are formed (14th
figure). Then, by a photolithography process, the semiconductor layers a-5i (n, a-S 1(i)) formed in FIGS. 12 and 14 are simultaneously formed into the island-like pattern 7 in FIG. (Fig. 15).Next, the gate oxide film SiN
Drill a through hole 9 in x (Fig. 16). After that, titanium was sputter-deposited to a film thickness of 500 to 5000 (
(Fig. 17), titanium, a-3i (n) is formed by a photolithography process into the pattern of the source bus line as shown in Fig. 7), and the IT which becomes the picture element electrode
After sputter-depositing O to a film thickness of 300 to 3000 mm (Figure 19), patterning is performed as shown in the shaded area in Figure 8 (
Figure 20). The above is the manufacturing process regarding the AA' cross section in FIG. Finally, for reference, the sectional view C-C'' in Figure 1 is shown in Figure 2.
This is shown in Figure 1. [Effect] It is possible to reduce the probability of occurrence of linear defects in an active matrix liquid crystal display device using an active matrix substrate according to the present invention. Therefore, the manufacturing yield of active matrix liquid crystal display devices can be improved.

[Brief explanation of the drawing]

FIG. 1 is a structural diagram of a thin film transistor on an active matrix substrate according to the present invention. FIGS. 2 to 8 are diagrams showing the thin film transistor array manufacturing process in FIG. 1, respectively, and FIGS.
Each figure is a cross-sectional view showing the manufacturing process of the thin film transistor array in the direction of line AA' in FIG. 1. FIG. 21 is a cross-sectional view of the thin film transistor array in FIG. B-
24 is a cross-sectional view in the direction of line B''. FIG. 24 is a diagram showing an active matrix substrate in which picture elements (A1,) including thin film transistors are arranged in a matrix. l...Gate bus line, 4... - Cross section of source bus line and gate bus line, 5... Source bus line, 6... Bypass line of source bus line, 7
... Semiconductor thin film layer, 8... Insulator thin film layer, 50...
・Glass substrate.

Claims (1)

[Claims] (1) A thin film transistor array is formed in a matrix on an insulating substrate, and the source bus line branches into two or more lines at the intersection of the gate bus line and source bus line of the transistor array. , in the cross section, between the source bus line and the gate bus line, there is a layer of an insulator or a layer of one or more superimposed layers of an insulator and a semiconductor, and each layer is an island. An active matrix substrate characterized in that the active matrix substrate is formed in separate shapes.