JPS58190042A - Thin film semiconductor device - Google Patents

Abstract

PURPOSE:To effectively prevent electric short-circuit between multi-layered metal wirings by providing a high resistance a-Si film, to which impurity is not particularly added, at the crossing portion of multi-layer metal wiring layers. CONSTITUTION:First, Al film is vacuum-deposited in the thickness of 1,500Angstrom on a glass substrate 1 and a gate electrode of TFT and other wirings 22 are patterned. The SiO2 film 3 is deposited at the entire part. This SiO2 film 3 becomes the gate insulating film and inter-layer insulating film of TFT. A non- impurity added a-Si film is deposited in the thickness of 2,000Angstrom and thereafter P-doped a-Si film is deposited in the thickness of 500Angstrom , and these laminated films are left in the channel part of TFT and the area where multi-layer wirings are crossing. The second wiring material, Al is vacuum-deposited in the thickness of 4,000Angstrom and the source electrode wiring 61 and drain electrode wiring 62 are formed by patterning. Finally, the N<+> a-Si film 5 is etched with this second layer electrode wiring used as the mask and thereby a TFT circuit can be completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a thin film semiconductor device having an element using an amorphous silicon film and multilayer metal wiring.

[Technical background of the invention and its problems]

In recent years, with the progress of semiconductor integrated circuit technology, the integration density and the number of integrated elements have increased significantly, and the area of the elements has become larger. With this progress in integration, the single-chip wiring between each element has become more complex, changing from the conventional single-layer metal wiring to two or more layers of multilayer metal wiring.
- Wiring is required, and a random method is being used. This type of intermediate dipping also applies to thin film semiconductor devices in which elements such as thin film field effect transistors (TPT) are integrated using an amorphous silicon (a-8t) film.

In thin film semiconductor devices, an inexpensive glass substrate is usually used, and elements and wiring are formed on this by thin film technology. In this case, the interlayer insulating film for forming the multilayer metal wiring is formed using an OVD method, sputtering, etc. at a temperature range that does not melt the substrate or the metal wiring material that has already been formed. Ei, S I a N4M 婢 is mainly used. These various interlevel insulating films have many living holes, which are different from, for example, an oxide film caused by low-temperature oxidation of silicon, and the upper and lower metal wiring layers may be electrically short-circuited through these pinholes. Particularly in high-integration density or large-area substrates, the probability of short-circuiting of multilayer metal interconnections due to pinholes is extremely high, and is a major cause of reduced yield.

OBJECTS OF THE INVENTION The present invention improves the above-mentioned conventional drawbacks and provides a #film semiconductor device having a structure that can effectively prevent electrical short circuits between multilayer metal interconnections.

[Summary of the invention]

The present invention provides a thin film semiconductor device in which an element using an A-81 film and a multilayer metal wiring are formed on an insulating substrate.
In addition to the interlayer insulation j- such as 4, a high-resistance a-8i film to which no impurities are particularly added is interposed.

This a-Si film is produced using glow discharge decomposition method of SiH, O
An a-81 film for elements such as TPT formed by vD method, sputtering method, etc. can be patterned and used so as to remain selectively at the intersections of multilayer wiring. Further, in order to improve the film quality in this case, it is desirable to contain H, F, etc.

〔Effect of the invention〕

According to the present invention, if the pinholes in the interlayer insulating film are extremely large, electrical short circuits between multilayer metal interconnects can be effectively prevented. This is because the specific resistance of the A-8L film is extremely large, 108 to 10" IQ, when it is an undoped film, and the A-8T film can be formed at low temperatures with fewer defects such as pinholes. Low temperature formation Since it is possible, l
Since it is relatively easy to apply to a large area area exceeding 0XIO 2, it is possible to stably form multiple 11 wirings on a large area substrate.

In addition, if the a-81 film for element formation is used as is for short-circuit prevention a-81f) 11, the reliability and yield can be improved without complicating the manufacturing process of the double-film semiconductor device. .

[Embodiments of the invention]

The details of the present invention will be explained below using Examples.

It is a diagram. This will be explained according to the manufacturing process as follows. First of all, 1500 AI on the first board!
A film is deposited to form the TPT gate electrode 21 and other wiring 22.
Buttering.

Next, a Sin film 3 having a thickness of 30QO&) is deposited on the entire surface by RF sputtering or i,j OV D method.

This 8i0. II! J corresponds to the gate insulating film and interlayer insulating film of TPT. When electrical connection between the first and second layer wiring is required, a contact hole is made in this 8102-3. Next, the impurity-doped a-8IIIJ with a thickness of 2000 Ao was applied, followed by the P-doped 50
A-S I film of 0Ie is deposited, and the stacked I-film is left on the TPT channel portion and the intersection of the multilayer wiring by buttering. Upper 41A and 41 are undoped a-S i N for TPT and short circuit prevention, respectively.
[5 is an n''a-81 film. Next, A/, which is the second wiring material, is vapor-deposited to a thickness of 4000!e, and the source electrode wiring 6 and the drain electrode wiring 6 are formed by patterning. form.

The drain electrode wiring 6□ is the first layer wiring 2. It is placed across the top. Finally, using this second layer electrode wiring as a mask, the n"a-8ip main 5 is etched by ODE to complete the T'FT circuit. Note that the n"a-al
s''L5 is the electrode wiring 61,'!'a 81N4
This is a layer for making good ohmic contact with 1.

With this configuration, even if there is a pinhole at 810, 1pJJ between the intersecting wirings 2° and 6□, a
-S l membrane 4. This prevents electrical short circuits. Figure 2 shows the relationship between the short mi resistance as between the wiring 2t and 6□ and the size of the pinhole when there is a pinhole in the 5lot film 3, and the specific resistance ρ of the intervening wire 81 IQ 4t.
is shown as a parameter. The horizontal axis shows the area of the pinhole as well as the diameter when the pinhole is ideally circular. As is clear from Figure 2, unless the pinhole is extremely large, for example,
It can be seen that if the thickness is .mu.m or less, the inter-story insulation properties of a5ti41 can be sufficiently ensured.

In addition, according to this example, since the a-Sk film can be formed at low temperature and with good homogeneity over a large area, it can be applied to thin film integrated circuits with a large number of bilayer elements and complex multilayer wiring, and is therefore highly effective. can get.

Furthermore, TPT is used as an a-S + film to prevent short circuits.
If a-7-8t [tube formed at the same time] is used, there is no need to add any special process to the conventional manufacturing process of thin film integrated circuits, and the yield and reliability of thin film integrated circuits can be easily improved. can be achieved.

Note that in the embodiment, the first layer wiring 2. and second layer wiring 6. To prevent short circuits, the area is larger than the area of the intersection of a-S i tA.
4 is left, but it suffices if it is large enough to at least cover the intersection.

Further, although the a-8i film generally has high photoconductive properties, there is no problem at the intersections of the wirings because external light is blocked by the wirings. In addition, in the embodiment, a-silliji is interposed between the interlayer insulating film and the upper wiring at the intersection of the wiring, but it may be interposed between the interlayer insulating film and the lower wiring, or both may be interposed between the interlayer insulating film and the lower wiring. may be interposed. Furthermore, the interlayer insulating film may be 8 i 0.0 if it uses thin film formation technology at low temperatures. In addition to H, the present invention is also useful when using other insulating films such as 8i and N4i.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the present invention and its sectional view taken along the line AA', and FIG. 2 is a diagram showing data on short-circuit resistance between wiring layers due to the a-84 gland. 1...Glass substrate, 2....Gate electrode, 2....
・Wiring, 3...8to, film (interlayer insulation film and gate isolation M
film),' t + ' t "' completed dope a -
8i [%, 15...P-doped a 8 tp, 61
...source electrode wiring, 6. ...Drain electrode wiring. 21

Claims (2)

[Claims] (1) A thin film semiconductor device comprising an element using an amorphous silicon film and multilayer metal wiring formed on an insulating substrate, characterized in that an amorphous silicon film is interposed at each intersection of the multilayer metal wiring. thin film semiconductor devices. (2) The device is an Fi thin film field effect transistor, and the amorphous silicon film provided at the intersection of the multilayer wiring is formed at the same time as the amorphous silicon film used in the thin film field effect transistor. The thin film semiconductor device according to item 1.